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32x: rework scheduling/timing
[picodrive.git] / pico / 32x / memory.c
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1/*
2 * PicoDrive
3 * (C) notaz, 2009,2010
4 *
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
7 *
8 * SH2 addr lines:
9 * iii. .cc. ..xx * // Internal, Cs, x
10 *
11 * Register map:
12 * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
13 * a15102 ........ ......SM ? 4002 // intS intM
14 * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
15 * a15106 F....... .....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
16 * a15108 (32bit DREQ src) 4008
17 * a1510c (32bit DREQ dst) 400c
18 * a15110 llllllll llllll00 4010 // DREQ Len
19 * a15112 (16bit FIFO reg) 4012
20 * a15114 ? (16bit VRES clr) 4014
21 * a15116 ? (16bit Vint clr) 4016
22 * a15118 ? (16bit Hint clr) 4018
23 * a1511a ........ .......C (16bit CMD clr) 401a // Cm
24 * a1511c ? (16bit PWM clr) 401c
25 * a1511e ? ? 401e
26 * a15120 (16 bytes comm) 2020
27 * a15130 (PWM) 2030
28 */
29#include "../pico_int.h"
30#include "../memory.h"
31#ifdef DRC_SH2
32#include "../../cpu/sh2/compiler.h"
33#endif
34
35#if 0
36#undef ash2_end_run
37#undef SekEndRun
38#define ash2_end_run(x)
39#define SekEndRun(x)
40#endif
41
42static const char str_mars[] = "MARS";
43
44void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
45struct Pico32xMem *Pico32xMem;
46
47static void bank_switch(int b);
48
49// poll detection
50#define POLL_THRESHOLD 6
51
52struct poll_det {
53 u32 addr, cycles, cyc_max;
54 int cnt, flag;
55};
56static struct poll_det m68k_poll, sh2_poll[2];
57
58static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 cycles, int is_vdp)
59{
60 int ret = 0, flag = pd->flag;
61
62 if (is_vdp)
63 flag <<= 3;
64
65 if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles <= pd->cyc_max) {
66 pd->cnt++;
67 if (pd->cnt > POLL_THRESHOLD) {
68 if (!(Pico32x.emu_flags & flag)) {
69 elprintf(EL_32X, "%s poll addr %08x, cyc %u",
70 flag & (P32XF_68KPOLL|P32XF_68KVPOLL) ? "m68k" :
71 (flag & (P32XF_MSH2POLL|P32XF_MSH2VPOLL) ? "msh2" : "ssh2"), a, cycles - pd->cycles);
72 ret = 1;
73 }
74 Pico32x.emu_flags |= flag;
75 }
76 }
77 else {
78 pd->cnt = 0;
79 pd->addr = a;
80 }
81 pd->cycles = cycles;
82
83 return ret;
84}
85
86static int p32x_poll_undetect(struct poll_det *pd, int is_vdp)
87{
88 int ret = 0, flag = pd->flag;
89 if (is_vdp)
90 flag <<= 3; // VDP only
91 else
92 flag |= flag << 3; // both
93 if (Pico32x.emu_flags & flag) {
94 elprintf(EL_32X, "poll %02x -> %02x", Pico32x.emu_flags, Pico32x.emu_flags & ~flag);
95 ret = 1;
96 }
97 Pico32x.emu_flags &= ~flag;
98 pd->addr = pd->cnt = 0;
99 return ret;
100}
101
102void p32x_poll_event(int cpu_mask, int is_vdp)
103{
104 if (cpu_mask & 1)
105 p32x_poll_undetect(&sh2_poll[0], is_vdp);
106 if (cpu_mask & 2)
107 p32x_poll_undetect(&sh2_poll[1], is_vdp);
108}
109
110// SH2 faking
111//#define FAKE_SH2
112int p32x_csum_faked;
113#ifdef FAKE_SH2
114static const u16 comm_fakevals[] = {
115 0x4d5f, 0x4f4b, // M_OK
116 0x535f, 0x4f4b, // S_OK
117 0x4D41, 0x5346, // MASF - Brutal Unleashed
118 0x5331, 0x4d31, // Darxide
119 0x5332, 0x4d32,
120 0x5333, 0x4d33,
121 0x0000, 0x0000, // eq for doom
122 0x0002, // Mortal Kombat
123// 0, // pad
124};
125
126static u32 sh2_comm_faker(u32 a)
127{
128 static int f = 0;
129 if (a == 0x28 && !p32x_csum_faked) {
130 p32x_csum_faked = 1;
131 return *(unsigned short *)(Pico.rom + 0x18e);
132 }
133 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
134 f = 0;
135 return comm_fakevals[f++];
136}
137#endif
138
139// DMAC handling
140static struct {
141 unsigned int sar0, dar0, tcr0; // src addr, dst addr, transfer count
142 unsigned int chcr0; // chan ctl
143 unsigned int sar1, dar1, tcr1; // same for chan 1
144 unsigned int chcr1;
145 int pad[4];
146 unsigned int dmaor;
147} * dmac0;
148
149static void dma_68k2sh2_do(void)
150{
151 unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
152 int i;
153
154 if (dmac0->tcr0 != *dreqlen)
155 elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen);
156
157 // HACK: assume bus is busy and SH2 is halted
158 // XXX: use different mechanism for this, not poll det
159 Pico32x.emu_flags |= P32XF_MSH2POLL; // id ? P32XF_SSH2POLL : P32XF_MSH2POLL;
160
161 for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) {
162 elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen);
163 p32x_sh2_write16(dmac0->dar0, Pico32x.dmac_fifo[i], &msh2);
164 dmac0->dar0 += 2;
165 dmac0->tcr0--;
166 (*dreqlen)--;
167 }
168
169 Pico32x.dmac_ptr = 0; // HACK
170 Pico32x.regs[6 / 2] &= ~P32XS_FULL;
171 if (*dreqlen == 0)
172 Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
173 if (dmac0->tcr0 == 0) {
174 dmac0->chcr0 |= 2; // DMA has ended normally
175 p32x_poll_undetect(&sh2_poll[0], 0);
176 }
177}
178
179// ------------------------------------------------------------------
180// 68k regs
181
182static u32 p32x_reg_read16(u32 a)
183{
184 a &= 0x3e;
185
186#if 0
187 if ((a & 0x30) == 0x20)
188 return sh2_comm_faker(a);
189#else
190 if ((a & 0x30) == 0x20) {
191 static u32 dr2 = 0;
192 unsigned int cycles = SekCyclesDoneT();
193 int comreg = 1 << (a & 0x0f) / 2;
194
195 // evil X-Men proto polls in a dbra loop and expects it to expire..
196 if (SekDar(2) != dr2)
197 m68k_poll.cnt = 0;
198 dr2 = SekDar(2);
199
200 if (cycles - msh2.m68krcycles_done > 500)
201 p32x_sync_sh2s(cycles);
202 if (Pico32x.comm_dirty_sh2 & comreg)
203 Pico32x.comm_dirty_sh2 &= ~comreg;
204 else if (p32x_poll_detect(&m68k_poll, a, cycles, 0)) {
205 SekSetStop(1);
206 SekEndTimeslice(16);
207 }
208 dr2 = SekDar(2);
209 goto out;
210 }
211#endif
212
213 if (a == 2) { // INTM, INTS
214 unsigned int cycles = SekCyclesDoneT();
215 if (cycles - msh2.m68krcycles_done > 64)
216 p32x_sync_sh2s(cycles);
217 return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
218 }
219
220 if ((a & 0x30) == 0x30)
221 return p32x_pwm_read16(a);
222
223out:
224 return Pico32x.regs[a / 2];
225}
226
227static void p32x_reg_write8(u32 a, u32 d)
228{
229 u16 *r = Pico32x.regs;
230 a &= 0x3f;
231
232 // for things like bset on comm port
233 m68k_poll.cnt = 0;
234
235 switch (a) {
236 case 0: // adapter ctl
237 r[0] = (r[0] & ~P32XS_FM) | ((d << 8) & P32XS_FM);
238 return;
239 case 1: // adapter ctl, RES bit writeable
240 if ((d ^ r[0]) & d & P32XS_nRES)
241 p32x_reset_sh2s();
242 r[0] = (r[0] & ~P32XS_nRES) | (d & P32XS_nRES);
243 return;
244 case 3: // irq ctl
245 if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
246 p32x_sync_sh2s(SekCyclesDoneT());
247 Pico32x.sh2irqi[0] |= P32XI_CMD;
248 p32x_update_irls(0);
249 }
250 if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
251 p32x_sync_sh2s(SekCyclesDoneT());
252 Pico32x.sh2irqi[1] |= P32XI_CMD;
253 p32x_update_irls(0);
254 }
255 return;
256 case 5: // bank
257 d &= 7;
258 if (r[4 / 2] != d) {
259 r[4 / 2] = d;
260 bank_switch(d);
261 }
262 return;
263 case 7: // DREQ ctl
264 r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV));
265 return;
266 case 0x1b: // TV
267 r[0x1a / 2] = d;
268 return;
269 }
270
271 if ((a & 0x30) == 0x20) {
272 u8 *r8 = (u8 *)r;
273 int cycles = SekCyclesDoneT();
274 int comreg;
275
276 if (r8[a ^ 1] == d)
277 return;
278
279 comreg = 1 << (a & 0x0f) / 2;
280 if (Pico32x.comm_dirty_68k & comreg)
281 p32x_sync_sh2s(cycles);
282
283 r8[a ^ 1] = d;
284 p32x_poll_undetect(&sh2_poll[0], 0);
285 p32x_poll_undetect(&sh2_poll[1], 0);
286 Pico32x.comm_dirty_68k |= comreg;
287
288 if (cycles - (int)msh2.m68krcycles_done > 120)
289 p32x_sync_sh2s(cycles);
290 return;
291 }
292}
293
294static void p32x_reg_write16(u32 a, u32 d)
295{
296 u16 *r = Pico32x.regs;
297 a &= 0x3e;
298
299 // for things like bset on comm port
300 m68k_poll.cnt = 0;
301
302 switch (a) {
303 case 0x00: // adapter ctl
304 if ((d ^ r[0]) & d & P32XS_nRES)
305 p32x_reset_sh2s();
306 r[0] = (r[0] & ~(P32XS_FM|P32XS_nRES)) | (d & (P32XS_FM|P32XS_nRES));
307 return;
308 case 0x10: // DREQ len
309 r[a / 2] = d & ~3;
310 return;
311 case 0x12: // FIFO reg
312 if (!(r[6 / 2] & P32XS_68S)) {
313 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
314 return;
315 }
316 if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) {
317 Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d;
318 if ((Pico32x.dmac_ptr & 3) == 0 && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1))
319 dma_68k2sh2_do();
320 if (Pico32x.dmac_ptr == DMAC_FIFO_LEN)
321 r[6 / 2] |= P32XS_FULL;
322 }
323 break;
324 }
325
326 // DREQ src, dst
327 if ((a & 0x38) == 0x08) {
328 r[a / 2] = d;
329 return;
330 }
331 // comm port
332 else if ((a & 0x30) == 0x20) {
333 int cycles = SekCyclesDoneT();
334 int comreg;
335
336 if (r[a / 2] == d)
337 return;
338
339 comreg = 1 << (a & 0x0f) / 2;
340 if (Pico32x.comm_dirty_68k & comreg)
341 p32x_sync_sh2s(cycles);
342
343 r[a / 2] = d;
344 p32x_poll_undetect(&sh2_poll[0], 0);
345 p32x_poll_undetect(&sh2_poll[1], 0);
346 Pico32x.comm_dirty_68k |= comreg;
347
348 if (cycles - (int)msh2.m68krcycles_done > 120)
349 p32x_sync_sh2s(cycles);
350 return;
351 }
352 // PWM
353 else if ((a & 0x30) == 0x30) {
354 p32x_pwm_write16(a, d);
355 return;
356 }
357
358 p32x_reg_write8(a + 1, d);
359}
360
361// ------------------------------------------------------------------
362// VDP regs
363static u32 p32x_vdp_read16(u32 a)
364{
365 a &= 0x0e;
366
367 return Pico32x.vdp_regs[a / 2];
368}
369
370static void p32x_vdp_write8(u32 a, u32 d)
371{
372 u16 *r = Pico32x.vdp_regs;
373 a &= 0x0f;
374
375 // for FEN checks between writes
376 sh2_poll[0].cnt = 0;
377
378 // TODO: verify what's writeable
379 switch (a) {
380 case 0x01:
381 // priority inversion is handled in palette
382 if ((r[0] ^ d) & P32XV_PRI)
383 Pico32x.dirty_pal = 1;
384 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
385 break;
386 case 0x03: // shift (for pp mode)
387 r[2 / 2] = d & 1;
388 break;
389 case 0x05: // fill len
390 r[4 / 2] = d & 0xff;
391 break;
392 case 0x0b:
393 d &= 1;
394 Pico32x.pending_fb = d;
395 // if we are blanking and FS bit is changing
396 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
397 r[0x0a/2] ^= P32XV_FS;
398 Pico32xSwapDRAM(d ^ 1);
399 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
400 }
401 break;
402 }
403}
404
405static void p32x_vdp_write16(u32 a, u32 d, u32 cycles)
406{
407 a &= 0x0e;
408 if (a == 6) { // fill start
409 Pico32x.vdp_regs[6 / 2] = d;
410 return;
411 }
412 if (a == 8) { // fill data
413 u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
414 int len = Pico32x.vdp_regs[4 / 2] + 1;
415 int len1 = len;
416 a = Pico32x.vdp_regs[6 / 2];
417 while (len1--) {
418 dram[a] = d;
419 a = (a & 0xff00) | ((a + 1) & 0xff);
420 }
421 Pico32x.vdp_regs[0x06 / 2] = a;
422 Pico32x.vdp_regs[0x08 / 2] = d;
423 if (cycles > 0) {
424 Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
425 p32x_event_schedule(P32X_EVENT_FILLEND, cycles, len);
426 }
427 return;
428 }
429
430 p32x_vdp_write8(a | 1, d);
431}
432
433// ------------------------------------------------------------------
434// SH2 regs
435
436static u32 p32x_sh2reg_read16(u32 a, int cpuid)
437{
438 u16 *r = Pico32x.regs;
439 a &= 0xfe; // ?
440
441 switch (a) {
442 case 0x00: // adapter/irq ctl
443 return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
444 case 0x04: // H count (often as comm too)
445 if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
446 ash2_end_run(8);
447 return Pico32x.sh2_regs[4 / 2];
448 case 0x10: // DREQ len
449 return r[a / 2];
450 }
451
452 // DREQ src, dst
453 if ((a & 0x38) == 0x08)
454 return r[a / 2];
455 // comm port
456 if ((a & 0x30) == 0x20) {
457 int comreg = 1 << (a & 0x0f) / 2;
458 if (Pico32x.comm_dirty_68k & comreg)
459 Pico32x.comm_dirty_68k &= ~comreg;
460 else if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
461 ash2_end_run(8);
462 return r[a / 2];
463 }
464 if ((a & 0x30) == 0x30) {
465 sh2_poll[cpuid].cnt = 0;
466 return p32x_pwm_read16(a);
467 }
468
469 return 0;
470}
471
472static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
473{
474 a &= 0xff;
475 switch (a) {
476 case 0: // FM
477 Pico32x.regs[0] &= ~P32XS_FM;
478 Pico32x.regs[0] |= (d << 8) & P32XS_FM;
479 return;
480 case 1: //
481 Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
482 Pico32x.sh2_regs[0] &= ~0x80;
483 Pico32x.sh2_regs[0] |= d & 0x80;
484 if (d & 1)
485 p32x_pwm_schedule(sh2s[cpuid].m68krcycles_done); // XXX: timing?
486 p32x_update_irls(1);
487 return;
488 case 5: // H count
489 Pico32x.sh2_regs[4 / 2] = d & 0xff;
490 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
491 return;
492 }
493
494 if ((a & 0x30) == 0x20) {
495 u8 *r8 = (u8 *)Pico32x.regs;
496 int comreg;
497 if (r8[a ^ 1] == d)
498 return;
499
500 r8[a ^ 1] = d;
501 if (p32x_poll_undetect(&m68k_poll, 0))
502 SekSetStop(0);
503 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
504 comreg = 1 << (a & 0x0f) / 2;
505 Pico32x.comm_dirty_sh2 |= comreg;
506 return;
507 }
508}
509
510static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
511{
512 a &= 0xfe;
513
514 // comm
515 if ((a & 0x30) == 0x20) {
516 int comreg;
517 if (Pico32x.regs[a / 2] == d)
518 return;
519
520 Pico32x.regs[a / 2] = d;
521 if (p32x_poll_undetect(&m68k_poll, 0))
522 SekSetStop(0);
523 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
524 comreg = 1 << (a & 0x0f) / 2;
525 Pico32x.comm_dirty_sh2 |= comreg;
526 return;
527 }
528 // PWM
529 else if ((a & 0x30) == 0x30) {
530 p32x_pwm_write16(a, d);
531 return;
532 }
533
534 switch (a) {
535 case 0: // FM
536 Pico32x.regs[0] &= ~P32XS_FM;
537 Pico32x.regs[0] |= d & P32XS_FM;
538 break;
539 case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
540 case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls;
541 case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls;
542 case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
543 case 0x1c:
544 Pico32x.sh2irqs &= ~P32XI_PWM;
545 if (!(Pico32x.emu_flags & P32XF_PWM_PEND))
546 p32x_pwm_schedule(sh2s[cpuid].m68krcycles_done); // timing?
547 goto irls;
548 }
549
550 p32x_sh2reg_write8(a | 1, d, cpuid);
551 return;
552
553irls:
554 p32x_update_irls(1);
555}
556
557// ------------------------------------------------------------------
558// SH2 internal peripherals
559// we keep them in little endian format
560static u32 sh2_peripheral_read8(u32 a, int id)
561{
562 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
563 u32 d;
564
565 a &= 0x1ff;
566 d = PREG8(r, a);
567
568 elprintf(EL_32X, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
569 return d;
570}
571
572static u32 sh2_peripheral_read16(u32 a, int id)
573{
574 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
575 u32 d;
576
577 a &= 0x1ff;
578 d = r[(a / 2) ^ 1];
579
580 elprintf(EL_32X, "%csh2 peri r16 [%08x] %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
581 return d;
582}
583
584static u32 sh2_peripheral_read32(u32 a, int id)
585{
586 u32 d;
587 a &= 0x1fc;
588 d = Pico32xMem->sh2_peri_regs[id][a / 4];
589
590 elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
591 return d;
592}
593
594static int REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, int id)
595{
596 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
597 elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
598
599 a &= 0x1ff;
600 PREG8(r, a) = d;
601
602 // X-men SCI hack
603 if ((a == 2 && (d & 0x20)) || // transmiter enabled
604 (a == 4 && !(d & 0x80))) { // valid data in TDR
605 void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1];
606 if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
607 int level = PREG8(oregs, 0x60) >> 4;
608 int vector = PREG8(oregs, 0x63) & 0x7f;
609 elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
610 sh2_internal_irq(&sh2s[id ^ 1], level, vector);
611 return 1;
612 }
613 }
614 return 0;
615}
616
617static int REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, int id)
618{
619 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
620 elprintf(EL_32X, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
621
622 a &= 0x1ff;
623
624 // evil WDT
625 if (a == 0x80) {
626 if ((d & 0xff00) == 0xa500) { // WTCSR
627 PREG8(r, 0x80) = d;
628 p32x_timers_recalc();
629 }
630 if ((d & 0xff00) == 0x5a00) // WTCNT
631 PREG8(r, 0x81) = d;
632 return 0;
633 }
634
635 r[(a / 2) ^ 1] = d;
636 return 0;
637}
638
639static void sh2_peripheral_write32(u32 a, u32 d, int id)
640{
641 u32 *r = Pico32xMem->sh2_peri_regs[id];
642 elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
643
644 a &= 0x1fc;
645 r[a / 4] = d;
646
647 switch (a) {
648 // division unit (TODO: verify):
649 case 0x104: // DVDNT: divident L, starts divide
650 elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]);
651 if (r[0x100 / 4]) {
652 signed int divisor = r[0x100 / 4];
653 r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
654 r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor;
655 }
656 else
657 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
658 break;
659 case 0x114:
660 elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x",
661 id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id));
662 if (r[0x100 / 4]) {
663 signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
664 signed int divisor = r[0x100 / 4];
665 // XXX: undocumented mirroring to 0x118,0x11c?
666 r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
667 divident /= divisor;
668 r[0x11c / 4] = r[0x114 / 4] = divident;
669 divident >>= 31;
670 if ((unsigned long long)divident + 1 > 1) {
671 //elprintf(EL_32X, "%csh2 divide overflow! @%08x", id ? 's' : 'm', sh2_pc(id));
672 r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
673 }
674 }
675 else
676 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
677 break;
678 }
679
680 if ((a == 0x1b0 || a == 0x18c) && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) {
681 elprintf(EL_32X, "sh2 DMA %08x -> %08x, cnt %d, chcr %04x @%06x",
682 dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id));
683 dmac0->tcr0 &= 0xffffff;
684
685 // HACK: assume 68k starts writing soon and end the timeslice
686 ash2_end_run(16);
687
688 // DREQ is only sent after first 4 words are written.
689 // we do multiple of 4 words to avoid messing up alignment
690 if (dmac0->sar0 == 0x20004012 && Pico32x.dmac_ptr && (Pico32x.dmac_ptr & 3) == 0) {
691 elprintf(EL_32X, "68k -> sh2 DMA");
692 dma_68k2sh2_do();
693 }
694 }
695}
696
697// ------------------------------------------------------------------
698// 32x handlers
699
700// after ADEN
701static u32 PicoRead8_32x_on(u32 a)
702{
703 u32 d = 0;
704 if ((a & 0xffc0) == 0x5100) { // a15100
705 d = p32x_reg_read16(a);
706 goto out_16to8;
707 }
708
709 if ((a & 0xfc00) != 0x5000)
710 return PicoRead8_io(a);
711
712 if ((a & 0xfff0) == 0x5180) { // a15180
713 d = p32x_vdp_read16(a);
714 goto out_16to8;
715 }
716
717 if ((a & 0xfe00) == 0x5200) { // a15200
718 d = Pico32xMem->pal[(a & 0x1ff) / 2];
719 goto out_16to8;
720 }
721
722 if ((a & 0xfffc) == 0x30ec) { // a130ec
723 d = str_mars[a & 3];
724 goto out;
725 }
726
727 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
728 return d;
729
730out_16to8:
731 if (a & 1)
732 d &= 0xff;
733 else
734 d >>= 8;
735
736out:
737 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
738 return d;
739}
740
741static u32 PicoRead16_32x_on(u32 a)
742{
743 u32 d = 0;
744 if ((a & 0xffc0) == 0x5100) { // a15100
745 d = p32x_reg_read16(a);
746 goto out;
747 }
748
749 if ((a & 0xfc00) != 0x5000)
750 return PicoRead16_io(a);
751
752 if ((a & 0xfff0) == 0x5180) { // a15180
753 d = p32x_vdp_read16(a);
754 goto out;
755 }
756
757 if ((a & 0xfe00) == 0x5200) { // a15200
758 d = Pico32xMem->pal[(a & 0x1ff) / 2];
759 goto out;
760 }
761
762 if ((a & 0xfffc) == 0x30ec) { // a130ec
763 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
764 goto out;
765 }
766
767 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
768 return d;
769
770out:
771 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
772 return d;
773}
774
775static void PicoWrite8_32x_on(u32 a, u32 d)
776{
777 if ((a & 0xfc00) == 0x5000)
778 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
779
780 if ((a & 0xffc0) == 0x5100) { // a15100
781 p32x_reg_write8(a, d);
782 return;
783 }
784
785 if ((a & 0xfc00) != 0x5000) {
786 PicoWrite8_io(a, d);
787 return;
788 }
789
790 if ((a & 0xfff0) == 0x5180) { // a15180
791 p32x_vdp_write8(a, d);
792 return;
793 }
794
795 // TODO: verify
796 if ((a & 0xfe00) == 0x5200) { // a15200
797 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
798 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
799 Pico32x.dirty_pal = 1;
800 return;
801 }
802
803 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
804}
805
806static void PicoWrite16_32x_on(u32 a, u32 d)
807{
808 if ((a & 0xfc00) == 0x5000)
809 elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
810
811 if ((a & 0xffc0) == 0x5100) { // a15100
812 p32x_reg_write16(a, d);
813 return;
814 }
815
816 if ((a & 0xfc00) != 0x5000) {
817 PicoWrite16_io(a, d);
818 return;
819 }
820
821 if ((a & 0xfff0) == 0x5180) { // a15180
822 p32x_vdp_write16(a, d, 0); // FIXME?
823 return;
824 }
825
826 if ((a & 0xfe00) == 0x5200) { // a15200
827 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
828 Pico32x.dirty_pal = 1;
829 return;
830 }
831
832 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
833}
834
835// before ADEN
836u32 PicoRead8_32x(u32 a)
837{
838 u32 d = 0;
839 if ((a & 0xffc0) == 0x5100) { // a15100
840 // regs are always readable
841 d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
842 goto out;
843 }
844
845 if ((a & 0xfffc) == 0x30ec) { // a130ec
846 d = str_mars[a & 3];
847 goto out;
848 }
849
850 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
851 return d;
852
853out:
854 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
855 return d;
856}
857
858u32 PicoRead16_32x(u32 a)
859{
860 u32 d = 0;
861 if ((a & 0xffc0) == 0x5100) { // a15100
862 d = Pico32x.regs[(a & 0x3f) / 2];
863 goto out;
864 }
865
866 if ((a & 0xfffc) == 0x30ec) { // a130ec
867 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
868 goto out;
869 }
870
871 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
872 return d;
873
874out:
875 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
876 return d;
877}
878
879void PicoWrite8_32x(u32 a, u32 d)
880{
881 if ((a & 0xffc0) == 0x5100) { // a15100
882 u16 *r = Pico32x.regs;
883
884 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
885 a &= 0x3f;
886 if (a == 1) {
887 if ((d ^ r[0]) & d & P32XS_ADEN) {
888 Pico32xStartup();
889 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
890 r[0] |= P32XS_ADEN;
891 p32x_reg_write8(a, d); // forward for reset processing
892 }
893 return;
894 }
895
896 // allow only COMM for now
897 if ((a & 0x30) == 0x20) {
898 u8 *r8 = (u8 *)r;
899 r8[a ^ 1] = d;
900 }
901 return;
902 }
903
904 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
905}
906
907void PicoWrite16_32x(u32 a, u32 d)
908{
909 if ((a & 0xffc0) == 0x5100) { // a15100
910 u16 *r = Pico32x.regs;
911
912 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
913 a &= 0x3e;
914 if (a == 0) {
915 if ((d ^ r[0]) & d & P32XS_ADEN) {
916 Pico32xStartup();
917 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
918 r[0] |= P32XS_ADEN;
919 p32x_reg_write16(a, d); // forward for reset processing
920 }
921 return;
922 }
923
924 // allow only COMM for now
925 if ((a & 0x30) == 0x20)
926 r[a / 2] = d;
927 return;
928 }
929
930 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
931}
932
933// -----------------------------------------------------------------
934
935// hint vector is writeable
936static void PicoWrite8_hint(u32 a, u32 d)
937{
938 if ((a & 0xfffc) == 0x0070) {
939 Pico32xMem->m68k_rom[a ^ 1] = d;
940 return;
941 }
942
943 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
944}
945
946static void PicoWrite16_hint(u32 a, u32 d)
947{
948 if ((a & 0xfffc) == 0x0070) {
949 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
950 return;
951 }
952
953 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
954}
955
956static void bank_switch(int b)
957{
958 unsigned int rs, bank;
959
960 bank = b << 20;
961 if (bank >= Pico.romsize) {
962 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
963 return;
964 }
965
966 // 32X ROM (unbanked, XXX: consider mirroring?)
967 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
968 rs -= bank;
969 if (rs > 0x100000)
970 rs = 0x100000;
971 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
972 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
973
974 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
975
976#ifdef EMU_F68K
977 // setup FAME fetchmap
978 for (rs = 0x90; rs < 0xa0; rs++)
979 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom + bank - 0x900000;
980#endif
981}
982
983// -----------------------------------------------------------------
984// SH2
985// -----------------------------------------------------------------
986
987// read8
988static u32 sh2_read8_unmapped(u32 a, int id)
989{
990 elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x",
991 id ? 's' : 'm', a, 0, sh2_pc(id));
992 return 0;
993}
994
995static u32 sh2_read8_cs0(u32 a, int id)
996{
997 u32 d = 0;
998
999 // 0x3ff00 is veridied
1000 if ((a & 0x3ff00) == 0x4000) {
1001 d = p32x_sh2reg_read16(a, id);
1002 goto out_16to8;
1003 }
1004
1005 if ((a & 0x3ff00) == 0x4100) {
1006 d = p32x_vdp_read16(a);
1007 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
1008 ash2_end_run(8);
1009 goto out_16to8;
1010 }
1011
1012 // TODO: mirroring?
1013 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
1014 return Pico32xMem->sh2_rom_m[a ^ 1];
1015 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
1016 return Pico32xMem->sh2_rom_s[a ^ 1];
1017
1018 if ((a & 0x3fe00) == 0x4200) {
1019 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1020 goto out_16to8;
1021 }
1022
1023 return sh2_read8_unmapped(a, id);
1024
1025out_16to8:
1026 if (a & 1)
1027 d &= 0xff;
1028 else
1029 d >>= 8;
1030
1031 elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x",
1032 id ? 's' : 'm', a, d, sh2_pc(id));
1033 return d;
1034}
1035
1036static u32 sh2_read8_da(u32 a, int id)
1037{
1038 return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
1039}
1040
1041// read16
1042static u32 sh2_read16_unmapped(u32 a, int id)
1043{
1044 elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x",
1045 id ? 's' : 'm', a, 0, sh2_pc(id));
1046 return 0;
1047}
1048
1049static u32 sh2_read16_cs0(u32 a, int id)
1050{
1051 u32 d = 0;
1052
1053 if ((a & 0x3ff00) == 0x4000) {
1054 d = p32x_sh2reg_read16(a, id);
1055 if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
1056 return d;
1057 goto out;
1058 }
1059
1060 if ((a & 0x3ff00) == 0x4100) {
1061 d = p32x_vdp_read16(a);
1062 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
1063 ash2_end_run(8);
1064 goto out;
1065 }
1066
1067 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
1068 return *(u16 *)(Pico32xMem->sh2_rom_m + a);
1069 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
1070 return *(u16 *)(Pico32xMem->sh2_rom_s + a);
1071
1072 if ((a & 0x3fe00) == 0x4200) {
1073 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1074 goto out;
1075 }
1076
1077 return sh2_read16_unmapped(a, id);
1078
1079out:
1080 elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x",
1081 id ? 's' : 'm', a, d, sh2_pc(id));
1082 return d;
1083}
1084
1085static u32 sh2_read16_da(u32 a, int id)
1086{
1087 return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
1088}
1089
1090static int REGPARM(3) sh2_write_ignore(u32 a, u32 d, int id)
1091{
1092 return 0;
1093}
1094
1095// write8
1096static int REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, int id)
1097{
1098 elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
1099 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
1100 return 0;
1101}
1102
1103static int REGPARM(3) sh2_write8_cs0(u32 a, u32 d, int id)
1104{
1105 elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
1106 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
1107
1108 if ((a & 0x3ff00) == 0x4100) {
1109 p32x_vdp_write8(a, d);
1110 return 0;
1111 }
1112
1113 if ((a & 0x3ff00) == 0x4000) {
1114 p32x_sh2reg_write8(a, d, id);
1115 return 1;
1116 }
1117
1118 return sh2_write8_unmapped(a, d, id);
1119}
1120
1121/* quirk: in both normal and overwrite areas only nonzero values go through */
1122#define sh2_write8_dramN(n) \
1123 if ((d & 0xff) != 0) { \
1124 u8 *dram = (u8 *)Pico32xMem->dram[n]; \
1125 dram[(a & 0x1ffff) ^ 1] = d; \
1126 } \
1127 return 0;
1128
1129static int REGPARM(3) sh2_write8_dram0(u32 a, u32 d, int id)
1130{
1131 sh2_write8_dramN(0);
1132}
1133
1134static int REGPARM(3) sh2_write8_dram1(u32 a, u32 d, int id)
1135{
1136 sh2_write8_dramN(1);
1137}
1138
1139static int REGPARM(3) sh2_write8_sdram(u32 a, u32 d, int id)
1140{
1141 u32 a1 = a & 0x3ffff;
1142#ifdef DRC_SH2
1143 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1144 if (t)
1145 sh2_drc_wcheck_ram(a, t, id);
1146#endif
1147 Pico32xMem->sdram[a1 ^ 1] = d;
1148 return 0;
1149}
1150
1151static int REGPARM(3) sh2_write8_da(u32 a, u32 d, int id)
1152{
1153 u32 a1 = a & 0xfff;
1154#ifdef DRC_SH2
1155 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1156 if (t)
1157 sh2_drc_wcheck_da(a, t, id);
1158#endif
1159 Pico32xMem->data_array[id][a1 ^ 1] = d;
1160 return 0;
1161}
1162
1163// write16
1164static int REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, int id)
1165{
1166 elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
1167 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1168 return 0;
1169}
1170
1171static int REGPARM(3) sh2_write16_cs0(u32 a, u32 d, int id)
1172{
1173 if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
1174 elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
1175 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1176
1177 if ((a & 0x3ff00) == 0x4100) {
1178 sh2_poll[id].cnt = 0; // for poll before VDP accesses
1179 p32x_vdp_write16(a, d, sh2s[id].m68krcycles_done);
1180 return 0;
1181 }
1182
1183 if ((a & 0x3fe00) == 0x4200) {
1184 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
1185 Pico32x.dirty_pal = 1;
1186 return 0;
1187 }
1188
1189 if ((a & 0x3ff00) == 0x4000) {
1190 p32x_sh2reg_write16(a, d, id);
1191 return 1;
1192 }
1193
1194 return sh2_write16_unmapped(a, d, id);
1195}
1196
1197#define sh2_write16_dramN(n) \
1198 u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
1199 if (!(a & 0x20000)) { \
1200 *pd = d; \
1201 return 0; \
1202 } \
1203 /* overwrite */ \
1204 if (!(d & 0xff00)) d |= *pd & 0xff00; \
1205 if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
1206 *pd = d; \
1207 return 0
1208
1209static int REGPARM(3) sh2_write16_dram0(u32 a, u32 d, int id)
1210{
1211 sh2_write16_dramN(0);
1212}
1213
1214static int REGPARM(3) sh2_write16_dram1(u32 a, u32 d, int id)
1215{
1216 sh2_write16_dramN(1);
1217}
1218
1219static int REGPARM(3) sh2_write16_sdram(u32 a, u32 d, int id)
1220{
1221 u32 a1 = a & 0x3ffff;
1222#ifdef DRC_SH2
1223 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1224 if (t)
1225 sh2_drc_wcheck_ram(a, t, id);
1226#endif
1227 ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
1228 return 0;
1229}
1230
1231static int REGPARM(3) sh2_write16_da(u32 a, u32 d, int id)
1232{
1233 u32 a1 = a & 0xfff;
1234#ifdef DRC_SH2
1235 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1236 if (t)
1237 sh2_drc_wcheck_da(a, t, id);
1238#endif
1239 ((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d;
1240 return 0;
1241}
1242
1243
1244typedef struct {
1245 uptr addr; // stores (membase >> 1) or ((handler >> 1) | (1<<31))
1246 u32 mask;
1247} sh2_memmap;
1248
1249typedef u32 (sh2_read_handler)(u32 a, int id);
1250typedef int REGPARM(3) (sh2_write_handler)(u32 a, u32 d, int id);
1251
1252#define SH2MAP_ADDR2OFFS_R(a) \
1253 ((((a) >> 25) & 3) | (((a) >> 27) & 0x1c))
1254
1255#define SH2MAP_ADDR2OFFS_W(a) \
1256 ((u32)(a) >> SH2_WRITE_SHIFT)
1257
1258u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
1259{
1260 const sh2_memmap *sh2_map = sh2->read8_map;
1261 uptr p;
1262
1263 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1264 p = sh2_map->addr;
1265 if (map_flag_set(p))
1266 return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
1267 else
1268 return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
1269}
1270
1271u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
1272{
1273 const sh2_memmap *sh2_map = sh2->read16_map;
1274 uptr p;
1275
1276 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1277 p = sh2_map->addr;
1278 if (map_flag_set(p))
1279 return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
1280 else
1281 return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1282}
1283
1284u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
1285{
1286 const sh2_memmap *sh2_map = sh2->read16_map;
1287 sh2_read_handler *handler;
1288 u32 offs;
1289 uptr p;
1290
1291 offs = SH2MAP_ADDR2OFFS_R(a);
1292 sh2_map += offs;
1293 p = sh2_map->addr;
1294 if (!map_flag_set(p)) {
1295 // XXX: maybe 32bit access instead with ror?
1296 u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1297 return (pd[0] << 16) | pd[1];
1298 }
1299
1300 if (offs == 0x1f)
1301 return sh2_peripheral_read32(a, sh2->is_slave);
1302
1303 handler = (sh2_read_handler *)(p << 1);
1304 return (handler(a, sh2->is_slave) << 16) | handler(a + 2, sh2->is_slave);
1305}
1306
1307// return nonzero if write potentially causes an interrupt (used by drc)
1308int REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
1309{
1310 const void **sh2_wmap = sh2->write8_tab;
1311 sh2_write_handler *wh;
1312
1313 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1314 return wh(a, d, sh2->is_slave);
1315}
1316
1317int REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
1318{
1319 const void **sh2_wmap = sh2->write16_tab;
1320 sh2_write_handler *wh;
1321
1322 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1323 return wh(a, d, sh2->is_slave);
1324}
1325
1326int REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
1327{
1328 const void **sh2_wmap = sh2->write16_tab;
1329 sh2_write_handler *handler;
1330 u32 offs;
1331
1332 offs = SH2MAP_ADDR2OFFS_W(a);
1333
1334 if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
1335 sh2_peripheral_write32(a, d, sh2->is_slave);
1336 return 0;
1337 }
1338
1339 handler = sh2_wmap[offs];
1340 handler(a, d >> 16, sh2->is_slave);
1341 handler(a + 2, d, sh2->is_slave);
1342 return 0;
1343}
1344
1345// -----------------------------------------------------------------
1346
1347static const u16 msh2_code[] = {
1348 // trap instructions
1349 0xaffe, // bra <self>
1350 0x0009, // nop
1351 // have to wait a bit until m68k initial program finishes clearing stuff
1352 // to avoid races with game SH2 code, like in Tempo
1353 0xd004, // mov.l @(_m_ok,pc), r0
1354 0xd105, // mov.l @(_cnt,pc), r1
1355 0xd205, // mov.l @(_start,pc), r2
1356 0x71ff, // add #-1, r1
1357 0x4115, // cmp/pl r1
1358 0x89fc, // bt -2
1359 0xc208, // mov.l r0, @(h'20,gbr)
1360 0x6822, // mov.l @r2, r8
1361 0x482b, // jmp @r8
1362 0x0009, // nop
1363 ('M'<<8)|'_', ('O'<<8)|'K',
1364 0x0001, 0x0000,
1365 0x2200, 0x03e0 // master start pointer in ROM
1366};
1367
1368static const u16 ssh2_code[] = {
1369 0xaffe, // bra <self>
1370 0x0009, // nop
1371 // code to wait for master, in case authentic master BIOS is used
1372 0xd104, // mov.l @(_m_ok,pc), r1
1373 0xd206, // mov.l @(_start,pc), r2
1374 0xc608, // mov.l @(h'20,gbr), r0
1375 0x3100, // cmp/eq r0, r1
1376 0x8bfc, // bf #-2
1377 0xd003, // mov.l @(_s_ok,pc), r0
1378 0xc209, // mov.l r0, @(h'24,gbr)
1379 0x6822, // mov.l @r2, r8
1380 0x482b, // jmp @r8
1381 0x0009, // nop
1382 ('M'<<8)|'_', ('O'<<8)|'K',
1383 ('S'<<8)|'_', ('O'<<8)|'K',
1384 0x2200, 0x03e4 // slave start pointer in ROM
1385};
1386
1387#define HWSWAP(x) (((x) << 16) | ((x) >> 16))
1388static void get_bios(void)
1389{
1390 u16 *ps;
1391 u32 *pl;
1392 int i;
1393
1394 // M68K ROM
1395 if (p32x_bios_g != NULL) {
1396 elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
1397 Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom));
1398 }
1399 else {
1400 // generate 68k ROM
1401 ps = (u16 *)Pico32xMem->m68k_rom;
1402 pl = (u32 *)ps;
1403 for (i = 1; i < 0xc0/4; i++)
1404 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
1405
1406 // fill with nops
1407 for (i = 0xc0/2; i < 0x100/2; i++)
1408 ps[i] = 0x4e71;
1409
1410#if 0
1411 ps[0xc0/2] = 0x46fc;
1412 ps[0xc2/2] = 0x2700; // move #0x2700,sr
1413 ps[0xfe/2] = 0x60fe; // jump to self
1414#else
1415 ps[0xfe/2] = 0x4e75; // rts
1416#endif
1417 }
1418 // fill remaining m68k_rom page with game ROM
1419 memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom),
1420 Pico.rom + sizeof(Pico32xMem->m68k_rom),
1421 sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom));
1422
1423 // MSH2
1424 if (p32x_bios_m != NULL) {
1425 elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS");
1426 Byteswap(Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m));
1427 }
1428 else {
1429 pl = (u32 *)Pico32xMem->sh2_rom_m;
1430
1431 // fill exception vector table to our trap address
1432 for (i = 0; i < 128; i++)
1433 pl[i] = HWSWAP(0x200);
1434
1435 // startup code
1436 memcpy(Pico32xMem->sh2_rom_m + 0x200, msh2_code, sizeof(msh2_code));
1437
1438 // reset SP
1439 pl[1] = pl[3] = HWSWAP(0x6040000);
1440 // start
1441 pl[0] = pl[2] = HWSWAP(0x204);
1442 }
1443
1444 // SSH2
1445 if (p32x_bios_s != NULL) {
1446 elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS");
1447 Byteswap(Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s));
1448 }
1449 else {
1450 pl = (u32 *)Pico32xMem->sh2_rom_s;
1451
1452 // fill exception vector table to our trap address
1453 for (i = 0; i < 128; i++)
1454 pl[i] = HWSWAP(0x200);
1455
1456 // startup code
1457 memcpy(Pico32xMem->sh2_rom_s + 0x200, ssh2_code, sizeof(ssh2_code));
1458
1459 // reset SP
1460 pl[1] = pl[3] = HWSWAP(0x603f800);
1461 // start
1462 pl[0] = pl[2] = HWSWAP(0x204);
1463 }
1464}
1465
1466#define MAP_MEMORY(m) ((uptr)(m) >> 1)
1467#define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
1468
1469static sh2_memmap sh2_read8_map[0x20], sh2_read16_map[0x20];
1470// for writes we are using handlers only
1471static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
1472
1473void Pico32xSwapDRAM(int b)
1474{
1475 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1476 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1477 cpu68k_map_set(m68k_write8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1478 cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1479
1480 // SH2
1481 sh2_read8_map[2].addr = sh2_read8_map[6].addr =
1482 sh2_read16_map[2].addr = sh2_read16_map[6].addr = MAP_MEMORY(Pico32xMem->dram[b]);
1483
1484 sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
1485 sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
1486}
1487
1488void PicoMemSetup32x(void)
1489{
1490 unsigned int rs;
1491 int i;
1492
1493 Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0);
1494 if (Pico32xMem == NULL) {
1495 elprintf(EL_STATUS, "OOM");
1496 return;
1497 }
1498
1499 dmac0 = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
1500
1501 get_bios();
1502
1503 // cartridge area becomes unmapped
1504 // XXX: we take the easy way and don't unmap ROM,
1505 // so that we can avoid handling the RV bit.
1506 // m68k_map_unmap(0x000000, 0x3fffff);
1507
1508 // MD ROM area
1509 rs = sizeof(Pico32xMem->m68k_rom_bank);
1510 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1511 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1512 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
1513 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
1514
1515 // 32X ROM (unbanked, XXX: consider mirroring?)
1516 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1517 if (rs > 0x80000)
1518 rs = 0x80000;
1519 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1520 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1521#ifdef EMU_F68K
1522 // setup FAME fetchmap
1523 PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
1524 for (rs = 0x88; rs < 0x90; rs++)
1525 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000;
1526#endif
1527
1528 // 32X ROM (banked)
1529 bank_switch(0);
1530
1531 // SYS regs
1532 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
1533 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
1534 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
1535 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
1536
1537 // SH2 maps: A31,A30,A29,CS1,CS0
1538 // all unmapped by default
1539 for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
1540 sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
1541 sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
1542 }
1543
1544 for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
1545 sh2_write8_map[i] = sh2_write8_unmapped;
1546 sh2_write16_map[i] = sh2_write16_unmapped;
1547 }
1548
1549 // "purge area"
1550 for (i = 0x40; i <= 0x5f; i++) {
1551 sh2_write8_map[i >> 1] =
1552 sh2_write16_map[i >> 1] = sh2_write_ignore;
1553 }
1554
1555 // CS0
1556 sh2_read8_map[0].addr = sh2_read8_map[4].addr = MAP_HANDLER(sh2_read8_cs0);
1557 sh2_read16_map[0].addr = sh2_read16_map[4].addr = MAP_HANDLER(sh2_read16_cs0);
1558 sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
1559 sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
1560 // CS1 - ROM
1561 sh2_read8_map[1].addr = sh2_read8_map[5].addr =
1562 sh2_read16_map[1].addr = sh2_read16_map[5].addr = MAP_MEMORY(Pico.rom);
1563 sh2_read8_map[1].mask = sh2_read8_map[5].mask =
1564 sh2_read16_map[1].mask = sh2_read16_map[5].mask = 0x3fffff; // FIXME
1565 // CS2 - DRAM - done by Pico32xSwapDRAM()
1566 sh2_read8_map[2].mask = sh2_read8_map[6].mask =
1567 sh2_read16_map[2].mask = sh2_read16_map[6].mask = 0x01ffff;
1568 // CS3 - SDRAM
1569 sh2_read8_map[3].addr = sh2_read8_map[7].addr =
1570 sh2_read16_map[3].addr = sh2_read16_map[7].addr = MAP_MEMORY(Pico32xMem->sdram);
1571 sh2_write8_map[0x06/2] = sh2_write8_map[0x26/2] = sh2_write8_sdram;
1572 sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
1573 sh2_read8_map[3].mask = sh2_read8_map[7].mask =
1574 sh2_read16_map[3].mask = sh2_read16_map[7].mask = 0x03ffff;
1575 // SH2 data array
1576 sh2_read8_map[0x18].addr = MAP_HANDLER(sh2_read8_da);
1577 sh2_read16_map[0x18].addr = MAP_HANDLER(sh2_read16_da);
1578 sh2_write8_map[0xc0/2] = sh2_write8_da;
1579 sh2_write16_map[0xc0/2] = sh2_write16_da;
1580 // SH2 IO
1581 sh2_read8_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read8);
1582 sh2_read16_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read16);
1583 sh2_write8_map[0xff/2] = sh2_peripheral_write8;
1584 sh2_write16_map[0xff/2] = sh2_peripheral_write16;
1585
1586 // map DRAM area, both 68k and SH2
1587 Pico32xSwapDRAM(1);
1588
1589 msh2.read8_map = ssh2.read8_map = sh2_read8_map;
1590 msh2.read16_map = ssh2.read16_map = sh2_read16_map;
1591 msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
1592 msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
1593
1594 // setup poll detector
1595 m68k_poll.flag = P32XF_68KPOLL;
1596 m68k_poll.cyc_max = 64;
1597 sh2_poll[0].flag = P32XF_MSH2POLL;
1598 sh2_poll[0].cyc_max = 21;
1599 sh2_poll[1].flag = P32XF_SSH2POLL;
1600 sh2_poll[1].cyc_max = 16;
1601
1602#ifdef DRC_SH2
1603 sh2_drc_mem_setup(&msh2);
1604 sh2_drc_mem_setup(&ssh2);
1605#endif
1606}
1607
1608void Pico32xStateLoaded(void)
1609{
1610 bank_switch(Pico32x.regs[4 / 2]);
1611 Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
1612 p32x_poll_event(3, 0);
1613 Pico32x.dirty_pal = 1;
1614 memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
1615 p32x_timers_recalc();
1616#ifdef DRC_SH2
1617 sh2_drc_flush_all();
1618#endif
1619}
1620
1621// vim:shiftwidth=2:ts=2:expandtab
fast MegaDrive/MegaCD/32X emulator