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1// Pico Library - Internal Header File\r
2\r
3// (c) Copyright 2004 Dave, All rights reserved.\r
4// (c) Copyright 2006-2008 Grazvydas "notaz" Ignotas, all rights reserved.\r
5// Free for non-commercial use.\r
6\r
7// For commercial use, separate licencing terms must be obtained.\r
8\r
9#ifndef PICO_INTERNAL_INCLUDED\r
10#define PICO_INTERNAL_INCLUDED\r
11\r
12#include <stdio.h>\r
13#include <stdlib.h>\r
14#include <string.h>\r
15#include "pico.h"\r
16#include "carthw/carthw.h"\r
17\r
18//\r
19#define USE_POLL_DETECT\r
20\r
21#ifndef PICO_INTERNAL\r
22#define PICO_INTERNAL\r
23#endif\r
24#ifndef PICO_INTERNAL_ASM\r
25#define PICO_INTERNAL_ASM\r
26#endif\r
27\r
28// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
29\r
30#ifdef __cplusplus\r
31extern "C" {\r
32#endif\r
33\r
34\r
35// ----------------------- 68000 CPU -----------------------\r
36#ifdef EMU_C68K\r
37#include "../cpu/Cyclone/Cyclone.h"\r
38extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
39#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
40#define SekCyclesLeft \\r
41 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
42#define SekCyclesLeftS68k \\r
43 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
44#define SekSetCyclesLeftNoMCD(c) PicoCpuCM68k.cycles=c\r
45#define SekSetCyclesLeft(c) { \\r
46 if ((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
47}\r
48#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
49#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
50#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
51#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
52#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
53#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
54\r
55#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
56\r
57#ifdef EMU_M68K\r
58#define EMU_CORE_DEBUG\r
59#endif\r
60#endif\r
61\r
62#ifdef EMU_F68K\r
63#include "../cpu/fame/fame.h"\r
64extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
65#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
66#define SekCyclesLeft \\r
67 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
68#define SekCyclesLeftS68k \\r
69 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
70#define SekSetCyclesLeftNoMCD(c) PicoCpuFM68k.io_cycle_counter=c\r
71#define SekSetCyclesLeft(c) { \\r
72 if ((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) SekCycleCnt=SekCycleAim-(c); else SekSetCyclesLeftNoMCD(c); \\r
73}\r
74#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
75#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
76#define SekSetStop(x) { \\r
77 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
78 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
79}\r
80#define SekSetStopS68k(x) { \\r
81 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
82 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
83}\r
84#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
85#define SekShouldInterrupt fm68k_would_interrupt()\r
86\r
87#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
88\r
89#ifdef EMU_M68K\r
90#define EMU_CORE_DEBUG\r
91#endif\r
92#endif\r
93\r
94#ifdef EMU_M68K\r
95#include "../cpu/musashi/m68kcpu.h"\r
96extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
97#ifndef SekCyclesLeft\r
98#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
99#define SekCyclesLeft \\r
100 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
101#define SekCyclesLeftS68k \\r
102 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
103#define SekSetCyclesLeftNoMCD(c) SET_CYCLES(c)\r
104#define SekSetCyclesLeft(c) { \\r
105 if ((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) SekCycleCnt=SekCycleAim-(c); else SET_CYCLES(c); \\r
106}\r
107#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
108#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
109#define SekSetStop(x) { \\r
110 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
111 else PicoCpuMM68k.stopped=0; \\r
112}\r
113#define SekSetStopS68k(x) { \\r
114 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
115 else PicoCpuMS68k.stopped=0; \\r
116}\r
117#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
118#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)\r
119\r
120#define SekInterrupt(irq) { \\r
121 void *oldcontext = m68ki_cpu_p; \\r
122 m68k_set_context(&PicoCpuMM68k); \\r
123 m68k_set_irq(irq); \\r
124 m68k_set_context(oldcontext); \\r
125}\r
126\r
127#endif\r
128#endif\r
129\r
130extern int SekCycleCnt; // cycles done in this frame\r
131extern int SekCycleAim; // cycle aim\r
132extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
133\r
134#define SekCyclesReset() { \\r
135 SekCycleCntT+=SekCycleAim; \\r
136 SekCycleCnt-=SekCycleAim; \\r
137 SekCycleAim=0; \\r
138}\r
139#define SekCyclesBurn(c) SekCycleCnt+=c\r
140#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r
141#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
142\r
143#define SekEndRun(after) { \\r
144 SekCycleCnt -= SekCyclesLeft - after; \\r
145 if(SekCycleCnt < 0) SekCycleCnt = 0; \\r
146 SekSetCyclesLeft(after); \\r
147}\r
148\r
149extern int SekCycleCntS68k;\r
150extern int SekCycleAimS68k;\r
151\r
152#define SekCyclesResetS68k() { \\r
153 SekCycleCntS68k-=SekCycleAimS68k; \\r
154 SekCycleAimS68k=0; \\r
155}\r
156#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
157\r
158#ifdef EMU_CORE_DEBUG\r
159extern int dbg_irq_level;\r
160#undef SekSetCyclesLeftNoMCD\r
161#undef SekSetCyclesLeft\r
162#undef SekCyclesBurn\r
163#undef SekEndRun\r
164#undef SekInterrupt\r
165#define SekSetCyclesLeftNoMCD(c)\r
166#define SekSetCyclesLeft(c)\r
167#define SekCyclesBurn(c) c\r
168#define SekEndRun(c)\r
169#define SekInterrupt(irq) dbg_irq_level=irq\r
170#endif\r
171\r
172// ----------------------- Z80 CPU -----------------------\r
173\r
174#if defined(_USE_MZ80)\r
175#include "../cpu/mz80/mz80.h"\r
176\r
177#define z80_run(cycles) { mz80GetElapsedTicks(1); mz80_run(cycles) }\r
178#define z80_run_nr(cycles) mz80_run(cycles)\r
179#define z80_int() mz80int(0)\r
180\r
181#elif defined(_USE_DRZ80)\r
182#include "../cpu/DrZ80/drz80.h"\r
183\r
184extern struct DrZ80 drZ80;\r
185\r
186#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
187#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
188#define z80_int() drZ80.Z80_IRQ = 1\r
189\r
190#define z80_cyclesLeft drZ80.cycles\r
191\r
192#elif defined(_USE_CZ80)\r
193#include "../cpu/cz80/cz80.h"\r
194\r
195#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
196#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
197#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
198\r
199#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
200\r
201#else\r
202\r
203#define z80_run(cycles) (cycles)\r
204#define z80_run_nr(cycles)\r
205#define z80_int()\r
206\r
207#endif\r
208\r
209extern int z80stopCycle; /* in 68k cycles */\r
210extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
211extern int z80_cycle_aim;\r
212extern int z80_scanline;\r
213extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
214\r
215#define z80_resetCycles() \\r
216 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
217\r
218#define z80_cyclesDone() \\r
219 (z80_cycle_aim - z80_cyclesLeft)\r
220\r
221#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
222\r
223// ---------------------------------------------------------\r
224\r
225// main oscillator clock which controls timing\r
226#define OSC_NTSC 53693100\r
227// seems to be accurate, see scans from http://www.hot.ee/tmeeco/\r
228#define OSC_PAL 53203424\r
229\r
230struct PicoVideo\r
231{\r
232 unsigned char reg[0x20];\r
233 unsigned int command; // 32-bit Command\r
234 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
235 unsigned char type; // Command type (v/c/vsram read/write)\r
236 unsigned short addr; // Read/Write address\r
237 int status; // Status bits\r
238 unsigned char pending_ints; // pending interrupts: ??VH????\r
239 signed char lwrite_cnt; // VDP write count during active display line\r
240 unsigned short v_counter; // V-counter\r
241 unsigned char pad[0x10];\r
242};\r
243\r
244struct PicoMisc\r
245{\r
246 unsigned char rotate;\r
247 unsigned char z80Run;\r
248 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
249 unsigned short scanline; // 04 0 to 261||311\r
250 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
251 unsigned char hardware; // 07 Hardware value for country\r
252 unsigned char pal; // 08 1=PAL 0=NTSC\r
253 unsigned char sram_reg; // SRAM mode register. bit0: allow read? bit1: deny write? bit2: EEPROM? bit4: detected? (header or by access)\r
254 unsigned short z80_bank68k; // 0a\r
255 unsigned short z80_lastaddr; // this is for Z80 faking\r
256 unsigned char z80_fakeval;\r
257 unsigned char z80_reset; // z80 reset held\r
258 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
259 unsigned short eeprom_addr; // EEPROM address register\r
260 unsigned char eeprom_cycle; // EEPROM SRAM cycle number\r
261 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
262 unsigned char prot_bytes[2]; // simple protection faking\r
263 unsigned short dma_xfers; // 18\r
264 unsigned char pad[2];\r
265 unsigned int frame_count; // 1c for movies and idle det\r
266};\r
267\r
268// some assembly stuff depend on these, do not touch!\r
269struct Pico\r
270{\r
271 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
272 unsigned short vram[0x8000]; // 0x10000\r
273 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
274 unsigned char ioports[0x10];\r
275 unsigned int pad[0x3c]; // unused\r
276 unsigned short cram[0x40]; // 0x22100\r
277 unsigned short vsram[0x40]; // 0x22180\r
278\r
279 unsigned char *rom; // 0x22200\r
280 unsigned int romsize; // 0x22204\r
281\r
282 struct PicoMisc m;\r
283 struct PicoVideo video;\r
284};\r
285\r
286// sram\r
287struct PicoSRAM\r
288{\r
289 unsigned char *data; // actual data\r
290 unsigned int start; // start address in 68k address space\r
291 unsigned int end;\r
292 unsigned char unused1; // 0c: unused\r
293 unsigned char unused2;\r
294 unsigned char changed;\r
295 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: device with 2 addr words (X24C02+), 3: dev with 3 addr words\r
296 unsigned char eeprom_abits; // eeprom access must be odd addr for: bit0 ~ cl, bit1 ~ out\r
297 unsigned char eeprom_bit_cl; // bit number for cl\r
298 unsigned char eeprom_bit_in; // bit number for in\r
299 unsigned char eeprom_bit_out; // bit number for out\r
300};\r
301\r
302// MCD\r
303#include "cd/cd_sys.h"\r
304#include "cd/LC89510.h"\r
305#include "cd/gfx_cd.h"\r
306\r
307struct mcd_pcm\r
308{\r
309 unsigned char control; // reg7\r
310 unsigned char enabled; // reg8\r
311 unsigned char cur_ch;\r
312 unsigned char bank;\r
313 int pad1;\r
314\r
315 struct pcm_chan // 08, size 0x10\r
316 {\r
317 unsigned char regs[8];\r
318 unsigned int addr; // .08: played sample address\r
319 int pad;\r
320 } ch[8];\r
321};\r
322\r
323struct mcd_misc\r
324{\r
325 unsigned short hint_vector;\r
326 unsigned char busreq;\r
327 unsigned char s68k_pend_ints;\r
328 unsigned int state_flags; // 04: emu state: reset_pending, dmna_pending\r
329 unsigned int counter75hz;\r
330 unsigned int pad0;\r
331 int timer_int3; // 10\r
332 unsigned int timer_stopwatch;\r
333 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
334 unsigned char pad2;\r
335 unsigned short pad3;\r
336 int pad[9];\r
337};\r
338\r
339typedef struct\r
340{\r
341 unsigned char bios[0x20000]; // 000000: 128K\r
342 union { // 020000: 512K\r
343 unsigned char prg_ram[0x80000];\r
344 unsigned char prg_ram_b[4][0x20000];\r
345 };\r
346 union { // 0a0000: 256K\r
347 struct {\r
348 unsigned char word_ram2M[0x40000];\r
349 unsigned char unused0[0x20000];\r
350 };\r
351 struct {\r
352 unsigned char unused1[0x20000];\r
353 unsigned char word_ram1M[2][0x20000];\r
354 };\r
355 };\r
356 union { // 100000: 64K\r
357 unsigned char pcm_ram[0x10000];\r
358 unsigned char pcm_ram_b[0x10][0x1000];\r
359 };\r
360 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
361 unsigned char bram[0x2000]; // 110200: 8K\r
362 struct mcd_misc m; // 112200: misc\r
363 struct mcd_pcm pcm; // 112240:\r
364 _scd_toc TOC; // not to be saved\r
365 CDD cdd;\r
366 CDC cdc;\r
367 _scd scd;\r
368 Rot_Comp rot_comp;\r
369} mcd_state;\r
370\r
371#define Pico_mcd ((mcd_state *)Pico.rom)\r
372\r
373\r
374// Area.c\r
375PICO_INTERNAL void PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
376PICO_INTERNAL void PicoAreaUnpackCpu(unsigned char *cpu, int is_sub);\r
377extern void (*PicoLoadStateHook)(void);\r
378\r
379// cd/Area.c\r
380PICO_INTERNAL int PicoCdSaveState(void *file);\r
381PICO_INTERNAL int PicoCdLoadState(void *file);\r
382\r
383typedef struct {\r
384 int chunk;\r
385 int size;\r
386 void *ptr;\r
387} carthw_state_chunk;\r
388extern carthw_state_chunk *carthw_chunks;\r
389#define CHUNK_CARTHW 64\r
390\r
391// area.c\r
392typedef size_t (arearw)(void *p, size_t _size, size_t _n, void *file);\r
393typedef size_t (areaeof)(void *file);\r
394typedef int (areaseek)(void *file, long offset, int whence);\r
395typedef int (areaclose)(void *file);\r
396extern arearw *areaRead; // external read and write function pointers for\r
397extern arearw *areaWrite; // gzip save state ability\r
398extern areaeof *areaEof;\r
399extern areaseek *areaSeek;\r
400extern areaclose *areaClose;\r
401\r
402// Cart.c\r
403extern void (*PicoCartUnloadHook)(void);\r
404\r
405// Debug.c\r
406int CM_compareRun(int cyc, int is_sub);\r
407\r
408// Draw.c\r
409PICO_INTERNAL void PicoFrameStart(void);\r
410void PicoDrawSync(int to, int blank_last_line);\r
411extern int DrawScanline;\r
412#define MAX_LINE_SPRITES 29\r
413extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
414\r
415// Draw2.c\r
416PICO_INTERNAL void PicoFrameFull();\r
417\r
418// Memory.c\r
419PICO_INTERNAL void PicoInitPc(unsigned int pc);\r
420PICO_INTERNAL unsigned int PicoCheckPc(unsigned int pc);\r
421PICO_INTERNAL_ASM unsigned int PicoRead32(unsigned int a);\r
422PICO_INTERNAL void PicoMemSetup(void);\r
423PICO_INTERNAL_ASM void PicoMemReset(void);\r
424PICO_INTERNAL void PicoMemResetHooks(void);\r
425PICO_INTERNAL int PadRead(int i);\r
426PICO_INTERNAL unsigned char z80_read(unsigned short a);\r
427#ifndef _USE_CZ80\r
428PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a);\r
429PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a);\r
430PICO_INTERNAL unsigned short z80_read16(unsigned short a);\r
431#else\r
432PICO_INTERNAL_ASM void z80_write(unsigned int a, unsigned char data);\r
433#endif\r
434PICO_INTERNAL int ym2612_write_local(unsigned int a, unsigned int d, int is_from_z80);\r
435extern unsigned int (*PicoRead16Hook)(unsigned int a, int realsize);\r
436extern void (*PicoWrite8Hook) (unsigned int a,unsigned int d,int realsize);\r
437extern void (*PicoWrite16Hook)(unsigned int a,unsigned int d,int realsize);\r
438\r
439// cd/Memory.c\r
440PICO_INTERNAL void PicoMemSetupCD(void);\r
441PICO_INTERNAL_ASM void PicoMemResetCD(int r3);\r
442PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
443\r
444// Pico/Memory.c\r
445PICO_INTERNAL void PicoMemSetupPico(void);\r
446PICO_INTERNAL unsigned int ym2612_read_local_68k(void);\r
447\r
448// Pico.c\r
449extern struct Pico Pico;\r
450extern struct PicoSRAM SRam;\r
451extern int PicoPadInt[2];\r
452extern int emustatus;\r
453extern void (*PicoResetHook)(void);\r
454extern void (*PicoLineHook)(void);\r
455PICO_INTERNAL int CheckDMA(void);\r
456PICO_INTERNAL void PicoDetectRegion(void);\r
457PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r
458\r
459// cd/Pico.c\r
460PICO_INTERNAL void PicoInitMCD(void);\r
461PICO_INTERNAL void PicoExitMCD(void);\r
462PICO_INTERNAL void PicoPowerMCD(void);\r
463PICO_INTERNAL int PicoResetMCD(void);\r
464PICO_INTERNAL void PicoFrameMCD(void);\r
465\r
466// Pico/Pico.c\r
467PICO_INTERNAL void PicoInitPico(void);\r
468PICO_INTERNAL void PicoReratePico(void);\r
469\r
470// Pico/xpcm.c\r
471PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
472PICO_INTERNAL void PicoPicoPCMReset(void);\r
473PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
474\r
475// Sek.c\r
476PICO_INTERNAL void SekInit(void);\r
477PICO_INTERNAL int SekReset(void);\r
478PICO_INTERNAL void SekState(int *data);\r
479PICO_INTERNAL void SekSetRealTAS(int use_real);\r
480void SekStepM68k(void);\r
481void SekInitIdleDet(void);\r
482void SekFinishIdleDet(void);\r
483\r
484// cd/Sek.c\r
485PICO_INTERNAL void SekInitS68k(void);\r
486PICO_INTERNAL int SekResetS68k(void);\r
487PICO_INTERNAL int SekInterruptS68k(int irq);\r
488\r
489// sound/sound.c\r
490PICO_INTERNAL void cdda_start_play();\r
491extern short cdda_out_buffer[2*1152];\r
492extern int PsndLen_exc_cnt;\r
493extern int PsndLen_exc_add;\r
494extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
495extern int timer_b_next_oflow, timer_b_step;\r
496\r
497void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
498void ym2612_pack_state(void);\r
499void ym2612_unpack_state(void);\r
500\r
501#define TIMER_NO_OFLOW 0x70000000\r
502// tA = 72 * (1024 - NA) / M\r
503#define TIMER_A_TICK_ZCYCLES 17203\r
504// tB = 1152 * (256 - NA) / M\r
505#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
506\r
507#define timers_cycle() \\r
508 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
509 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
510 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
511 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
512 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
513\r
514#define timers_reset() \\r
515 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
516 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
517 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
518\r
519\r
520// VideoPort.c\r
521PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
522PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
523PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
524extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
525\r
526// Misc.c\r
527PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d);\r
528PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d);\r
529PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void);\r
530PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
531PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
532PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
533PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
534\r
535// cd/Misc.c\r
536PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
537PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
538\r
539// cd/buffering.c\r
540PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);\r
541\r
542// sound/sound.c\r
543PICO_INTERNAL void PsndReset(void);\r
544PICO_INTERNAL void PsndDoDAC(int line_to);\r
545PICO_INTERNAL void PsndClear(void);\r
546PICO_INTERNAL void PsndGetSamples(int y);\r
547// z80 functionality wrappers\r
548PICO_INTERNAL void z80_init(void);\r
549PICO_INTERNAL void z80_pack(unsigned char *data);\r
550PICO_INTERNAL void z80_unpack(unsigned char *data);\r
551PICO_INTERNAL void z80_reset(void);\r
552PICO_INTERNAL void z80_exit(void);\r
553extern int PsndDacLine;\r
554\r
555// emulation event logging\r
556#ifndef EL_LOGMASK\r
557#define EL_LOGMASK 0\r
558#endif\r
559\r
560#define EL_HVCNT 0x00000001 /* hv counter reads */\r
561#define EL_SR 0x00000002 /* SR reads */\r
562#define EL_INTS 0x00000004 /* ints and acks */\r
563#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
564#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
565#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
566#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
567#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
568#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
569#define EL_SRAMIO 0x00000200 /* sram i/o */\r
570#define EL_EEPROM 0x00000400 /* eeprom debug */\r
571#define EL_UIO 0x00000800 /* unmapped i/o */\r
572#define EL_IO 0x00001000 /* all i/o */\r
573#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
574#define EL_SVP 0x00004000 /* SVP stuff */\r
575#define EL_PICOHW 0x00008000 /* Pico stuff */\r
576#define EL_IDLE 0x00010000 /* idle loop det. */\r
577\r
578#define EL_STATUS 0x40000000 /* status messages */\r
579#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
580\r
581#if EL_LOGMASK\r
582extern void lprintf(const char *fmt, ...);\r
583#define elprintf(w,f,...) \\r
584{ \\r
585 if ((w) & EL_LOGMASK) \\r
586 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
587}\r
588#elif defined(_MSC_VER)\r
589#define elprintf\r
590#else\r
591#define elprintf(w,f,...)\r
592#endif\r
593\r
594#ifdef _MSC_VER\r
595#define cdprintf\r
596#else\r
597#define cdprintf(x...)\r
598#endif\r
599\r
600#ifdef __cplusplus\r
601} // End of extern "C"\r
602#endif\r
603\r
604#endif // PICO_INTERNAL_INCLUDED\r
605\r
fast MegaDrive/MegaCD/32X emulator