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add a hack for Decap Attack
[picodrive.git] / pico / pico_int.h
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1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
9\r
10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
12\r
13#include <stdio.h>\r
14#include <string.h>\r
15#include "pico_port.h"\r
16#include "pico.h"\r
17#include "carthw/carthw.h"\r
18\r
19//\r
20#define USE_POLL_DETECT\r
21\r
22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
28\r
29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
35\r
36// ----------------------- 68000 CPU -----------------------\r
37#ifdef EMU_C68K\r
38#include "../cpu/cyclone/Cyclone.h"\r
39extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
40#define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run\r
41#define SekCyclesLeftS68k PicoCpuCS68k.cycles\r
42#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
43#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
44#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
45#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r
46#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
47#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r
48#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
49#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
50#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
51#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
52#define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
53\r
54#define SekNotPolling PicoCpuCM68k.not_pol\r
55#define SekNotPollingS68k PicoCpuCS68k.not_pol\r
56\r
57#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
58#define SekIrqLevel PicoCpuCM68k.irq\r
59\r
60#endif\r
61\r
62#ifdef EMU_F68K\r
63#include "../cpu/fame/fame.h"\r
64extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
65#define SekCyclesLeft PicoCpuFM68k.io_cycle_counter\r
66#define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter\r
67#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
68#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
69#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
70#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r
71#define SekSr PicoCpuFM68k.sr\r
72#define SekSrS68k PicoCpuFS68k.sr\r
73#define SekSetStop(x) { \\r
74 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
75 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
76}\r
77#define SekSetStopS68k(x) { \\r
78 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
79 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
80}\r
81#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
82#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
83#define SekShouldInterrupt() fm68k_would_interrupt(&PicoCpuFM68k)\r
84\r
85#define SekNotPolling PicoCpuFM68k.not_polling\r
86#define SekNotPollingS68k PicoCpuFS68k.not_polling\r
87\r
88#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
89#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
90\r
91#endif\r
92\r
93#ifdef EMU_M68K\r
94#include "../cpu/musashi/m68kcpu.h"\r
95extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
96#ifndef SekCyclesLeft\r
97#define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles\r
98#define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles\r
99#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
100#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
101#define SekDar(x) PicoCpuMM68k.dar[x]\r
102#define SekDarS68k(x) PicoCpuMS68k.dar[x]\r
103#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
104#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r
105#define SekSetStop(x) { \\r
106 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
107 else PicoCpuMM68k.stopped=0; \\r
108}\r
109#define SekSetStopS68k(x) { \\r
110 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
111 else PicoCpuMS68k.stopped=0; \\r
112}\r
113#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
114#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
115#define SekShouldInterrupt() (CPU_INT_LEVEL > FLAG_INT_MASK)\r
116\r
117#define SekNotPolling PicoCpuMM68k.not_polling\r
118#define SekNotPollingS68k PicoCpuMS68k.not_polling\r
119\r
120// avoid m68k_set_irq() for delaying to work\r
121#define SekInterrupt(irq) PicoCpuMM68k.int_level = (irq) << 8\r
122#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
123\r
124#endif\r
125#endif // EMU_M68K\r
126\r
127// number of cycles done (can be checked anywhere)\r
128#define SekCyclesDone() (Pico.t.m68c_cnt - SekCyclesLeft)\r
129\r
130// burn cycles while not in SekRun() and while in\r
131#define SekCyclesBurn(c) Pico.t.m68c_cnt += c\r
132#define SekCyclesBurnRun(c) { \\r
133 SekCyclesLeft -= c; \\r
134}\r
135\r
136// note: sometimes may extend timeslice to delay an irq\r
137#define SekEndRun(after) { \\r
138 Pico.t.m68c_cnt -= SekCyclesLeft - (after); \\r
139 SekCyclesLeft = after; \\r
140}\r
141\r
142extern unsigned int SekCycleCntS68k;\r
143extern unsigned int SekCycleAimS68k;\r
144\r
145#define SekEndRunS68k(after) { \\r
146 if (SekCyclesLeftS68k > (after)) { \\r
147 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
148 SekCyclesLeftS68k = after; \\r
149 } \\r
150}\r
151\r
152#define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)\r
153\r
154// compare cycles, handling overflows\r
155// check if a > b\r
156#define CYCLES_GT(a, b) \\r
157 ((int)((a) - (b)) > 0)\r
158// check if a >= b\r
159#define CYCLES_GE(a, b) \\r
160 ((int)((a) - (b)) >= 0)\r
161\r
162// ----------------------- Z80 CPU -----------------------\r
163\r
164#if defined(_USE_DRZ80)\r
165#include "../cpu/DrZ80/drz80.h"\r
166\r
167extern struct DrZ80 drZ80;\r
168\r
169#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
170#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
171#define z80_int() drZ80.Z80_IRQ = 1\r
172#define z80_int_assert(a) drZ80.Z80_IRQ = (a)\r
173#define z80_nmi() drZ80.Z80IF |= 8\r
174\r
175#define z80_cyclesLeft drZ80.cycles\r
176#define z80_subCLeft(c) drZ80.cycles -= c\r
177#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
178\r
179#elif defined(_USE_CZ80)\r
180#include "../cpu/cz80/cz80.h"\r
181\r
182#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
183#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
184#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
185#define z80_int_assert(a) Cz80_Set_IRQ(&CZ80, 0, (a) ? ASSERT_LINE : CLEAR_LINE)\r
186#define z80_nmi() Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, 0)\r
187\r
188#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
189#define z80_subCLeft(c) CZ80.ICount -= c\r
190#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
191\r
192#else\r
193\r
194#define z80_run(cycles) (cycles)\r
195#define z80_run_nr(cycles)\r
196#define z80_int()\r
197#define z80_int_assert(a)\r
198#define z80_nmi()\r
199\r
200#endif\r
201\r
202#define Z80_STATE_SIZE 0x60\r
203\r
204#define z80_resetCycles() \\r
205 Pico.t.z80c_cnt = Pico.t.z80c_aim = Pico.t.z80_scanline = 0\r
206\r
207#define z80_cyclesDone() \\r
208 (Pico.t.z80c_aim - z80_cyclesLeft)\r
209\r
210#define cycles_68k_to_z80(x) ((x) * 3823 >> 13)\r
211\r
212// ----------------------- SH2 CPU -----------------------\r
213\r
214#include "cpu/sh2/sh2.h"\r
215\r
216extern SH2 sh2s[2];\r
217#define msh2 sh2s[0]\r
218#define ssh2 sh2s[1]\r
219\r
220#ifndef DRC_SH2\r
221# define sh2_end_run(sh2, after_) do { \\r
222 if ((sh2)->icount > (after_)) { \\r
223 (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
224 (sh2)->icount = after_; \\r
225 } \\r
226} while (0)\r
227# define sh2_cycles_left(sh2) (sh2)->icount\r
228# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
229# define sh2_pc(sh2) (sh2)->ppc\r
230#else\r
231# define sh2_end_run(sh2, after_) do { \\r
232 int left_ = (signed int)(sh2)->sr >> 12; \\r
233 if (left_ > (after_)) { \\r
234 (sh2)->cycles_timeslice -= left_ - (after_); \\r
235 (sh2)->sr &= 0xfff; \\r
236 (sh2)->sr |= (after_) << 12; \\r
237 } \\r
238} while (0)\r
239# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
240# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
241# define sh2_pc(sh2) (sh2)->pc\r
242#endif\r
243\r
244#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
245#define sh2_cycles_done_t(sh2) \\r
246 ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
247#define sh2_cycles_done_m68k(sh2) \\r
248 ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
249\r
250#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
251#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
252#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
253#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
254\r
255#define sh2_set_gbr(c, v) \\r
256 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
257#define sh2_set_vbr(c, v) \\r
258 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
259\r
260#define elprintf_sh2(sh2, w, f, ...) \\r
261 elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
262\r
263// ---------------------------------------------------------\r
264\r
265// main oscillator clock which controls timing\r
266#define OSC_NTSC 53693100\r
267#define OSC_PAL 53203424\r
268\r
269// PicoVideo.debug_p\r
270#define PVD_KILL_A (1 << 0)\r
271#define PVD_KILL_B (1 << 1)\r
272#define PVD_KILL_S_LO (1 << 2)\r
273#define PVD_KILL_S_HI (1 << 3)\r
274#define PVD_KILL_32X (1 << 4)\r
275#define PVD_FORCE_A (1 << 5)\r
276#define PVD_FORCE_B (1 << 6)\r
277#define PVD_FORCE_S (1 << 7)\r
278\r
279// PicoVideo.status, not part of real SR\r
280#define SR_PAL (1 << 0)\r
281#define SR_DMA (1 << 1)\r
282#define SR_HB (1 << 2)\r
283#define SR_VB (1 << 3)\r
284#define SR_ODD (1 << 4)\r
285#define SR_C (1 << 5)\r
286#define SR_SOVR (1 << 6)\r
287#define SR_F (1 << 7)\r
288#define SR_FULL (1 << 8)\r
289#define SR_EMPT (1 << 9)\r
290// not part of real SR\r
291#define PVS_ACTIVE (1 << 16)\r
292#define PVS_VB2 (1 << 17) // ignores forced blanking\r
293\r
294struct PicoVideo\r
295{\r
296 unsigned char reg[0x20];\r
297 unsigned int command; // 32-bit Command\r
298 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
299 unsigned char type; // Command type (v/c/vsram read/write)\r
300 unsigned short addr; // Read/Write address\r
301 unsigned int status; // Status bits (SR) and extra flags\r
302 unsigned char pending_ints; // pending interrupts: ??VH????\r
303 signed char lwrite_cnt; // VDP write count during active display line\r
304 unsigned short v_counter; // V-counter\r
305 unsigned short debug; // raw debug register\r
306 unsigned char debug_p; // ... parsed: PVD_*\r
307 unsigned char addr_u; // bit16 of .addr\r
308 unsigned char hint_cnt;\r
309 unsigned char pad[0x0b];\r
310};\r
311\r
312struct PicoMisc\r
313{\r
314 unsigned char rotate;\r
315 unsigned char z80Run;\r
316 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
317 unsigned short scanline; // 04 0 to 261||311\r
318 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
319 unsigned char hardware; // 07 Hardware value for country\r
320 unsigned char pal; // 08 1=PAL 0=NTSC\r
321 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
322 unsigned short z80_bank68k; // 0a\r
323 unsigned short pad0;\r
324 unsigned char ncart_in; // 0e !cart_in\r
325 unsigned char z80_reset; // 0f z80 reset held\r
326 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
327 unsigned short eeprom_addr; // EEPROM address register\r
328 unsigned char eeprom_cycle; // EEPROM cycle number\r
329 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
330 unsigned char eeprom_status;\r
331 unsigned char status; // rapid_ym2612, multi_ym_updates\r
332 unsigned short dma_xfers; // 18\r
333 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
334 unsigned int frame_count; // 1c for movies and idle det\r
335};\r
336\r
337struct PicoMS\r
338{\r
339 unsigned char carthw[0x10];\r
340 unsigned char io_ctl;\r
341 unsigned char nmi_state;\r
342 unsigned char pad[0x4e];\r
343};\r
344\r
345// emu state and data for the asm code\r
346struct PicoEState\r
347{\r
348 int DrawScanline;\r
349 int rendstatus;\r
350 void *DrawLineDest; // draw destination\r
351 unsigned char *HighCol;\r
352 int *HighPreSpr;\r
353 struct Pico *Pico;\r
354 void *PicoMem_vram;\r
355 void *PicoMem_cram;\r
356 unsigned int *PicoOpt;\r
357 unsigned char *Draw2FB;\r
358 unsigned short HighPal[0x100];\r
359};\r
360\r
361struct PicoMem\r
362{\r
363 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
364 union { // vram is byteswapped for easier reads when drawing\r
365 unsigned short vram[0x8000]; // 0x10000\r
366 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
367 };\r
368 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
369 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
370 unsigned short cram[0x40]; // 0x22010\r
371 unsigned char pad[0x70]; // 0x22050 DrawStripVSRam reads 0 from here\r
372 unsigned short vsram[0x40]; // 0x22100\r
373};\r
374\r
375// sram\r
376#define SRR_MAPPED (1 << 0)\r
377#define SRR_READONLY (1 << 1)\r
378\r
379#define SRF_ENABLED (1 << 0)\r
380#define SRF_EEPROM (1 << 1)\r
381\r
382struct PicoCartSave\r
383{\r
384 unsigned char *data; // actual data\r
385 unsigned int start; // start address in 68k address space\r
386 unsigned int end;\r
387 unsigned char flags; // 0c: SRF_*\r
388 unsigned char unused2;\r
389 unsigned char changed;\r
390 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
391 unsigned char unused3;\r
392 unsigned char eeprom_bit_cl; // bit number for cl\r
393 unsigned char eeprom_bit_in; // bit number for in\r
394 unsigned char eeprom_bit_out; // bit number for out\r
395 unsigned int size;\r
396};\r
397\r
398struct PicoTiming\r
399{\r
400 // while running, cnt represents target of current timeslice\r
401 // while not in SekRun(), it's actual cycles done\r
402 // (but always use SekCyclesDone() if you need current position)\r
403 // _cnt may change if timeslice is ended prematurely or extended,\r
404 // so we use _aim for the actual target\r
405 unsigned int m68c_cnt;\r
406 unsigned int m68c_aim;\r
407 unsigned int m68c_frame_start; // m68k cycles\r
408 unsigned int m68c_line_start;\r
409\r
410 unsigned int z80c_cnt; // z80 cycles done (this frame)\r
411 unsigned int z80c_aim;\r
412 int z80_scanline;\r
413\r
414 int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
415 int timer_b_next_oflow, timer_b_step;\r
416};\r
417\r
418struct PicoSound\r
419{\r
420 short len; // number of mono samples\r
421 short len_use; // adjusted\r
422 int len_e_add; // for non-int samples/frame\r
423 int len_e_cnt;\r
424 short dac_line;\r
425 short psg_line;\r
426};\r
427\r
428// run tools/mkoffsets pico/pico_int_o32.h if you change these\r
429// careful with savestate compat\r
430struct Pico\r
431{\r
432 struct PicoVideo video;\r
433 struct PicoMisc m;\r
434 struct PicoTiming t;\r
435 struct PicoCartSave sv;\r
436 struct PicoSound snd;\r
437 struct PicoEState est;\r
438 struct PicoMS ms;\r
439\r
440 unsigned char *rom;\r
441 unsigned int romsize;\r
442};\r
443\r
444// MCD\r
445#define PCM_MIXBUF_LEN ((12500000 / 384) / 50 + 1)\r
446\r
447struct mcd_pcm\r
448{\r
449 unsigned char control; // reg7\r
450 unsigned char enabled; // reg8\r
451 unsigned char cur_ch;\r
452 unsigned char bank;\r
453 unsigned int update_cycles;\r
454\r
455 struct pcm_chan // 08, size 0x10\r
456 {\r
457 unsigned char regs[8];\r
458 unsigned int addr; // .08: played sample address\r
459 int pad;\r
460 } ch[8];\r
461};\r
462\r
463#define PCD_ST_S68K_RST 1\r
464\r
465struct mcd_misc\r
466{\r
467 unsigned short hint_vector;\r
468 unsigned char busreq; // not s68k_regs[1]\r
469 unsigned char s68k_pend_ints;\r
470 unsigned int state_flags; // 04\r
471 unsigned int stopwatch_base_c;\r
472 unsigned short m68k_poll_a;\r
473 unsigned short m68k_poll_cnt;\r
474 unsigned short s68k_poll_a;\r
475 unsigned short s68k_poll_cnt;\r
476 unsigned int s68k_poll_clk;\r
477 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
478 unsigned char dmna_ret_2m;\r
479 unsigned char need_sync;\r
480 unsigned char pad3;\r
481 int pad4[9];\r
482};\r
483\r
484typedef struct\r
485{\r
486 unsigned char bios[0x20000]; // 000000: 128K\r
487 union { // 020000: 512K\r
488 unsigned char prg_ram[0x80000];\r
489 unsigned char prg_ram_b[4][0x20000];\r
490 };\r
491 union { // 0a0000: 256K\r
492 struct {\r
493 unsigned char word_ram2M[0x40000];\r
494 unsigned char unused0[0x20000];\r
495 };\r
496 struct {\r
497 unsigned char unused1[0x20000];\r
498 unsigned char word_ram1M[2][0x20000];\r
499 };\r
500 };\r
501 union { // 100000: 64K\r
502 unsigned char pcm_ram[0x10000];\r
503 unsigned char pcm_ram_b[0x10][0x1000];\r
504 };\r
505 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
506 unsigned char bram[0x2000]; // 110200: 8K\r
507 struct mcd_misc m; // 112200: misc\r
508 struct mcd_pcm pcm; // 112240:\r
509 void *cdda_stream;\r
510 int cdda_type;\r
511 int pcm_mixbuf[PCM_MIXBUF_LEN * 2];\r
512 int pcm_mixpos;\r
513 char pcm_mixbuf_dirty;\r
514 char pcm_regs_dirty;\r
515} mcd_state;\r
516\r
517// XXX: this will need to be reworked for cart+cd support.\r
518#define Pico_mcd ((mcd_state *)Pico.rom)\r
519\r
520// 32X\r
521#define P32XS_FM (1<<15)\r
522#define P32XS_nCART (1<< 8)\r
523#define P32XS_REN (1<< 7)\r
524#define P32XS_nRES (1<< 1)\r
525#define P32XS_ADEN (1<< 0)\r
526#define P32XS2_ADEN (1<< 9)\r
527#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
528#define P32XS_68S (1<< 2)\r
529#define P32XS_DMA (1<< 1)\r
530#define P32XS_RV (1<< 0)\r
531\r
532#define P32XV_nPAL (1<<15) // VDP\r
533#define P32XV_PRI (1<< 7)\r
534#define P32XV_Mx (3<< 0) // display mode mask\r
535\r
536#define P32XV_SFT (1<< 0)\r
537\r
538#define P32XV_VBLK (1<<15)\r
539#define P32XV_HBLK (1<<14)\r
540#define P32XV_PEN (1<<13)\r
541#define P32XV_nFEN (1<< 1)\r
542#define P32XV_FS (1<< 0)\r
543\r
544#define P32XP_RTP (1<<7) // PWM control\r
545#define P32XP_FULL (1<<15) // PWM pulse\r
546#define P32XP_EMPTY (1<<14)\r
547\r
548#define P32XF_68KCPOLL (1 << 0)\r
549#define P32XF_68KVPOLL (1 << 1)\r
550#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
551#define P32XF_DRC_ROM_C (1 << 8) // cached code from ROM\r
552\r
553#define P32XI_VRES (1 << 14/2) // IRL/2\r
554#define P32XI_VINT (1 << 12/2)\r
555#define P32XI_HINT (1 << 10/2)\r
556#define P32XI_CMD (1 << 8/2)\r
557#define P32XI_PWM (1 << 6/2)\r
558\r
559// peripheral reg access\r
560#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
561\r
562#define DMAC_FIFO_LEN (4*2)\r
563#define PWM_BUFF_LEN 1024 // in one channel samples\r
564\r
565#define SH2_DRCBLK_RAM_SHIFT 1\r
566#define SH2_DRCBLK_DA_SHIFT 1\r
567\r
568#define SH2_READ_SHIFT 25\r
569#define SH2_WRITE_SHIFT 25\r
570\r
571struct Pico32x\r
572{\r
573 unsigned short regs[0x20];\r
574 unsigned short vdp_regs[0x10]; // 0x40\r
575 unsigned short sh2_regs[3]; // 0x60\r
576 unsigned char pending_fb;\r
577 unsigned char dirty_pal;\r
578 unsigned int emu_flags;\r
579 unsigned char sh2irq_mask[2];\r
580 unsigned char sh2irqi[2]; // individual\r
581 unsigned int sh2irqs; // common irqs\r
582 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
583 unsigned int pad[4];\r
584 unsigned int dmac0_fifo_ptr;\r
585 unsigned short vdp_fbcr_fake;\r
586 unsigned short pad2;\r
587 unsigned char comm_dirty;\r
588 unsigned char pad3; // was comm_dirty_sh2\r
589 unsigned char pwm_irq_cnt;\r
590 unsigned char pad1;\r
591 unsigned short pwm_p[2]; // pwm pos in fifo\r
592 unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
593 unsigned int reserved[6];\r
594};\r
595\r
596struct Pico32xMem\r
597{\r
598 unsigned char sdram[0x40000];\r
599#ifdef DRC_SH2\r
600 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
601#endif\r
602 unsigned short dram[2][0x20000/2]; // AKA fb\r
603 union {\r
604 unsigned char m68k_rom[0x100];\r
605 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
606 };\r
607#ifdef DRC_SH2\r
608 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
609#endif\r
610 union {\r
611 unsigned char b[0x800];\r
612 unsigned short w[0x800/2];\r
613 } sh2_rom_m;\r
614 union {\r
615 unsigned char b[0x400];\r
616 unsigned short w[0x400/2];\r
617 } sh2_rom_s;\r
618 unsigned short pal[0x100];\r
619 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
620 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
621 signed short pwm_current[2]; // current converted samples\r
622 unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries\r
623};\r
624\r
625// area.c\r
626extern void (*PicoLoadStateHook)(void);\r
627\r
628typedef struct {\r
629 int chunk;\r
630 int size;\r
631 void *ptr;\r
632} carthw_state_chunk;\r
633extern carthw_state_chunk *carthw_chunks;\r
634#define CHUNK_CARTHW 64\r
635\r
636// cart.c\r
637extern int PicoCartResize(int newsize);\r
638extern void Byteswap(void *dst, const void *src, int len);\r
639extern void (*PicoCartMemSetup)(void);\r
640extern void (*PicoCartUnloadHook)(void);\r
641\r
642// debug.c\r
643int CM_compareRun(int cyc, int is_sub);\r
644\r
645// draw.c\r
646void PicoDrawInit(void);\r
647PICO_INTERNAL void PicoFrameStart(void);\r
648void PicoDrawSync(int to, int blank_last_line);\r
649void BackFill(int reg7, int sh, struct PicoEState *est);\r
650void FinalizeLine555(int sh, int line, struct PicoEState *est);\r
651extern int (*PicoScanBegin)(unsigned int num);\r
652extern int (*PicoScanEnd)(unsigned int num);\r
653#define MAX_LINE_SPRITES 29\r
654extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
655extern void *DrawLineDestBase;\r
656extern int DrawLineDestIncrement;\r
657\r
658// draw2.c\r
659void PicoDraw2Init(void);\r
660PICO_INTERNAL void PicoFrameFull();\r
661\r
662// mode4.c\r
663void PicoFrameStartMode4(void);\r
664void PicoLineMode4(int line);\r
665void PicoDoHighPal555M4(void);\r
666void PicoDrawSetOutputMode4(pdso_t which);\r
667\r
668// memory.c\r
669PICO_INTERNAL void PicoMemSetup(void);\r
670unsigned int PicoRead8_io(unsigned int a);\r
671unsigned int PicoRead16_io(unsigned int a);\r
672void PicoWrite8_io(unsigned int a, unsigned int d);\r
673void PicoWrite16_io(unsigned int a, unsigned int d);\r
674\r
675// pico/memory.c\r
676PICO_INTERNAL void PicoMemSetupPico(void);\r
677\r
678// cd/cdc.c\r
679void cdc_init(void);\r
680void cdc_reset(void);\r
681int cdc_context_save(unsigned char *state);\r
682int cdc_context_load(unsigned char *state);\r
683int cdc_context_load_old(unsigned char *state);\r
684void cdc_dma_update(void);\r
685int cdc_decoder_update(unsigned char header[4]);\r
686void cdc_reg_w(unsigned char data);\r
687unsigned char cdc_reg_r(void);\r
688unsigned short cdc_host_r(void);\r
689\r
690// cd/cdd.c\r
691void cdd_reset(void);\r
692int cdd_context_save(unsigned char *state);\r
693int cdd_context_load(unsigned char *state);\r
694int cdd_context_load_old(unsigned char *state);\r
695void cdd_read_data(unsigned char *dst);\r
696void cdd_read_audio(unsigned int samples);\r
697void cdd_update(void);\r
698void cdd_process(void);\r
699\r
700// cd/cd_image.c\r
701int load_cd_image(const char *cd_img_name, int *type);\r
702\r
703// cd/gfx.c\r
704void gfx_init(void);\r
705void gfx_start(unsigned int base);\r
706void gfx_update(unsigned int cycles);\r
707int gfx_context_save(unsigned char *state);\r
708int gfx_context_load(const unsigned char *state);\r
709\r
710// cd/gfx_dma.c\r
711void DmaSlowCell(unsigned int source, unsigned int a, int len, unsigned char inc);\r
712\r
713// cd/memory.c\r
714PICO_INTERNAL void PicoMemSetupCD(void);\r
715unsigned int PicoRead8_mcd_io(unsigned int a);\r
716unsigned int PicoRead16_mcd_io(unsigned int a);\r
717void PicoWrite8_mcd_io(unsigned int a, unsigned int d);\r
718void PicoWrite16_mcd_io(unsigned int a, unsigned int d);\r
719void pcd_state_loaded_mem(void);\r
720\r
721// pico.c\r
722extern struct Pico Pico;\r
723extern struct PicoMem PicoMem;\r
724extern void (*PicoResetHook)(void);\r
725extern void (*PicoLineHook)(void);\r
726PICO_INTERNAL int CheckDMA(void);\r
727PICO_INTERNAL void PicoDetectRegion(void);\r
728PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);\r
729\r
730// cd/mcd.c\r
731#define PCDS_IEN1 (1<<1)\r
732#define PCDS_IEN2 (1<<2)\r
733#define PCDS_IEN3 (1<<3)\r
734#define PCDS_IEN4 (1<<4)\r
735#define PCDS_IEN5 (1<<5)\r
736#define PCDS_IEN6 (1<<6)\r
737\r
738PICO_INTERNAL void PicoInitMCD(void);\r
739PICO_INTERNAL void PicoExitMCD(void);\r
740PICO_INTERNAL void PicoPowerMCD(void);\r
741PICO_INTERNAL int PicoResetMCD(void);\r
742PICO_INTERNAL void PicoFrameMCD(void);\r
743\r
744enum pcd_event {\r
745 PCD_EVENT_CDC,\r
746 PCD_EVENT_TIMER3,\r
747 PCD_EVENT_GFX,\r
748 PCD_EVENT_DMA,\r
749 PCD_EVENT_COUNT,\r
750};\r
751extern unsigned int pcd_event_times[PCD_EVENT_COUNT];\r
752void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);\r
753void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
754void pcd_prepare_frame(void);\r
755unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
756int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);\r
757void pcd_run_cpus(int m68k_cycles);\r
758void pcd_soft_reset(void);\r
759void pcd_state_loaded(void);\r
760\r
761// cd/pcm.c\r
762void pcd_pcm_sync(unsigned int to);\r
763void pcd_pcm_update(int *buffer, int length, int stereo);\r
764void pcd_pcm_write(unsigned int a, unsigned int d);\r
765unsigned int pcd_pcm_read(unsigned int a);\r
766\r
767// pico/pico.c\r
768PICO_INTERNAL void PicoInitPico(void);\r
769PICO_INTERNAL void PicoReratePico(void);\r
770\r
771// pico/xpcm.c\r
772PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
773PICO_INTERNAL void PicoPicoPCMReset(void);\r
774PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
775\r
776// sek.c\r
777PICO_INTERNAL void SekInit(void);\r
778PICO_INTERNAL int SekReset(void);\r
779PICO_INTERNAL void SekState(int *data);\r
780PICO_INTERNAL void SekSetRealTAS(int use_real);\r
781PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
782PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
783void SekStepM68k(void);\r
784void SekInitIdleDet(void);\r
785void SekFinishIdleDet(void);\r
786#if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r
787void SekTrace(int is_s68k);\r
788#else\r
789#define SekTrace(x)\r
790#endif\r
791\r
792// cd/sek.c\r
793PICO_INTERNAL void SekInitS68k(void);\r
794PICO_INTERNAL int SekResetS68k(void);\r
795PICO_INTERNAL int SekInterruptS68k(int irq);\r
796void SekInterruptClearS68k(int irq);\r
797\r
798// sound/sound.c\r
799extern short cdda_out_buffer[2*1152];\r
800\r
801void cdda_start_play(int lba_base, int lba_offset, int lb_len);\r
802\r
803void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
804void ym2612_pack_state(void);\r
805void ym2612_unpack_state(void);\r
806\r
807#define TIMER_NO_OFLOW 0x70000000\r
808// tA = 72 * (1024 - NA) / M\r
809#define TIMER_A_TICK_ZCYCLES 17203\r
810// tB = 1152 * (256 - NA) / M\r
811#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
812\r
813#define timers_cycle() \\r
814 if (Pico.t.timer_a_next_oflow > 0 && Pico.t.timer_a_next_oflow < TIMER_NO_OFLOW) \\r
815 Pico.t.timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
816 if (Pico.t.timer_b_next_oflow > 0 && Pico.t.timer_b_next_oflow < TIMER_NO_OFLOW) \\r
817 Pico.t.timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
818 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
819\r
820#define timers_reset() \\r
821 Pico.t.timer_a_next_oflow = Pico.t.timer_b_next_oflow = TIMER_NO_OFLOW; \\r
822 Pico.t.timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
823 Pico.t.timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
824\r
825\r
826// videoport.c\r
827PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
828PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
829unsigned char PicoVideoRead8DataH(void);\r
830unsigned char PicoVideoRead8DataL(void);\r
831unsigned char PicoVideoRead8CtlH(void);\r
832unsigned char PicoVideoRead8CtlL(void);\r
833unsigned char PicoVideoRead8HV_H(void);\r
834unsigned char PicoVideoRead8HV_L(void);\r
835extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned int *mask);\r
836\r
837// misc.c\r
838PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
839PICO_INTERNAL_ASM void memset32(void *dest, int c, int count);\r
840\r
841// eeprom.c\r
842void EEPROM_write8(unsigned int a, unsigned int d);\r
843void EEPROM_write16(unsigned int d);\r
844unsigned int EEPROM_read(void);\r
845\r
846// z80 functionality wrappers\r
847PICO_INTERNAL void z80_init(void);\r
848PICO_INTERNAL void z80_pack(void *data);\r
849PICO_INTERNAL int z80_unpack(const void *data);\r
850PICO_INTERNAL void z80_reset(void);\r
851PICO_INTERNAL void z80_exit(void);\r
852\r
853// cd/misc.c\r
854PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
855PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
856\r
857// sound/sound.c\r
858PICO_INTERNAL void PsndReset(void);\r
859PICO_INTERNAL void PsndStartFrame(void);\r
860PICO_INTERNAL void PsndDoDAC(int line_to);\r
861PICO_INTERNAL void PsndDoPSG(int line_to);\r
862PICO_INTERNAL void PsndClear(void);\r
863PICO_INTERNAL void PsndGetSamples(int y);\r
864PICO_INTERNAL void PsndGetSamplesMS(void);\r
865\r
866// sms.c\r
867#ifndef NO_SMS\r
868void PicoPowerMS(void);\r
869void PicoResetMS(void);\r
870void PicoMemSetupMS(void);\r
871void PicoStateLoadedMS(void);\r
872void PicoFrameMS(void);\r
873void PicoFrameDrawOnlyMS(void);\r
874#else\r
875#define PicoPowerMS()\r
876#define PicoResetMS()\r
877#define PicoMemSetupMS()\r
878#define PicoStateLoadedMS()\r
879#define PicoFrameMS()\r
880#define PicoFrameDrawOnlyMS()\r
881#endif\r
882\r
883// 32x/32x.c\r
884#ifndef NO_32X\r
885extern struct Pico32x Pico32x;\r
886enum p32x_event {\r
887 P32X_EVENT_PWM,\r
888 P32X_EVENT_FILLEND,\r
889 P32X_EVENT_HINT,\r
890 P32X_EVENT_COUNT,\r
891};\r
892extern unsigned int p32x_event_times[P32X_EVENT_COUNT];\r
893\r
894void Pico32xInit(void);\r
895void PicoPower32x(void);\r
896void PicoReset32x(void);\r
897void Pico32xStartup(void);\r
898void PicoUnload32x(void);\r
899void PicoFrame32x(void);\r
900void Pico32xStateLoaded(int is_early);\r
901void p32x_sync_sh2s(unsigned int m68k_target);\r
902void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
903void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
904void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);\r
905void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);\r
906void p32x_reset_sh2s(void);\r
907void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
908void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
909void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
910\r
911// 32x/memory.c\r
912extern struct Pico32xMem *Pico32xMem;\r
913unsigned int PicoRead8_32x(unsigned int a);\r
914unsigned int PicoRead16_32x(unsigned int a);\r
915void PicoWrite8_32x(unsigned int a, unsigned int d);\r
916void PicoWrite16_32x(unsigned int a, unsigned int d);\r
917void PicoMemSetup32x(void);\r
918void Pico32xSwapDRAM(int b);\r
919void Pico32xMemStateLoaded(void);\r
920void p32x_update_banks(void);\r
921void p32x_m68k_poll_event(unsigned int flags);\r
922void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r
923\r
924// 32x/draw.c\r
925void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r
926void FinalizeLine32xRGB555(int sh, int line, struct PicoEState *est);\r
927void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
928void PicoDraw32xLayerMdOnly(int offs, int lines);\r
929extern int (*PicoScan32xBegin)(unsigned int num);\r
930extern int (*PicoScan32xEnd)(unsigned int num);\r
931enum {\r
932 PDM32X_OFF,\r
933 PDM32X_32X_ONLY,\r
934 PDM32X_BOTH,\r
935};\r
936extern int Pico32xDrawMode;\r
937\r
938// 32x/pwm.c\r
939unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
940 unsigned int m68k_cycles);\r
941void p32x_pwm_write16(unsigned int a, unsigned int d,\r
942 SH2 *sh2, unsigned int m68k_cycles);\r
943void p32x_pwm_update(int *buf32, int length, int stereo);\r
944void p32x_pwm_ctl_changed(void);\r
945void p32x_pwm_schedule(unsigned int m68k_now);\r
946void p32x_pwm_schedule_sh2(SH2 *sh2);\r
947void p32x_pwm_sync_to_sh2(SH2 *sh2);\r
948void p32x_pwm_irq_event(unsigned int m68k_now);\r
949void p32x_pwm_state_loaded(void);\r
950\r
951// 32x/sh2soc.c\r
952void p32x_dreq0_trigger(void);\r
953void p32x_dreq1_trigger(void);\r
954void p32x_timers_recalc(void);\r
955void p32x_timers_do(unsigned int m68k_slice);\r
956void sh2_peripheral_reset(SH2 *sh2);\r
957unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
958unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
959unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
960void REGPARM(3) sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
961void REGPARM(3) sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
962void REGPARM(3) sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
963\r
964#else\r
965#define Pico32xInit()\r
966#define PicoPower32x()\r
967#define PicoReset32x()\r
968#define PicoFrame32x()\r
969#define PicoUnload32x()\r
970#define Pico32xStateLoaded()\r
971#define FinalizeLine32xRGB555 NULL\r
972#define p32x_pwm_update(...)\r
973#define p32x_timers_recalc()\r
974#endif\r
975\r
976/* avoid dependency on newer glibc */\r
977static __inline int isspace_(int c)\r
978{\r
979 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
980}\r
981\r
982#ifndef ARRAY_SIZE\r
983#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
984#endif\r
985\r
986// emulation event logging\r
987#ifndef EL_LOGMASK\r
988# ifdef __x86_64__ // HACK\r
989# define EL_LOGMASK (EL_STATUS|EL_ANOMALY)\r
990# else\r
991# define EL_LOGMASK (EL_STATUS)\r
992# endif\r
993#endif\r
994\r
995#define EL_HVCNT 0x00000001 /* hv counter reads */\r
996#define EL_SR 0x00000002 /* SR reads */\r
997#define EL_INTS 0x00000004 /* ints and acks */\r
998#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
999#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
1000#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
1001#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
1002#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
1003#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
1004#define EL_SRAMIO 0x00000200 /* sram i/o */\r
1005#define EL_EEPROM 0x00000400 /* eeprom debug */\r
1006#define EL_UIO 0x00000800 /* unmapped i/o */\r
1007#define EL_IO 0x00001000 /* all i/o */\r
1008#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
1009#define EL_SVP 0x00004000 /* SVP stuff */\r
1010#define EL_PICOHW 0x00008000 /* Pico stuff */\r
1011#define EL_IDLE 0x00010000 /* idle loop det. */\r
1012#define EL_CDREGS 0x00020000 /* MCD: register access */\r
1013#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
1014#define EL_32X 0x00080000\r
1015#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
1016#define EL_32XP 0x00200000 /* 32X peripherals */\r
1017#define EL_CD 0x00400000 /* MCD */\r
1018\r
1019#define EL_STATUS 0x40000000 /* status messages */\r
1020#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
1021\r
1022#if EL_LOGMASK\r
1023#define elprintf(w,f,...) \\r
1024do { \\r
1025 if ((w) & EL_LOGMASK) \\r
1026 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
1027} while (0)\r
1028#elif defined(_MSC_VER)\r
1029#define elprintf\r
1030#else\r
1031#define elprintf(w,f,...)\r
1032#endif\r
1033\r
1034// profiling\r
1035#ifdef PPROF\r
1036#include <platform/linux/pprof.h>\r
1037#else\r
1038#define pprof_init()\r
1039#define pprof_finish()\r
1040#define pprof_start(x)\r
1041#define pprof_end(...)\r
1042#define pprof_end_sub(...)\r
1043#endif\r
1044\r
1045#ifdef EVT_LOG\r
1046enum evt {\r
1047 EVT_FRAME_START,\r
1048 EVT_NEXT_LINE,\r
1049 EVT_RUN_START,\r
1050 EVT_RUN_END,\r
1051 EVT_POLL_START,\r
1052 EVT_POLL_END,\r
1053 EVT_CNT\r
1054};\r
1055\r
1056enum evt_cpu {\r
1057 EVT_M68K,\r
1058 EVT_S68K,\r
1059 EVT_MSH2,\r
1060 EVT_SSH2,\r
1061 EVT_CPU_CNT\r
1062};\r
1063\r
1064void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r
1065void pevt_dump(void);\r
1066\r
1067#define pevt_log_m68k(e) \\r
1068 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
1069#define pevt_log_m68k_o(e) \\r
1070 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
1071#define pevt_log_sh2(sh2, e) \\r
1072 pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r
1073#define pevt_log_sh2_o(sh2, e) \\r
1074 pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r
1075#else\r
1076#define pevt_log(c, e)\r
1077#define pevt_log_m68k(e)\r
1078#define pevt_log_m68k_o(e)\r
1079#define pevt_log_sh2(sh2, e)\r
1080#define pevt_log_sh2_o(sh2, e)\r
1081#define pevt_dump()\r
1082#endif\r
1083\r
1084#ifdef __cplusplus\r
1085} // End of extern "C"\r
1086#endif\r
1087\r
1088#endif // PICO_INTERNAL_INCLUDED\r
1089\r
1090// vim:shiftwidth=2:ts=2:expandtab\r
fast MegaDrive/MegaCD/32X emulator