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re-import all libretro code from it's fork
[picodrive.git] / pico / pico_int.h
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CommitLineData
1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
9\r
10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
12\r
13#include <stdio.h>\r
14#include <stdlib.h>\r
15#include <string.h>\r
16#include "pico.h"\r
17#include "carthw/carthw.h"\r
18\r
19//\r
20#define USE_POLL_DETECT\r
21\r
22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
28\r
29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
35\r
36// ----------------------- 68000 CPU -----------------------\r
37#ifdef EMU_C68K\r
38#include "../cpu/cyclone/Cyclone.h"\r
39extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
40#define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run\r
41#define SekCyclesLeftS68k PicoCpuCS68k.cycles\r
42#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
43#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
44#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
45#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r
46#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
47#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r
48#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
49#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
50#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
51#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
52#define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
53\r
54#define SekNotPolling PicoCpuCM68k.not_pol\r
55#define SekNotPollingS68k PicoCpuCS68k.not_pol\r
56\r
57#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
58#define SekIrqLevel PicoCpuCM68k.irq\r
59\r
60#endif\r
61\r
62#ifdef EMU_F68K\r
63#include "../cpu/fame/fame.h"\r
64extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
65#define SekCyclesLeft PicoCpuFM68k.io_cycle_counter\r
66#define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter\r
67#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
68#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
69#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
70#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r
71#define SekSr PicoCpuFM68k.sr\r
72#define SekSrS68k PicoCpuFS68k.sr\r
73#define SekSetStop(x) { \\r
74 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
75 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
76}\r
77#define SekSetStopS68k(x) { \\r
78 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
79 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
80}\r
81#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
82#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
83#define SekShouldInterrupt() fm68k_would_interrupt()\r
84\r
85#define SekNotPolling PicoCpuFM68k.not_polling\r
86#define SekNotPollingS68k PicoCpuFS68k.not_polling\r
87\r
88#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
89#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
90\r
91#endif\r
92\r
93#ifdef EMU_M68K\r
94#include "../cpu/musashi/m68kcpu.h"\r
95extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
96#ifndef SekCyclesLeft\r
97#define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles\r
98#define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles\r
99#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
100#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
101#define SekDar(x) PicoCpuMM68k.dar[x]\r
102#define SekDarS68k(x) PicoCpuMS68k.dar[x]\r
103#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
104#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r
105#define SekSetStop(x) { \\r
106 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
107 else PicoCpuMM68k.stopped=0; \\r
108}\r
109#define SekSetStopS68k(x) { \\r
110 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
111 else PicoCpuMS68k.stopped=0; \\r
112}\r
113#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
114#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
115#define SekShouldInterrupt() (CPU_INT_LEVEL > FLAG_INT_MASK)\r
116\r
117#define SekNotPolling PicoCpuMM68k.not_polling\r
118#define SekNotPollingS68k PicoCpuMS68k.not_polling\r
119\r
120// avoid m68k_set_irq() for delaying to work\r
121#define SekInterrupt(irq) PicoCpuMM68k.int_level = (irq) << 8\r
122#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
123\r
124#endif\r
125#endif // EMU_M68K\r
126\r
127// number of cycles done (can be checked anywhere)\r
128#define SekCyclesDone() (Pico.t.m68c_cnt - SekCyclesLeft)\r
129\r
130// burn cycles while not in SekRun() and while in\r
131#define SekCyclesBurn(c) Pico.t.m68c_cnt += c\r
132#define SekCyclesBurnRun(c) { \\r
133 SekCyclesLeft -= c; \\r
134}\r
135\r
136// note: sometimes may extend timeslice to delay an irq\r
137#define SekEndRun(after) { \\r
138 Pico.t.m68c_cnt -= SekCyclesLeft - (after); \\r
139 SekCyclesLeft = after; \\r
140}\r
141\r
142extern unsigned int SekCycleCntS68k;\r
143extern unsigned int SekCycleAimS68k;\r
144\r
145#define SekEndRunS68k(after) { \\r
146 if (SekCyclesLeftS68k > (after)) { \\r
147 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
148 SekCyclesLeftS68k = after; \\r
149 } \\r
150}\r
151\r
152#define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)\r
153\r
154// compare cycles, handling overflows\r
155// check if a > b\r
156#define CYCLES_GT(a, b) \\r
157 ((int)((a) - (b)) > 0)\r
158// check if a >= b\r
159#define CYCLES_GE(a, b) \\r
160 ((int)((a) - (b)) >= 0)\r
161\r
162// ----------------------- Z80 CPU -----------------------\r
163\r
164#if defined(_USE_DRZ80)\r
165#include "../cpu/DrZ80/drz80.h"\r
166\r
167extern struct DrZ80 drZ80;\r
168\r
169#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
170#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
171#define z80_int() drZ80.Z80_IRQ = 1\r
172#define z80_int() drZ80.Z80_IRQ = 1\r
173#define z80_nmi() drZ80.Z80IF |= 8\r
174\r
175#define z80_cyclesLeft drZ80.cycles\r
176#define z80_subCLeft(c) drZ80.cycles -= c\r
177#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
178\r
179#elif defined(_USE_CZ80)\r
180#include "../cpu/cz80/cz80.h"\r
181\r
182#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
183#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
184#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
185#define z80_nmi() Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, 0)\r
186\r
187#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
188#define z80_subCLeft(c) CZ80.ICount -= c\r
189#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
190\r
191#else\r
192\r
193#define z80_run(cycles) (cycles)\r
194#define z80_run_nr(cycles)\r
195#define z80_int()\r
196#define z80_nmi()\r
197\r
198#endif\r
199\r
200#define Z80_STATE_SIZE 0x60\r
201\r
202#define z80_resetCycles() \\r
203 Pico.t.z80c_cnt = Pico.t.z80c_aim = Pico.t.z80_scanline = 0\r
204\r
205#define z80_cyclesDone() \\r
206 (Pico.t.z80c_aim - z80_cyclesLeft)\r
207\r
208#define cycles_68k_to_z80(x) ((x) * 3823 >> 13)\r
209\r
210// ----------------------- SH2 CPU -----------------------\r
211\r
212#include "cpu/sh2/sh2.h"\r
213\r
214extern SH2 sh2s[2];\r
215#define msh2 sh2s[0]\r
216#define ssh2 sh2s[1]\r
217\r
218#ifndef DRC_SH2\r
219# define sh2_end_run(sh2, after_) do { \\r
220 if ((sh2)->icount > (after_)) { \\r
221 (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
222 (sh2)->icount = after_; \\r
223 } \\r
224} while (0)\r
225# define sh2_cycles_left(sh2) (sh2)->icount\r
226# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
227# define sh2_pc(sh2) (sh2)->ppc\r
228#else\r
229# define sh2_end_run(sh2, after_) do { \\r
230 int left_ = (signed int)(sh2)->sr >> 12; \\r
231 if (left_ > (after_)) { \\r
232 (sh2)->cycles_timeslice -= left_ - (after_); \\r
233 (sh2)->sr &= 0xfff; \\r
234 (sh2)->sr |= (after_) << 12; \\r
235 } \\r
236} while (0)\r
237# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
238# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
239# define sh2_pc(sh2) (sh2)->pc\r
240#endif\r
241\r
242#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
243#define sh2_cycles_done_t(sh2) \\r
244 ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
245#define sh2_cycles_done_m68k(sh2) \\r
246 ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
247\r
248#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
249#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
250#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
251#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
252\r
253#define sh2_set_gbr(c, v) \\r
254 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
255#define sh2_set_vbr(c, v) \\r
256 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
257\r
258#define elprintf_sh2(sh2, w, f, ...) \\r
259 elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
260\r
261// ---------------------------------------------------------\r
262\r
263// main oscillator clock which controls timing\r
264#define OSC_NTSC 53693100\r
265#define OSC_PAL 53203424\r
266\r
267// PicoVideo.debug_p\r
268#define PVD_KILL_A (1 << 0)\r
269#define PVD_KILL_B (1 << 1)\r
270#define PVD_KILL_S_LO (1 << 2)\r
271#define PVD_KILL_S_HI (1 << 3)\r
272#define PVD_KILL_32X (1 << 4)\r
273#define PVD_FORCE_A (1 << 5)\r
274#define PVD_FORCE_B (1 << 6)\r
275#define PVD_FORCE_S (1 << 7)\r
276\r
277// PicoVideo.status, not part of real SR\r
278#define SR_PAL (1 << 0)\r
279#define SR_DMA (1 << 1)\r
280#define SR_HB (1 << 2)\r
281#define SR_VB (1 << 3)\r
282#define SR_ODD (1 << 4)\r
283#define SR_C (1 << 5)\r
284#define SR_SOVR (1 << 6)\r
285#define SR_F (1 << 7)\r
286#define SR_FULL (1 << 8)\r
287#define SR_EMPT (1 << 9)\r
288// not part of real SR\r
289#define PVS_ACTIVE (1 << 16)\r
290#define PVS_VB2 (1 << 17) // ignores forced blanking\r
291\r
292struct PicoVideo\r
293{\r
294 unsigned char reg[0x20];\r
295 unsigned int command; // 32-bit Command\r
296 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
297 unsigned char type; // Command type (v/c/vsram read/write)\r
298 unsigned short addr; // Read/Write address\r
299 unsigned int status; // Status bits (SR) and extra flags\r
300 unsigned char pending_ints; // pending interrupts: ??VH????\r
301 signed char lwrite_cnt; // VDP write count during active display line\r
302 unsigned short v_counter; // V-counter\r
303 unsigned short debug; // raw debug register\r
304 unsigned char debug_p; // ... parsed: PVD_*\r
305 unsigned char addr_u; // bit16 of .addr\r
306 unsigned char hint_cnt;\r
307 unsigned char pad[0x0b];\r
308};\r
309\r
310struct PicoMisc\r
311{\r
312 unsigned char rotate;\r
313 unsigned char z80Run;\r
314 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
315 unsigned short scanline; // 04 0 to 261||311\r
316 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
317 unsigned char hardware; // 07 Hardware value for country\r
318 unsigned char pal; // 08 1=PAL 0=NTSC\r
319 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
320 unsigned short z80_bank68k; // 0a\r
321 unsigned short pad0;\r
322 unsigned char ncart_in; // 0e !cart_in\r
323 unsigned char z80_reset; // 0f z80 reset held\r
324 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
325 unsigned short eeprom_addr; // EEPROM address register\r
326 unsigned char eeprom_cycle; // EEPROM cycle number\r
327 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
328 unsigned char eeprom_status;\r
329 unsigned char pad2;\r
330 unsigned short dma_xfers; // 18\r
331 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
332 unsigned int frame_count; // 1c for movies and idle det\r
333};\r
334\r
335struct PicoMS\r
336{\r
337 unsigned char carthw[0x10];\r
338 unsigned char io_ctl;\r
339 unsigned char nmi_state;\r
340 unsigned char pad[0x4e];\r
341};\r
342\r
343// emu state and data for the asm code\r
344struct PicoEState\r
345{\r
346 int DrawScanline;\r
347 int rendstatus;\r
348 void *DrawLineDest; // draw destination\r
349 unsigned char *HighCol;\r
350 int *HighPreSpr;\r
351 struct Pico *Pico;\r
352 void *PicoMem_vram;\r
353 void *PicoMem_cram;\r
354 int *PicoOpt;\r
355 unsigned char *Draw2FB;\r
356 unsigned short HighPal[0x100];\r
357};\r
358\r
359struct PicoMem\r
360{\r
361 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
362 union { // vram is byteswapped for easier reads when drawing\r
363 unsigned short vram[0x8000]; // 0x10000\r
364 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
365 };\r
366 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
367 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
368 unsigned short cram[0x40]; // 0x22010\r
369 unsigned char pad[0x70]; // 0x22050 DrawStripVSRam reads 0 from here\r
370 unsigned short vsram[0x40]; // 0x22100\r
371};\r
372\r
373// sram\r
374#define SRR_MAPPED (1 << 0)\r
375#define SRR_READONLY (1 << 1)\r
376\r
377#define SRF_ENABLED (1 << 0)\r
378#define SRF_EEPROM (1 << 1)\r
379\r
380struct PicoCartSave\r
381{\r
382 unsigned char *data; // actual data\r
383 unsigned int start; // start address in 68k address space\r
384 unsigned int end;\r
385 unsigned char flags; // 0c: SRF_*\r
386 unsigned char unused2;\r
387 unsigned char changed;\r
388 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
389 unsigned char unused3;\r
390 unsigned char eeprom_bit_cl; // bit number for cl\r
391 unsigned char eeprom_bit_in; // bit number for in\r
392 unsigned char eeprom_bit_out; // bit number for out\r
393 unsigned int size;\r
394};\r
395\r
396struct PicoTiming\r
397{\r
398 // while running, cnt represents target of current timeslice\r
399 // while not in SekRun(), it's actual cycles done\r
400 // (but always use SekCyclesDone() if you need current position)\r
401 // _cnt may change if timeslice is ended prematurely or extended,\r
402 // so we use _aim for the actual target\r
403 unsigned int m68c_cnt;\r
404 unsigned int m68c_aim;\r
405 unsigned int m68c_frame_start; // m68k cycles\r
406 unsigned int m68c_line_start;\r
407\r
408 unsigned int z80c_cnt; // z80 cycles done (this frame)\r
409 unsigned int z80c_aim;\r
410 int z80_scanline;\r
411};\r
412\r
413// run tools/mkoffsets pico/pico_int_o32.h if you change these\r
414// careful with savestate compat\r
415struct Pico\r
416{\r
417 struct PicoVideo video;\r
418 struct PicoMisc m;\r
419 struct PicoTiming t;\r
420 struct PicoCartSave sv;\r
421 struct PicoEState est;\r
422 struct PicoMS ms;\r
423\r
424 unsigned char *rom;\r
425 unsigned int romsize;\r
426};\r
427\r
428// MCD\r
429#define PCM_MIXBUF_LEN ((12500000 / 384) / 50 + 1)\r
430\r
431struct mcd_pcm\r
432{\r
433 unsigned char control; // reg7\r
434 unsigned char enabled; // reg8\r
435 unsigned char cur_ch;\r
436 unsigned char bank;\r
437 unsigned int update_cycles;\r
438\r
439 struct pcm_chan // 08, size 0x10\r
440 {\r
441 unsigned char regs[8];\r
442 unsigned int addr; // .08: played sample address\r
443 int pad;\r
444 } ch[8];\r
445};\r
446\r
447#define PCD_ST_S68K_RST 1\r
448\r
449struct mcd_misc\r
450{\r
451 unsigned short hint_vector;\r
452 unsigned char busreq; // not s68k_regs[1]\r
453 unsigned char s68k_pend_ints;\r
454 unsigned int state_flags; // 04\r
455 unsigned int stopwatch_base_c;\r
456 unsigned short m68k_poll_a;\r
457 unsigned short m68k_poll_cnt;\r
458 unsigned short s68k_poll_a;\r
459 unsigned short s68k_poll_cnt;\r
460 unsigned int s68k_poll_clk;\r
461 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
462 unsigned char dmna_ret_2m;\r
463 unsigned char need_sync;\r
464 unsigned char pad3;\r
465 int pad4[9];\r
466};\r
467\r
468typedef struct\r
469{\r
470 unsigned char bios[0x20000]; // 000000: 128K\r
471 union { // 020000: 512K\r
472 unsigned char prg_ram[0x80000];\r
473 unsigned char prg_ram_b[4][0x20000];\r
474 };\r
475 union { // 0a0000: 256K\r
476 struct {\r
477 unsigned char word_ram2M[0x40000];\r
478 unsigned char unused0[0x20000];\r
479 };\r
480 struct {\r
481 unsigned char unused1[0x20000];\r
482 unsigned char word_ram1M[2][0x20000];\r
483 };\r
484 };\r
485 union { // 100000: 64K\r
486 unsigned char pcm_ram[0x10000];\r
487 unsigned char pcm_ram_b[0x10][0x1000];\r
488 };\r
489 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
490 unsigned char bram[0x2000]; // 110200: 8K\r
491 struct mcd_misc m; // 112200: misc\r
492 struct mcd_pcm pcm; // 112240:\r
493 void *cdda_stream;\r
494 int cdda_type;\r
495 int pcm_mixbuf[PCM_MIXBUF_LEN * 2];\r
496 int pcm_mixpos;\r
497 char pcm_mixbuf_dirty;\r
498 char pcm_regs_dirty;\r
499} mcd_state;\r
500\r
501// XXX: this will need to be reworked for cart+cd support.\r
502#define Pico_mcd ((mcd_state *)Pico.rom)\r
503\r
504// 32X\r
505#define P32XS_FM (1<<15)\r
506#define P32XS_nCART (1<< 8)\r
507#define P32XS_REN (1<< 7)\r
508#define P32XS_nRES (1<< 1)\r
509#define P32XS_ADEN (1<< 0)\r
510#define P32XS2_ADEN (1<< 9)\r
511#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
512#define P32XS_68S (1<< 2)\r
513#define P32XS_DMA (1<< 1)\r
514#define P32XS_RV (1<< 0)\r
515\r
516#define P32XV_nPAL (1<<15) // VDP\r
517#define P32XV_PRI (1<< 7)\r
518#define P32XV_Mx (3<< 0) // display mode mask\r
519\r
520#define P32XV_SFT (1<< 0)\r
521\r
522#define P32XV_VBLK (1<<15)\r
523#define P32XV_HBLK (1<<14)\r
524#define P32XV_PEN (1<<13)\r
525#define P32XV_nFEN (1<< 1)\r
526#define P32XV_FS (1<< 0)\r
527\r
528#define P32XP_RTP (1<<7) // PWM control\r
529#define P32XP_FULL (1<<15) // PWM pulse\r
530#define P32XP_EMPTY (1<<14)\r
531\r
532#define P32XF_68KCPOLL (1 << 0)\r
533#define P32XF_68KVPOLL (1 << 1)\r
534#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
535\r
536#define P32XI_VRES (1 << 14/2) // IRL/2\r
537#define P32XI_VINT (1 << 12/2)\r
538#define P32XI_HINT (1 << 10/2)\r
539#define P32XI_CMD (1 << 8/2)\r
540#define P32XI_PWM (1 << 6/2)\r
541\r
542// peripheral reg access\r
543#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
544\r
545#define DMAC_FIFO_LEN (4*2)\r
546#define PWM_BUFF_LEN 1024 // in one channel samples\r
547\r
548#define SH2_DRCBLK_RAM_SHIFT 1\r
549#define SH2_DRCBLK_DA_SHIFT 1\r
550\r
551#define SH2_READ_SHIFT 25\r
552#define SH2_WRITE_SHIFT 25\r
553\r
554struct Pico32x\r
555{\r
556 unsigned short regs[0x20];\r
557 unsigned short vdp_regs[0x10]; // 0x40\r
558 unsigned short sh2_regs[3]; // 0x60\r
559 unsigned char pending_fb;\r
560 unsigned char dirty_pal;\r
561 unsigned int emu_flags;\r
562 unsigned char sh2irq_mask[2];\r
563 unsigned char sh2irqi[2]; // individual\r
564 unsigned int sh2irqs; // common irqs\r
565 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
566 unsigned int pad[4];\r
567 unsigned int dmac0_fifo_ptr;\r
568 unsigned short vdp_fbcr_fake;\r
569 unsigned short pad2;\r
570 unsigned char comm_dirty_68k;\r
571 unsigned char comm_dirty_sh2;\r
572 unsigned char pwm_irq_cnt;\r
573 unsigned char pad1;\r
574 unsigned short pwm_p[2]; // pwm pos in fifo\r
575 unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
576 unsigned int reserved[6];\r
577};\r
578\r
579struct Pico32xMem\r
580{\r
581 unsigned char sdram[0x40000];\r
582#ifdef DRC_SH2\r
583 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
584#endif\r
585 unsigned short dram[2][0x20000/2]; // AKA fb\r
586 union {\r
587 unsigned char m68k_rom[0x100];\r
588 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
589 };\r
590#ifdef DRC_SH2\r
591 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
592#endif\r
593 union {\r
594 unsigned char b[0x800];\r
595 unsigned short w[0x800/2];\r
596 } sh2_rom_m;\r
597 union {\r
598 unsigned char b[0x400];\r
599 unsigned short w[0x400/2];\r
600 } sh2_rom_s;\r
601 unsigned short pal[0x100];\r
602 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
603 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
604 signed short pwm_current[2]; // current converted samples\r
605 unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries\r
606};\r
607\r
608// area.c\r
609extern void (*PicoLoadStateHook)(void);\r
610\r
611typedef struct {\r
612 int chunk;\r
613 int size;\r
614 void *ptr;\r
615} carthw_state_chunk;\r
616extern carthw_state_chunk *carthw_chunks;\r
617#define CHUNK_CARTHW 64\r
618\r
619// cart.c\r
620extern int PicoCartResize(int newsize);\r
621extern void Byteswap(void *dst, const void *src, int len);\r
622extern void (*PicoCartMemSetup)(void);\r
623extern void (*PicoCartUnloadHook)(void);\r
624\r
625// debug.c\r
626int CM_compareRun(int cyc, int is_sub);\r
627\r
628// draw.c\r
629void PicoDrawInit(void);\r
630PICO_INTERNAL void PicoFrameStart(void);\r
631void PicoDrawSync(int to, int blank_last_line);\r
632void BackFill(int reg7, int sh, struct PicoEState *est);\r
633void FinalizeLine555(int sh, int line, struct PicoEState *est);\r
634extern int (*PicoScanBegin)(unsigned int num);\r
635extern int (*PicoScanEnd)(unsigned int num);\r
636#define MAX_LINE_SPRITES 29\r
637extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
638extern void *DrawLineDestBase;\r
639extern int DrawLineDestIncrement;\r
640\r
641// draw2.c\r
642void PicoDraw2Init(void);\r
643PICO_INTERNAL void PicoFrameFull();\r
644\r
645// mode4.c\r
646void PicoFrameStartMode4(void);\r
647void PicoLineMode4(int line);\r
648void PicoDoHighPal555M4(void);\r
649void PicoDrawSetOutputMode4(pdso_t which);\r
650\r
651// memory.c\r
652PICO_INTERNAL void PicoMemSetup(void);\r
653unsigned int PicoRead8_io(unsigned int a);\r
654unsigned int PicoRead16_io(unsigned int a);\r
655void PicoWrite8_io(unsigned int a, unsigned int d);\r
656void PicoWrite16_io(unsigned int a, unsigned int d);\r
657\r
658// pico/memory.c\r
659PICO_INTERNAL void PicoMemSetupPico(void);\r
660\r
661// cd/cdc.c\r
662void cdc_init(void);\r
663void cdc_reset(void);\r
664int cdc_context_save(unsigned char *state);\r
665int cdc_context_load(unsigned char *state);\r
666int cdc_context_load_old(unsigned char *state);\r
667void cdc_dma_update(void);\r
668int cdc_decoder_update(unsigned char header[4]);\r
669void cdc_reg_w(unsigned char data);\r
670unsigned char cdc_reg_r(void);\r
671unsigned short cdc_host_r(void);\r
672\r
673// cd/cdd.c\r
674void cdd_reset(void);\r
675int cdd_context_save(unsigned char *state);\r
676int cdd_context_load(unsigned char *state);\r
677int cdd_context_load_old(unsigned char *state);\r
678void cdd_read_data(unsigned char *dst);\r
679void cdd_read_audio(unsigned int samples);\r
680void cdd_update(void);\r
681void cdd_process(void);\r
682\r
683// cd/cd_image.c\r
684int load_cd_image(const char *cd_img_name, int *type);\r
685\r
686// cd/gfx.c\r
687void gfx_init(void);\r
688void gfx_start(unsigned int base);\r
689void gfx_update(unsigned int cycles);\r
690int gfx_context_save(unsigned char *state);\r
691int gfx_context_load(const unsigned char *state);\r
692\r
693// cd/gfx_dma.c\r
694void DmaSlowCell(unsigned int source, unsigned int a, int len, unsigned char inc);\r
695\r
696// cd/memory.c\r
697PICO_INTERNAL void PicoMemSetupCD(void);\r
698unsigned int PicoRead8_mcd_io(unsigned int a);\r
699unsigned int PicoRead16_mcd_io(unsigned int a);\r
700void PicoWrite8_mcd_io(unsigned int a, unsigned int d);\r
701void PicoWrite16_mcd_io(unsigned int a, unsigned int d);\r
702void pcd_state_loaded_mem(void);\r
703\r
704// pico.c\r
705extern struct Pico Pico;\r
706extern struct PicoMem PicoMem;\r
707extern int PicoPadInt[2];\r
708extern int emustatus;\r
709extern void (*PicoResetHook)(void);\r
710extern void (*PicoLineHook)(void);\r
711PICO_INTERNAL int CheckDMA(void);\r
712PICO_INTERNAL void PicoDetectRegion(void);\r
713PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);\r
714\r
715// cd/mcd.c\r
716#define PCDS_IEN1 (1<<1)\r
717#define PCDS_IEN2 (1<<2)\r
718#define PCDS_IEN3 (1<<3)\r
719#define PCDS_IEN4 (1<<4)\r
720#define PCDS_IEN5 (1<<5)\r
721#define PCDS_IEN6 (1<<6)\r
722\r
723PICO_INTERNAL void PicoInitMCD(void);\r
724PICO_INTERNAL void PicoExitMCD(void);\r
725PICO_INTERNAL void PicoPowerMCD(void);\r
726PICO_INTERNAL int PicoResetMCD(void);\r
727PICO_INTERNAL void PicoFrameMCD(void);\r
728\r
729enum pcd_event {\r
730 PCD_EVENT_CDC,\r
731 PCD_EVENT_TIMER3,\r
732 PCD_EVENT_GFX,\r
733 PCD_EVENT_DMA,\r
734 PCD_EVENT_COUNT,\r
735};\r
736extern unsigned int pcd_event_times[PCD_EVENT_COUNT];\r
737void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);\r
738void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
739void pcd_prepare_frame(void);\r
740unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
741int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);\r
742void pcd_run_cpus(int m68k_cycles);\r
743void pcd_soft_reset(void);\r
744void pcd_state_loaded(void);\r
745\r
746// cd/pcm.c\r
747void pcd_pcm_sync(unsigned int to);\r
748void pcd_pcm_update(int *buffer, int length, int stereo);\r
749void pcd_pcm_write(unsigned int a, unsigned int d);\r
750unsigned int pcd_pcm_read(unsigned int a);\r
751\r
752// pico/pico.c\r
753PICO_INTERNAL void PicoInitPico(void);\r
754PICO_INTERNAL void PicoReratePico(void);\r
755\r
756// pico/xpcm.c\r
757PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
758PICO_INTERNAL void PicoPicoPCMReset(void);\r
759PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
760\r
761// sek.c\r
762PICO_INTERNAL void SekInit(void);\r
763PICO_INTERNAL int SekReset(void);\r
764PICO_INTERNAL void SekState(int *data);\r
765PICO_INTERNAL void SekSetRealTAS(int use_real);\r
766PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
767PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
768void SekStepM68k(void);\r
769void SekInitIdleDet(void);\r
770void SekFinishIdleDet(void);\r
771#if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r
772void SekTrace(int is_s68k);\r
773#else\r
774#define SekTrace(x)\r
775#endif\r
776\r
777// cd/sek.c\r
778PICO_INTERNAL void SekInitS68k(void);\r
779PICO_INTERNAL int SekResetS68k(void);\r
780PICO_INTERNAL int SekInterruptS68k(int irq);\r
781void SekInterruptClearS68k(int irq);\r
782\r
783// sound/sound.c\r
784extern short cdda_out_buffer[2*1152];\r
785extern int PsndLen_exc_cnt;\r
786extern int PsndLen_exc_add;\r
787extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
788extern int timer_b_next_oflow, timer_b_step;\r
789\r
790void cdda_start_play(int lba_base, int lba_offset, int lb_len);\r
791\r
792void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
793void ym2612_pack_state(void);\r
794void ym2612_unpack_state(void);\r
795\r
796#define TIMER_NO_OFLOW 0x70000000\r
797// tA = 72 * (1024 - NA) / M\r
798#define TIMER_A_TICK_ZCYCLES 17203\r
799// tB = 1152 * (256 - NA) / M\r
800#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
801\r
802#define timers_cycle() \\r
803 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
804 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
805 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
806 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
807 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
808\r
809#define timers_reset() \\r
810 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
811 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
812 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
813\r
814\r
815// videoport.c\r
816PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
817PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
818unsigned char PicoVideoRead8DataH(void);\r
819unsigned char PicoVideoRead8DataL(void);\r
820unsigned char PicoVideoRead8CtlH(void);\r
821unsigned char PicoVideoRead8CtlL(void);\r
822unsigned char PicoVideoRead8HV_H(void);\r
823unsigned char PicoVideoRead8HV_L(void);\r
824extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned int *mask);\r
825\r
826// misc.c\r
827PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
828PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
829PICO_INTERNAL_ASM void memcpy32(void *dest, const void *src, int count); // 32bit word count\r
830PICO_INTERNAL_ASM void memset32(void *dest, int c, int count);\r
831\r
832// eeprom.c\r
833void EEPROM_write8(unsigned int a, unsigned int d);\r
834void EEPROM_write16(unsigned int d);\r
835unsigned int EEPROM_read(void);\r
836\r
837// z80 functionality wrappers\r
838PICO_INTERNAL void z80_init(void);\r
839PICO_INTERNAL void z80_pack(void *data);\r
840PICO_INTERNAL int z80_unpack(const void *data);\r
841PICO_INTERNAL void z80_reset(void);\r
842PICO_INTERNAL void z80_exit(void);\r
843\r
844// cd/misc.c\r
845PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
846PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
847\r
848// sound/sound.c\r
849PICO_INTERNAL void PsndReset(void);\r
850PICO_INTERNAL void PsndStartFrame(void);\r
851PICO_INTERNAL void PsndDoDAC(int line_to);\r
852PICO_INTERNAL void PsndDoPSG(int line_to);\r
853PICO_INTERNAL void PsndClear(void);\r
854PICO_INTERNAL void PsndGetSamples(int y);\r
855PICO_INTERNAL void PsndGetSamplesMS(void);\r
856extern int PsndDacLine, PsndPsgLine;\r
857\r
858// sms.c\r
859#ifndef NO_SMS\r
860void PicoPowerMS(void);\r
861void PicoResetMS(void);\r
862void PicoMemSetupMS(void);\r
863void PicoStateLoadedMS(void);\r
864void PicoFrameMS(void);\r
865void PicoFrameDrawOnlyMS(void);\r
866#else\r
867#define PicoPowerMS()\r
868#define PicoResetMS()\r
869#define PicoMemSetupMS()\r
870#define PicoStateLoadedMS()\r
871#define PicoFrameMS()\r
872#define PicoFrameDrawOnlyMS()\r
873#endif\r
874\r
875// 32x/32x.c\r
876#ifndef NO_32X\r
877extern struct Pico32x Pico32x;\r
878enum p32x_event {\r
879 P32X_EVENT_PWM,\r
880 P32X_EVENT_FILLEND,\r
881 P32X_EVENT_HINT,\r
882 P32X_EVENT_COUNT,\r
883};\r
884extern unsigned int p32x_event_times[P32X_EVENT_COUNT];\r
885\r
886void Pico32xInit(void);\r
887void PicoPower32x(void);\r
888void PicoReset32x(void);\r
889void Pico32xStartup(void);\r
890void PicoUnload32x(void);\r
891void PicoFrame32x(void);\r
892void Pico32xStateLoaded(int is_early);\r
893void p32x_sync_sh2s(unsigned int m68k_target);\r
894void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
895void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
896void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);\r
897void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);\r
898void p32x_reset_sh2s(void);\r
899void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
900void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
901void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
902\r
903// 32x/memory.c\r
904extern struct Pico32xMem *Pico32xMem;\r
905unsigned int PicoRead8_32x(unsigned int a);\r
906unsigned int PicoRead16_32x(unsigned int a);\r
907void PicoWrite8_32x(unsigned int a, unsigned int d);\r
908void PicoWrite16_32x(unsigned int a, unsigned int d);\r
909void PicoMemSetup32x(void);\r
910void Pico32xSwapDRAM(int b);\r
911void Pico32xMemStateLoaded(void);\r
912void p32x_m68k_poll_event(unsigned int flags);\r
913void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r
914\r
915// 32x/draw.c\r
916void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r
917void FinalizeLine32xRGB555(int sh, int line, struct PicoEState *est);\r
918void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
919void PicoDraw32xLayerMdOnly(int offs, int lines);\r
920extern int (*PicoScan32xBegin)(unsigned int num);\r
921extern int (*PicoScan32xEnd)(unsigned int num);\r
922enum {\r
923 PDM32X_OFF,\r
924 PDM32X_32X_ONLY,\r
925 PDM32X_BOTH,\r
926};\r
927extern int Pico32xDrawMode;\r
928\r
929// 32x/pwm.c\r
930unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
931 unsigned int m68k_cycles);\r
932void p32x_pwm_write16(unsigned int a, unsigned int d,\r
933 SH2 *sh2, unsigned int m68k_cycles);\r
934void p32x_pwm_update(int *buf32, int length, int stereo);\r
935void p32x_pwm_ctl_changed(void);\r
936void p32x_pwm_schedule(unsigned int m68k_now);\r
937void p32x_pwm_schedule_sh2(SH2 *sh2);\r
938void p32x_pwm_sync_to_sh2(SH2 *sh2);\r
939void p32x_pwm_irq_event(unsigned int m68k_now);\r
940void p32x_pwm_state_loaded(void);\r
941\r
942// 32x/sh2soc.c\r
943void p32x_dreq0_trigger(void);\r
944void p32x_dreq1_trigger(void);\r
945void p32x_timers_recalc(void);\r
946void p32x_timers_do(unsigned int m68k_slice);\r
947void sh2_peripheral_reset(SH2 *sh2);\r
948unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
949unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
950unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
951void REGPARM(3) sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
952void REGPARM(3) sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
953void REGPARM(3) sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
954\r
955#else\r
956#define Pico32xInit()\r
957#define PicoPower32x()\r
958#define PicoReset32x()\r
959#define PicoFrame32x()\r
960#define PicoUnload32x()\r
961#define Pico32xStateLoaded()\r
962#define FinalizeLine32xRGB555 NULL\r
963#define p32x_pwm_update(...)\r
964#define p32x_timers_recalc()\r
965#endif\r
966\r
967/* avoid dependency on newer glibc */\r
968static __inline int isspace_(int c)\r
969{\r
970 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
971}\r
972\r
973#ifndef ARRAY_SIZE\r
974#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
975#endif\r
976\r
977// emulation event logging\r
978#ifndef EL_LOGMASK\r
979# ifdef __x86_64__ // HACK\r
980# define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r
981# else\r
982# define EL_LOGMASK (EL_STATUS)\r
983# endif\r
984#endif\r
985\r
986#define EL_HVCNT 0x00000001 /* hv counter reads */\r
987#define EL_SR 0x00000002 /* SR reads */\r
988#define EL_INTS 0x00000004 /* ints and acks */\r
989#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
990#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
991#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
992#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
993#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
994#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
995#define EL_SRAMIO 0x00000200 /* sram i/o */\r
996#define EL_EEPROM 0x00000400 /* eeprom debug */\r
997#define EL_UIO 0x00000800 /* unmapped i/o */\r
998#define EL_IO 0x00001000 /* all i/o */\r
999#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
1000#define EL_SVP 0x00004000 /* SVP stuff */\r
1001#define EL_PICOHW 0x00008000 /* Pico stuff */\r
1002#define EL_IDLE 0x00010000 /* idle loop det. */\r
1003#define EL_CDREGS 0x00020000 /* MCD: register access */\r
1004#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
1005#define EL_32X 0x00080000\r
1006#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
1007#define EL_32XP 0x00200000 /* 32X peripherals */\r
1008#define EL_CD 0x00400000 /* MCD */\r
1009\r
1010#define EL_STATUS 0x40000000 /* status messages */\r
1011#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
1012\r
1013#if EL_LOGMASK\r
1014#define elprintf(w,f,...) \\r
1015do { \\r
1016 if ((w) & EL_LOGMASK) \\r
1017 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
1018} while (0)\r
1019#elif defined(_MSC_VER)\r
1020#define elprintf\r
1021#else\r
1022#define elprintf(w,f,...)\r
1023#endif\r
1024\r
1025// profiling\r
1026#ifdef PPROF\r
1027#include <platform/linux/pprof.h>\r
1028#else\r
1029#define pprof_init()\r
1030#define pprof_finish()\r
1031#define pprof_start(x)\r
1032#define pprof_end(...)\r
1033#define pprof_end_sub(...)\r
1034#endif\r
1035\r
1036#ifdef EVT_LOG\r
1037enum evt {\r
1038 EVT_FRAME_START,\r
1039 EVT_NEXT_LINE,\r
1040 EVT_RUN_START,\r
1041 EVT_RUN_END,\r
1042 EVT_POLL_START,\r
1043 EVT_POLL_END,\r
1044 EVT_CNT\r
1045};\r
1046\r
1047enum evt_cpu {\r
1048 EVT_M68K,\r
1049 EVT_S68K,\r
1050 EVT_MSH2,\r
1051 EVT_SSH2,\r
1052 EVT_CPU_CNT\r
1053};\r
1054\r
1055void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r
1056void pevt_dump(void);\r
1057\r
1058#define pevt_log_m68k(e) \\r
1059 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
1060#define pevt_log_m68k_o(e) \\r
1061 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
1062#define pevt_log_sh2(sh2, e) \\r
1063 pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r
1064#define pevt_log_sh2_o(sh2, e) \\r
1065 pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r
1066#else\r
1067#define pevt_log(c, e)\r
1068#define pevt_log_m68k(e)\r
1069#define pevt_log_m68k_o(e)\r
1070#define pevt_log_sh2(sh2, e)\r
1071#define pevt_log_sh2_o(sh2, e)\r
1072#define pevt_dump()\r
1073#endif\r
1074\r
1075// misc\r
1076#ifdef _MSC_VER\r
1077#define cdprintf\r
1078#else\r
1079#define cdprintf(x...)\r
1080#endif\r
1081\r
1082#if defined(__GNUC__) && defined(__i386__)\r
1083#define REGPARM(x) __attribute__((regparm(x)))\r
1084#else\r
1085#define REGPARM(x)\r
1086#endif\r
1087\r
1088#ifdef __GNUC__\r
1089#define NOINLINE __attribute__((noinline))\r
1090#else\r
1091#define NOINLINE\r
1092#endif\r
1093\r
1094#ifdef __cplusplus\r
1095} // End of extern "C"\r
1096#endif\r
1097\r
1098#endif // PICO_INTERNAL_INCLUDED\r
1099\r
1100// vim:shiftwidth=2:ts=2:expandtab\r
fast MegaDrive/MegaCD/32X emulator