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fix underalloc
[picodrive.git] / pico / pico_int.h
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1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
9\r
10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
12\r
13#include <stdio.h>\r
14#include <stdlib.h>\r
15#include <string.h>\r
16#include "pico.h"\r
17#include "carthw/carthw.h"\r
18\r
19//\r
20#define USE_POLL_DETECT\r
21\r
22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
28\r
29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
35\r
36// ----------------------- 68000 CPU -----------------------\r
37#ifdef EMU_C68K\r
38#include "../cpu/cyclone/Cyclone.h"\r
39extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
40#define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run\r
41#define SekCyclesLeftS68k PicoCpuCS68k.cycles\r
42#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
43#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
44#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
45#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r
46#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
47#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r
48#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
49#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
50#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
51#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
52#define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
53\r
54#define SekNotPolling PicoCpuCM68k.not_pol\r
55#define SekNotPollingS68k PicoCpuCS68k.not_pol\r
56\r
57#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
58#define SekIrqLevel PicoCpuCM68k.irq\r
59\r
60#endif\r
61\r
62#ifdef EMU_F68K\r
63#include "../cpu/fame/fame.h"\r
64extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
65#define SekCyclesLeft PicoCpuFM68k.io_cycle_counter\r
66#define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter\r
67#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
68#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
69#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
70#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r
71#define SekSr PicoCpuFM68k.sr\r
72#define SekSrS68k PicoCpuFS68k.sr\r
73#define SekSetStop(x) { \\r
74 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
75 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
76}\r
77#define SekSetStopS68k(x) { \\r
78 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
79 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
80}\r
81#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
82#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
83#define SekShouldInterrupt() fm68k_would_interrupt()\r
84\r
85#define SekNotPolling PicoCpuFM68k.not_polling\r
86#define SekNotPollingS68k PicoCpuFS68k.not_polling\r
87\r
88#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
89#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
90\r
91#endif\r
92\r
93#ifdef EMU_M68K\r
94#include "../cpu/musashi/m68kcpu.h"\r
95extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
96#ifndef SekCyclesLeft\r
97#define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles\r
98#define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles\r
99#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
100#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
101#define SekDar(x) PicoCpuMM68k.dar[x]\r
102#define SekDarS68k(x) PicoCpuMS68k.dar[x]\r
103#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
104#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r
105#define SekSetStop(x) { \\r
106 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
107 else PicoCpuMM68k.stopped=0; \\r
108}\r
109#define SekSetStopS68k(x) { \\r
110 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
111 else PicoCpuMS68k.stopped=0; \\r
112}\r
113#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
114#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
115#define SekShouldInterrupt() (CPU_INT_LEVEL > FLAG_INT_MASK)\r
116\r
117#define SekNotPolling PicoCpuMM68k.not_polling\r
118#define SekNotPollingS68k PicoCpuMS68k.not_polling\r
119\r
120#define SekInterrupt(irq) { \\r
121 void *oldcontext = m68ki_cpu_p; \\r
122 m68k_set_context(&PicoCpuMM68k); \\r
123 m68k_set_irq(irq); \\r
124 m68k_set_context(oldcontext); \\r
125}\r
126#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
127\r
128#endif\r
129#endif // EMU_M68K\r
130\r
131// while running, cnt represents target of current timeslice\r
132// while not in SekRun(), it's actual cycles done\r
133// (but always use SekCyclesDone() if you need current position)\r
134// cnt may change if timeslice is ended prematurely or extended,\r
135// so we use SekCycleAim for the actual target\r
136extern unsigned int SekCycleCnt;\r
137extern unsigned int SekCycleAim;\r
138\r
139// number of cycles done (can be checked anywhere)\r
140#define SekCyclesDone() (SekCycleCnt - SekCyclesLeft)\r
141\r
142// burn cycles while not in SekRun() and while in\r
143#define SekCyclesBurn(c) SekCycleCnt += c\r
144#define SekCyclesBurnRun(c) { \\r
145 SekCyclesLeft -= c; \\r
146}\r
147\r
148// note: sometimes may extend timeslice to delay an irq\r
149#define SekEndRun(after) { \\r
150 SekCycleCnt -= SekCyclesLeft - (after); \\r
151 SekCyclesLeft = after; \\r
152}\r
153\r
154extern unsigned int SekCycleCntS68k;\r
155extern unsigned int SekCycleAimS68k;\r
156\r
157#define SekEndRunS68k(after) { \\r
158 if (SekCyclesLeftS68k > (after)) { \\r
159 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
160 SekCyclesLeftS68k = after; \\r
161 } \\r
162}\r
163\r
164#define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)\r
165\r
166// compare cycles, handling overflows\r
167// check if a > b\r
168#define CYCLES_GT(a, b) \\r
169 ((int)((a) - (b)) > 0)\r
170// check if a >= b\r
171#define CYCLES_GE(a, b) \\r
172 ((int)((a) - (b)) >= 0)\r
173\r
174// ----------------------- Z80 CPU -----------------------\r
175\r
176#if defined(_USE_DRZ80)\r
177#include "../cpu/DrZ80/drz80.h"\r
178\r
179extern struct DrZ80 drZ80;\r
180\r
181#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
182#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
183#define z80_int() drZ80.Z80_IRQ = 1\r
184#define z80_int() drZ80.Z80_IRQ = 1\r
185#define z80_nmi() drZ80.Z80IF |= 8\r
186\r
187#define z80_cyclesLeft drZ80.cycles\r
188#define z80_subCLeft(c) drZ80.cycles -= c\r
189#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
190\r
191#elif defined(_USE_CZ80)\r
192#include "../cpu/cz80/cz80.h"\r
193\r
194#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
195#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
196#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
197#define z80_nmi() Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, 0)\r
198\r
199#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
200#define z80_subCLeft(c) CZ80.ICount -= c\r
201#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
202\r
203#else\r
204\r
205#define z80_run(cycles) (cycles)\r
206#define z80_run_nr(cycles)\r
207#define z80_int()\r
208#define z80_nmi()\r
209\r
210#endif\r
211\r
212#define Z80_STATE_SIZE 0x60\r
213\r
214extern unsigned int last_z80_sync;\r
215extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
216extern int z80_cycle_aim;\r
217extern int z80_scanline;\r
218extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
219\r
220#define z80_resetCycles() \\r
221 last_z80_sync = SekCyclesDone(); \\r
222 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
223\r
224#define z80_cyclesDone() \\r
225 (z80_cycle_aim - z80_cyclesLeft)\r
226\r
227#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
228\r
229// ----------------------- SH2 CPU -----------------------\r
230\r
231#include "cpu/sh2/sh2.h"\r
232\r
233extern SH2 sh2s[2];\r
234#define msh2 sh2s[0]\r
235#define ssh2 sh2s[1]\r
236\r
237#ifndef DRC_SH2\r
238# define sh2_end_run(sh2, after_) do { \\r
239 if ((sh2)->icount > (after_)) { \\r
240 (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
241 (sh2)->icount = after_; \\r
242 } \\r
243} while (0)\r
244# define sh2_cycles_left(sh2) (sh2)->icount\r
245# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
246# define sh2_pc(sh2) (sh2)->ppc\r
247#else\r
248# define sh2_end_run(sh2, after_) do { \\r
249 int left_ = (signed int)(sh2)->sr >> 12; \\r
250 if (left_ > (after_)) { \\r
251 (sh2)->cycles_timeslice -= left_ - (after_); \\r
252 (sh2)->sr &= 0xfff; \\r
253 (sh2)->sr |= (after_) << 12; \\r
254 } \\r
255} while (0)\r
256# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
257# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
258# define sh2_pc(sh2) (sh2)->pc\r
259#endif\r
260\r
261#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
262#define sh2_cycles_done_t(sh2) \\r
263 ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
264#define sh2_cycles_done_m68k(sh2) \\r
265 ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
266\r
267#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
268#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
269#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
270#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
271\r
272#define sh2_set_gbr(c, v) \\r
273 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
274#define sh2_set_vbr(c, v) \\r
275 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
276\r
277#define elprintf_sh2(sh2, w, f, ...) \\r
278 elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
279\r
280// ---------------------------------------------------------\r
281\r
282// main oscillator clock which controls timing\r
283#define OSC_NTSC 53693100\r
284#define OSC_PAL 53203424\r
285\r
286#define PVD_KILL_A (1 << 0)\r
287#define PVD_KILL_B (1 << 1)\r
288#define PVD_KILL_S_LO (1 << 2)\r
289#define PVD_KILL_S_HI (1 << 3)\r
290#define PVD_KILL_32X (1 << 4)\r
291#define PVD_FORCE_A (1 << 5)\r
292#define PVD_FORCE_B (1 << 6)\r
293#define PVD_FORCE_S (1 << 7)\r
294\r
295struct PicoVideo\r
296{\r
297 unsigned char reg[0x20];\r
298 unsigned int command; // 32-bit Command\r
299 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
300 unsigned char type; // Command type (v/c/vsram read/write)\r
301 unsigned short addr; // Read/Write address\r
302 int status; // Status bits\r
303 unsigned char pending_ints; // pending interrupts: ??VH????\r
304 signed char lwrite_cnt; // VDP write count during active display line\r
305 unsigned short v_counter; // V-counter\r
306 unsigned short debug; // raw debug register\r
307 unsigned char debug_p; // ... parsed: PVD_*\r
308 unsigned char addr_u;\r
309 unsigned char pad[0x0c];\r
310};\r
311\r
312struct PicoMisc\r
313{\r
314 unsigned char rotate;\r
315 unsigned char z80Run;\r
316 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
317 unsigned short scanline; // 04 0 to 261||311\r
318 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
319 unsigned char hardware; // 07 Hardware value for country\r
320 unsigned char pal; // 08 1=PAL 0=NTSC\r
321 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
322 unsigned short z80_bank68k; // 0a\r
323 unsigned short pad0;\r
324 unsigned char ncart_in; // 0e !cart_in\r
325 unsigned char z80_reset; // 0f z80 reset held\r
326 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
327 unsigned short eeprom_addr; // EEPROM address register\r
328 unsigned char eeprom_cycle; // EEPROM cycle number\r
329 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
330 unsigned char eeprom_status;\r
331 unsigned char pad2;\r
332 unsigned short dma_xfers; // 18\r
333 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
334 unsigned int frame_count; // 1c for movies and idle det\r
335};\r
336\r
337struct PicoMS\r
338{\r
339 unsigned char carthw[0x10];\r
340 unsigned char io_ctl;\r
341 unsigned char nmi_state;\r
342 unsigned char pad[0x4e];\r
343};\r
344\r
345// emu state and data for the asm code\r
346struct PicoEState\r
347{\r
348 int DrawScanline;\r
349 int rendstatus;\r
350 void *DrawLineDest; // draw destination\r
351 unsigned char *HighCol;\r
352 int *HighPreSpr;\r
353 void *Pico_video;\r
354 void *Pico_vram;\r
355 int *PicoOpt;\r
356 unsigned char *Draw2FB;\r
357 unsigned short HighPal[0x100];\r
358};\r
359\r
360// some assembly stuff depend on these, do not touch!\r
361struct Pico\r
362{\r
363 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
364 union { // vram is byteswapped for easier reads when drawing\r
365 unsigned short vram[0x8000]; // 0x10000\r
366 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
367 };\r
368 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
369 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
370 unsigned char pad[0xf0]; // unused\r
371 unsigned short cram[0x40]; // 0x22100\r
372 unsigned short vsram[0x40]; // 0x22180\r
373\r
374 unsigned char *rom; // 0x22200\r
375 unsigned int romsize; // 0x22204 (on 32bits)\r
376\r
377 struct PicoMisc m;\r
378 struct PicoVideo video;\r
379 struct PicoMS ms;\r
380 struct PicoEState est;\r
381};\r
382\r
383// sram\r
384#define SRR_MAPPED (1 << 0)\r
385#define SRR_READONLY (1 << 1)\r
386\r
387#define SRF_ENABLED (1 << 0)\r
388#define SRF_EEPROM (1 << 1)\r
389\r
390struct PicoSRAM\r
391{\r
392 unsigned char *data; // actual data\r
393 unsigned int start; // start address in 68k address space\r
394 unsigned int end;\r
395 unsigned char flags; // 0c: SRF_*\r
396 unsigned char unused2;\r
397 unsigned char changed;\r
398 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
399 unsigned char unused3;\r
400 unsigned char eeprom_bit_cl; // bit number for cl\r
401 unsigned char eeprom_bit_in; // bit number for in\r
402 unsigned char eeprom_bit_out; // bit number for out\r
403 unsigned int size;\r
404};\r
405\r
406// MCD\r
407#define PCM_MIXBUF_LEN ((12500000 / 384) / 50 + 1)\r
408\r
409struct mcd_pcm\r
410{\r
411 unsigned char control; // reg7\r
412 unsigned char enabled; // reg8\r
413 unsigned char cur_ch;\r
414 unsigned char bank;\r
415 unsigned int update_cycles;\r
416\r
417 struct pcm_chan // 08, size 0x10\r
418 {\r
419 unsigned char regs[8];\r
420 unsigned int addr; // .08: played sample address\r
421 int pad;\r
422 } ch[8];\r
423};\r
424\r
425#define PCD_ST_S68K_RST 1\r
426\r
427struct mcd_misc\r
428{\r
429 unsigned short hint_vector;\r
430 unsigned char busreq; // not s68k_regs[1]\r
431 unsigned char s68k_pend_ints;\r
432 unsigned int state_flags; // 04\r
433 unsigned int stopwatch_base_c;\r
434 unsigned short m68k_poll_a;\r
435 unsigned short m68k_poll_cnt;\r
436 unsigned short s68k_poll_a;\r
437 unsigned short s68k_poll_cnt;\r
438 unsigned int s68k_poll_clk;\r
439 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
440 unsigned char dmna_ret_2m;\r
441 unsigned char need_sync;\r
442 unsigned char pad3;\r
443 int pad4[9];\r
444};\r
445\r
446typedef struct\r
447{\r
448 unsigned char bios[0x20000]; // 000000: 128K\r
449 union { // 020000: 512K\r
450 unsigned char prg_ram[0x80000];\r
451 unsigned char prg_ram_b[4][0x20000];\r
452 };\r
453 union { // 0a0000: 256K\r
454 struct {\r
455 unsigned char word_ram2M[0x40000];\r
456 unsigned char unused0[0x20000];\r
457 };\r
458 struct {\r
459 unsigned char unused1[0x20000];\r
460 unsigned char word_ram1M[2][0x20000];\r
461 };\r
462 };\r
463 union { // 100000: 64K\r
464 unsigned char pcm_ram[0x10000];\r
465 unsigned char pcm_ram_b[0x10][0x1000];\r
466 };\r
467 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
468 unsigned char bram[0x2000]; // 110200: 8K\r
469 struct mcd_misc m; // 112200: misc\r
470 struct mcd_pcm pcm; // 112240:\r
471 void *cdda_stream;\r
472 int cdda_type;\r
473 int pcm_mixbuf[PCM_MIXBUF_LEN * 2];\r
474 int pcm_mixpos;\r
475 char pcm_mixbuf_dirty;\r
476 char pcm_regs_dirty;\r
477} mcd_state;\r
478\r
479// XXX: this will need to be reworked for cart+cd support.\r
480#define Pico_mcd ((mcd_state *)Pico.rom)\r
481\r
482// 32X\r
483#define P32XS_FM (1<<15)\r
484#define P32XS_nCART (1<< 8)\r
485#define P32XS_REN (1<< 7)\r
486#define P32XS_nRES (1<< 1)\r
487#define P32XS_ADEN (1<< 0)\r
488#define P32XS2_ADEN (1<< 9)\r
489#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
490#define P32XS_68S (1<< 2)\r
491#define P32XS_DMA (1<< 1)\r
492#define P32XS_RV (1<< 0)\r
493\r
494#define P32XV_nPAL (1<<15) // VDP\r
495#define P32XV_PRI (1<< 7)\r
496#define P32XV_Mx (3<< 0) // display mode mask\r
497\r
498#define P32XV_SFT (1<< 0)\r
499\r
500#define P32XV_VBLK (1<<15)\r
501#define P32XV_HBLK (1<<14)\r
502#define P32XV_PEN (1<<13)\r
503#define P32XV_nFEN (1<< 1)\r
504#define P32XV_FS (1<< 0)\r
505\r
506#define P32XP_RTP (1<<7) // PWM control\r
507#define P32XP_FULL (1<<15) // PWM pulse\r
508#define P32XP_EMPTY (1<<14)\r
509\r
510#define P32XF_68KCPOLL (1 << 0)\r
511#define P32XF_68KVPOLL (1 << 1)\r
512#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
513\r
514#define P32XI_VRES (1 << 14/2) // IRL/2\r
515#define P32XI_VINT (1 << 12/2)\r
516#define P32XI_HINT (1 << 10/2)\r
517#define P32XI_CMD (1 << 8/2)\r
518#define P32XI_PWM (1 << 6/2)\r
519\r
520// peripheral reg access\r
521#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
522\r
523#define DMAC_FIFO_LEN (4*2)\r
524#define PWM_BUFF_LEN 1024 // in one channel samples\r
525\r
526#define SH2_DRCBLK_RAM_SHIFT 1\r
527#define SH2_DRCBLK_DA_SHIFT 1\r
528\r
529#define SH2_READ_SHIFT 25\r
530#define SH2_WRITE_SHIFT 25\r
531\r
532struct Pico32x\r
533{\r
534 unsigned short regs[0x20];\r
535 unsigned short vdp_regs[0x10]; // 0x40\r
536 unsigned short sh2_regs[3]; // 0x60\r
537 unsigned char pending_fb;\r
538 unsigned char dirty_pal;\r
539 unsigned int emu_flags;\r
540 unsigned char sh2irq_mask[2];\r
541 unsigned char sh2irqi[2]; // individual\r
542 unsigned int sh2irqs; // common irqs\r
543 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
544 unsigned int pad[4];\r
545 unsigned int dmac0_fifo_ptr;\r
546 unsigned short vdp_fbcr_fake;\r
547 unsigned short pad2;\r
548 unsigned char comm_dirty_68k;\r
549 unsigned char comm_dirty_sh2;\r
550 unsigned char pwm_irq_cnt;\r
551 unsigned char pad1;\r
552 unsigned short pwm_p[2]; // pwm pos in fifo\r
553 unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
554 unsigned int reserved[6];\r
555};\r
556\r
557struct Pico32xMem\r
558{\r
559 unsigned char sdram[0x40000];\r
560#ifdef DRC_SH2\r
561 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
562#endif\r
563 unsigned short dram[2][0x20000/2]; // AKA fb\r
564 union {\r
565 unsigned char m68k_rom[0x100];\r
566 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
567 };\r
568#ifdef DRC_SH2\r
569 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
570#endif\r
571 union {\r
572 unsigned char b[0x800];\r
573 unsigned short w[0x800/2];\r
574 } sh2_rom_m;\r
575 union {\r
576 unsigned char b[0x400];\r
577 unsigned short w[0x400/2];\r
578 } sh2_rom_s;\r
579 unsigned short pal[0x100];\r
580 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
581 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
582 signed short pwm_current[2]; // current converted samples\r
583 unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries\r
584};\r
585\r
586// area.c\r
587extern void (*PicoLoadStateHook)(void);\r
588\r
589typedef struct {\r
590 int chunk;\r
591 int size;\r
592 void *ptr;\r
593} carthw_state_chunk;\r
594extern carthw_state_chunk *carthw_chunks;\r
595#define CHUNK_CARTHW 64\r
596\r
597// cart.c\r
598extern int PicoCartResize(int newsize);\r
599extern void Byteswap(void *dst, const void *src, int len);\r
600extern void (*PicoCartMemSetup)(void);\r
601extern void (*PicoCartUnloadHook)(void);\r
602\r
603// debug.c\r
604int CM_compareRun(int cyc, int is_sub);\r
605\r
606// draw.c\r
607void PicoDrawInit(void);\r
608PICO_INTERNAL void PicoFrameStart(void);\r
609void PicoDrawSync(int to, int blank_last_line);\r
610void BackFill(int reg7, int sh, struct PicoEState *est);\r
611void FinalizeLine555(int sh, int line, struct PicoEState *est);\r
612extern int (*PicoScanBegin)(unsigned int num);\r
613extern int (*PicoScanEnd)(unsigned int num);\r
614#define MAX_LINE_SPRITES 29\r
615extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
616extern void *DrawLineDestBase;\r
617extern int DrawLineDestIncrement;\r
618\r
619// draw2.c\r
620void PicoDraw2Init(void);\r
621PICO_INTERNAL void PicoFrameFull();\r
622\r
623// mode4.c\r
624void PicoFrameStartMode4(void);\r
625void PicoLineMode4(int line);\r
626void PicoDoHighPal555M4(void);\r
627void PicoDrawSetOutputMode4(pdso_t which);\r
628\r
629// memory.c\r
630PICO_INTERNAL void PicoMemSetup(void);\r
631unsigned int PicoRead8_io(unsigned int a);\r
632unsigned int PicoRead16_io(unsigned int a);\r
633void PicoWrite8_io(unsigned int a, unsigned int d);\r
634void PicoWrite16_io(unsigned int a, unsigned int d);\r
635\r
636// pico/memory.c\r
637PICO_INTERNAL void PicoMemSetupPico(void);\r
638\r
639// cd/cdc.c\r
640void cdc_init(void);\r
641void cdc_reset(void);\r
642int cdc_context_save(unsigned char *state);\r
643int cdc_context_load(unsigned char *state);\r
644int cdc_context_load_old(unsigned char *state);\r
645void cdc_dma_update(void);\r
646int cdc_decoder_update(unsigned char header[4]);\r
647void cdc_reg_w(unsigned char data);\r
648unsigned char cdc_reg_r(void);\r
649unsigned short cdc_host_r(void);\r
650\r
651// cd/cdd.c\r
652void cdd_reset(void);\r
653int cdd_context_save(unsigned char *state);\r
654int cdd_context_load(unsigned char *state);\r
655int cdd_context_load_old(unsigned char *state);\r
656void cdd_read_data(unsigned char *dst);\r
657void cdd_read_audio(unsigned int samples);\r
658void cdd_update(void);\r
659void cdd_process(void);\r
660\r
661// cd/cd_image.c\r
662int load_cd_image(const char *cd_img_name, int *type);\r
663\r
664// cd/gfx.c\r
665void gfx_init(void);\r
666void gfx_start(unsigned int base);\r
667void gfx_update(unsigned int cycles);\r
668int gfx_context_save(unsigned char *state);\r
669int gfx_context_load(const unsigned char *state);\r
670\r
671// cd/gfx_dma.c\r
672void DmaSlowCell(unsigned int source, unsigned int a, int len, unsigned char inc);\r
673\r
674// cd/memory.c\r
675PICO_INTERNAL void PicoMemSetupCD(void);\r
676unsigned int PicoRead8_mcd_io(unsigned int a);\r
677unsigned int PicoRead16_mcd_io(unsigned int a);\r
678void PicoWrite8_mcd_io(unsigned int a, unsigned int d);\r
679void PicoWrite16_mcd_io(unsigned int a, unsigned int d);\r
680void pcd_state_loaded_mem(void);\r
681\r
682// pico.c\r
683extern struct Pico Pico;\r
684extern struct PicoSRAM SRam;\r
685extern int PicoPadInt[2];\r
686extern int emustatus;\r
687extern int scanlines_total;\r
688extern void (*PicoResetHook)(void);\r
689extern void (*PicoLineHook)(void);\r
690PICO_INTERNAL int CheckDMA(void);\r
691PICO_INTERNAL void PicoDetectRegion(void);\r
692PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);\r
693\r
694// cd/mcd.c\r
695#define PCDS_IEN1 (1<<1)\r
696#define PCDS_IEN2 (1<<2)\r
697#define PCDS_IEN3 (1<<3)\r
698#define PCDS_IEN4 (1<<4)\r
699#define PCDS_IEN5 (1<<5)\r
700#define PCDS_IEN6 (1<<6)\r
701\r
702PICO_INTERNAL void PicoInitMCD(void);\r
703PICO_INTERNAL void PicoExitMCD(void);\r
704PICO_INTERNAL void PicoPowerMCD(void);\r
705PICO_INTERNAL int PicoResetMCD(void);\r
706PICO_INTERNAL void PicoFrameMCD(void);\r
707\r
708enum pcd_event {\r
709 PCD_EVENT_CDC,\r
710 PCD_EVENT_TIMER3,\r
711 PCD_EVENT_GFX,\r
712 PCD_EVENT_DMA,\r
713 PCD_EVENT_COUNT,\r
714};\r
715extern unsigned int pcd_event_times[PCD_EVENT_COUNT];\r
716void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);\r
717void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
718void pcd_prepare_frame(void);\r
719unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
720int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);\r
721void pcd_run_cpus(int m68k_cycles);\r
722void pcd_soft_reset(void);\r
723void pcd_state_loaded(void);\r
724\r
725// cd/pcm.c\r
726void pcd_pcm_sync(unsigned int to);\r
727void pcd_pcm_update(int *buffer, int length, int stereo);\r
728void pcd_pcm_write(unsigned int a, unsigned int d);\r
729unsigned int pcd_pcm_read(unsigned int a);\r
730\r
731// pico/pico.c\r
732PICO_INTERNAL void PicoInitPico(void);\r
733PICO_INTERNAL void PicoReratePico(void);\r
734\r
735// pico/xpcm.c\r
736PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
737PICO_INTERNAL void PicoPicoPCMReset(void);\r
738PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
739\r
740// sek.c\r
741PICO_INTERNAL void SekInit(void);\r
742PICO_INTERNAL int SekReset(void);\r
743PICO_INTERNAL void SekState(int *data);\r
744PICO_INTERNAL void SekSetRealTAS(int use_real);\r
745PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
746PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
747void SekStepM68k(void);\r
748void SekInitIdleDet(void);\r
749void SekFinishIdleDet(void);\r
750#if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r
751void SekTrace(int is_s68k);\r
752#else\r
753#define SekTrace(x)\r
754#endif\r
755\r
756// cd/sek.c\r
757PICO_INTERNAL void SekInitS68k(void);\r
758PICO_INTERNAL int SekResetS68k(void);\r
759PICO_INTERNAL int SekInterruptS68k(int irq);\r
760void SekInterruptClearS68k(int irq);\r
761\r
762// sound/sound.c\r
763extern short cdda_out_buffer[2*1152];\r
764extern int PsndLen_exc_cnt;\r
765extern int PsndLen_exc_add;\r
766extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
767extern int timer_b_next_oflow, timer_b_step;\r
768\r
769void cdda_start_play(int lba_base, int lba_offset, int lb_len);\r
770\r
771void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
772void ym2612_pack_state(void);\r
773void ym2612_unpack_state(void);\r
774\r
775#define TIMER_NO_OFLOW 0x70000000\r
776// tA = 72 * (1024 - NA) / M\r
777#define TIMER_A_TICK_ZCYCLES 17203\r
778// tB = 1152 * (256 - NA) / M\r
779#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
780\r
781#define timers_cycle() \\r
782 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
783 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
784 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
785 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
786 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
787\r
788#define timers_reset() \\r
789 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
790 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
791 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
792\r
793\r
794// videoport.c\r
795extern int line_base_cycles;\r
796PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
797PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
798unsigned char PicoVideoRead8DataH(void);\r
799unsigned char PicoVideoRead8DataL(void);\r
800unsigned char PicoVideoRead8CtlH(void);\r
801unsigned char PicoVideoRead8CtlL(void);\r
802unsigned char PicoVideoRead8HV_H(void);\r
803unsigned char PicoVideoRead8HV_L(void);\r
804extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned int *mask);\r
805\r
806// misc.c\r
807PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
808PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
809PICO_INTERNAL_ASM void memcpy32(void *dest, const void *src, int count); // 32bit word count\r
810PICO_INTERNAL_ASM void memset32(void *dest, int c, int count);\r
811\r
812// eeprom.c\r
813void EEPROM_write8(unsigned int a, unsigned int d);\r
814void EEPROM_write16(unsigned int d);\r
815unsigned int EEPROM_read(void);\r
816\r
817// z80 functionality wrappers\r
818PICO_INTERNAL void z80_init(void);\r
819PICO_INTERNAL void z80_pack(void *data);\r
820PICO_INTERNAL int z80_unpack(const void *data);\r
821PICO_INTERNAL void z80_reset(void);\r
822PICO_INTERNAL void z80_exit(void);\r
823\r
824// cd/misc.c\r
825PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
826PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
827\r
828// sound/sound.c\r
829PICO_INTERNAL void PsndReset(void);\r
830PICO_INTERNAL void PsndStartFrame(void);\r
831PICO_INTERNAL void PsndDoDAC(int line_to);\r
832PICO_INTERNAL void PsndDoPSG(int line_to);\r
833PICO_INTERNAL void PsndClear(void);\r
834PICO_INTERNAL void PsndGetSamples(int y);\r
835PICO_INTERNAL void PsndGetSamplesMS(void);\r
836extern int PsndDacLine, PsndPsgLine;\r
837\r
838// sms.c\r
839#ifndef NO_SMS\r
840void PicoPowerMS(void);\r
841void PicoResetMS(void);\r
842void PicoMemSetupMS(void);\r
843void PicoStateLoadedMS(void);\r
844void PicoFrameMS(void);\r
845void PicoFrameDrawOnlyMS(void);\r
846#else\r
847#define PicoPowerMS()\r
848#define PicoResetMS()\r
849#define PicoMemSetupMS()\r
850#define PicoStateLoadedMS()\r
851#define PicoFrameMS()\r
852#define PicoFrameDrawOnlyMS()\r
853#endif\r
854\r
855// 32x/32x.c\r
856#ifndef NO_32X\r
857extern struct Pico32x Pico32x;\r
858enum p32x_event {\r
859 P32X_EVENT_PWM,\r
860 P32X_EVENT_FILLEND,\r
861 P32X_EVENT_HINT,\r
862 P32X_EVENT_COUNT,\r
863};\r
864extern unsigned int p32x_event_times[P32X_EVENT_COUNT];\r
865\r
866void Pico32xInit(void);\r
867void PicoPower32x(void);\r
868void PicoReset32x(void);\r
869void Pico32xStartup(void);\r
870void PicoUnload32x(void);\r
871void PicoFrame32x(void);\r
872void Pico32xStateLoaded(int is_early);\r
873void p32x_sync_sh2s(unsigned int m68k_target);\r
874void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
875void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
876void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);\r
877void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);\r
878void p32x_reset_sh2s(void);\r
879void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
880void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
881void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
882\r
883// 32x/memory.c\r
884struct Pico32xMem *Pico32xMem;\r
885unsigned int PicoRead8_32x(unsigned int a);\r
886unsigned int PicoRead16_32x(unsigned int a);\r
887void PicoWrite8_32x(unsigned int a, unsigned int d);\r
888void PicoWrite16_32x(unsigned int a, unsigned int d);\r
889void PicoMemSetup32x(void);\r
890void Pico32xSwapDRAM(int b);\r
891void Pico32xMemStateLoaded(void);\r
892void p32x_m68k_poll_event(unsigned int flags);\r
893void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r
894\r
895// 32x/draw.c\r
896void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r
897void FinalizeLine32xRGB555(int sh, int line, struct PicoEState *est);\r
898void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
899void PicoDraw32xLayerMdOnly(int offs, int lines);\r
900extern int (*PicoScan32xBegin)(unsigned int num);\r
901extern int (*PicoScan32xEnd)(unsigned int num);\r
902enum {\r
903 PDM32X_OFF,\r
904 PDM32X_32X_ONLY,\r
905 PDM32X_BOTH,\r
906};\r
907extern int Pico32xDrawMode;\r
908\r
909// 32x/pwm.c\r
910unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
911 unsigned int m68k_cycles);\r
912void p32x_pwm_write16(unsigned int a, unsigned int d,\r
913 SH2 *sh2, unsigned int m68k_cycles);\r
914void p32x_pwm_update(int *buf32, int length, int stereo);\r
915void p32x_pwm_ctl_changed(void);\r
916void p32x_pwm_schedule(unsigned int m68k_now);\r
917void p32x_pwm_schedule_sh2(SH2 *sh2);\r
918void p32x_pwm_sync_to_sh2(SH2 *sh2);\r
919void p32x_pwm_irq_event(unsigned int m68k_now);\r
920void p32x_pwm_state_loaded(void);\r
921\r
922// 32x/sh2soc.c\r
923void p32x_dreq0_trigger(void);\r
924void p32x_dreq1_trigger(void);\r
925void p32x_timers_recalc(void);\r
926void p32x_timers_do(unsigned int m68k_slice);\r
927void sh2_peripheral_reset(SH2 *sh2);\r
928unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
929unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
930unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
931void REGPARM(3) sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
932void REGPARM(3) sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
933void REGPARM(3) sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
934\r
935#else\r
936#define Pico32xInit()\r
937#define PicoPower32x()\r
938#define PicoReset32x()\r
939#define PicoFrame32x()\r
940#define PicoUnload32x()\r
941#define Pico32xStateLoaded()\r
942#define FinalizeLine32xRGB555 NULL\r
943#define p32x_pwm_update(...)\r
944#define p32x_timers_recalc()\r
945#endif\r
946\r
947/* avoid dependency on newer glibc */\r
948static __inline int isspace_(int c)\r
949{\r
950 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
951}\r
952\r
953#ifndef ARRAY_SIZE\r
954#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
955#endif\r
956\r
957// emulation event logging\r
958#ifndef EL_LOGMASK\r
959# ifdef __x86_64__ // HACK\r
960# define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r
961# else\r
962# define EL_LOGMASK (EL_STATUS)\r
963# endif\r
964#endif\r
965\r
966#define EL_HVCNT 0x00000001 /* hv counter reads */\r
967#define EL_SR 0x00000002 /* SR reads */\r
968#define EL_INTS 0x00000004 /* ints and acks */\r
969#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
970#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
971#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
972#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
973#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
974#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
975#define EL_SRAMIO 0x00000200 /* sram i/o */\r
976#define EL_EEPROM 0x00000400 /* eeprom debug */\r
977#define EL_UIO 0x00000800 /* unmapped i/o */\r
978#define EL_IO 0x00001000 /* all i/o */\r
979#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
980#define EL_SVP 0x00004000 /* SVP stuff */\r
981#define EL_PICOHW 0x00008000 /* Pico stuff */\r
982#define EL_IDLE 0x00010000 /* idle loop det. */\r
983#define EL_CDREGS 0x00020000 /* MCD: register access */\r
984#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
985#define EL_32X 0x00080000\r
986#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
987#define EL_32XP 0x00200000 /* 32X peripherals */\r
988#define EL_CD 0x00400000 /* MCD */\r
989\r
990#define EL_STATUS 0x40000000 /* status messages */\r
991#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
992\r
993#if EL_LOGMASK\r
994#define elprintf(w,f,...) \\r
995do { \\r
996 if ((w) & EL_LOGMASK) \\r
997 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
998} while (0)\r
999#elif defined(_MSC_VER)\r
1000#define elprintf\r
1001#else\r
1002#define elprintf(w,f,...)\r
1003#endif\r
1004\r
1005// profiling\r
1006#ifdef PPROF\r
1007#include <platform/linux/pprof.h>\r
1008#else\r
1009#define pprof_init()\r
1010#define pprof_finish()\r
1011#define pprof_start(x)\r
1012#define pprof_end(...)\r
1013#define pprof_end_sub(...)\r
1014#endif\r
1015\r
1016#ifdef EVT_LOG\r
1017enum evt {\r
1018 EVT_FRAME_START,\r
1019 EVT_NEXT_LINE,\r
1020 EVT_RUN_START,\r
1021 EVT_RUN_END,\r
1022 EVT_POLL_START,\r
1023 EVT_POLL_END,\r
1024 EVT_CNT\r
1025};\r
1026\r
1027enum evt_cpu {\r
1028 EVT_M68K,\r
1029 EVT_S68K,\r
1030 EVT_MSH2,\r
1031 EVT_SSH2,\r
1032 EVT_CPU_CNT\r
1033};\r
1034\r
1035void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r
1036void pevt_dump(void);\r
1037\r
1038#define pevt_log_m68k(e) \\r
1039 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
1040#define pevt_log_m68k_o(e) \\r
1041 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
1042#define pevt_log_sh2(sh2, e) \\r
1043 pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r
1044#define pevt_log_sh2_o(sh2, e) \\r
1045 pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r
1046#else\r
1047#define pevt_log(c, e)\r
1048#define pevt_log_m68k(e)\r
1049#define pevt_log_m68k_o(e)\r
1050#define pevt_log_sh2(sh2, e)\r
1051#define pevt_log_sh2_o(sh2, e)\r
1052#define pevt_dump()\r
1053#endif\r
1054\r
1055// misc\r
1056#ifdef _MSC_VER\r
1057#define cdprintf\r
1058#else\r
1059#define cdprintf(x...)\r
1060#endif\r
1061\r
1062#if defined(__GNUC__) && defined(__i386__)\r
1063#define REGPARM(x) __attribute__((regparm(x)))\r
1064#else\r
1065#define REGPARM(x)\r
1066#endif\r
1067\r
1068#ifdef __GNUC__\r
1069#define NOINLINE __attribute__((noinline))\r
1070#else\r
1071#define NOINLINE\r
1072#endif\r
1073\r
1074#ifdef __cplusplus\r
1075} // End of extern "C"\r
1076#endif\r
1077\r
1078#endif // PICO_INTERNAL_INCLUDED\r
1079\r
fast MegaDrive/MegaCD/32X emulator