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1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
9\r
10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
12\r
13#include <stdio.h>\r
14#include <stdlib.h>\r
15#include <string.h>\r
16#include "pico.h"\r
17#include "carthw/carthw.h"\r
18\r
19//\r
20#define USE_POLL_DETECT\r
21\r
22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
28\r
29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
35#ifdef _MSC_VER\r
36#define snprintf _snprintf\r
37#define strcasecmp _stricmp\r
38#define strncasecmp _strnicmp\r
39#endif\r
40\r
41// ----------------------- 68000 CPU -----------------------\r
42#ifdef EMU_C68K\r
43#include "../cpu/cyclone/Cyclone.h"\r
44extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
45#define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run\r
46#define SekCyclesLeftS68k PicoCpuCS68k.cycles\r
47#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
48#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
49#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
50#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r
51#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
52#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r
53#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
54#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
55#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
56#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
57#define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
58\r
59#define SekNotPolling PicoCpuCM68k.not_pol\r
60#define SekNotPollingS68k PicoCpuCS68k.not_pol\r
61\r
62#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
63#define SekIrqLevel PicoCpuCM68k.irq\r
64\r
65#endif\r
66\r
67#ifdef EMU_F68K\r
68#include "../cpu/fame/fame.h"\r
69extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
70#define SekCyclesLeft PicoCpuFM68k.io_cycle_counter\r
71#define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter\r
72#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
73#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
74#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
75#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r
76#define SekSr PicoCpuFM68k.sr\r
77#define SekSrS68k PicoCpuFS68k.sr\r
78#define SekSetStop(x) { \\r
79 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
80 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
81}\r
82#define SekSetStopS68k(x) { \\r
83 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
84 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
85}\r
86#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
87#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
88#define SekShouldInterrupt() fm68k_would_interrupt()\r
89\r
90#define SekNotPolling PicoCpuFM68k.not_polling\r
91#define SekNotPollingS68k PicoCpuFS68k.not_polling\r
92\r
93#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
94#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
95\r
96#endif\r
97\r
98#ifdef EMU_M68K\r
99#include "../cpu/musashi/m68kcpu.h"\r
100extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
101#ifndef SekCyclesLeft\r
102#define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles\r
103#define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles\r
104#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
105#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
106#define SekDar(x) PicoCpuMM68k.dar[x]\r
107#define SekDarS68k(x) PicoCpuMS68k.dar[x]\r
108#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
109#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r
110#define SekSetStop(x) { \\r
111 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
112 else PicoCpuMM68k.stopped=0; \\r
113}\r
114#define SekSetStopS68k(x) { \\r
115 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
116 else PicoCpuMS68k.stopped=0; \\r
117}\r
118#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
119#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
120#define SekShouldInterrupt() (CPU_INT_LEVEL > FLAG_INT_MASK)\r
121\r
122#define SekNotPolling PicoCpuMM68k.not_polling\r
123#define SekNotPollingS68k PicoCpuMS68k.not_polling\r
124\r
125#define SekInterrupt(irq) { \\r
126 void *oldcontext = m68ki_cpu_p; \\r
127 m68k_set_context(&PicoCpuMM68k); \\r
128 m68k_set_irq(irq); \\r
129 m68k_set_context(oldcontext); \\r
130}\r
131#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
132\r
133#endif\r
134#endif // EMU_M68K\r
135\r
136// while running, cnt represents target of current timeslice\r
137// while not in SekRun(), it's actual cycles done\r
138// (but always use SekCyclesDone() if you need current position)\r
139// cnt may change if timeslice is ended prematurely or extended,\r
140// so we use SekCycleAim for the actual target\r
141extern unsigned int SekCycleCnt;\r
142extern unsigned int SekCycleAim;\r
143\r
144// number of cycles done (can be checked anywhere)\r
145#define SekCyclesDone() (SekCycleCnt - SekCyclesLeft)\r
146\r
147// burn cycles while not in SekRun() and while in\r
148#define SekCyclesBurn(c) SekCycleCnt += c\r
149#define SekCyclesBurnRun(c) { \\r
150 SekCyclesLeft -= c; \\r
151}\r
152\r
153// note: sometimes may extend timeslice to delay an irq\r
154#define SekEndRun(after) { \\r
155 SekCycleCnt -= SekCyclesLeft - (after); \\r
156 SekCyclesLeft = after; \\r
157}\r
158\r
159extern unsigned int SekCycleCntS68k;\r
160extern unsigned int SekCycleAimS68k;\r
161\r
162#define SekEndRunS68k(after) { \\r
163 if (SekCyclesLeftS68k > (after)) { \\r
164 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
165 SekCyclesLeftS68k = after; \\r
166 } \\r
167}\r
168\r
169#define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)\r
170\r
171// compare cycles, handling overflows\r
172// check if a > b\r
173#define CYCLES_GT(a, b) \\r
174 ((int)((a) - (b)) > 0)\r
175// check if a >= b\r
176#define CYCLES_GE(a, b) \\r
177 ((int)((a) - (b)) >= 0)\r
178\r
179// ----------------------- Z80 CPU -----------------------\r
180\r
181#if defined(_USE_DRZ80)\r
182#include "../cpu/DrZ80/drz80.h"\r
183\r
184extern struct DrZ80 drZ80;\r
185\r
186#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
187#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
188#define z80_int() drZ80.Z80_IRQ = 1\r
189#define z80_int() drZ80.Z80_IRQ = 1\r
190#define z80_nmi() drZ80.Z80IF |= 8\r
191\r
192#define z80_cyclesLeft drZ80.cycles\r
193#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
194\r
195#elif defined(_USE_CZ80)\r
196#include "../cpu/cz80/cz80.h"\r
197\r
198#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
199#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
200#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
201#define z80_nmi() Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, 0)\r
202\r
203#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
204#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
205\r
206#else\r
207\r
208#define z80_run(cycles) (cycles)\r
209#define z80_run_nr(cycles)\r
210#define z80_int()\r
211#define z80_nmi()\r
212\r
213#endif\r
214\r
215#define Z80_STATE_SIZE 0x60\r
216\r
217extern unsigned int last_z80_sync;\r
218extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
219extern int z80_cycle_aim;\r
220extern int z80_scanline;\r
221extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
222\r
223#define z80_resetCycles() \\r
224 last_z80_sync = SekCyclesDone(); \\r
225 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
226\r
227#define z80_cyclesDone() \\r
228 (z80_cycle_aim - z80_cyclesLeft)\r
229\r
230#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
231\r
232// ----------------------- SH2 CPU -----------------------\r
233\r
234#include "cpu/sh2/sh2.h"\r
235\r
236extern SH2 sh2s[2];\r
237#define msh2 sh2s[0]\r
238#define ssh2 sh2s[1]\r
239\r
240#ifndef DRC_SH2\r
241# define sh2_end_run(sh2, after_) do { \\r
242 if ((sh2)->icount > (after_)) { \\r
243 (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
244 (sh2)->icount = after_; \\r
245 } \\r
246} while (0)\r
247# define sh2_cycles_left(sh2) (sh2)->icount\r
248# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
249# define sh2_pc(sh2) (sh2)->ppc\r
250#else\r
251# define sh2_end_run(sh2, after_) do { \\r
252 int left_ = (signed int)(sh2)->sr >> 12; \\r
253 if (left_ > (after_)) { \\r
254 (sh2)->cycles_timeslice -= left_ - (after_); \\r
255 (sh2)->sr &= 0xfff; \\r
256 (sh2)->sr |= (after_) << 12; \\r
257 } \\r
258} while (0)\r
259# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
260# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
261# define sh2_pc(sh2) (sh2)->pc\r
262#endif\r
263\r
264#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
265#define sh2_cycles_done_t(sh2) \\r
266 ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
267#define sh2_cycles_done_m68k(sh2) \\r
268 ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
269\r
270#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
271#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
272#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
273#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
274\r
275#define sh2_set_gbr(c, v) \\r
276 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
277#define sh2_set_vbr(c, v) \\r
278 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
279\r
280#define elprintf_sh2(sh2, w, f, ...) \\r
281 elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
282\r
283// ---------------------------------------------------------\r
284\r
285// main oscillator clock which controls timing\r
286#define OSC_NTSC 53693100\r
287#define OSC_PAL 53203424\r
288\r
289struct PicoVideo\r
290{\r
291 unsigned char reg[0x20];\r
292 unsigned int command; // 32-bit Command\r
293 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
294 unsigned char type; // Command type (v/c/vsram read/write)\r
295 unsigned short addr; // Read/Write address\r
296 int status; // Status bits\r
297 unsigned char pending_ints; // pending interrupts: ??VH????\r
298 signed char lwrite_cnt; // VDP write count during active display line\r
299 unsigned short v_counter; // V-counter\r
300 unsigned char pad[0x10];\r
301};\r
302\r
303struct PicoMisc\r
304{\r
305 unsigned char rotate;\r
306 unsigned char z80Run;\r
307 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
308 unsigned short scanline; // 04 0 to 261||311\r
309 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
310 unsigned char hardware; // 07 Hardware value for country\r
311 unsigned char pal; // 08 1=PAL 0=NTSC\r
312 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
313 unsigned short z80_bank68k; // 0a\r
314 unsigned short pad0;\r
315 unsigned char ncart_in; // 0e !cart_in\r
316 unsigned char z80_reset; // 0f z80 reset held\r
317 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
318 unsigned short eeprom_addr; // EEPROM address register\r
319 unsigned char eeprom_cycle; // EEPROM cycle number\r
320 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
321 unsigned char eeprom_status;\r
322 unsigned char pad2;\r
323 unsigned short dma_xfers; // 18\r
324 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
325 unsigned int frame_count; // 1c for movies and idle det\r
326};\r
327\r
328struct PicoMS\r
329{\r
330 unsigned char carthw[0x10];\r
331 unsigned char io_ctl;\r
332 unsigned char nmi_state;\r
333 unsigned char pad[0x4e];\r
334};\r
335\r
336// emu state and data for the asm code\r
337struct PicoEState\r
338{\r
339 int DrawScanline;\r
340 int rendstatus;\r
341 void *Pico_video;\r
342 void *Pico_vram;\r
343};\r
344\r
345// some assembly stuff depend on these, do not touch!\r
346struct Pico\r
347{\r
348 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
349 union { // vram is byteswapped for easier reads when drawing\r
350 unsigned short vram[0x8000]; // 0x10000\r
351 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
352 };\r
353 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
354 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
355 unsigned char pad[0xf0]; // unused\r
356 unsigned short cram[0x40]; // 0x22100\r
357 unsigned short vsram[0x40]; // 0x22180\r
358\r
359 unsigned char *rom; // 0x22200\r
360 unsigned int romsize; // 0x22204 (on 32bits)\r
361\r
362 struct PicoMisc m;\r
363 struct PicoVideo video;\r
364 struct PicoMS ms;\r
365 struct PicoEState est;\r
366};\r
367\r
368// sram\r
369#define SRR_MAPPED (1 << 0)\r
370#define SRR_READONLY (1 << 1)\r
371\r
372#define SRF_ENABLED (1 << 0)\r
373#define SRF_EEPROM (1 << 1)\r
374\r
375struct PicoSRAM\r
376{\r
377 unsigned char *data; // actual data\r
378 unsigned int start; // start address in 68k address space\r
379 unsigned int end;\r
380 unsigned char flags; // 0c: SRF_*\r
381 unsigned char unused2;\r
382 unsigned char changed;\r
383 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
384 unsigned char unused3;\r
385 unsigned char eeprom_bit_cl; // bit number for cl\r
386 unsigned char eeprom_bit_in; // bit number for in\r
387 unsigned char eeprom_bit_out; // bit number for out\r
388 unsigned int size;\r
389};\r
390\r
391// MCD\r
392#define PCM_MIXBUF_LEN ((12500000 / 384) / 50 + 1)\r
393\r
394struct mcd_pcm\r
395{\r
396 unsigned char control; // reg7\r
397 unsigned char enabled; // reg8\r
398 unsigned char cur_ch;\r
399 unsigned char bank;\r
400 unsigned int update_cycles;\r
401\r
402 struct pcm_chan // 08, size 0x10\r
403 {\r
404 unsigned char regs[8];\r
405 unsigned int addr; // .08: played sample address\r
406 int pad;\r
407 } ch[8];\r
408};\r
409\r
410#define PCD_ST_S68K_RST 1\r
411\r
412struct mcd_misc\r
413{\r
414 unsigned short hint_vector;\r
415 unsigned char busreq; // not s68k_regs[1]\r
416 unsigned char s68k_pend_ints;\r
417 unsigned int state_flags; // 04\r
418 unsigned int stopwatch_base_c;\r
419 unsigned short m68k_poll_a;\r
420 unsigned short m68k_poll_cnt;\r
421 unsigned short s68k_poll_a;\r
422 unsigned short s68k_poll_cnt;\r
423 unsigned int s68k_poll_clk;\r
424 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
425 unsigned char dmna_ret_2m;\r
426 unsigned char need_sync;\r
427 unsigned char pad3;\r
428 int pad4[9];\r
429};\r
430\r
431typedef struct\r
432{\r
433 unsigned char bios[0x20000]; // 000000: 128K\r
434 union { // 020000: 512K\r
435 unsigned char prg_ram[0x80000];\r
436 unsigned char prg_ram_b[4][0x20000];\r
437 };\r
438 union { // 0a0000: 256K\r
439 struct {\r
440 unsigned char word_ram2M[0x40000];\r
441 unsigned char unused0[0x20000];\r
442 };\r
443 struct {\r
444 unsigned char unused1[0x20000];\r
445 unsigned char word_ram1M[2][0x20000];\r
446 };\r
447 };\r
448 union { // 100000: 64K\r
449 unsigned char pcm_ram[0x10000];\r
450 unsigned char pcm_ram_b[0x10][0x1000];\r
451 };\r
452 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
453 unsigned char bram[0x2000]; // 110200: 8K\r
454 struct mcd_misc m; // 112200: misc\r
455 struct mcd_pcm pcm; // 112240:\r
456 void *cdda_stream;\r
457 int cdda_type;\r
458 int pcm_mixbuf[PCM_MIXBUF_LEN * 2];\r
459 int pcm_mixpos;\r
460 char pcm_mixbuf_dirty;\r
461 char pcm_regs_dirty;\r
462} mcd_state;\r
463\r
464// XXX: this will need to be reworked for cart+cd support.\r
465#define Pico_mcd ((mcd_state *)Pico.rom)\r
466\r
467// 32X\r
468#define P32XS_FM (1<<15)\r
469#define P32XS_nCART (1<< 8)\r
470#define P32XS_REN (1<< 7)\r
471#define P32XS_nRES (1<< 1)\r
472#define P32XS_ADEN (1<< 0)\r
473#define P32XS2_ADEN (1<< 9)\r
474#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
475#define P32XS_68S (1<< 2)\r
476#define P32XS_DMA (1<< 1)\r
477#define P32XS_RV (1<< 0)\r
478\r
479#define P32XV_nPAL (1<<15) // VDP\r
480#define P32XV_PRI (1<< 7)\r
481#define P32XV_Mx (3<< 0) // display mode mask\r
482\r
483#define P32XV_SFT (1<< 0)\r
484\r
485#define P32XV_VBLK (1<<15)\r
486#define P32XV_HBLK (1<<14)\r
487#define P32XV_PEN (1<<13)\r
488#define P32XV_nFEN (1<< 1)\r
489#define P32XV_FS (1<< 0)\r
490\r
491#define P32XP_RTP (1<<7) // PWM control\r
492#define P32XP_FULL (1<<15) // PWM pulse\r
493#define P32XP_EMPTY (1<<14)\r
494\r
495#define P32XF_68KCPOLL (1 << 0)\r
496#define P32XF_68KVPOLL (1 << 1)\r
497#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
498\r
499#define P32XI_VRES (1 << 14/2) // IRL/2\r
500#define P32XI_VINT (1 << 12/2)\r
501#define P32XI_HINT (1 << 10/2)\r
502#define P32XI_CMD (1 << 8/2)\r
503#define P32XI_PWM (1 << 6/2)\r
504\r
505// peripheral reg access\r
506#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
507\r
508#define DMAC_FIFO_LEN (4*2)\r
509#define PWM_BUFF_LEN 1024 // in one channel samples\r
510\r
511#define SH2_DRCBLK_RAM_SHIFT 1\r
512#define SH2_DRCBLK_DA_SHIFT 1\r
513\r
514#define SH2_READ_SHIFT 25\r
515#define SH2_WRITE_SHIFT 25\r
516\r
517struct Pico32x\r
518{\r
519 unsigned short regs[0x20];\r
520 unsigned short vdp_regs[0x10]; // 0x40\r
521 unsigned short sh2_regs[3]; // 0x60\r
522 unsigned char pending_fb;\r
523 unsigned char dirty_pal;\r
524 unsigned int emu_flags;\r
525 unsigned char sh2irq_mask[2];\r
526 unsigned char sh2irqi[2]; // individual\r
527 unsigned int sh2irqs; // common irqs\r
528 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
529 unsigned int pad[4];\r
530 unsigned int dmac0_fifo_ptr;\r
531 unsigned short vdp_fbcr_fake;\r
532 unsigned short pad2;\r
533 unsigned char comm_dirty_68k;\r
534 unsigned char comm_dirty_sh2;\r
535 unsigned char pwm_irq_cnt;\r
536 unsigned char pad1;\r
537 unsigned short pwm_p[2]; // pwm pos in fifo\r
538 unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
539 unsigned int reserved[6];\r
540};\r
541\r
542struct Pico32xMem\r
543{\r
544 unsigned char sdram[0x40000];\r
545#ifdef DRC_SH2\r
546 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
547#endif\r
548 unsigned short dram[2][0x20000/2]; // AKA fb\r
549 union {\r
550 unsigned char m68k_rom[0x100];\r
551 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
552 };\r
553#ifdef DRC_SH2\r
554 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
555#endif\r
556 union {\r
557 unsigned char b[0x800];\r
558 unsigned short w[0x800/2];\r
559 } sh2_rom_m;\r
560 union {\r
561 unsigned char b[0x400];\r
562 unsigned short w[0x400/2];\r
563 } sh2_rom_s;\r
564 unsigned short pal[0x100];\r
565 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
566 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
567 signed short pwm_current[2]; // current converted samples\r
568 unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries\r
569};\r
570\r
571// area.c\r
572extern void (*PicoLoadStateHook)(void);\r
573\r
574typedef struct {\r
575 int chunk;\r
576 int size;\r
577 void *ptr;\r
578} carthw_state_chunk;\r
579extern carthw_state_chunk *carthw_chunks;\r
580#define CHUNK_CARTHW 64\r
581\r
582// cart.c\r
583extern int PicoCartResize(int newsize);\r
584extern void Byteswap(void *dst, const void *src, int len);\r
585extern void (*PicoCartMemSetup)(void);\r
586extern void (*PicoCartUnloadHook)(void);\r
587\r
588// debug.c\r
589int CM_compareRun(int cyc, int is_sub);\r
590\r
591// draw.c\r
592PICO_INTERNAL void PicoFrameStart(void);\r
593void PicoDrawSync(int to, int blank_last_line);\r
594void BackFill(int reg7, int sh);\r
595void FinalizeLine555(int sh, int line, struct PicoEState *est);\r
596extern int (*PicoScanBegin)(unsigned int num);\r
597extern int (*PicoScanEnd)(unsigned int num);\r
598#define MAX_LINE_SPRITES 29\r
599extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
600extern void *DrawLineDestBase;\r
601extern int DrawLineDestIncrement;\r
602\r
603// draw2.c\r
604PICO_INTERNAL void PicoFrameFull();\r
605\r
606// mode4.c\r
607void PicoFrameStartMode4(void);\r
608void PicoLineMode4(int line);\r
609void PicoDoHighPal555M4(void);\r
610void PicoDrawSetOutputMode4(pdso_t which);\r
611\r
612// memory.c\r
613PICO_INTERNAL void PicoMemSetup(void);\r
614unsigned int PicoRead8_io(unsigned int a);\r
615unsigned int PicoRead16_io(unsigned int a);\r
616void PicoWrite8_io(unsigned int a, unsigned int d);\r
617void PicoWrite16_io(unsigned int a, unsigned int d);\r
618\r
619// pico/memory.c\r
620PICO_INTERNAL void PicoMemSetupPico(void);\r
621\r
622// cd/cdc.c\r
623void cdc_init(void);\r
624void cdc_reset(void);\r
625int cdc_context_save(unsigned char *state);\r
626int cdc_context_load(unsigned char *state);\r
627int cdc_context_load_old(unsigned char *state);\r
628void cdc_dma_update(void);\r
629int cdc_decoder_update(unsigned char header[4]);\r
630void cdc_reg_w(unsigned char data);\r
631unsigned char cdc_reg_r(void);\r
632unsigned short cdc_host_r(void);\r
633\r
634// cd/cdd.c\r
635void cdd_reset(void);\r
636int cdd_context_save(unsigned char *state);\r
637int cdd_context_load(unsigned char *state);\r
638int cdd_context_load_old(unsigned char *state);\r
639void cdd_read_data(unsigned char *dst);\r
640void cdd_read_audio(unsigned int samples);\r
641void cdd_update(void);\r
642void cdd_process(void);\r
643\r
644// cd/cd_image.c\r
645int load_cd_image(const char *cd_img_name, int *type);\r
646\r
647// cd/gfx.c\r
648void gfx_init(void);\r
649void gfx_start(unsigned int base);\r
650void gfx_update(unsigned int cycles);\r
651int gfx_context_save(unsigned char *state);\r
652int gfx_context_load(const unsigned char *state);\r
653\r
654// cd/gfx_dma.c\r
655void DmaSlowCell(unsigned int source, unsigned int a, int len, unsigned char inc);\r
656\r
657// cd/memory.c\r
658PICO_INTERNAL void PicoMemSetupCD(void);\r
659unsigned int PicoRead8_mcd_io(unsigned int a);\r
660unsigned int PicoRead16_mcd_io(unsigned int a);\r
661void PicoWrite8_mcd_io(unsigned int a, unsigned int d);\r
662void PicoWrite16_mcd_io(unsigned int a, unsigned int d);\r
663void pcd_state_loaded_mem(void);\r
664\r
665// pico.c\r
666extern struct Pico Pico;\r
667extern struct PicoSRAM SRam;\r
668extern int PicoPadInt[2];\r
669extern int emustatus;\r
670extern int scanlines_total;\r
671extern void (*PicoResetHook)(void);\r
672extern void (*PicoLineHook)(void);\r
673PICO_INTERNAL int CheckDMA(void);\r
674PICO_INTERNAL void PicoDetectRegion(void);\r
675PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);\r
676\r
677// cd/mcd.c\r
678#define PCDS_IEN1 (1<<1)\r
679#define PCDS_IEN2 (1<<2)\r
680#define PCDS_IEN3 (1<<3)\r
681#define PCDS_IEN4 (1<<4)\r
682#define PCDS_IEN5 (1<<5)\r
683#define PCDS_IEN6 (1<<6)\r
684\r
685PICO_INTERNAL void PicoInitMCD(void);\r
686PICO_INTERNAL void PicoExitMCD(void);\r
687PICO_INTERNAL void PicoPowerMCD(void);\r
688PICO_INTERNAL int PicoResetMCD(void);\r
689PICO_INTERNAL void PicoFrameMCD(void);\r
690\r
691enum pcd_event {\r
692 PCD_EVENT_CDC,\r
693 PCD_EVENT_TIMER3,\r
694 PCD_EVENT_GFX,\r
695 PCD_EVENT_DMA,\r
696 PCD_EVENT_COUNT,\r
697};\r
698extern unsigned int pcd_event_times[PCD_EVENT_COUNT];\r
699void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);\r
700void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
701void pcd_prepare_frame(void);\r
702unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
703int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);\r
704void pcd_run_cpus(int m68k_cycles);\r
705void pcd_soft_reset(void);\r
706void pcd_state_loaded(void);\r
707\r
708// cd/pcm.c\r
709void pcd_pcm_sync(unsigned int to);\r
710void pcd_pcm_update(int *buffer, int length, int stereo);\r
711void pcd_pcm_write(unsigned int a, unsigned int d);\r
712unsigned int pcd_pcm_read(unsigned int a);\r
713\r
714// pico/pico.c\r
715PICO_INTERNAL void PicoInitPico(void);\r
716PICO_INTERNAL void PicoReratePico(void);\r
717\r
718// pico/xpcm.c\r
719PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
720PICO_INTERNAL void PicoPicoPCMReset(void);\r
721PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
722\r
723// sek.c\r
724PICO_INTERNAL void SekInit(void);\r
725PICO_INTERNAL int SekReset(void);\r
726PICO_INTERNAL void SekState(int *data);\r
727PICO_INTERNAL void SekSetRealTAS(int use_real);\r
728PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
729PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
730void SekStepM68k(void);\r
731void SekInitIdleDet(void);\r
732void SekFinishIdleDet(void);\r
733#if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r
734void SekTrace(int is_s68k);\r
735#else\r
736#define SekTrace(x)\r
737#endif\r
738\r
739// cd/sek.c\r
740PICO_INTERNAL void SekInitS68k(void);\r
741PICO_INTERNAL int SekResetS68k(void);\r
742PICO_INTERNAL int SekInterruptS68k(int irq);\r
743void SekInterruptClearS68k(int irq);\r
744\r
745// sound/sound.c\r
746extern short cdda_out_buffer[2*1152];\r
747extern int PsndLen_exc_cnt;\r
748extern int PsndLen_exc_add;\r
749extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
750extern int timer_b_next_oflow, timer_b_step;\r
751\r
752void cdda_start_play(int lba_base, int lba_offset, int lb_len);\r
753\r
754void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
755void ym2612_pack_state(void);\r
756void ym2612_unpack_state(void);\r
757\r
758#define TIMER_NO_OFLOW 0x70000000\r
759// tA = 72 * (1024 - NA) / M\r
760#define TIMER_A_TICK_ZCYCLES 17203\r
761// tB = 1152 * (256 - NA) / M\r
762#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
763\r
764#define timers_cycle() \\r
765 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
766 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
767 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
768 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
769 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
770\r
771#define timers_reset() \\r
772 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
773 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
774 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
775\r
776\r
777// videoport.c\r
778extern int line_base_cycles;\r
779PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
780PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
781PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
782extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);\r
783\r
784// misc.c\r
785PICO_INTERNAL_ASM void pmemcpy16(unsigned short *dest, unsigned short *src, int count);\r
786PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
787PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count\r
788PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);\r
789\r
790// eeprom.c\r
791void EEPROM_write8(unsigned int a, unsigned int d);\r
792void EEPROM_write16(unsigned int d);\r
793unsigned int EEPROM_read(void);\r
794\r
795// z80 functionality wrappers\r
796PICO_INTERNAL void z80_init(void);\r
797PICO_INTERNAL void z80_pack(void *data);\r
798PICO_INTERNAL int z80_unpack(const void *data);\r
799PICO_INTERNAL void z80_reset(void);\r
800PICO_INTERNAL void z80_exit(void);\r
801\r
802// cd/misc.c\r
803PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
804PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
805\r
806// sound/sound.c\r
807PICO_INTERNAL void PsndReset(void);\r
808PICO_INTERNAL void PsndDoDAC(int line_to);\r
809PICO_INTERNAL void PsndClear(void);\r
810PICO_INTERNAL void PsndGetSamples(int y);\r
811PICO_INTERNAL void PsndGetSamplesMS(void);\r
812extern int PsndDacLine;\r
813\r
814// sms.c\r
815#ifndef NO_SMS\r
816void PicoPowerMS(void);\r
817void PicoResetMS(void);\r
818void PicoMemSetupMS(void);\r
819void PicoStateLoadedMS(void);\r
820void PicoFrameMS(void);\r
821void PicoFrameDrawOnlyMS(void);\r
822#else\r
823#define PicoPowerMS()\r
824#define PicoResetMS()\r
825#define PicoMemSetupMS()\r
826#define PicoStateLoadedMS()\r
827#define PicoFrameMS()\r
828#define PicoFrameDrawOnlyMS()\r
829#endif\r
830\r
831// 32x/32x.c\r
832#ifndef NO_32X\r
833extern struct Pico32x Pico32x;\r
834enum p32x_event {\r
835 P32X_EVENT_PWM,\r
836 P32X_EVENT_FILLEND,\r
837 P32X_EVENT_HINT,\r
838 P32X_EVENT_COUNT,\r
839};\r
840extern unsigned int p32x_event_times[P32X_EVENT_COUNT];\r
841\r
842void Pico32xInit(void);\r
843void PicoPower32x(void);\r
844void PicoReset32x(void);\r
845void Pico32xStartup(void);\r
846void PicoUnload32x(void);\r
847void PicoFrame32x(void);\r
848void Pico32xStateLoaded(int is_early);\r
849void p32x_sync_sh2s(unsigned int m68k_target);\r
850void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
851void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
852void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);\r
853void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);\r
854void p32x_reset_sh2s(void);\r
855void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
856void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
857void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
858\r
859// 32x/memory.c\r
860struct Pico32xMem *Pico32xMem;\r
861unsigned int PicoRead8_32x(unsigned int a);\r
862unsigned int PicoRead16_32x(unsigned int a);\r
863void PicoWrite8_32x(unsigned int a, unsigned int d);\r
864void PicoWrite16_32x(unsigned int a, unsigned int d);\r
865void PicoMemSetup32x(void);\r
866void Pico32xSwapDRAM(int b);\r
867void Pico32xMemStateLoaded(void);\r
868void p32x_m68k_poll_event(unsigned int flags);\r
869void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r
870\r
871// 32x/draw.c\r
872void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r
873void FinalizeLine32xRGB555(int sh, int line, struct PicoEState *est);\r
874void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
875void PicoDraw32xLayerMdOnly(int offs, int lines);\r
876extern int (*PicoScan32xBegin)(unsigned int num);\r
877extern int (*PicoScan32xEnd)(unsigned int num);\r
878enum {\r
879 PDM32X_OFF,\r
880 PDM32X_32X_ONLY,\r
881 PDM32X_BOTH,\r
882};\r
883extern int Pico32xDrawMode;\r
884\r
885// 32x/pwm.c\r
886unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
887 unsigned int m68k_cycles);\r
888void p32x_pwm_write16(unsigned int a, unsigned int d,\r
889 SH2 *sh2, unsigned int m68k_cycles);\r
890void p32x_pwm_update(int *buf32, int length, int stereo);\r
891void p32x_pwm_ctl_changed(void);\r
892void p32x_pwm_schedule(unsigned int m68k_now);\r
893void p32x_pwm_schedule_sh2(SH2 *sh2);\r
894void p32x_pwm_sync_to_sh2(SH2 *sh2);\r
895void p32x_pwm_irq_event(unsigned int m68k_now);\r
896void p32x_pwm_state_loaded(void);\r
897\r
898// 32x/sh2soc.c\r
899void p32x_dreq0_trigger(void);\r
900void p32x_dreq1_trigger(void);\r
901void p32x_timers_recalc(void);\r
902void p32x_timers_do(unsigned int m68k_slice);\r
903void sh2_peripheral_reset(SH2 *sh2);\r
904unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
905unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
906unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
907void REGPARM(3) sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
908void REGPARM(3) sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
909void REGPARM(3) sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
910\r
911#else\r
912#define Pico32xInit()\r
913#define PicoPower32x()\r
914#define PicoReset32x()\r
915#define PicoFrame32x()\r
916#define PicoUnload32x()\r
917#define Pico32xStateLoaded()\r
918#define FinalizeLine32xRGB555 NULL\r
919#define p32x_pwm_update(...)\r
920#define p32x_timers_recalc()\r
921#endif\r
922\r
923/* avoid dependency on newer glibc */\r
924static INLINE int isspace_(int c)\r
925{\r
926 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
927}\r
928\r
929#ifndef ARRAY_SIZE\r
930#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
931#endif\r
932\r
933// emulation event logging\r
934#ifndef EL_LOGMASK\r
935# ifdef __x86_64__ // HACK\r
936# define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r
937# else\r
938# define EL_LOGMASK (EL_STATUS)\r
939# endif\r
940#endif\r
941\r
942#define EL_HVCNT 0x00000001 /* hv counter reads */\r
943#define EL_SR 0x00000002 /* SR reads */\r
944#define EL_INTS 0x00000004 /* ints and acks */\r
945#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
946#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
947#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
948#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
949#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
950#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
951#define EL_SRAMIO 0x00000200 /* sram i/o */\r
952#define EL_EEPROM 0x00000400 /* eeprom debug */\r
953#define EL_UIO 0x00000800 /* unmapped i/o */\r
954#define EL_IO 0x00001000 /* all i/o */\r
955#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
956#define EL_SVP 0x00004000 /* SVP stuff */\r
957#define EL_PICOHW 0x00008000 /* Pico stuff */\r
958#define EL_IDLE 0x00010000 /* idle loop det. */\r
959#define EL_CDREGS 0x00020000 /* MCD: register access */\r
960#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
961#define EL_32X 0x00080000\r
962#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
963#define EL_32XP 0x00200000 /* 32X peripherals */\r
964#define EL_CD 0x00400000 /* MCD */\r
965\r
966#define EL_STATUS 0x40000000 /* status messages */\r
967#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
968\r
969#if EL_LOGMASK\r
970#define elprintf(w,f,...) \\r
971do { \\r
972 if ((w) & EL_LOGMASK) \\r
973 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
974} while (0)\r
975#elif defined(_MSC_VER)\r
976#define elprintf\r
977#else\r
978#define elprintf(w,f,...)\r
979#endif\r
980\r
981// profiling\r
982#ifdef PPROF\r
983#include <platform/linux/pprof.h>\r
984#else\r
985#define pprof_init()\r
986#define pprof_finish()\r
987#define pprof_start(x)\r
988#define pprof_end(...)\r
989#define pprof_end_sub(...)\r
990#endif\r
991\r
992#ifdef EVT_LOG\r
993enum evt {\r
994 EVT_FRAME_START,\r
995 EVT_NEXT_LINE,\r
996 EVT_RUN_START,\r
997 EVT_RUN_END,\r
998 EVT_POLL_START,\r
999 EVT_POLL_END,\r
1000 EVT_CNT\r
1001};\r
1002\r
1003enum evt_cpu {\r
1004 EVT_M68K,\r
1005 EVT_S68K,\r
1006 EVT_MSH2,\r
1007 EVT_SSH2,\r
1008 EVT_CPU_CNT\r
1009};\r
1010\r
1011void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r
1012void pevt_dump(void);\r
1013\r
1014#define pevt_log_m68k(e) \\r
1015 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
1016#define pevt_log_m68k_o(e) \\r
1017 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
1018#define pevt_log_sh2(sh2, e) \\r
1019 pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r
1020#define pevt_log_sh2_o(sh2, e) \\r
1021 pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r
1022#else\r
1023#define pevt_log(c, e)\r
1024#define pevt_log_m68k(e)\r
1025#define pevt_log_m68k_o(e)\r
1026#define pevt_log_sh2(sh2, e)\r
1027#define pevt_log_sh2_o(sh2, e)\r
1028#define pevt_dump()\r
1029#endif\r
1030\r
1031// misc\r
1032#ifdef _MSC_VER\r
1033#define cdprintf\r
1034#else\r
1035#define cdprintf(x...)\r
1036#endif\r
1037\r
1038#if defined(__GNUC__) && defined(__i386__)\r
1039#define REGPARM(x) __attribute__((regparm(x)))\r
1040#else\r
1041#define REGPARM(x)\r
1042#endif\r
1043\r
1044#ifdef __GNUC__\r
1045#define NOINLINE __attribute__((noinline))\r
1046#else\r
1047#define NOINLINE\r
1048#endif\r
1049\r
1050#ifdef __cplusplus\r
1051} // End of extern "C"\r
1052#endif\r
1053\r
1054#endif // PICO_INTERNAL_INCLUDED\r
1055\r
fast MegaDrive/MegaCD/32X emulator