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1/*\r
2 * PicoDrive - Internal Header File\r
3 * (c) Copyright Dave, 2004\r
4 * (C) notaz, 2006-2010\r
5 *\r
6 * This work is licensed under the terms of MAME license.\r
7 * See COPYING file in the top-level directory.\r
8 */\r
9\r
10#ifndef PICO_INTERNAL_INCLUDED\r
11#define PICO_INTERNAL_INCLUDED\r
12\r
13#include <stdio.h>\r
14#include <stdlib.h>\r
15#include <string.h>\r
16#include "pico.h"\r
17#include "carthw/carthw.h"\r
18\r
19//\r
20#define USE_POLL_DETECT\r
21\r
22#ifndef PICO_INTERNAL\r
23#define PICO_INTERNAL\r
24#endif\r
25#ifndef PICO_INTERNAL_ASM\r
26#define PICO_INTERNAL_ASM\r
27#endif\r
28\r
29// to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project\r
30\r
31#ifdef __cplusplus\r
32extern "C" {\r
33#endif\r
34\r
35\r
36// ----------------------- 68000 CPU -----------------------\r
37#ifdef EMU_C68K\r
38#include "../cpu/cyclone/Cyclone.h"\r
39extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
40#define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run\r
41#define SekCyclesLeftS68k PicoCpuCS68k.cycles\r
42#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
43#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
44#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
45#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r
46#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
47#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r
48#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
49#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
50#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
51#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
52#define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
53\r
54#define SekNotPolling PicoCpuCM68k.not_pol\r
55#define SekNotPollingS68k PicoCpuCS68k.not_pol\r
56\r
57#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
58#define SekIrqLevel PicoCpuCM68k.irq\r
59\r
60#endif\r
61\r
62#ifdef EMU_F68K\r
63#include "../cpu/fame/fame.h"\r
64extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
65#define SekCyclesLeft PicoCpuFM68k.io_cycle_counter\r
66#define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter\r
67#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
68#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
69#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
70#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r
71#define SekSr PicoCpuFM68k.sr\r
72#define SekSrS68k PicoCpuFS68k.sr\r
73#define SekSetStop(x) { \\r
74 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
75 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
76}\r
77#define SekSetStopS68k(x) { \\r
78 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \\r
79 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \\r
80}\r
81#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)\r
82#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
83#define SekShouldInterrupt() fm68k_would_interrupt()\r
84\r
85#define SekNotPolling PicoCpuFM68k.not_polling\r
86#define SekNotPollingS68k PicoCpuFS68k.not_polling\r
87\r
88#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
89#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
90\r
91#endif\r
92\r
93#ifdef EMU_M68K\r
94#include "../cpu/musashi/m68kcpu.h"\r
95extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
96#ifndef SekCyclesLeft\r
97#define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles\r
98#define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles\r
99#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
100#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
101#define SekDar(x) PicoCpuMM68k.dar[x]\r
102#define SekDarS68k(x) PicoCpuMS68k.dar[x]\r
103#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
104#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r
105#define SekSetStop(x) { \\r
106 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
107 else PicoCpuMM68k.stopped=0; \\r
108}\r
109#define SekSetStopS68k(x) { \\r
110 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \\r
111 else PicoCpuMS68k.stopped=0; \\r
112}\r
113#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)\r
114#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
115#define SekShouldInterrupt() (CPU_INT_LEVEL > FLAG_INT_MASK)\r
116\r
117#define SekNotPolling PicoCpuMM68k.not_polling\r
118#define SekNotPollingS68k PicoCpuMS68k.not_polling\r
119\r
120#define SekInterrupt(irq) { \\r
121 void *oldcontext = m68ki_cpu_p; \\r
122 m68k_set_context(&PicoCpuMM68k); \\r
123 m68k_set_irq(irq); \\r
124 m68k_set_context(oldcontext); \\r
125}\r
126#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
127\r
128#endif\r
129#endif // EMU_M68K\r
130\r
131// number of cycles done (can be checked anywhere)\r
132#define SekCyclesDone() (Pico.t.m68c_cnt - SekCyclesLeft)\r
133\r
134// burn cycles while not in SekRun() and while in\r
135#define SekCyclesBurn(c) Pico.t.m68c_cnt += c\r
136#define SekCyclesBurnRun(c) { \\r
137 SekCyclesLeft -= c; \\r
138}\r
139\r
140// note: sometimes may extend timeslice to delay an irq\r
141#define SekEndRun(after) { \\r
142 Pico.t.m68c_cnt -= SekCyclesLeft - (after); \\r
143 SekCyclesLeft = after; \\r
144}\r
145\r
146extern unsigned int SekCycleCntS68k;\r
147extern unsigned int SekCycleAimS68k;\r
148\r
149#define SekEndRunS68k(after) { \\r
150 if (SekCyclesLeftS68k > (after)) { \\r
151 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
152 SekCyclesLeftS68k = after; \\r
153 } \\r
154}\r
155\r
156#define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)\r
157\r
158// compare cycles, handling overflows\r
159// check if a > b\r
160#define CYCLES_GT(a, b) \\r
161 ((int)((a) - (b)) > 0)\r
162// check if a >= b\r
163#define CYCLES_GE(a, b) \\r
164 ((int)((a) - (b)) >= 0)\r
165\r
166// ----------------------- Z80 CPU -----------------------\r
167\r
168#if defined(_USE_DRZ80)\r
169#include "../cpu/DrZ80/drz80.h"\r
170\r
171extern struct DrZ80 drZ80;\r
172\r
173#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))\r
174#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
175#define z80_int() drZ80.Z80_IRQ = 1\r
176#define z80_int() drZ80.Z80_IRQ = 1\r
177#define z80_nmi() drZ80.Z80IF |= 8\r
178\r
179#define z80_cyclesLeft drZ80.cycles\r
180#define z80_subCLeft(c) drZ80.cycles -= c\r
181#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
182\r
183#elif defined(_USE_CZ80)\r
184#include "../cpu/cz80/cz80.h"\r
185\r
186#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)\r
187#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
188#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
189#define z80_nmi() Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, 0)\r
190\r
191#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)\r
192#define z80_subCLeft(c) CZ80.ICount -= c\r
193#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)\r
194\r
195#else\r
196\r
197#define z80_run(cycles) (cycles)\r
198#define z80_run_nr(cycles)\r
199#define z80_int()\r
200#define z80_nmi()\r
201\r
202#endif\r
203\r
204#define Z80_STATE_SIZE 0x60\r
205\r
206#define z80_resetCycles() \\r
207 Pico.t.z80c_cnt = Pico.t.z80c_aim = Pico.t.z80_scanline = 0\r
208\r
209#define z80_cyclesDone() \\r
210 (Pico.t.z80c_aim - z80_cyclesLeft)\r
211\r
212#define cycles_68k_to_z80(x) ((x) * 3823 >> 13)\r
213\r
214// ----------------------- SH2 CPU -----------------------\r
215\r
216#include "cpu/sh2/sh2.h"\r
217\r
218extern SH2 sh2s[2];\r
219#define msh2 sh2s[0]\r
220#define ssh2 sh2s[1]\r
221\r
222#ifndef DRC_SH2\r
223# define sh2_end_run(sh2, after_) do { \\r
224 if ((sh2)->icount > (after_)) { \\r
225 (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
226 (sh2)->icount = after_; \\r
227 } \\r
228} while (0)\r
229# define sh2_cycles_left(sh2) (sh2)->icount\r
230# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
231# define sh2_pc(sh2) (sh2)->ppc\r
232#else\r
233# define sh2_end_run(sh2, after_) do { \\r
234 int left_ = (signed int)(sh2)->sr >> 12; \\r
235 if (left_ > (after_)) { \\r
236 (sh2)->cycles_timeslice -= left_ - (after_); \\r
237 (sh2)->sr &= 0xfff; \\r
238 (sh2)->sr |= (after_) << 12; \\r
239 } \\r
240} while (0)\r
241# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
242# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
243# define sh2_pc(sh2) (sh2)->pc\r
244#endif\r
245\r
246#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
247#define sh2_cycles_done_t(sh2) \\r
248 ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
249#define sh2_cycles_done_m68k(sh2) \\r
250 ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
251\r
252#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
253#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
254#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
255#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
256\r
257#define sh2_set_gbr(c, v) \\r
258 { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
259#define sh2_set_vbr(c, v) \\r
260 { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
261\r
262#define elprintf_sh2(sh2, w, f, ...) \\r
263 elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
264\r
265// ---------------------------------------------------------\r
266\r
267// main oscillator clock which controls timing\r
268#define OSC_NTSC 53693100\r
269#define OSC_PAL 53203424\r
270\r
271// PicoVideo.debug_p\r
272#define PVD_KILL_A (1 << 0)\r
273#define PVD_KILL_B (1 << 1)\r
274#define PVD_KILL_S_LO (1 << 2)\r
275#define PVD_KILL_S_HI (1 << 3)\r
276#define PVD_KILL_32X (1 << 4)\r
277#define PVD_FORCE_A (1 << 5)\r
278#define PVD_FORCE_B (1 << 6)\r
279#define PVD_FORCE_S (1 << 7)\r
280\r
281// PicoVideo.status, not part of real SR\r
282#define SR_PAL (1 << 0)\r
283#define SR_DMA (1 << 1)\r
284#define SR_HB (1 << 2)\r
285#define SR_VB (1 << 3)\r
286#define SR_ODD (1 << 4)\r
287#define SR_C (1 << 5)\r
288#define SR_SOVR (1 << 6)\r
289#define SR_F (1 << 7)\r
290#define SR_FULL (1 << 8)\r
291#define SR_EMPT (1 << 9)\r
292// not part of real SR\r
293#define PVS_ACTIVE (1 << 16)\r
294\r
295struct PicoVideo\r
296{\r
297 unsigned char reg[0x20];\r
298 unsigned int command; // 32-bit Command\r
299 unsigned char pending; // 1 if waiting for second half of 32-bit command\r
300 unsigned char type; // Command type (v/c/vsram read/write)\r
301 unsigned short addr; // Read/Write address\r
302 unsigned int status; // Status bits (SR) and extra flags\r
303 unsigned char pending_ints; // pending interrupts: ??VH????\r
304 signed char lwrite_cnt; // VDP write count during active display line\r
305 unsigned short v_counter; // V-counter\r
306 unsigned short debug; // raw debug register\r
307 unsigned char debug_p; // ... parsed: PVD_*\r
308 unsigned char addr_u; // bit16 of .addr\r
309 unsigned char hint_cnt;\r
310 unsigned char pad[0x0b];\r
311};\r
312\r
313struct PicoMisc\r
314{\r
315 unsigned char rotate;\r
316 unsigned char z80Run;\r
317 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches\r
318 unsigned short scanline; // 04 0 to 261||311\r
319 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)\r
320 unsigned char hardware; // 07 Hardware value for country\r
321 unsigned char pal; // 08 1=PAL 0=NTSC\r
322 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
323 unsigned short z80_bank68k; // 0a\r
324 unsigned short pad0;\r
325 unsigned char ncart_in; // 0e !cart_in\r
326 unsigned char z80_reset; // 0f z80 reset held\r
327 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
328 unsigned short eeprom_addr; // EEPROM address register\r
329 unsigned char eeprom_cycle; // EEPROM cycle number\r
330 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
331 unsigned char eeprom_status;\r
332 unsigned char pad2;\r
333 unsigned short dma_xfers; // 18\r
334 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
335 unsigned int frame_count; // 1c for movies and idle det\r
336};\r
337\r
338struct PicoMS\r
339{\r
340 unsigned char carthw[0x10];\r
341 unsigned char io_ctl;\r
342 unsigned char nmi_state;\r
343 unsigned char pad[0x4e];\r
344};\r
345\r
346// emu state and data for the asm code\r
347struct PicoEState\r
348{\r
349 int DrawScanline;\r
350 int rendstatus;\r
351 void *DrawLineDest; // draw destination\r
352 unsigned char *HighCol;\r
353 int *HighPreSpr;\r
354 struct Pico *Pico;\r
355 void *PicoMem_vram;\r
356 void *PicoMem_cram;\r
357 int *PicoOpt;\r
358 unsigned char *Draw2FB;\r
359 unsigned short HighPal[0x100];\r
360};\r
361\r
362// some assembly stuff still depends on these, do not touch!\r
363struct PicoMem\r
364{\r
365 unsigned char ram[0x10000]; // 0x00000 scratch ram\r
366 union { // vram is byteswapped for easier reads when drawing\r
367 unsigned short vram[0x8000]; // 0x10000\r
368 unsigned char vramb[0x4000]; // VRAM in SMS mode\r
369 };\r
370 unsigned char zram[0x2000]; // 0x20000 Z80 ram\r
371 unsigned char ioports[0x10]; // XXX: fix asm and mv\r
372 unsigned char pad[0xf0]; // unused\r
373 unsigned short cram[0x40]; // 0x22100\r
374 unsigned short vsram[0x40]; // 0x22180\r
375};\r
376\r
377// sram\r
378#define SRR_MAPPED (1 << 0)\r
379#define SRR_READONLY (1 << 1)\r
380\r
381#define SRF_ENABLED (1 << 0)\r
382#define SRF_EEPROM (1 << 1)\r
383\r
384struct PicoCartSave\r
385{\r
386 unsigned char *data; // actual data\r
387 unsigned int start; // start address in 68k address space\r
388 unsigned int end;\r
389 unsigned char flags; // 0c: SRF_*\r
390 unsigned char unused2;\r
391 unsigned char changed;\r
392 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words\r
393 unsigned char unused3;\r
394 unsigned char eeprom_bit_cl; // bit number for cl\r
395 unsigned char eeprom_bit_in; // bit number for in\r
396 unsigned char eeprom_bit_out; // bit number for out\r
397 unsigned int size;\r
398};\r
399\r
400struct PicoTiming\r
401{\r
402 // while running, cnt represents target of current timeslice\r
403 // while not in SekRun(), it's actual cycles done\r
404 // (but always use SekCyclesDone() if you need current position)\r
405 // _cnt may change if timeslice is ended prematurely or extended,\r
406 // so we use _aim for the actual target\r
407 unsigned int m68c_cnt;\r
408 unsigned int m68c_aim;\r
409 unsigned int m68c_frame_start; // m68k cycles\r
410 unsigned int m68c_line_start;\r
411\r
412 unsigned int z80c_cnt; // z80 cycles done (this frame)\r
413 unsigned int z80c_aim;\r
414 int z80_scanline;\r
415};\r
416\r
417// run tools/mkoffsets pico/pico_int_o32.h if you change these\r
418// careful with savestate compat\r
419struct Pico\r
420{\r
421 struct PicoVideo video;\r
422 struct PicoMisc m;\r
423 struct PicoTiming t;\r
424 struct PicoCartSave sv;\r
425 struct PicoEState est;\r
426 struct PicoMS ms;\r
427\r
428 unsigned char *rom;\r
429 unsigned int romsize;\r
430};\r
431\r
432// MCD\r
433#define PCM_MIXBUF_LEN ((12500000 / 384) / 50 + 1)\r
434\r
435struct mcd_pcm\r
436{\r
437 unsigned char control; // reg7\r
438 unsigned char enabled; // reg8\r
439 unsigned char cur_ch;\r
440 unsigned char bank;\r
441 unsigned int update_cycles;\r
442\r
443 struct pcm_chan // 08, size 0x10\r
444 {\r
445 unsigned char regs[8];\r
446 unsigned int addr; // .08: played sample address\r
447 int pad;\r
448 } ch[8];\r
449};\r
450\r
451#define PCD_ST_S68K_RST 1\r
452\r
453struct mcd_misc\r
454{\r
455 unsigned short hint_vector;\r
456 unsigned char busreq; // not s68k_regs[1]\r
457 unsigned char s68k_pend_ints;\r
458 unsigned int state_flags; // 04\r
459 unsigned int stopwatch_base_c;\r
460 unsigned short m68k_poll_a;\r
461 unsigned short m68k_poll_cnt;\r
462 unsigned short s68k_poll_a;\r
463 unsigned short s68k_poll_cnt;\r
464 unsigned int s68k_poll_clk;\r
465 unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
466 unsigned char dmna_ret_2m;\r
467 unsigned char need_sync;\r
468 unsigned char pad3;\r
469 int pad4[9];\r
470};\r
471\r
472typedef struct\r
473{\r
474 unsigned char bios[0x20000]; // 000000: 128K\r
475 union { // 020000: 512K\r
476 unsigned char prg_ram[0x80000];\r
477 unsigned char prg_ram_b[4][0x20000];\r
478 };\r
479 union { // 0a0000: 256K\r
480 struct {\r
481 unsigned char word_ram2M[0x40000];\r
482 unsigned char unused0[0x20000];\r
483 };\r
484 struct {\r
485 unsigned char unused1[0x20000];\r
486 unsigned char word_ram1M[2][0x20000];\r
487 };\r
488 };\r
489 union { // 100000: 64K\r
490 unsigned char pcm_ram[0x10000];\r
491 unsigned char pcm_ram_b[0x10][0x1000];\r
492 };\r
493 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
494 unsigned char bram[0x2000]; // 110200: 8K\r
495 struct mcd_misc m; // 112200: misc\r
496 struct mcd_pcm pcm; // 112240:\r
497 void *cdda_stream;\r
498 int cdda_type;\r
499 int pcm_mixbuf[PCM_MIXBUF_LEN * 2];\r
500 int pcm_mixpos;\r
501 char pcm_mixbuf_dirty;\r
502 char pcm_regs_dirty;\r
503} mcd_state;\r
504\r
505// XXX: this will need to be reworked for cart+cd support.\r
506#define Pico_mcd ((mcd_state *)Pico.rom)\r
507\r
508// 32X\r
509#define P32XS_FM (1<<15)\r
510#define P32XS_nCART (1<< 8)\r
511#define P32XS_REN (1<< 7)\r
512#define P32XS_nRES (1<< 1)\r
513#define P32XS_ADEN (1<< 0)\r
514#define P32XS2_ADEN (1<< 9)\r
515#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
516#define P32XS_68S (1<< 2)\r
517#define P32XS_DMA (1<< 1)\r
518#define P32XS_RV (1<< 0)\r
519\r
520#define P32XV_nPAL (1<<15) // VDP\r
521#define P32XV_PRI (1<< 7)\r
522#define P32XV_Mx (3<< 0) // display mode mask\r
523\r
524#define P32XV_SFT (1<< 0)\r
525\r
526#define P32XV_VBLK (1<<15)\r
527#define P32XV_HBLK (1<<14)\r
528#define P32XV_PEN (1<<13)\r
529#define P32XV_nFEN (1<< 1)\r
530#define P32XV_FS (1<< 0)\r
531\r
532#define P32XP_RTP (1<<7) // PWM control\r
533#define P32XP_FULL (1<<15) // PWM pulse\r
534#define P32XP_EMPTY (1<<14)\r
535\r
536#define P32XF_68KCPOLL (1 << 0)\r
537#define P32XF_68KVPOLL (1 << 1)\r
538#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
539\r
540#define P32XI_VRES (1 << 14/2) // IRL/2\r
541#define P32XI_VINT (1 << 12/2)\r
542#define P32XI_HINT (1 << 10/2)\r
543#define P32XI_CMD (1 << 8/2)\r
544#define P32XI_PWM (1 << 6/2)\r
545\r
546// peripheral reg access\r
547#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
548\r
549#define DMAC_FIFO_LEN (4*2)\r
550#define PWM_BUFF_LEN 1024 // in one channel samples\r
551\r
552#define SH2_DRCBLK_RAM_SHIFT 1\r
553#define SH2_DRCBLK_DA_SHIFT 1\r
554\r
555#define SH2_READ_SHIFT 25\r
556#define SH2_WRITE_SHIFT 25\r
557\r
558struct Pico32x\r
559{\r
560 unsigned short regs[0x20];\r
561 unsigned short vdp_regs[0x10]; // 0x40\r
562 unsigned short sh2_regs[3]; // 0x60\r
563 unsigned char pending_fb;\r
564 unsigned char dirty_pal;\r
565 unsigned int emu_flags;\r
566 unsigned char sh2irq_mask[2];\r
567 unsigned char sh2irqi[2]; // individual\r
568 unsigned int sh2irqs; // common irqs\r
569 unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
570 unsigned int pad[4];\r
571 unsigned int dmac0_fifo_ptr;\r
572 unsigned short vdp_fbcr_fake;\r
573 unsigned short pad2;\r
574 unsigned char comm_dirty_68k;\r
575 unsigned char comm_dirty_sh2;\r
576 unsigned char pwm_irq_cnt;\r
577 unsigned char pad1;\r
578 unsigned short pwm_p[2]; // pwm pos in fifo\r
579 unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
580 unsigned int reserved[6];\r
581};\r
582\r
583struct Pico32xMem\r
584{\r
585 unsigned char sdram[0x40000];\r
586#ifdef DRC_SH2\r
587 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
588#endif\r
589 unsigned short dram[2][0x20000/2]; // AKA fb\r
590 union {\r
591 unsigned char m68k_rom[0x100];\r
592 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
593 };\r
594#ifdef DRC_SH2\r
595 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
596#endif\r
597 union {\r
598 unsigned char b[0x800];\r
599 unsigned short w[0x800/2];\r
600 } sh2_rom_m;\r
601 union {\r
602 unsigned char b[0x400];\r
603 unsigned short w[0x400/2];\r
604 } sh2_rom_s;\r
605 unsigned short pal[0x100];\r
606 unsigned short pal_native[0x100]; // converted to native (for renderer)\r
607 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
608 signed short pwm_current[2]; // current converted samples\r
609 unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries\r
610};\r
611\r
612// area.c\r
613extern void (*PicoLoadStateHook)(void);\r
614\r
615typedef struct {\r
616 int chunk;\r
617 int size;\r
618 void *ptr;\r
619} carthw_state_chunk;\r
620extern carthw_state_chunk *carthw_chunks;\r
621#define CHUNK_CARTHW 64\r
622\r
623// cart.c\r
624extern int PicoCartResize(int newsize);\r
625extern void Byteswap(void *dst, const void *src, int len);\r
626extern void (*PicoCartMemSetup)(void);\r
627extern void (*PicoCartUnloadHook)(void);\r
628\r
629// debug.c\r
630int CM_compareRun(int cyc, int is_sub);\r
631\r
632// draw.c\r
633void PicoDrawInit(void);\r
634PICO_INTERNAL void PicoFrameStart(void);\r
635void PicoDrawSync(int to, int blank_last_line);\r
636void BackFill(int reg7, int sh, struct PicoEState *est);\r
637void FinalizeLine555(int sh, int line, struct PicoEState *est);\r
638extern int (*PicoScanBegin)(unsigned int num);\r
639extern int (*PicoScanEnd)(unsigned int num);\r
640#define MAX_LINE_SPRITES 29\r
641extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
642extern void *DrawLineDestBase;\r
643extern int DrawLineDestIncrement;\r
644\r
645// draw2.c\r
646void PicoDraw2Init(void);\r
647PICO_INTERNAL void PicoFrameFull();\r
648\r
649// mode4.c\r
650void PicoFrameStartMode4(void);\r
651void PicoLineMode4(int line);\r
652void PicoDoHighPal555M4(void);\r
653void PicoDrawSetOutputMode4(pdso_t which);\r
654\r
655// memory.c\r
656PICO_INTERNAL void PicoMemSetup(void);\r
657unsigned int PicoRead8_io(unsigned int a);\r
658unsigned int PicoRead16_io(unsigned int a);\r
659void PicoWrite8_io(unsigned int a, unsigned int d);\r
660void PicoWrite16_io(unsigned int a, unsigned int d);\r
661\r
662// pico/memory.c\r
663PICO_INTERNAL void PicoMemSetupPico(void);\r
664\r
665// cd/cdc.c\r
666void cdc_init(void);\r
667void cdc_reset(void);\r
668int cdc_context_save(unsigned char *state);\r
669int cdc_context_load(unsigned char *state);\r
670int cdc_context_load_old(unsigned char *state);\r
671void cdc_dma_update(void);\r
672int cdc_decoder_update(unsigned char header[4]);\r
673void cdc_reg_w(unsigned char data);\r
674unsigned char cdc_reg_r(void);\r
675unsigned short cdc_host_r(void);\r
676\r
677// cd/cdd.c\r
678void cdd_reset(void);\r
679int cdd_context_save(unsigned char *state);\r
680int cdd_context_load(unsigned char *state);\r
681int cdd_context_load_old(unsigned char *state);\r
682void cdd_read_data(unsigned char *dst);\r
683void cdd_read_audio(unsigned int samples);\r
684void cdd_update(void);\r
685void cdd_process(void);\r
686\r
687// cd/cd_image.c\r
688int load_cd_image(const char *cd_img_name, int *type);\r
689\r
690// cd/gfx.c\r
691void gfx_init(void);\r
692void gfx_start(unsigned int base);\r
693void gfx_update(unsigned int cycles);\r
694int gfx_context_save(unsigned char *state);\r
695int gfx_context_load(const unsigned char *state);\r
696\r
697// cd/gfx_dma.c\r
698void DmaSlowCell(unsigned int source, unsigned int a, int len, unsigned char inc);\r
699\r
700// cd/memory.c\r
701PICO_INTERNAL void PicoMemSetupCD(void);\r
702unsigned int PicoRead8_mcd_io(unsigned int a);\r
703unsigned int PicoRead16_mcd_io(unsigned int a);\r
704void PicoWrite8_mcd_io(unsigned int a, unsigned int d);\r
705void PicoWrite16_mcd_io(unsigned int a, unsigned int d);\r
706void pcd_state_loaded_mem(void);\r
707\r
708// pico.c\r
709extern struct Pico Pico;\r
710extern struct PicoMem PicoMem;\r
711extern int PicoPadInt[2];\r
712extern int emustatus;\r
713extern void (*PicoResetHook)(void);\r
714extern void (*PicoLineHook)(void);\r
715PICO_INTERNAL int CheckDMA(void);\r
716PICO_INTERNAL void PicoDetectRegion(void);\r
717PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);\r
718\r
719// cd/mcd.c\r
720#define PCDS_IEN1 (1<<1)\r
721#define PCDS_IEN2 (1<<2)\r
722#define PCDS_IEN3 (1<<3)\r
723#define PCDS_IEN4 (1<<4)\r
724#define PCDS_IEN5 (1<<5)\r
725#define PCDS_IEN6 (1<<6)\r
726\r
727PICO_INTERNAL void PicoInitMCD(void);\r
728PICO_INTERNAL void PicoExitMCD(void);\r
729PICO_INTERNAL void PicoPowerMCD(void);\r
730PICO_INTERNAL int PicoResetMCD(void);\r
731PICO_INTERNAL void PicoFrameMCD(void);\r
732\r
733enum pcd_event {\r
734 PCD_EVENT_CDC,\r
735 PCD_EVENT_TIMER3,\r
736 PCD_EVENT_GFX,\r
737 PCD_EVENT_DMA,\r
738 PCD_EVENT_COUNT,\r
739};\r
740extern unsigned int pcd_event_times[PCD_EVENT_COUNT];\r
741void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);\r
742void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
743void pcd_prepare_frame(void);\r
744unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
745int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);\r
746void pcd_run_cpus(int m68k_cycles);\r
747void pcd_soft_reset(void);\r
748void pcd_state_loaded(void);\r
749\r
750// cd/pcm.c\r
751void pcd_pcm_sync(unsigned int to);\r
752void pcd_pcm_update(int *buffer, int length, int stereo);\r
753void pcd_pcm_write(unsigned int a, unsigned int d);\r
754unsigned int pcd_pcm_read(unsigned int a);\r
755\r
756// pico/pico.c\r
757PICO_INTERNAL void PicoInitPico(void);\r
758PICO_INTERNAL void PicoReratePico(void);\r
759\r
760// pico/xpcm.c\r
761PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);\r
762PICO_INTERNAL void PicoPicoPCMReset(void);\r
763PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);\r
764\r
765// sek.c\r
766PICO_INTERNAL void SekInit(void);\r
767PICO_INTERNAL int SekReset(void);\r
768PICO_INTERNAL void SekState(int *data);\r
769PICO_INTERNAL void SekSetRealTAS(int use_real);\r
770PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);\r
771PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);\r
772void SekStepM68k(void);\r
773void SekInitIdleDet(void);\r
774void SekFinishIdleDet(void);\r
775#if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r
776void SekTrace(int is_s68k);\r
777#else\r
778#define SekTrace(x)\r
779#endif\r
780\r
781// cd/sek.c\r
782PICO_INTERNAL void SekInitS68k(void);\r
783PICO_INTERNAL int SekResetS68k(void);\r
784PICO_INTERNAL int SekInterruptS68k(int irq);\r
785void SekInterruptClearS68k(int irq);\r
786\r
787// sound/sound.c\r
788extern short cdda_out_buffer[2*1152];\r
789extern int PsndLen_exc_cnt;\r
790extern int PsndLen_exc_add;\r
791extern int timer_a_next_oflow, timer_a_step; // in z80 cycles\r
792extern int timer_b_next_oflow, timer_b_step;\r
793\r
794void cdda_start_play(int lba_base, int lba_offset, int lb_len);\r
795\r
796void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);\r
797void ym2612_pack_state(void);\r
798void ym2612_unpack_state(void);\r
799\r
800#define TIMER_NO_OFLOW 0x70000000\r
801// tA = 72 * (1024 - NA) / M\r
802#define TIMER_A_TICK_ZCYCLES 17203\r
803// tB = 1152 * (256 - NA) / M\r
804#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
805\r
806#define timers_cycle() \\r
807 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \\r
808 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
809 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \\r
810 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \\r
811 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);\r
812\r
813#define timers_reset() \\r
814 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \\r
815 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
816 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
817\r
818\r
819// videoport.c\r
820PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
821PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
822unsigned char PicoVideoRead8DataH(void);\r
823unsigned char PicoVideoRead8DataL(void);\r
824unsigned char PicoVideoRead8CtlH(void);\r
825unsigned char PicoVideoRead8CtlL(void);\r
826unsigned char PicoVideoRead8HV_H(void);\r
827unsigned char PicoVideoRead8HV_L(void);\r
828extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned int *mask);\r
829\r
830// misc.c\r
831PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);\r
832PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);\r
833PICO_INTERNAL_ASM void memcpy32(void *dest, const void *src, int count); // 32bit word count\r
834PICO_INTERNAL_ASM void memset32(void *dest, int c, int count);\r
835\r
836// eeprom.c\r
837void EEPROM_write8(unsigned int a, unsigned int d);\r
838void EEPROM_write16(unsigned int d);\r
839unsigned int EEPROM_read(void);\r
840\r
841// z80 functionality wrappers\r
842PICO_INTERNAL void z80_init(void);\r
843PICO_INTERNAL void z80_pack(void *data);\r
844PICO_INTERNAL int z80_unpack(const void *data);\r
845PICO_INTERNAL void z80_reset(void);\r
846PICO_INTERNAL void z80_exit(void);\r
847\r
848// cd/misc.c\r
849PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);\r
850PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);\r
851\r
852// sound/sound.c\r
853PICO_INTERNAL void PsndReset(void);\r
854PICO_INTERNAL void PsndStartFrame(void);\r
855PICO_INTERNAL void PsndDoDAC(int line_to);\r
856PICO_INTERNAL void PsndDoPSG(int line_to);\r
857PICO_INTERNAL void PsndClear(void);\r
858PICO_INTERNAL void PsndGetSamples(int y);\r
859PICO_INTERNAL void PsndGetSamplesMS(void);\r
860extern int PsndDacLine, PsndPsgLine;\r
861\r
862// sms.c\r
863#ifndef NO_SMS\r
864void PicoPowerMS(void);\r
865void PicoResetMS(void);\r
866void PicoMemSetupMS(void);\r
867void PicoStateLoadedMS(void);\r
868void PicoFrameMS(void);\r
869void PicoFrameDrawOnlyMS(void);\r
870#else\r
871#define PicoPowerMS()\r
872#define PicoResetMS()\r
873#define PicoMemSetupMS()\r
874#define PicoStateLoadedMS()\r
875#define PicoFrameMS()\r
876#define PicoFrameDrawOnlyMS()\r
877#endif\r
878\r
879// 32x/32x.c\r
880#ifndef NO_32X\r
881extern struct Pico32x Pico32x;\r
882enum p32x_event {\r
883 P32X_EVENT_PWM,\r
884 P32X_EVENT_FILLEND,\r
885 P32X_EVENT_HINT,\r
886 P32X_EVENT_COUNT,\r
887};\r
888extern unsigned int p32x_event_times[P32X_EVENT_COUNT];\r
889\r
890void Pico32xInit(void);\r
891void PicoPower32x(void);\r
892void PicoReset32x(void);\r
893void Pico32xStartup(void);\r
894void PicoUnload32x(void);\r
895void PicoFrame32x(void);\r
896void Pico32xStateLoaded(int is_early);\r
897void p32x_sync_sh2s(unsigned int m68k_target);\r
898void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
899void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
900void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);\r
901void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);\r
902void p32x_reset_sh2s(void);\r
903void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
904void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
905void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
906\r
907// 32x/memory.c\r
908extern struct Pico32xMem *Pico32xMem;\r
909unsigned int PicoRead8_32x(unsigned int a);\r
910unsigned int PicoRead16_32x(unsigned int a);\r
911void PicoWrite8_32x(unsigned int a, unsigned int d);\r
912void PicoWrite16_32x(unsigned int a, unsigned int d);\r
913void PicoMemSetup32x(void);\r
914void Pico32xSwapDRAM(int b);\r
915void Pico32xMemStateLoaded(void);\r
916void p32x_m68k_poll_event(unsigned int flags);\r
917void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r
918\r
919// 32x/draw.c\r
920void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r
921void FinalizeLine32xRGB555(int sh, int line, struct PicoEState *est);\r
922void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
923void PicoDraw32xLayerMdOnly(int offs, int lines);\r
924extern int (*PicoScan32xBegin)(unsigned int num);\r
925extern int (*PicoScan32xEnd)(unsigned int num);\r
926enum {\r
927 PDM32X_OFF,\r
928 PDM32X_32X_ONLY,\r
929 PDM32X_BOTH,\r
930};\r
931extern int Pico32xDrawMode;\r
932\r
933// 32x/pwm.c\r
934unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
935 unsigned int m68k_cycles);\r
936void p32x_pwm_write16(unsigned int a, unsigned int d,\r
937 SH2 *sh2, unsigned int m68k_cycles);\r
938void p32x_pwm_update(int *buf32, int length, int stereo);\r
939void p32x_pwm_ctl_changed(void);\r
940void p32x_pwm_schedule(unsigned int m68k_now);\r
941void p32x_pwm_schedule_sh2(SH2 *sh2);\r
942void p32x_pwm_sync_to_sh2(SH2 *sh2);\r
943void p32x_pwm_irq_event(unsigned int m68k_now);\r
944void p32x_pwm_state_loaded(void);\r
945\r
946// 32x/sh2soc.c\r
947void p32x_dreq0_trigger(void);\r
948void p32x_dreq1_trigger(void);\r
949void p32x_timers_recalc(void);\r
950void p32x_timers_do(unsigned int m68k_slice);\r
951void sh2_peripheral_reset(SH2 *sh2);\r
952unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
953unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
954unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
955void REGPARM(3) sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
956void REGPARM(3) sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
957void REGPARM(3) sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
958\r
959#else\r
960#define Pico32xInit()\r
961#define PicoPower32x()\r
962#define PicoReset32x()\r
963#define PicoFrame32x()\r
964#define PicoUnload32x()\r
965#define Pico32xStateLoaded()\r
966#define FinalizeLine32xRGB555 NULL\r
967#define p32x_pwm_update(...)\r
968#define p32x_timers_recalc()\r
969#endif\r
970\r
971/* avoid dependency on newer glibc */\r
972static __inline int isspace_(int c)\r
973{\r
974 return (0x09 <= c && c <= 0x0d) || c == ' ';\r
975}\r
976\r
977#ifndef ARRAY_SIZE\r
978#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
979#endif\r
980\r
981// emulation event logging\r
982#ifndef EL_LOGMASK\r
983# ifdef __x86_64__ // HACK\r
984# define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r
985# else\r
986# define EL_LOGMASK (EL_STATUS)\r
987# endif\r
988#endif\r
989\r
990#define EL_HVCNT 0x00000001 /* hv counter reads */\r
991#define EL_SR 0x00000002 /* SR reads */\r
992#define EL_INTS 0x00000004 /* ints and acks */\r
993#define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */\r
994#define EL_INTSW 0x00000010 /* log irq switching on/off */\r
995#define EL_ASVDP 0x00000020 /* VDP accesses during active scan */\r
996#define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */\r
997#define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */\r
998#define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */\r
999#define EL_SRAMIO 0x00000200 /* sram i/o */\r
1000#define EL_EEPROM 0x00000400 /* eeprom debug */\r
1001#define EL_UIO 0x00000800 /* unmapped i/o */\r
1002#define EL_IO 0x00001000 /* all i/o */\r
1003#define EL_CDPOLL 0x00002000 /* MCD: log poll detection */\r
1004#define EL_SVP 0x00004000 /* SVP stuff */\r
1005#define EL_PICOHW 0x00008000 /* Pico stuff */\r
1006#define EL_IDLE 0x00010000 /* idle loop det. */\r
1007#define EL_CDREGS 0x00020000 /* MCD: register access */\r
1008#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
1009#define EL_32X 0x00080000\r
1010#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
1011#define EL_32XP 0x00200000 /* 32X peripherals */\r
1012#define EL_CD 0x00400000 /* MCD */\r
1013\r
1014#define EL_STATUS 0x40000000 /* status messages */\r
1015#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
1016\r
1017#if EL_LOGMASK\r
1018#define elprintf(w,f,...) \\r
1019do { \\r
1020 if ((w) & EL_LOGMASK) \\r
1021 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
1022} while (0)\r
1023#elif defined(_MSC_VER)\r
1024#define elprintf\r
1025#else\r
1026#define elprintf(w,f,...)\r
1027#endif\r
1028\r
1029// profiling\r
1030#ifdef PPROF\r
1031#include <platform/linux/pprof.h>\r
1032#else\r
1033#define pprof_init()\r
1034#define pprof_finish()\r
1035#define pprof_start(x)\r
1036#define pprof_end(...)\r
1037#define pprof_end_sub(...)\r
1038#endif\r
1039\r
1040#ifdef EVT_LOG\r
1041enum evt {\r
1042 EVT_FRAME_START,\r
1043 EVT_NEXT_LINE,\r
1044 EVT_RUN_START,\r
1045 EVT_RUN_END,\r
1046 EVT_POLL_START,\r
1047 EVT_POLL_END,\r
1048 EVT_CNT\r
1049};\r
1050\r
1051enum evt_cpu {\r
1052 EVT_M68K,\r
1053 EVT_S68K,\r
1054 EVT_MSH2,\r
1055 EVT_SSH2,\r
1056 EVT_CPU_CNT\r
1057};\r
1058\r
1059void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r
1060void pevt_dump(void);\r
1061\r
1062#define pevt_log_m68k(e) \\r
1063 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
1064#define pevt_log_m68k_o(e) \\r
1065 pevt_log(SekCyclesDone(), EVT_M68K, e)\r
1066#define pevt_log_sh2(sh2, e) \\r
1067 pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r
1068#define pevt_log_sh2_o(sh2, e) \\r
1069 pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r
1070#else\r
1071#define pevt_log(c, e)\r
1072#define pevt_log_m68k(e)\r
1073#define pevt_log_m68k_o(e)\r
1074#define pevt_log_sh2(sh2, e)\r
1075#define pevt_log_sh2_o(sh2, e)\r
1076#define pevt_dump()\r
1077#endif\r
1078\r
1079// misc\r
1080#ifdef _MSC_VER\r
1081#define cdprintf\r
1082#else\r
1083#define cdprintf(x...)\r
1084#endif\r
1085\r
1086#if defined(__GNUC__) && defined(__i386__)\r
1087#define REGPARM(x) __attribute__((regparm(x)))\r
1088#else\r
1089#define REGPARM(x)\r
1090#endif\r
1091\r
1092#ifdef __GNUC__\r
1093#define NOINLINE __attribute__((noinline))\r
1094#else\r
1095#define NOINLINE\r
1096#endif\r
1097\r
1098#ifdef __cplusplus\r
1099} // End of extern "C"\r
1100#endif\r
1101\r
1102#endif // PICO_INTERNAL_INCLUDED\r
1103\r
1104// vim:shiftwidth=2:ts=2:expandtab\r
fast MegaDrive/MegaCD/32X emulator