1 diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c
2 index 06612dbf..9a9d7b05 100644
3 --- a/libpcsxcore/new_dynarec/emu_if.c
4 +++ b/libpcsxcore/new_dynarec/emu_if.c
5 @@ -323,13 +323,18 @@ static void ari64_shutdown()
8 new_dyna_pcsx_mem_shutdown();
10 + (void)ari64_execute_block;
13 +extern void intExecuteT();
14 +extern void intExecuteBlockT();
20 - ari64_execute_block,
26 @@ -398,7 +403,7 @@ static u32 memcheck_read(u32 a)
27 return *(u32 *)(psxM + (a & 0x1ffffc));
32 void do_insn_trace(void)
34 static psxRegisters oldregs;
35 diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c
36 index 190f8fc7..5feb7a02 100644
37 --- a/libpcsxcore/new_dynarec/pcsxmem.c
38 +++ b/libpcsxcore/new_dynarec/pcsxmem.c
39 @@ -289,6 +289,8 @@ static void write_biu(u32 value)
43 +extern u32 handler_cycle;
44 +handler_cycle = psxRegs.cycle;
45 memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle);
46 psxRegs.biuReg = value;
48 diff --git a/libpcsxcore/psxcounters.c b/libpcsxcore/psxcounters.c
49 index 18bd6a4e..bc2eb3f6 100644
50 --- a/libpcsxcore/psxcounters.c
51 +++ b/libpcsxcore/psxcounters.c
52 @@ -389,9 +389,12 @@ void psxRcntUpdate()
54 /******************************************************************************/
56 +extern u32 handler_cycle;
58 void psxRcntWcount( u32 index, u32 value )
60 verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
61 +handler_cycle = psxRegs.cycle;
63 _psxRcntWcount( index, value );
65 @@ -400,6 +403,7 @@ void psxRcntWcount( u32 index, u32 value )
66 void psxRcntWmode( u32 index, u32 value )
68 verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
69 +handler_cycle = psxRegs.cycle;
71 _psxRcntWmode( index, value );
72 _psxRcntWcount( index, 0 );
73 @@ -411,6 +415,7 @@ void psxRcntWmode( u32 index, u32 value )
74 void psxRcntWtarget( u32 index, u32 value )
76 verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
77 +handler_cycle = psxRegs.cycle;
79 rcnts[index].target = value;
81 @@ -423,6 +428,7 @@ void psxRcntWtarget( u32 index, u32 value )
82 u32 psxRcntRcount( u32 index )
85 +handler_cycle = psxRegs.cycle;
87 count = _psxRcntRcount( index );
89 diff --git a/libpcsxcore/psxhw.c b/libpcsxcore/psxhw.c
90 index 27ddfeab..d7c6ff05 100644
91 --- a/libpcsxcore/psxhw.c
92 +++ b/libpcsxcore/psxhw.c
93 @@ -377,13 +377,14 @@ void psxHwWrite8(u32 add, u8 value) {
94 case 0x1f801803: cdrWrite3(value); break;
97 + if (add < 0x1f802000)
100 PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
104 - psxHu8(add) = value;
105 + //psxHu8(add) = value;
107 PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
109 @@ -506,6 +507,7 @@ void psxHwWrite16(u32 add, u16 value) {
113 + if (add < 0x1f802000)
114 psxHu16ref(add) = SWAPu16(value);
116 PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
117 @@ -701,9 +703,9 @@ void psxHwWrite32(u32 add, u32 value) {
121 - mdecWrite0(value); break;
122 + mdecWrite0(value); return;
124 - mdecWrite1(value); break;
125 + mdecWrite1(value); return;
129 @@ -761,6 +763,7 @@ void psxHwWrite32(u32 add, u32 value) {
133 + if (add < 0x1f802000)
134 psxHu32ref(add) = SWAPu32(value);
136 PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
137 diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
138 index f473ddf6..49c4143b 100644
139 --- a/libpcsxcore/psxinterpreter.c
140 +++ b/libpcsxcore/psxinterpreter.c
141 @@ -237,7 +237,7 @@ static inline void addCycle(psxRegisters *regs)
143 assert(regs->subCycleStep >= 0x10000);
144 regs->subCycle += regs->subCycleStep;
145 - regs->cycle += regs->subCycle >> 16;
146 + regs->cycle += 2; //regs->subCycle >> 16;
147 regs->subCycle &= 0xffff;
150 @@ -434,7 +434,9 @@ static void doBranch(psxRegisters *regs, u32 tar, enum R3000Abdt taken) {
151 regs->CP0.n.Target = pc_final;
154 + psxRegs.cycle += 2;
156 + psxRegs.cycle -= 2;
159 static void doBranchReg(psxRegisters *regs, u32 tar) {
160 @@ -959,7 +961,7 @@ void MTC0(psxRegisters *regs_, int reg, u32 val) {
164 -OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); }
165 +OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); psxBranchTest(); }
168 static inline void psxNULLne(psxRegisters *regs) {
169 @@ -1167,18 +1169,20 @@ static void intReset() {
170 static inline void execI_(u8 **memRLUT, psxRegisters *regs) {
178 regs->code = fetch(regs, memRLUT, pc);
179 psxBSC[regs->code >> 26](regs, regs->code);
180 + psxRegs.cycle += 2;
181 + fetchNoCache(regs, memRLUT, regs->pc); // bus err check
184 static inline void execIbp(u8 **memRLUT, psxRegisters *regs) {
191 if (execBreakCheck(regs, pc))
192 @@ -1187,6 +1191,8 @@ static inline void execIbp(u8 **memRLUT, psxRegisters *regs) {
194 regs->code = fetch(regs, memRLUT, pc);
195 psxBSC[regs->code >> 26](regs, regs->code);
196 + psxRegs.cycle += 2;
197 + fetchNoCache(regs, memRLUT, regs->pc); // bus err check
200 static void intExecute() {
201 @@ -1216,6 +1222,30 @@ void intExecuteBlock(enum blockExecCaller caller) {
202 execI_(memRLUT, regs_);
205 +extern void do_insn_trace(void);
207 +void intExecuteT() {
208 + psxRegisters *regs_ = &psxRegs;
209 + u8 **memRLUT = psxMemRLUT;
214 + execIbp(memRLUT, regs_);
218 +void intExecuteBlockT() {
219 + psxRegisters *regs_ = &psxRegs;
220 + u8 **memRLUT = psxMemRLUT;
223 + while (!branchSeen) {
225 + execIbp(memRLUT, regs_);
229 static void intClear(u32 Addr, u32 Size) {
232 @@ -1244,7 +1274,7 @@ static void setupCop(u32 sr)
234 psxBSC[17] = psxCOPd;
236 - psxBSC[18] = Config.DisableStalls ? psxCOP2 : psxCOP2_stall;
237 + psxBSC[18] = psxCOP2;
239 psxBSC[18] = psxCOPd;
241 @@ -1263,7 +1293,7 @@ void intApplyConfig() {
242 assert(psxSPC[26] == psxDIV || psxSPC[26] == psxDIV_stall);
243 assert(psxSPC[27] == psxDIVU || psxSPC[27] == psxDIVU_stall);
245 - if (Config.DisableStalls) {
247 psxBSC[18] = psxCOP2;
248 psxBSC[50] = gteLWC2;
249 psxBSC[58] = gteSWC2;
250 diff --git a/libpcsxcore/psxmem.c b/libpcsxcore/psxmem.c
251 index 54219ae0..41168ced 100644
252 --- a/libpcsxcore/psxmem.c
253 +++ b/libpcsxcore/psxmem.c
254 @@ -278,10 +278,13 @@ void psxMemOnIsolate(int enable)
255 : R3000ACPU_NOTIFY_CACHE_UNISOLATED, NULL);
258 +extern u32 last_io_addr;
260 u8 psxMemRead8(u32 mem) {
264 + last_io_addr = mem;
266 if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
267 if ((mem & 0xffff) < 0x400)
268 @@ -307,6 +310,7 @@ u16 psxMemRead16(u32 mem) {
272 + last_io_addr = mem;
274 if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
275 if ((mem & 0xffff) < 0x400)
276 @@ -332,6 +336,7 @@ u32 psxMemRead32(u32 mem) {
280 + last_io_addr = mem;
282 if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
283 if ((mem & 0xffff) < 0x400)
284 @@ -359,6 +364,7 @@ void psxMemWrite8(u32 mem, u8 value) {
288 + last_io_addr = mem;
290 if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
291 if ((mem & 0xffff) < 0x400)
292 @@ -386,6 +392,7 @@ void psxMemWrite16(u32 mem, u16 value) {
296 + last_io_addr = mem;
298 if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
299 if ((mem & 0xffff) < 0x400)
300 @@ -413,6 +420,7 @@ void psxMemWrite32(u32 mem, u32 value) {
304 + last_io_addr = mem;
305 // if ((mem&0x1fffff) == 0x71E18 || value == 0x48088800) SysPrintf("t2fix!!\n");
307 if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
308 @@ -431,6 +439,8 @@ void psxMemWrite32(u32 mem, u32 value) {
311 if (mem == 0xfffe0130) {
312 +extern u32 handler_cycle;
313 +handler_cycle = psxRegs.cycle;
314 psxRegs.biuReg = value;
317 diff --git a/libpcsxcore/r3000a.c b/libpcsxcore/r3000a.c
318 index dffbf6e7..0a3bdb65 100644
319 --- a/libpcsxcore/r3000a.c
320 +++ b/libpcsxcore/r3000a.c
321 @@ -124,6 +124,8 @@ void psxException(u32 cause, enum R3000Abdt bdt, psxCP0Regs *cp0) {
324 void psxBranchTest() {
325 + extern u32 irq_test_cycle;
326 + irq_test_cycle = psxRegs.cycle;
327 if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)