1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Functions for PSX hardware control.
29 if (Config.Sio) psxHu32ref(0x1070) |= SWAP32(0x80);
30 if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAP32(0x200);
32 memset(psxH, 0, 0x10000);
34 mdecInit(); // initialize mdec decoder
39 u8 psxHwRead8(u32 add) {
43 case 0x1f801040: hard = sioRead8();break;
\r
45 case 0x1f801050: hard = SIO1_readData8(); break;
\r
47 case 0x1f801800: hard = cdrRead0(); break;
48 case 0x1f801801: hard = cdrRead1(); break;
49 case 0x1f801802: hard = cdrRead2(); break;
50 case 0x1f801803: hard = cdrRead3(); break;
54 PSXHW_LOG("*Unkwnown 8bit read at address %x\n", add);
60 PSXHW_LOG("*Known 8bit read at address %x value %x\n", add, hard);
65 u16 psxHwRead16(u32 add) {
70 case 0x1f801070: PSXHW_LOG("IREG 16bit read %x\n", psxHu16(0x1070));
71 return psxHu16(0x1070);
74 case 0x1f801074: PSXHW_LOG("IMASK 16bit read %x\n", psxHu16(0x1074));
75 return psxHu16(0x1074);
80 hard|= sioRead8() << 8;
82 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
86 hard = sioReadStat16();
88 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
92 hard = sioReadMode16();
94 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
98 hard = sioReadCtrl16();
100 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
104 hard = sioReadBaud16();
106 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
109 #ifdef ENABLE_SIO1API
111 hard = SIO1_readData16();
114 hard = SIO1_readStat16();
117 hard = SIO1_readCtrl16();
120 hard = SIO1_readBaud16();
124 hard = psxRcntRcount(0);
126 PSXHW_LOG("T0 count read16: %x\n", hard);
130 hard = psxRcntRmode(0);
132 PSXHW_LOG("T0 mode read16: %x\n", hard);
136 hard = psxRcntRtarget(0);
138 PSXHW_LOG("T0 target read16: %x\n", hard);
142 hard = psxRcntRcount(1);
144 PSXHW_LOG("T1 count read16: %x\n", hard);
148 hard = psxRcntRmode(1);
150 PSXHW_LOG("T1 mode read16: %x\n", hard);
154 hard = psxRcntRtarget(1);
156 PSXHW_LOG("T1 target read16: %x\n", hard);
160 hard = psxRcntRcount(2);
162 PSXHW_LOG("T2 count read16: %x\n", hard);
166 hard = psxRcntRmode(2);
168 PSXHW_LOG("T2 mode read16: %x\n", hard);
172 hard = psxRcntRtarget(2);
174 PSXHW_LOG("T2 target read16: %x\n", hard);
178 //case 0x1f802030: hard = //int_2000????
179 //case 0x1f802040: hard =//dip switches...??
182 if (add >= 0x1f801c00 && add < 0x1f801e00) {
183 hard = SPU_readRegister(add);
187 PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add);
194 PSXHW_LOG("*Known 16bit read at address %x value %x\n", add, hard);
199 u32 psxHwRead32(u32 add) {
205 hard |= sioRead8() << 8;
206 hard |= sioRead8() << 16;
207 hard |= sioRead8() << 24;
209 PAD_LOG("sio read32 ;ret = %x\n", hard);
212 #ifdef ENABLE_SIO1API
214 hard = SIO1_readData32();
219 PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060));
220 return psxHu32(0x1060);
223 case 0x1f801070: PSXHW_LOG("IREG 32bit read %x\n", psxHu32(0x1070));
224 return psxHu32(0x1070);
227 case 0x1f801074: PSXHW_LOG("IMASK 32bit read %x\n", psxHu32(0x1074));
228 return psxHu32(0x1074);
232 hard = GPU_readData();
234 PSXHW_LOG("GPU DATA 32bit read %x\n", hard);
238 hard = GPU_readStatus();
240 PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
244 case 0x1f801820: hard = mdecRead0(); break;
245 case 0x1f801824: hard = mdecRead1(); break;
249 PSXHW_LOG("DMA2 MADR 32bit read %x\n", psxHu32(0x10a0));
250 return SWAPu32(HW_DMA2_MADR);
252 PSXHW_LOG("DMA2 BCR 32bit read %x\n", psxHu32(0x10a4));
253 return SWAPu32(HW_DMA2_BCR);
255 PSXHW_LOG("DMA2 CHCR 32bit read %x\n", psxHu32(0x10a8));
256 return SWAPu32(HW_DMA2_CHCR);
261 PSXHW_LOG("DMA3 MADR 32bit read %x\n", psxHu32(0x10b0));
262 return SWAPu32(HW_DMA3_MADR);
264 PSXHW_LOG("DMA3 BCR 32bit read %x\n", psxHu32(0x10b4));
265 return SWAPu32(HW_DMA3_BCR);
267 PSXHW_LOG("DMA3 CHCR 32bit read %x\n", psxHu32(0x10b8));
268 return SWAPu32(HW_DMA3_CHCR);
273 PSXHW_LOG("DMA PCR 32bit read %x\n", psxHu32(0x10f0));
274 return SWAPu32(HW_DMA_PCR); // dma rest channel
276 PSXHW_LOG("DMA ICR 32bit read %x\n", psxHu32(0x10f4));
277 return SWAPu32(HW_DMA_ICR); // interrupt enabler?*/
280 // time for rootcounters :)
282 hard = psxRcntRcount(0);
284 PSXHW_LOG("T0 count read32: %x\n", hard);
288 hard = psxRcntRmode(0);
290 PSXHW_LOG("T0 mode read32: %x\n", hard);
294 hard = psxRcntRtarget(0);
296 PSXHW_LOG("T0 target read32: %x\n", hard);
300 hard = psxRcntRcount(1);
302 PSXHW_LOG("T1 count read32: %x\n", hard);
306 hard = psxRcntRmode(1);
308 PSXHW_LOG("T1 mode read32: %x\n", hard);
312 hard = psxRcntRtarget(1);
314 PSXHW_LOG("T1 target read32: %x\n", hard);
318 hard = psxRcntRcount(2);
320 PSXHW_LOG("T2 count read32: %x\n", hard);
324 hard = psxRcntRmode(2);
326 PSXHW_LOG("T2 mode read32: %x\n", hard);
330 hard = psxRcntRtarget(2);
332 PSXHW_LOG("T2 target read32: %x\n", hard);
339 PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add);
344 PSXHW_LOG("*Known 32bit read at address %x\n", add);
349 void psxHwWrite8(u32 add, u8 value) {
351 case 0x1f801040: sioWrite8(value); break;
\r
352 #ifdef ENABLE_SIO1API
353 case 0x1f801050: SIO1_writeData8(value); break;
\r
355 case 0x1f801800: cdrWrite0(value); break;
356 case 0x1f801801: cdrWrite1(value); break;
357 case 0x1f801802: cdrWrite2(value); break;
358 case 0x1f801803: cdrWrite3(value); break;
363 PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
369 PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
373 void psxHwWrite16(u32 add, u16 value) {
376 sioWrite8((unsigned char)value);
377 sioWrite8((unsigned char)(value>>8));
379 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
383 sioWriteStat16(value);
385 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
389 sioWriteMode16(value);
391 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
394 case 0x1f80104a: // control register
395 sioWriteCtrl16(value);
397 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
400 case 0x1f80104e: // baudrate register
401 sioWriteBaud16(value);
403 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
406 #ifdef ENABLE_SIO1API
408 SIO1_writeData16(value);
411 SIO1_writeStat16(value);
414 SIO1_writeCtrl16(value);
417 SIO1_writeBaud16(value);
422 PSXHW_LOG("IREG 16bit write %x\n", value);
424 if (Config.Sio) psxHu16ref(0x1070) |= SWAPu16(0x80);
425 if (Config.SpuIrq) psxHu16ref(0x1070) |= SWAPu16(0x200);
426 psxHu16ref(0x1070) &= SWAPu16((psxHu16(0x1074) & value));
431 PSXHW_LOG("IMASK 16bit write %x\n", value);
433 psxHu16ref(0x1074) = SWAPu16(value);
434 if (psxHu16ref(0x1070) & value)
435 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
440 PSXHW_LOG("COUNTER 0 COUNT 16bit write %x\n", value);
442 psxRcntWcount(0, value); return;
445 PSXHW_LOG("COUNTER 0 MODE 16bit write %x\n", value);
447 psxRcntWmode(0, value); return;
450 PSXHW_LOG("COUNTER 0 TARGET 16bit write %x\n", value);
452 psxRcntWtarget(0, value); return;
456 PSXHW_LOG("COUNTER 1 COUNT 16bit write %x\n", value);
458 psxRcntWcount(1, value); return;
461 PSXHW_LOG("COUNTER 1 MODE 16bit write %x\n", value);
463 psxRcntWmode(1, value); return;
466 PSXHW_LOG("COUNTER 1 TARGET 16bit write %x\n", value);
468 psxRcntWtarget(1, value); return;
472 PSXHW_LOG("COUNTER 2 COUNT 16bit write %x\n", value);
474 psxRcntWcount(2, value); return;
477 PSXHW_LOG("COUNTER 2 MODE 16bit write %x\n", value);
479 psxRcntWmode(2, value); return;
482 PSXHW_LOG("COUNTER 2 TARGET 16bit write %x\n", value);
484 psxRcntWtarget(2, value); return;
487 if (add>=0x1f801c00 && add<0x1f801e00) {
488 SPU_writeRegister(add, value);
492 psxHu16ref(add) = SWAPu16(value);
494 PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
498 psxHu16ref(add) = SWAPu16(value);
500 PSXHW_LOG("*Known 16bit write at address %x value %x\n", add, value);
504 #define DmaExec(n) { \
505 HW_DMA##n##_CHCR = SWAPu32(value); \
507 if (SWAPu32(HW_DMA##n##_CHCR) & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8 << (n * 4))) { \
508 psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), SWAPu32(HW_DMA##n##_CHCR)); \
512 void psxHwWrite32(u32 add, u32 value) {
515 sioWrite8((unsigned char)value);
516 sioWrite8((unsigned char)((value&0xff) >> 8));
517 sioWrite8((unsigned char)((value&0xff) >> 16));
518 sioWrite8((unsigned char)((value&0xff) >> 24));
520 PAD_LOG("sio write32 %x\n", value);
523 #ifdef ENABLE_SIO1API
525 SIO1_writeData32(value);
530 PSXHW_LOG("RAM size write %x\n", value);
531 psxHu32ref(add) = SWAPu32(value);
537 PSXHW_LOG("IREG 32bit write %x\n", value);
539 if (Config.Sio) psxHu32ref(0x1070) |= SWAPu32(0x80);
540 if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAPu32(0x200);
541 psxHu32ref(0x1070) &= SWAPu32((psxHu32(0x1074) & value));
545 PSXHW_LOG("IMASK 32bit write %x\n", value);
547 psxHu32ref(0x1074) = SWAPu32(value);
548 if (psxHu32ref(0x1070) & value)
549 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
554 PSXHW_LOG("DMA0 MADR 32bit write %x\n", value);
555 HW_DMA0_MADR = SWAPu32(value); return; // DMA0 madr
557 PSXHW_LOG("DMA0 BCR 32bit write %x\n", value);
558 HW_DMA0_BCR = SWAPu32(value); return; // DMA0 bcr
562 PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value);
564 DmaExec(0); // DMA0 chcr (MDEC in DMA)
569 PSXHW_LOG("DMA1 MADR 32bit write %x\n", value);
570 HW_DMA1_MADR = SWAPu32(value); return; // DMA1 madr
572 PSXHW_LOG("DMA1 BCR 32bit write %x\n", value);
573 HW_DMA1_BCR = SWAPu32(value); return; // DMA1 bcr
577 PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value);
579 DmaExec(1); // DMA1 chcr (MDEC out DMA)
584 PSXHW_LOG("DMA2 MADR 32bit write %x\n", value);
585 HW_DMA2_MADR = SWAPu32(value); return; // DMA2 madr
587 PSXHW_LOG("DMA2 BCR 32bit write %x\n", value);
588 HW_DMA2_BCR = SWAPu32(value); return; // DMA2 bcr
592 PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value);
594 DmaExec(2); // DMA2 chcr (GPU DMA)
599 PSXHW_LOG("DMA3 MADR 32bit write %x\n", value);
600 HW_DMA3_MADR = SWAPu32(value); return; // DMA3 madr
602 PSXHW_LOG("DMA3 BCR 32bit write %x\n", value);
603 HW_DMA3_BCR = SWAPu32(value); return; // DMA3 bcr
607 PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value);
609 DmaExec(3); // DMA3 chcr (CDROM DMA)
615 PSXHW_LOG("DMA4 MADR 32bit write %x\n", value);
616 HW_DMA4_MADR = SWAPu32(value); return; // DMA4 madr
618 PSXHW_LOG("DMA4 BCR 32bit write %x\n", value);
619 HW_DMA4_BCR = SWAPu32(value); return; // DMA4 bcr
623 PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value);
625 DmaExec(4); // DMA4 chcr (SPU DMA)
629 case 0x1f8010d0: break; //DMA5write_madr();
630 case 0x1f8010d4: break; //DMA5write_bcr();
631 case 0x1f8010d8: break; //DMA5write_chcr(); // Not needed
636 PSXHW_LOG("DMA6 MADR 32bit write %x\n", value);
637 HW_DMA6_MADR = SWAPu32(value); return; // DMA6 bcr
639 PSXHW_LOG("DMA6 BCR 32bit write %x\n", value);
640 HW_DMA6_BCR = SWAPu32(value); return; // DMA6 bcr
644 PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value);
646 DmaExec(6); // DMA6 chcr (OT clear)
651 PSXHW_LOG("DMA PCR 32bit write %x\n", value);
652 HW_DMA_PCR = SWAPu32(value);
658 PSXHW_LOG("DMA ICR 32bit write %x\n", value);
661 u32 tmp = (~value) & SWAPu32(HW_DMA_ICR);
662 HW_DMA_ICR = SWAPu32(((tmp ^ value) & 0xffffff) ^ tmp);
668 PSXHW_LOG("GPU DATA 32bit write %x\n", value);
670 GPU_writeData(value); return;
673 PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
675 GPU_writeStatus(value); return;
678 mdecWrite0(value); break;
680 mdecWrite1(value); break;
684 PSXHW_LOG("COUNTER 0 COUNT 32bit write %x\n", value);
686 psxRcntWcount(0, value & 0xffff); return;
689 PSXHW_LOG("COUNTER 0 MODE 32bit write %x\n", value);
691 psxRcntWmode(0, value); return;
694 PSXHW_LOG("COUNTER 0 TARGET 32bit write %x\n", value);
696 psxRcntWtarget(0, value & 0xffff); return; // HW_DMA_ICR&= SWAP32((~value)&0xff000000);
700 PSXHW_LOG("COUNTER 1 COUNT 32bit write %x\n", value);
702 psxRcntWcount(1, value & 0xffff); return;
705 PSXHW_LOG("COUNTER 1 MODE 32bit write %x\n", value);
707 psxRcntWmode(1, value); return;
710 PSXHW_LOG("COUNTER 1 TARGET 32bit write %x\n", value);
712 psxRcntWtarget(1, value & 0xffff); return;
716 PSXHW_LOG("COUNTER 2 COUNT 32bit write %x\n", value);
718 psxRcntWcount(2, value & 0xffff); return;
721 PSXHW_LOG("COUNTER 2 MODE 32bit write %x\n", value);
723 psxRcntWmode(2, value); return;
726 PSXHW_LOG("COUNTER 2 TARGET 32bit write %x\n", value);
728 psxRcntWtarget(2, value & 0xffff); return;
731 psxHu32ref(add) = SWAPu32(value);
733 PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
737 psxHu32ref(add) = SWAPu32(value);
739 PSXHW_LOG("*Known 32bit write at address %x value %x\n", add, value);
743 int psxHwFreeze(gzFile f, int Mode) {