1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Functions for PSX hardware control.
30 //#define PSXHW_LOG printf
33 memset(psxH, 0, 0x10000);
35 mdecInit(); // initialize mdec decoder
38 HW_GPU_STATUS = SWAP32(0x14802000);
41 u8 psxHwRead8(u32 add) {
44 switch (add & 0x1fffffff) {
45 case 0x1f801040: hard = sioRead8();break;
\r
47 case 0x1f801050: hard = SIO1_readData8(); break;
\r
49 case 0x1f801800: hard = cdrRead0(); break;
50 case 0x1f801801: hard = cdrRead1(); break;
51 case 0x1f801802: hard = cdrRead2(); break;
52 case 0x1f801803: hard = cdrRead3(); break;
56 PSXHW_LOG("*Unkwnown 8bit read at address %x\n", add);
62 PSXHW_LOG("*Known 8bit read at address %x value %x\n", add, hard);
67 u16 psxHwRead16(u32 add) {
70 switch (add & 0x1fffffff) {
72 case 0x1f801070: PSXHW_LOG("IREG 16bit read %x\n", psxHu16(0x1070));
73 return psxHu16(0x1070);
76 case 0x1f801074: PSXHW_LOG("IMASK 16bit read %x\n", psxHu16(0x1074));
77 return psxHu16(0x1074);
82 hard|= sioRead8() << 8;
84 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
88 hard = sioReadStat16();
90 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
94 hard = sioReadMode16();
96 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
100 hard = sioReadCtrl16();
102 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
106 hard = sioReadBaud16();
108 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
111 #ifdef ENABLE_SIO1API
113 hard = SIO1_readData16();
116 hard = SIO1_readStat16();
119 hard = SIO1_readCtrl16();
122 hard = SIO1_readBaud16();
125 /* Fixes Armored Core misdetecting the Link cable being detected.
126 * We want to turn that thing off and force it to do local multiplayer instead.
127 * Thanks Sony for the fix, they fixed it in their PS Classic fork.
133 hard = psxRcntRcount(0);
135 PSXHW_LOG("T0 count read16: %x\n", hard);
139 hard = psxRcntRmode(0);
141 PSXHW_LOG("T0 mode read16: %x\n", hard);
145 hard = psxRcntRtarget(0);
147 PSXHW_LOG("T0 target read16: %x\n", hard);
151 hard = psxRcntRcount(1);
153 PSXHW_LOG("T1 count read16: %x\n", hard);
157 hard = psxRcntRmode(1);
159 PSXHW_LOG("T1 mode read16: %x\n", hard);
163 hard = psxRcntRtarget(1);
165 PSXHW_LOG("T1 target read16: %x\n", hard);
169 hard = psxRcntRcount(2);
171 PSXHW_LOG("T2 count read16: %x\n", hard);
175 hard = psxRcntRmode(2);
177 PSXHW_LOG("T2 mode read16: %x\n", hard);
181 hard = psxRcntRtarget(2);
183 PSXHW_LOG("T2 target read16: %x\n", hard);
187 //case 0x1f802030: hard = //int_2000????
188 //case 0x1f802040: hard =//dip switches...??
192 log_unhandled("cdrom r16 %x\n", add);
195 if (add >= 0x1f801c00 && add < 0x1f801e00) {
196 hard = SPU_readRegister(add);
200 PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add);
207 PSXHW_LOG("*Known 16bit read at address %x value %x\n", add, hard);
212 u32 psxHwRead32(u32 add) {
215 switch (add & 0x1fffffff) {
218 hard |= sioRead8() << 8;
219 hard |= sioRead8() << 16;
220 hard |= sioRead8() << 24;
222 PAD_LOG("sio read32 ;ret = %x\n", hard);
225 #ifdef ENABLE_SIO1API
227 hard = SIO1_readData32();
232 PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060));
233 return psxHu32(0x1060);
236 case 0x1f801070: PSXHW_LOG("IREG 32bit read %x\n", psxHu32(0x1070));
237 return psxHu32(0x1070);
240 case 0x1f801074: PSXHW_LOG("IMASK 32bit read %x\n", psxHu32(0x1074));
241 return psxHu32(0x1074);
245 hard = GPU_readData();
247 PSXHW_LOG("GPU DATA 32bit read %x\n", hard);
252 hard = SWAP32(HW_GPU_STATUS);
253 if (hSyncCount < 240 && (hard & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
254 hard |= PSXGPU_LCF & (psxRegs.cycle << 20);
256 PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
260 case 0x1f801820: hard = mdecRead0(); break;
261 case 0x1f801824: hard = mdecRead1(); break;
265 PSXHW_LOG("DMA2 MADR 32bit read %x\n", psxHu32(0x10a0));
266 return SWAPu32(HW_DMA2_MADR);
268 PSXHW_LOG("DMA2 BCR 32bit read %x\n", psxHu32(0x10a4));
269 return SWAPu32(HW_DMA2_BCR);
271 PSXHW_LOG("DMA2 CHCR 32bit read %x\n", psxHu32(0x10a8));
272 return SWAPu32(HW_DMA2_CHCR);
277 PSXHW_LOG("DMA3 MADR 32bit read %x\n", psxHu32(0x10b0));
278 return SWAPu32(HW_DMA3_MADR);
280 PSXHW_LOG("DMA3 BCR 32bit read %x\n", psxHu32(0x10b4));
281 return SWAPu32(HW_DMA3_BCR);
283 PSXHW_LOG("DMA3 CHCR 32bit read %x\n", psxHu32(0x10b8));
284 return SWAPu32(HW_DMA3_CHCR);
289 PSXHW_LOG("DMA PCR 32bit read %x\n", psxHu32(0x10f0));
290 return SWAPu32(HW_DMA_PCR); // dma rest channel
292 PSXHW_LOG("DMA ICR 32bit read %x\n", psxHu32(0x10f4));
293 return SWAPu32(HW_DMA_ICR); // interrupt enabler?*/
296 // time for rootcounters :)
298 hard = psxRcntRcount(0);
300 PSXHW_LOG("T0 count read32: %x\n", hard);
304 hard = psxRcntRmode(0);
306 PSXHW_LOG("T0 mode read32: %x\n", hard);
310 hard = psxRcntRtarget(0);
312 PSXHW_LOG("T0 target read32: %x\n", hard);
316 hard = psxRcntRcount(1);
318 PSXHW_LOG("T1 count read32: %x\n", hard);
322 hard = psxRcntRmode(1);
324 PSXHW_LOG("T1 mode read32: %x\n", hard);
328 hard = psxRcntRtarget(1);
330 PSXHW_LOG("T1 target read32: %x\n", hard);
334 hard = psxRcntRcount(2);
336 PSXHW_LOG("T2 count read32: %x\n", hard);
340 hard = psxRcntRmode(2);
342 PSXHW_LOG("T2 mode read32: %x\n", hard);
346 hard = psxRcntRtarget(2);
348 PSXHW_LOG("T2 target read32: %x\n", hard);
353 log_unhandled("cdrom r32 %x\n", add);
358 PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add);
363 PSXHW_LOG("*Known 32bit read at address %x\n", add);
368 void psxHwWrite8(u32 add, u8 value) {
369 switch (add & 0x1fffffff) {
370 case 0x1f801040: sioWrite8(value); break;
\r
371 #ifdef ENABLE_SIO1API
372 case 0x1f801050: SIO1_writeData8(value); break;
\r
374 case 0x1f801800: cdrWrite0(value); break;
375 case 0x1f801801: cdrWrite1(value); break;
376 case 0x1f801802: cdrWrite2(value); break;
377 case 0x1f801803: cdrWrite3(value); break;
382 PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
388 PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
392 void psxHwWrite16(u32 add, u16 value) {
393 switch (add & 0x1fffffff) {
395 sioWrite8((unsigned char)value);
396 sioWrite8((unsigned char)(value>>8));
398 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
402 sioWriteStat16(value);
404 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
408 sioWriteMode16(value);
410 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
413 case 0x1f80104a: // control register
414 sioWriteCtrl16(value);
416 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
419 case 0x1f80104e: // baudrate register
420 sioWriteBaud16(value);
422 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
425 #ifdef ENABLE_SIO1API
427 SIO1_writeData16(value);
430 SIO1_writeStat16(value);
433 SIO1_writeCtrl16(value);
436 SIO1_writeBaud16(value);
441 PSXHW_LOG("IREG 16bit write %x\n", value);
443 psxHu16ref(0x1070) &= SWAPu16(value);
448 PSXHW_LOG("IMASK 16bit write %x\n", value);
450 psxHu16ref(0x1074) = SWAPu16(value);
451 if (psxHu16ref(0x1070) & SWAPu16(value))
452 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
457 PSXHW_LOG("COUNTER 0 COUNT 16bit write %x\n", value);
459 psxRcntWcount(0, value); return;
462 PSXHW_LOG("COUNTER 0 MODE 16bit write %x\n", value);
464 psxRcntWmode(0, value); return;
467 PSXHW_LOG("COUNTER 0 TARGET 16bit write %x\n", value);
469 psxRcntWtarget(0, value); return;
473 PSXHW_LOG("COUNTER 1 COUNT 16bit write %x\n", value);
475 psxRcntWcount(1, value); return;
478 PSXHW_LOG("COUNTER 1 MODE 16bit write %x\n", value);
480 psxRcntWmode(1, value); return;
483 PSXHW_LOG("COUNTER 1 TARGET 16bit write %x\n", value);
485 psxRcntWtarget(1, value); return;
489 PSXHW_LOG("COUNTER 2 COUNT 16bit write %x\n", value);
491 psxRcntWcount(2, value); return;
494 PSXHW_LOG("COUNTER 2 MODE 16bit write %x\n", value);
496 psxRcntWmode(2, value); return;
499 PSXHW_LOG("COUNTER 2 TARGET 16bit write %x\n", value);
501 psxRcntWtarget(2, value); return;
504 if (add>=0x1f801c00 && add<0x1f801e00) {
505 SPU_writeRegister(add, value, psxRegs.cycle);
509 psxHu16ref(add) = SWAPu16(value);
511 PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
515 psxHu16ref(add) = SWAPu16(value);
517 PSXHW_LOG("*Known 16bit write at address %x value %x\n", add, value);
521 #define DmaExec(n) { \
522 if (value & SWAPu32(HW_DMA##n##_CHCR) & 0x01000000) \
523 log_unhandled("dma" #n " %08x -> %08x\n", HW_DMA##n##_CHCR, value); \
524 HW_DMA##n##_CHCR = SWAPu32(value); \
526 if (SWAPu32(HW_DMA##n##_CHCR) & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8 << (n * 4))) { \
527 psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), SWAPu32(HW_DMA##n##_CHCR)); \
531 void psxHwWrite32(u32 add, u32 value) {
532 switch (add & 0x1fffffff) {
534 sioWrite8((unsigned char)value);
535 sioWrite8((unsigned char)((value&0xff) >> 8));
536 sioWrite8((unsigned char)((value&0xff) >> 16));
537 sioWrite8((unsigned char)((value&0xff) >> 24));
539 PAD_LOG("sio write32 %x\n", value);
542 #ifdef ENABLE_SIO1API
544 SIO1_writeData32(value);
549 PSXHW_LOG("RAM size write %x\n", value);
550 psxHu32ref(add) = SWAPu32(value);
556 PSXHW_LOG("IREG 32bit write %x\n", value);
558 psxHu32ref(0x1070) &= SWAPu32(value);
562 PSXHW_LOG("IMASK 32bit write %x\n", value);
564 psxHu32ref(0x1074) = SWAPu32(value);
565 if (psxHu32ref(0x1070) & SWAPu32(value))
566 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
571 PSXHW_LOG("DMA0 MADR 32bit write %x\n", value);
572 HW_DMA0_MADR = SWAPu32(value); return; // DMA0 madr
574 PSXHW_LOG("DMA0 BCR 32bit write %x\n", value);
575 HW_DMA0_BCR = SWAPu32(value); return; // DMA0 bcr
579 PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value);
581 DmaExec(0); // DMA0 chcr (MDEC in DMA)
586 PSXHW_LOG("DMA1 MADR 32bit write %x\n", value);
587 HW_DMA1_MADR = SWAPu32(value); return; // DMA1 madr
589 PSXHW_LOG("DMA1 BCR 32bit write %x\n", value);
590 HW_DMA1_BCR = SWAPu32(value); return; // DMA1 bcr
594 PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value);
596 DmaExec(1); // DMA1 chcr (MDEC out DMA)
601 PSXHW_LOG("DMA2 MADR 32bit write %x\n", value);
602 HW_DMA2_MADR = SWAPu32(value); return; // DMA2 madr
604 PSXHW_LOG("DMA2 BCR 32bit write %x\n", value);
605 HW_DMA2_BCR = SWAPu32(value); return; // DMA2 bcr
609 PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value);
611 DmaExec(2); // DMA2 chcr (GPU DMA)
616 PSXHW_LOG("DMA3 MADR 32bit write %x\n", value);
617 HW_DMA3_MADR = SWAPu32(value); return; // DMA3 madr
619 PSXHW_LOG("DMA3 BCR 32bit write %x\n", value);
620 HW_DMA3_BCR = SWAPu32(value); return; // DMA3 bcr
624 PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value);
626 DmaExec(3); // DMA3 chcr (CDROM DMA)
632 PSXHW_LOG("DMA4 MADR 32bit write %x\n", value);
633 HW_DMA4_MADR = SWAPu32(value); return; // DMA4 madr
635 PSXHW_LOG("DMA4 BCR 32bit write %x\n", value);
636 HW_DMA4_BCR = SWAPu32(value); return; // DMA4 bcr
640 PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value);
642 DmaExec(4); // DMA4 chcr (SPU DMA)
646 case 0x1f8010d0: break; //DMA5write_madr();
647 case 0x1f8010d4: break; //DMA5write_bcr();
648 case 0x1f8010d8: break; //DMA5write_chcr(); // Not needed
653 PSXHW_LOG("DMA6 MADR 32bit write %x\n", value);
654 HW_DMA6_MADR = SWAPu32(value); return; // DMA6 bcr
656 PSXHW_LOG("DMA6 BCR 32bit write %x\n", value);
657 HW_DMA6_BCR = SWAPu32(value); return; // DMA6 bcr
661 PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value);
663 DmaExec(6); // DMA6 chcr (OT clear)
668 PSXHW_LOG("DMA PCR 32bit write %x\n", value);
669 HW_DMA_PCR = SWAPu32(value);
675 PSXHW_LOG("DMA ICR 32bit write %x\n", value);
678 u32 tmp = value & 0x00ff803f;
679 tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
680 if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
681 || tmp & HW_DMA_ICR_BUS_ERROR) {
682 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
683 psxHu32ref(0x1070) |= SWAP32(8);
684 tmp |= HW_DMA_ICR_IRQ_SENT;
686 HW_DMA_ICR = SWAPu32(tmp);
692 PSXHW_LOG("GPU DATA 32bit write %x\n", value);
694 GPU_writeData(value); return;
697 PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
699 GPU_writeStatus(value);
704 mdecWrite0(value); break;
706 mdecWrite1(value); break;
710 PSXHW_LOG("COUNTER 0 COUNT 32bit write %x\n", value);
712 psxRcntWcount(0, value & 0xffff); return;
715 PSXHW_LOG("COUNTER 0 MODE 32bit write %x\n", value);
717 psxRcntWmode(0, value); return;
720 PSXHW_LOG("COUNTER 0 TARGET 32bit write %x\n", value);
722 psxRcntWtarget(0, value & 0xffff); return; // HW_DMA_ICR&= SWAP32((~value)&0xff000000);
726 PSXHW_LOG("COUNTER 1 COUNT 32bit write %x\n", value);
728 psxRcntWcount(1, value & 0xffff); return;
731 PSXHW_LOG("COUNTER 1 MODE 32bit write %x\n", value);
733 psxRcntWmode(1, value); return;
736 PSXHW_LOG("COUNTER 1 TARGET 32bit write %x\n", value);
738 psxRcntWtarget(1, value & 0xffff); return;
742 PSXHW_LOG("COUNTER 2 COUNT 32bit write %x\n", value);
744 psxRcntWcount(2, value & 0xffff); return;
747 PSXHW_LOG("COUNTER 2 MODE 32bit write %x\n", value);
749 psxRcntWmode(2, value); return;
752 PSXHW_LOG("COUNTER 2 TARGET 32bit write %x\n", value);
754 psxRcntWtarget(2, value & 0xffff); return;
757 // Dukes of Hazard 2 - car engine noise
758 if (add>=0x1f801c00 && add<0x1f801e00) {
759 SPU_writeRegister(add, value&0xffff, psxRegs.cycle);
760 SPU_writeRegister(add + 2, value>>16, psxRegs.cycle);
764 psxHu32ref(add) = SWAPu32(value);
766 PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
770 psxHu32ref(add) = SWAPu32(value);
772 PSXHW_LOG("*Known 32bit write at address %x value %x\n", add, value);
776 int psxHwFreeze(void *f, int Mode) {