1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Functions for PSX hardware control.
29 //#define PSXHW_LOG printf
32 if (Config.Sio) psxHu32ref(0x1070) |= SWAP32(0x80);
33 if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAP32(0x200);
35 memset(psxH, 0, 0x10000);
37 mdecInit(); // initialize mdec decoder
42 u8 psxHwRead8(u32 add) {
46 case 0x1f801040: hard = sioRead8();break;
\r
48 case 0x1f801050: hard = SIO1_readData8(); break;
\r
50 case 0x1f801800: hard = cdrRead0(); break;
51 case 0x1f801801: hard = cdrRead1(); break;
52 case 0x1f801802: hard = cdrRead2(); break;
53 case 0x1f801803: hard = cdrRead3(); break;
57 PSXHW_LOG("*Unkwnown 8bit read at address %x\n", add);
63 PSXHW_LOG("*Known 8bit read at address %x value %x\n", add, hard);
68 u16 psxHwRead16(u32 add) {
73 case 0x1f801070: PSXHW_LOG("IREG 16bit read %x\n", psxHu16(0x1070));
74 return psxHu16(0x1070);
77 case 0x1f801074: PSXHW_LOG("IMASK 16bit read %x\n", psxHu16(0x1074));
78 return psxHu16(0x1074);
83 hard|= sioRead8() << 8;
85 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
89 hard = sioReadStat16();
91 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
95 hard = sioReadMode16();
97 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
101 hard = sioReadCtrl16();
103 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
107 hard = sioReadBaud16();
109 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
112 #ifdef ENABLE_SIO1API
114 hard = SIO1_readData16();
117 hard = SIO1_readStat16();
120 hard = SIO1_readCtrl16();
123 hard = SIO1_readBaud16();
127 hard = psxRcntRcount(0);
129 PSXHW_LOG("T0 count read16: %x\n", hard);
133 hard = psxRcntRmode(0);
135 PSXHW_LOG("T0 mode read16: %x\n", hard);
139 hard = psxRcntRtarget(0);
141 PSXHW_LOG("T0 target read16: %x\n", hard);
145 hard = psxRcntRcount(1);
147 PSXHW_LOG("T1 count read16: %x\n", hard);
151 hard = psxRcntRmode(1);
153 PSXHW_LOG("T1 mode read16: %x\n", hard);
157 hard = psxRcntRtarget(1);
159 PSXHW_LOG("T1 target read16: %x\n", hard);
163 hard = psxRcntRcount(2);
165 PSXHW_LOG("T2 count read16: %x\n", hard);
169 hard = psxRcntRmode(2);
171 PSXHW_LOG("T2 mode read16: %x\n", hard);
175 hard = psxRcntRtarget(2);
177 PSXHW_LOG("T2 target read16: %x\n", hard);
181 //case 0x1f802030: hard = //int_2000????
182 //case 0x1f802040: hard =//dip switches...??
185 if (add >= 0x1f801c00 && add < 0x1f801e00) {
186 hard = SPU_readRegister(add);
190 PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add);
197 PSXHW_LOG("*Known 16bit read at address %x value %x\n", add, hard);
202 u32 psxHwRead32(u32 add) {
208 hard |= sioRead8() << 8;
209 hard |= sioRead8() << 16;
210 hard |= sioRead8() << 24;
212 PAD_LOG("sio read32 ;ret = %x\n", hard);
215 #ifdef ENABLE_SIO1API
217 hard = SIO1_readData32();
222 PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060));
223 return psxHu32(0x1060);
226 case 0x1f801070: PSXHW_LOG("IREG 32bit read %x\n", psxHu32(0x1070));
227 return psxHu32(0x1070);
230 case 0x1f801074: PSXHW_LOG("IMASK 32bit read %x\n", psxHu32(0x1074));
231 return psxHu32(0x1074);
235 hard = GPU_readData();
237 PSXHW_LOG("GPU DATA 32bit read %x\n", hard);
241 hard = GPU_readStatus();
243 PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
247 case 0x1f801820: hard = mdecRead0(); break;
248 case 0x1f801824: hard = mdecRead1(); break;
252 PSXHW_LOG("DMA2 MADR 32bit read %x\n", psxHu32(0x10a0));
253 return SWAPu32(HW_DMA2_MADR);
255 PSXHW_LOG("DMA2 BCR 32bit read %x\n", psxHu32(0x10a4));
256 return SWAPu32(HW_DMA2_BCR);
258 PSXHW_LOG("DMA2 CHCR 32bit read %x\n", psxHu32(0x10a8));
259 return SWAPu32(HW_DMA2_CHCR);
264 PSXHW_LOG("DMA3 MADR 32bit read %x\n", psxHu32(0x10b0));
265 return SWAPu32(HW_DMA3_MADR);
267 PSXHW_LOG("DMA3 BCR 32bit read %x\n", psxHu32(0x10b4));
268 return SWAPu32(HW_DMA3_BCR);
270 PSXHW_LOG("DMA3 CHCR 32bit read %x\n", psxHu32(0x10b8));
271 return SWAPu32(HW_DMA3_CHCR);
276 PSXHW_LOG("DMA PCR 32bit read %x\n", psxHu32(0x10f0));
277 return SWAPu32(HW_DMA_PCR); // dma rest channel
279 PSXHW_LOG("DMA ICR 32bit read %x\n", psxHu32(0x10f4));
280 return SWAPu32(HW_DMA_ICR); // interrupt enabler?*/
283 // time for rootcounters :)
285 hard = psxRcntRcount(0);
287 PSXHW_LOG("T0 count read32: %x\n", hard);
291 hard = psxRcntRmode(0);
293 PSXHW_LOG("T0 mode read32: %x\n", hard);
297 hard = psxRcntRtarget(0);
299 PSXHW_LOG("T0 target read32: %x\n", hard);
303 hard = psxRcntRcount(1);
305 PSXHW_LOG("T1 count read32: %x\n", hard);
309 hard = psxRcntRmode(1);
311 PSXHW_LOG("T1 mode read32: %x\n", hard);
315 hard = psxRcntRtarget(1);
317 PSXHW_LOG("T1 target read32: %x\n", hard);
321 hard = psxRcntRcount(2);
323 PSXHW_LOG("T2 count read32: %x\n", hard);
327 hard = psxRcntRmode(2);
329 PSXHW_LOG("T2 mode read32: %x\n", hard);
333 hard = psxRcntRtarget(2);
335 PSXHW_LOG("T2 target read32: %x\n", hard);
342 PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add);
347 PSXHW_LOG("*Known 32bit read at address %x\n", add);
352 void psxHwWrite8(u32 add, u8 value) {
354 case 0x1f801040: sioWrite8(value); break;
\r
355 #ifdef ENABLE_SIO1API
356 case 0x1f801050: SIO1_writeData8(value); break;
\r
358 case 0x1f801800: cdrWrite0(value); break;
359 case 0x1f801801: cdrWrite1(value); break;
360 case 0x1f801802: cdrWrite2(value); break;
361 case 0x1f801803: cdrWrite3(value); break;
366 PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
372 PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
376 void psxHwWrite16(u32 add, u16 value) {
379 sioWrite8((unsigned char)value);
380 sioWrite8((unsigned char)(value>>8));
382 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
386 sioWriteStat16(value);
388 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
392 sioWriteMode16(value);
394 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
397 case 0x1f80104a: // control register
398 sioWriteCtrl16(value);
400 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
403 case 0x1f80104e: // baudrate register
404 sioWriteBaud16(value);
406 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
409 #ifdef ENABLE_SIO1API
411 SIO1_writeData16(value);
414 SIO1_writeStat16(value);
417 SIO1_writeCtrl16(value);
420 SIO1_writeBaud16(value);
425 PSXHW_LOG("IREG 16bit write %x\n", value);
427 if (Config.Sio) psxHu16ref(0x1070) |= SWAPu16(0x80);
428 if (Config.SpuIrq) psxHu16ref(0x1070) |= SWAPu16(0x200);
429 psxHu16ref(0x1070) &= SWAPu16((psxHu16(0x1074) & value));
434 PSXHW_LOG("IMASK 16bit write %x\n", value);
436 psxHu16ref(0x1074) = SWAPu16(value);
437 if (psxHu16ref(0x1070) & value)
438 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
443 PSXHW_LOG("COUNTER 0 COUNT 16bit write %x\n", value);
445 psxRcntWcount(0, value); return;
448 PSXHW_LOG("COUNTER 0 MODE 16bit write %x\n", value);
450 psxRcntWmode(0, value); return;
453 PSXHW_LOG("COUNTER 0 TARGET 16bit write %x\n", value);
455 psxRcntWtarget(0, value); return;
459 PSXHW_LOG("COUNTER 1 COUNT 16bit write %x\n", value);
461 psxRcntWcount(1, value); return;
464 PSXHW_LOG("COUNTER 1 MODE 16bit write %x\n", value);
466 psxRcntWmode(1, value); return;
469 PSXHW_LOG("COUNTER 1 TARGET 16bit write %x\n", value);
471 psxRcntWtarget(1, value); return;
475 PSXHW_LOG("COUNTER 2 COUNT 16bit write %x\n", value);
477 psxRcntWcount(2, value); return;
480 PSXHW_LOG("COUNTER 2 MODE 16bit write %x\n", value);
482 psxRcntWmode(2, value); return;
485 PSXHW_LOG("COUNTER 2 TARGET 16bit write %x\n", value);
487 psxRcntWtarget(2, value); return;
490 if (add>=0x1f801c00 && add<0x1f801e00) {
491 SPU_writeRegister(add, value);
495 psxHu16ref(add) = SWAPu16(value);
497 PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
501 psxHu16ref(add) = SWAPu16(value);
503 PSXHW_LOG("*Known 16bit write at address %x value %x\n", add, value);
507 #define DmaExec(n) { \
508 HW_DMA##n##_CHCR = SWAPu32(value); \
510 if (SWAPu32(HW_DMA##n##_CHCR) & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8 << (n * 4))) { \
511 psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), SWAPu32(HW_DMA##n##_CHCR)); \
515 void psxHwWrite32(u32 add, u32 value) {
518 sioWrite8((unsigned char)value);
519 sioWrite8((unsigned char)((value&0xff) >> 8));
520 sioWrite8((unsigned char)((value&0xff) >> 16));
521 sioWrite8((unsigned char)((value&0xff) >> 24));
523 PAD_LOG("sio write32 %x\n", value);
526 #ifdef ENABLE_SIO1API
528 SIO1_writeData32(value);
533 PSXHW_LOG("RAM size write %x\n", value);
534 psxHu32ref(add) = SWAPu32(value);
540 PSXHW_LOG("IREG 32bit write %x\n", value);
542 if (Config.Sio) psxHu32ref(0x1070) |= SWAPu32(0x80);
543 if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAPu32(0x200);
544 psxHu32ref(0x1070) &= SWAPu32((psxHu32(0x1074) & value));
548 PSXHW_LOG("IMASK 32bit write %x\n", value);
550 psxHu32ref(0x1074) = SWAPu32(value);
551 if (psxHu32ref(0x1070) & value)
552 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
557 PSXHW_LOG("DMA0 MADR 32bit write %x\n", value);
558 HW_DMA0_MADR = SWAPu32(value); return; // DMA0 madr
560 PSXHW_LOG("DMA0 BCR 32bit write %x\n", value);
561 HW_DMA0_BCR = SWAPu32(value); return; // DMA0 bcr
565 PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value);
567 DmaExec(0); // DMA0 chcr (MDEC in DMA)
572 PSXHW_LOG("DMA1 MADR 32bit write %x\n", value);
573 HW_DMA1_MADR = SWAPu32(value); return; // DMA1 madr
575 PSXHW_LOG("DMA1 BCR 32bit write %x\n", value);
576 HW_DMA1_BCR = SWAPu32(value); return; // DMA1 bcr
580 PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value);
582 DmaExec(1); // DMA1 chcr (MDEC out DMA)
587 PSXHW_LOG("DMA2 MADR 32bit write %x\n", value);
588 HW_DMA2_MADR = SWAPu32(value); return; // DMA2 madr
590 PSXHW_LOG("DMA2 BCR 32bit write %x\n", value);
591 HW_DMA2_BCR = SWAPu32(value); return; // DMA2 bcr
595 PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value);
597 DmaExec(2); // DMA2 chcr (GPU DMA)
602 PSXHW_LOG("DMA3 MADR 32bit write %x\n", value);
603 HW_DMA3_MADR = SWAPu32(value); return; // DMA3 madr
605 PSXHW_LOG("DMA3 BCR 32bit write %x\n", value);
606 HW_DMA3_BCR = SWAPu32(value); return; // DMA3 bcr
610 PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value);
612 DmaExec(3); // DMA3 chcr (CDROM DMA)
618 PSXHW_LOG("DMA4 MADR 32bit write %x\n", value);
619 HW_DMA4_MADR = SWAPu32(value); return; // DMA4 madr
621 PSXHW_LOG("DMA4 BCR 32bit write %x\n", value);
622 HW_DMA4_BCR = SWAPu32(value); return; // DMA4 bcr
626 PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value);
628 DmaExec(4); // DMA4 chcr (SPU DMA)
632 case 0x1f8010d0: break; //DMA5write_madr();
633 case 0x1f8010d4: break; //DMA5write_bcr();
634 case 0x1f8010d8: break; //DMA5write_chcr(); // Not needed
639 PSXHW_LOG("DMA6 MADR 32bit write %x\n", value);
640 HW_DMA6_MADR = SWAPu32(value); return; // DMA6 bcr
642 PSXHW_LOG("DMA6 BCR 32bit write %x\n", value);
643 HW_DMA6_BCR = SWAPu32(value); return; // DMA6 bcr
647 PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value);
649 DmaExec(6); // DMA6 chcr (OT clear)
654 PSXHW_LOG("DMA PCR 32bit write %x\n", value);
655 HW_DMA_PCR = SWAPu32(value);
661 PSXHW_LOG("DMA ICR 32bit write %x\n", value);
664 u32 tmp = value & 0x00ff803f;
665 tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
666 if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
667 || tmp & HW_DMA_ICR_BUS_ERROR) {
668 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
669 psxHu32ref(0x1070) |= SWAP32(8);
670 tmp |= HW_DMA_ICR_IRQ_SENT;
672 HW_DMA_ICR = SWAPu32(tmp);
678 PSXHW_LOG("GPU DATA 32bit write %x\n", value);
680 GPU_writeData(value); return;
683 PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
685 GPU_writeStatus(value); return;
688 mdecWrite0(value); break;
690 mdecWrite1(value); break;
694 PSXHW_LOG("COUNTER 0 COUNT 32bit write %x\n", value);
696 psxRcntWcount(0, value & 0xffff); return;
699 PSXHW_LOG("COUNTER 0 MODE 32bit write %x\n", value);
701 psxRcntWmode(0, value); return;
704 PSXHW_LOG("COUNTER 0 TARGET 32bit write %x\n", value);
706 psxRcntWtarget(0, value & 0xffff); return; // HW_DMA_ICR&= SWAP32((~value)&0xff000000);
710 PSXHW_LOG("COUNTER 1 COUNT 32bit write %x\n", value);
712 psxRcntWcount(1, value & 0xffff); return;
715 PSXHW_LOG("COUNTER 1 MODE 32bit write %x\n", value);
717 psxRcntWmode(1, value); return;
720 PSXHW_LOG("COUNTER 1 TARGET 32bit write %x\n", value);
722 psxRcntWtarget(1, value & 0xffff); return;
726 PSXHW_LOG("COUNTER 2 COUNT 32bit write %x\n", value);
728 psxRcntWcount(2, value & 0xffff); return;
731 PSXHW_LOG("COUNTER 2 MODE 32bit write %x\n", value);
733 psxRcntWmode(2, value); return;
736 PSXHW_LOG("COUNTER 2 TARGET 32bit write %x\n", value);
738 psxRcntWtarget(2, value & 0xffff); return;
741 // Dukes of Hazard 2 - car engine noise
742 if (add>=0x1f801c00 && add<0x1f801e00) {
743 SPU_writeRegister(add, value&0xffff);
744 SPU_writeRegister(add + 2, value>>16);
748 psxHu32ref(add) = SWAPu32(value);
750 PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
754 psxHu32ref(add) = SWAPu32(value);
756 PSXHW_LOG("*Known 32bit write at address %x value %x\n", add, value);
760 int psxHwFreeze(gzFile f, int Mode) {