1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Functions for PSX hardware control.
30 //#define PSXHW_LOG printf
36 memset(psxH, 0, 0x10000);
38 mdecInit(); // initialize mdec decoder
41 HW_GPU_STATUS = SWAP32(0x14802000);
44 void psxHwWriteIstat(u32 value)
46 u32 stat = psxHu16(0x1070) & value;
47 psxHu16ref(0x1070) = SWAPu16(stat);
49 psxRegs.CP0.n.Cause &= ~0x400;
50 if (stat & psxHu16(0x1074))
51 psxRegs.CP0.n.Cause |= 0x400;
54 void psxHwWriteImask(u32 value)
56 u32 stat = psxHu16(0x1070);
57 psxHu16ref(0x1074) = SWAPu16(value);
59 //if ((psxRegs.CP0.n.SR & 0x401) == 0x401)
60 // log_unhandled("irq on unmask @%08x\n", psxRegs.pc);
61 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
63 psxRegs.CP0.n.Cause &= ~0x400;
65 psxRegs.CP0.n.Cause |= 0x400;
68 void psxHwWriteDmaIcr32(u32 value)
70 u32 tmp = value & 0x00ff803f;
71 tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
72 if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
73 || tmp & HW_DMA_ICR_BUS_ERROR) {
74 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
75 psxHu32ref(0x1070) |= SWAP32(8);
76 tmp |= HW_DMA_ICR_IRQ_SENT;
78 HW_DMA_ICR = SWAPu32(tmp);
81 u8 psxHwRead8(u32 add) {
84 switch (add & 0x1fffffff) {
85 case 0x1f801040: hard = sioRead8(); break;
86 case 0x1f801800: hard = cdrRead0(); break;
87 case 0x1f801801: hard = cdrRead1(); break;
88 case 0x1f801802: hard = cdrRead2(); break;
89 case 0x1f801803: hard = cdrRead3(); break;
91 case 0x1f801041: case 0x1f801042: case 0x1f801043:
92 case 0x1f801044: case 0x1f801045:
93 case 0x1f801046: case 0x1f801047:
94 case 0x1f801048: case 0x1f801049:
95 case 0x1f80104a: case 0x1f80104b:
96 case 0x1f80104c: case 0x1f80104d:
97 case 0x1f80104e: case 0x1f80104f:
98 case 0x1f801050: case 0x1f801051:
99 case 0x1f801054: case 0x1f801055:
100 case 0x1f801058: case 0x1f801059:
101 case 0x1f80105a: case 0x1f80105b:
102 case 0x1f80105c: case 0x1f80105d:
103 case 0x1f801100: case 0x1f801101:
104 case 0x1f801104: case 0x1f801105:
105 case 0x1f801108: case 0x1f801109:
106 case 0x1f801110: case 0x1f801111:
107 case 0x1f801114: case 0x1f801115:
108 case 0x1f801118: case 0x1f801119:
109 case 0x1f801120: case 0x1f801121:
110 case 0x1f801124: case 0x1f801125:
111 case 0x1f801128: case 0x1f801129:
112 case 0x1f801810: case 0x1f801811:
113 case 0x1f801812: case 0x1f801813:
114 case 0x1f801814: case 0x1f801815:
115 case 0x1f801816: case 0x1f801817:
116 case 0x1f801820: case 0x1f801821:
117 case 0x1f801822: case 0x1f801823:
118 case 0x1f801824: case 0x1f801825:
119 case 0x1f801826: case 0x1f801827:
120 log_unhandled("unhandled r8 %08x @%08x\n", add, psxRegs.pc);
123 if (0x1f801c00 <= add && add < 0x1f802000) {
124 u16 val = SPU_readRegister(add & ~1, psxRegs.cycle);
125 hard = (add & 1) ? val >> 8 : val;
130 PSXHW_LOG("*Unkwnown 8bit read at address %x\n", add);
136 PSXHW_LOG("*Known 8bit read at address %x value %x\n", add, hard);
141 u16 psxHwRead16(u32 add) {
144 switch (add & 0x1fffffff) {
146 case 0x1f801070: PSXHW_LOG("IREG 16bit read %x\n", psxHu16(0x1070));
147 return psxHu16(0x1070);
148 case 0x1f801074: PSXHW_LOG("IMASK 16bit read %x\n", psxHu16(0x1074));
149 return psxHu16(0x1074);
153 hard|= sioRead8() << 8;
154 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
157 hard = sioReadStat16();
158 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
161 hard = sioReadMode16();
162 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
165 hard = sioReadCtrl16();
166 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
169 hard = sioReadBaud16();
170 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
173 /* Fixes Armored Core misdetecting the Link cable being detected.
174 * We want to turn that thing off and force it to do local multiplayer instead.
175 * Thanks Sony for the fix, they fixed it in their PS Classic fork.
181 hard = psxRcntRcount0();
183 PSXHW_LOG("T0 count read16: %x\n", hard);
187 hard = psxRcntRmode(0);
189 PSXHW_LOG("T0 mode read16: %x\n", hard);
193 hard = psxRcntRtarget(0);
195 PSXHW_LOG("T0 target read16: %x\n", hard);
199 hard = psxRcntRcount1();
201 PSXHW_LOG("T1 count read16: %x\n", hard);
205 hard = psxRcntRmode(1);
207 PSXHW_LOG("T1 mode read16: %x\n", hard);
211 hard = psxRcntRtarget(1);
213 PSXHW_LOG("T1 target read16: %x\n", hard);
217 hard = psxRcntRcount2();
219 PSXHW_LOG("T2 count read16: %x\n", hard);
223 hard = psxRcntRmode(2);
225 PSXHW_LOG("T2 mode read16: %x\n", hard);
229 hard = psxRcntRtarget(2);
231 PSXHW_LOG("T2 target read16: %x\n", hard);
235 //case 0x1f802030: hard = //int_2000????
236 //case 0x1f802040: hard =//dip switches...??
255 log_unhandled("unhandled r16 %08x @%08x\n", add, psxRegs.pc);
258 if (0x1f801c00 <= add && add < 0x1f802000)
259 return SPU_readRegister(add, psxRegs.cycle);
262 PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add);
268 PSXHW_LOG("*Known 16bit read at address %x value %x\n", add, hard);
273 u32 psxHwRead32(u32 add) {
276 switch (add & 0x1fffffff) {
279 hard |= sioRead8() << 8;
280 hard |= sioRead8() << 16;
281 hard |= sioRead8() << 24;
282 PAD_LOG("sio read32 ;ret = %x\n", hard);
285 hard = sioReadStat16();
286 PAD_LOG("sio read32 %x; ret = %x\n", add&0xf, hard);
290 PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060));
291 return psxHu32(0x1060);
292 case 0x1f801070: PSXHW_LOG("IREG 32bit read %x\n", psxHu32(0x1070));
293 return psxHu32(0x1070);
294 case 0x1f801074: PSXHW_LOG("IMASK 32bit read %x\n", psxHu32(0x1074));
295 return psxHu32(0x1074);
299 hard = GPU_readData();
301 PSXHW_LOG("GPU DATA 32bit read %x\n", hard);
306 hard = SWAP32(HW_GPU_STATUS);
307 if (hSyncCount < 240 && (hard & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
308 hard |= PSXGPU_LCF & (psxRegs.cycle << 20);
310 PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
314 case 0x1f801820: hard = mdecRead0(); break;
315 case 0x1f801824: hard = mdecRead1(); break;
319 PSXHW_LOG("DMA2 MADR 32bit read %x\n", psxHu32(0x10a0));
320 return SWAPu32(HW_DMA2_MADR);
322 PSXHW_LOG("DMA2 BCR 32bit read %x\n", psxHu32(0x10a4));
323 return SWAPu32(HW_DMA2_BCR);
325 PSXHW_LOG("DMA2 CHCR 32bit read %x\n", psxHu32(0x10a8));
326 return SWAPu32(HW_DMA2_CHCR);
331 PSXHW_LOG("DMA3 MADR 32bit read %x\n", psxHu32(0x10b0));
332 return SWAPu32(HW_DMA3_MADR);
334 PSXHW_LOG("DMA3 BCR 32bit read %x\n", psxHu32(0x10b4));
335 return SWAPu32(HW_DMA3_BCR);
337 PSXHW_LOG("DMA3 CHCR 32bit read %x\n", psxHu32(0x10b8));
338 return SWAPu32(HW_DMA3_CHCR);
343 PSXHW_LOG("DMA PCR 32bit read %x\n", psxHu32(0x10f0));
344 return SWAPu32(HW_DMA_PCR); // dma rest channel
346 PSXHW_LOG("DMA ICR 32bit read %x\n", psxHu32(0x10f4));
347 return SWAPu32(HW_DMA_ICR); // interrupt enabler?*/
350 // time for rootcounters :)
352 hard = psxRcntRcount0();
354 PSXHW_LOG("T0 count read32: %x\n", hard);
358 hard = psxRcntRmode(0);
360 PSXHW_LOG("T0 mode read32: %x\n", hard);
364 hard = psxRcntRtarget(0);
366 PSXHW_LOG("T0 target read32: %x\n", hard);
370 hard = psxRcntRcount1();
372 PSXHW_LOG("T1 count read32: %x\n", hard);
376 hard = psxRcntRmode(1);
378 PSXHW_LOG("T1 mode read32: %x\n", hard);
382 hard = psxRcntRtarget(1);
384 PSXHW_LOG("T1 target read32: %x\n", hard);
388 hard = psxRcntRcount2();
390 PSXHW_LOG("T2 count read32: %x\n", hard);
394 hard = psxRcntRmode(2);
396 PSXHW_LOG("T2 mode read32: %x\n", hard);
400 hard = psxRcntRtarget(2);
402 PSXHW_LOG("T2 target read32: %x\n", hard);
413 log_unhandled("unhandled r32 %08x @%08x\n", add, psxRegs.pc);
416 if (0x1f801c00 <= add && add < 0x1f802000) {
417 hard = SPU_readRegister(add, psxRegs.cycle);
418 hard |= SPU_readRegister(add + 2, psxRegs.cycle) << 16;
423 PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add);
428 PSXHW_LOG("*Known 32bit read at address %x\n", add);
433 void psxHwWrite8(u32 add, u8 value) {
434 switch (add & 0x1fffffff) {
435 case 0x1f801040: sioWrite8(value); break;
\r
436 case 0x1f801800: cdrWrite0(value); break;
437 case 0x1f801801: cdrWrite1(value); break;
438 case 0x1f801802: cdrWrite2(value); break;
439 case 0x1f801803: cdrWrite3(value); break;
441 case 0x1f801041: case 0x1f801042: case 0x1f801043:
442 case 0x1f801044: case 0x1f801045:
443 case 0x1f801046: case 0x1f801047:
444 case 0x1f801048: case 0x1f801049:
445 case 0x1f80104a: case 0x1f80104b:
446 case 0x1f80104c: case 0x1f80104d:
447 case 0x1f80104e: case 0x1f80104f:
448 case 0x1f801050: case 0x1f801051:
449 case 0x1f801054: case 0x1f801055:
450 case 0x1f801058: case 0x1f801059:
451 case 0x1f80105a: case 0x1f80105b:
452 case 0x1f80105c: case 0x1f80105d:
453 case 0x1f801100: case 0x1f801101:
454 case 0x1f801104: case 0x1f801105:
455 case 0x1f801108: case 0x1f801109:
456 case 0x1f801110: case 0x1f801111:
457 case 0x1f801114: case 0x1f801115:
458 case 0x1f801118: case 0x1f801119:
459 case 0x1f801120: case 0x1f801121:
460 case 0x1f801124: case 0x1f801125:
461 case 0x1f801128: case 0x1f801129:
462 case 0x1f801810: case 0x1f801811:
463 case 0x1f801812: case 0x1f801813:
464 case 0x1f801814: case 0x1f801815:
465 case 0x1f801816: case 0x1f801817:
466 case 0x1f801820: case 0x1f801821:
467 case 0x1f801822: case 0x1f801823:
468 case 0x1f801824: case 0x1f801825:
469 case 0x1f801826: case 0x1f801827:
470 log_unhandled("unhandled w8 %08x @%08x\n", add, psxRegs.pc);
473 if (0x1f801c00 <= add && add < 0x1f802000) {
474 log_unhandled("spu w8 %02x @%08x\n", value, psxRegs.pc);
476 SPU_writeRegister(add, value, psxRegs.cycle);
482 PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
488 PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
492 void psxHwWrite16(u32 add, u16 value) {
493 switch (add & 0x1fffffff) {
495 sioWrite8((unsigned char)value);
496 sioWrite8((unsigned char)(value>>8));
497 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
500 sioWriteStat16(value);
501 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
504 sioWriteMode16(value);
505 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
507 case 0x1f80104a: // control register
508 sioWriteCtrl16(value);
509 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
511 case 0x1f80104e: // baudrate register
512 sioWriteBaud16(value);
513 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
517 PSXHW_LOG("IREG 16bit write %x\n", value);
519 psxHwWriteIstat(value);
524 PSXHW_LOG("IMASK 16bit write %x\n", value);
526 psxHwWriteImask(value);
531 PSXHW_LOG("COUNTER 0 COUNT 16bit write %x\n", value);
533 psxRcntWcount(0, value); return;
536 PSXHW_LOG("COUNTER 0 MODE 16bit write %x\n", value);
538 psxRcntWmode(0, value); return;
541 PSXHW_LOG("COUNTER 0 TARGET 16bit write %x\n", value);
543 psxRcntWtarget(0, value); return;
547 PSXHW_LOG("COUNTER 1 COUNT 16bit write %x\n", value);
549 psxRcntWcount(1, value); return;
552 PSXHW_LOG("COUNTER 1 MODE 16bit write %x\n", value);
554 psxRcntWmode(1, value); return;
557 PSXHW_LOG("COUNTER 1 TARGET 16bit write %x\n", value);
559 psxRcntWtarget(1, value); return;
563 PSXHW_LOG("COUNTER 2 COUNT 16bit write %x\n", value);
565 psxRcntWcount(2, value); return;
568 PSXHW_LOG("COUNTER 2 MODE 16bit write %x\n", value);
570 psxRcntWmode(2, value); return;
573 PSXHW_LOG("COUNTER 2 TARGET 16bit write %x\n", value);
575 psxRcntWtarget(2, value); return;
595 log_unhandled("unhandled w16 %08x @%08x\n", add, psxRegs.pc);
598 if (0x1f801c00 <= add && add < 0x1f802000) {
599 SPU_writeRegister(add, value, psxRegs.cycle);
603 psxHu16ref(add) = SWAPu16(value);
605 PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
609 psxHu16ref(add) = SWAPu16(value);
611 PSXHW_LOG("*Known 16bit write at address %x value %x\n", add, value);
615 #define DmaExec(n) { \
616 if (value & SWAPu32(HW_DMA##n##_CHCR) & 0x01000000) \
617 log_unhandled("dma" #n " %08x -> %08x\n", HW_DMA##n##_CHCR, value); \
618 HW_DMA##n##_CHCR = SWAPu32(value); \
620 if (SWAPu32(HW_DMA##n##_CHCR) & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8 << (n * 4))) { \
621 psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), SWAPu32(HW_DMA##n##_CHCR)); \
625 void psxHwWrite32(u32 add, u32 value) {
626 switch (add & 0x1fffffff) {
628 sioWrite8((unsigned char)value);
629 sioWrite8((unsigned char)((value&0xff) >> 8));
630 sioWrite8((unsigned char)((value&0xff) >> 16));
631 sioWrite8((unsigned char)((value&0xff) >> 24));
632 PAD_LOG("sio write32 %x\n", value);
636 PSXHW_LOG("RAM size write %x\n", value);
637 psxHu32ref(add) = SWAPu32(value);
643 PSXHW_LOG("IREG 32bit write %x\n", value);
645 psxHwWriteIstat(value);
649 PSXHW_LOG("IMASK 32bit write %x\n", value);
651 psxHwWriteImask(value);
656 PSXHW_LOG("DMA0 MADR 32bit write %x\n", value);
657 HW_DMA0_MADR = SWAPu32(value); return; // DMA0 madr
659 PSXHW_LOG("DMA0 BCR 32bit write %x\n", value);
660 HW_DMA0_BCR = SWAPu32(value); return; // DMA0 bcr
664 PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value);
666 DmaExec(0); // DMA0 chcr (MDEC in DMA)
671 PSXHW_LOG("DMA1 MADR 32bit write %x\n", value);
672 HW_DMA1_MADR = SWAPu32(value); return; // DMA1 madr
674 PSXHW_LOG("DMA1 BCR 32bit write %x\n", value);
675 HW_DMA1_BCR = SWAPu32(value); return; // DMA1 bcr
679 PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value);
681 DmaExec(1); // DMA1 chcr (MDEC out DMA)
686 PSXHW_LOG("DMA2 MADR 32bit write %x\n", value);
687 HW_DMA2_MADR = SWAPu32(value); return; // DMA2 madr
689 PSXHW_LOG("DMA2 BCR 32bit write %x\n", value);
690 HW_DMA2_BCR = SWAPu32(value); return; // DMA2 bcr
694 PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value);
696 DmaExec(2); // DMA2 chcr (GPU DMA)
701 PSXHW_LOG("DMA3 MADR 32bit write %x\n", value);
702 HW_DMA3_MADR = SWAPu32(value); return; // DMA3 madr
704 PSXHW_LOG("DMA3 BCR 32bit write %x\n", value);
705 HW_DMA3_BCR = SWAPu32(value); return; // DMA3 bcr
709 PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value);
711 DmaExec(3); // DMA3 chcr (CDROM DMA)
717 PSXHW_LOG("DMA4 MADR 32bit write %x\n", value);
718 HW_DMA4_MADR = SWAPu32(value); return; // DMA4 madr
720 PSXHW_LOG("DMA4 BCR 32bit write %x\n", value);
721 HW_DMA4_BCR = SWAPu32(value); return; // DMA4 bcr
725 PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value);
727 DmaExec(4); // DMA4 chcr (SPU DMA)
731 case 0x1f8010d0: break; //DMA5write_madr();
732 case 0x1f8010d4: break; //DMA5write_bcr();
733 case 0x1f8010d8: break; //DMA5write_chcr(); // Not needed
738 PSXHW_LOG("DMA6 MADR 32bit write %x\n", value);
739 HW_DMA6_MADR = SWAPu32(value); return; // DMA6 bcr
741 PSXHW_LOG("DMA6 BCR 32bit write %x\n", value);
742 HW_DMA6_BCR = SWAPu32(value); return; // DMA6 bcr
746 PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value);
748 DmaExec(6); // DMA6 chcr (OT clear)
753 PSXHW_LOG("DMA PCR 32bit write %x\n", value);
754 HW_DMA_PCR = SWAPu32(value);
760 PSXHW_LOG("DMA ICR 32bit write %x\n", value);
762 psxHwWriteDmaIcr32(value);
767 PSXHW_LOG("GPU DATA 32bit write %x\n", value);
769 GPU_writeData(value); return;
772 PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
774 GPU_writeStatus(value);
779 mdecWrite0(value); break;
781 mdecWrite1(value); break;
785 PSXHW_LOG("COUNTER 0 COUNT 32bit write %x\n", value);
787 psxRcntWcount(0, value & 0xffff); return;
790 PSXHW_LOG("COUNTER 0 MODE 32bit write %x\n", value);
792 psxRcntWmode(0, value); return;
795 PSXHW_LOG("COUNTER 0 TARGET 32bit write %x\n", value);
797 psxRcntWtarget(0, value & 0xffff); return; // HW_DMA_ICR&= SWAP32((~value)&0xff000000);
801 PSXHW_LOG("COUNTER 1 COUNT 32bit write %x\n", value);
803 psxRcntWcount(1, value & 0xffff); return;
806 PSXHW_LOG("COUNTER 1 MODE 32bit write %x\n", value);
808 psxRcntWmode(1, value); return;
811 PSXHW_LOG("COUNTER 1 TARGET 32bit write %x\n", value);
813 psxRcntWtarget(1, value & 0xffff); return;
817 PSXHW_LOG("COUNTER 2 COUNT 32bit write %x\n", value);
819 psxRcntWcount(2, value & 0xffff); return;
822 PSXHW_LOG("COUNTER 2 MODE 32bit write %x\n", value);
824 psxRcntWmode(2, value); return;
827 PSXHW_LOG("COUNTER 2 TARGET 32bit write %x\n", value);
829 psxRcntWtarget(2, value & 0xffff); return;
839 log_unhandled("unhandled w32 %08x @%08x\n", add, psxRegs.pc);
842 // Dukes of Hazard 2 - car engine noise
843 if (0x1f801c00 <= add && add < 0x1f802000) {
844 SPU_writeRegister(add, value&0xffff, psxRegs.cycle);
845 SPU_writeRegister(add + 2, value>>16, psxRegs.cycle);
849 psxHu32ref(add) = SWAPu32(value);
851 PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
855 psxHu32ref(add) = SWAPu32(value);
857 PSXHW_LOG("*Known 32bit write at address %x value %x\n", add, value);
861 int psxHwFreeze(void *f, int Mode) {