1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Functions for PSX hardware control.
30 //#define PSXHW_LOG printf
33 if (Config.Sio) psxHu32ref(0x1070) |= SWAP32(0x80);
34 if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAP32(0x200);
36 memset(psxH, 0, 0x10000);
38 mdecInit(); // initialize mdec decoder
41 HW_GPU_STATUS = 0x14802000;
44 u8 psxHwRead8(u32 add) {
48 case 0x1f801040: hard = sioRead8();break;
\r
50 case 0x1f801050: hard = SIO1_readData8(); break;
\r
52 case 0x1f801800: hard = cdrRead0(); break;
53 case 0x1f801801: hard = cdrRead1(); break;
54 case 0x1f801802: hard = cdrRead2(); break;
55 case 0x1f801803: hard = cdrRead3(); break;
59 PSXHW_LOG("*Unkwnown 8bit read at address %x\n", add);
65 PSXHW_LOG("*Known 8bit read at address %x value %x\n", add, hard);
70 u16 psxHwRead16(u32 add) {
75 case 0x1f801070: PSXHW_LOG("IREG 16bit read %x\n", psxHu16(0x1070));
76 return psxHu16(0x1070);
79 case 0x1f801074: PSXHW_LOG("IMASK 16bit read %x\n", psxHu16(0x1074));
80 return psxHu16(0x1074);
85 hard|= sioRead8() << 8;
87 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
91 hard = sioReadStat16();
93 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
97 hard = sioReadMode16();
99 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
103 hard = sioReadCtrl16();
105 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
109 hard = sioReadBaud16();
111 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
114 #ifdef ENABLE_SIO1API
116 hard = SIO1_readData16();
119 hard = SIO1_readStat16();
122 hard = SIO1_readCtrl16();
125 hard = SIO1_readBaud16();
129 hard = psxRcntRcount(0);
131 PSXHW_LOG("T0 count read16: %x\n", hard);
135 hard = psxRcntRmode(0);
137 PSXHW_LOG("T0 mode read16: %x\n", hard);
141 hard = psxRcntRtarget(0);
143 PSXHW_LOG("T0 target read16: %x\n", hard);
147 hard = psxRcntRcount(1);
149 PSXHW_LOG("T1 count read16: %x\n", hard);
153 hard = psxRcntRmode(1);
155 PSXHW_LOG("T1 mode read16: %x\n", hard);
159 hard = psxRcntRtarget(1);
161 PSXHW_LOG("T1 target read16: %x\n", hard);
165 hard = psxRcntRcount(2);
167 PSXHW_LOG("T2 count read16: %x\n", hard);
171 hard = psxRcntRmode(2);
173 PSXHW_LOG("T2 mode read16: %x\n", hard);
177 hard = psxRcntRtarget(2);
179 PSXHW_LOG("T2 target read16: %x\n", hard);
183 //case 0x1f802030: hard = //int_2000????
184 //case 0x1f802040: hard =//dip switches...??
187 if (add >= 0x1f801c00 && add < 0x1f801e00) {
188 hard = SPU_readRegister(add);
192 PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add);
199 PSXHW_LOG("*Known 16bit read at address %x value %x\n", add, hard);
204 u32 psxHwRead32(u32 add) {
210 hard |= sioRead8() << 8;
211 hard |= sioRead8() << 16;
212 hard |= sioRead8() << 24;
214 PAD_LOG("sio read32 ;ret = %x\n", hard);
217 #ifdef ENABLE_SIO1API
219 hard = SIO1_readData32();
224 PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060));
225 return psxHu32(0x1060);
228 case 0x1f801070: PSXHW_LOG("IREG 32bit read %x\n", psxHu32(0x1070));
229 return psxHu32(0x1070);
232 case 0x1f801074: PSXHW_LOG("IMASK 32bit read %x\n", psxHu32(0x1074));
233 return psxHu32(0x1074);
237 hard = GPU_readData();
239 PSXHW_LOG("GPU DATA 32bit read %x\n", hard);
244 hard = HW_GPU_STATUS;
246 PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
250 case 0x1f801820: hard = mdecRead0(); break;
251 case 0x1f801824: hard = mdecRead1(); break;
255 PSXHW_LOG("DMA2 MADR 32bit read %x\n", psxHu32(0x10a0));
256 return SWAPu32(HW_DMA2_MADR);
258 PSXHW_LOG("DMA2 BCR 32bit read %x\n", psxHu32(0x10a4));
259 return SWAPu32(HW_DMA2_BCR);
261 PSXHW_LOG("DMA2 CHCR 32bit read %x\n", psxHu32(0x10a8));
262 return SWAPu32(HW_DMA2_CHCR);
267 PSXHW_LOG("DMA3 MADR 32bit read %x\n", psxHu32(0x10b0));
268 return SWAPu32(HW_DMA3_MADR);
270 PSXHW_LOG("DMA3 BCR 32bit read %x\n", psxHu32(0x10b4));
271 return SWAPu32(HW_DMA3_BCR);
273 PSXHW_LOG("DMA3 CHCR 32bit read %x\n", psxHu32(0x10b8));
274 return SWAPu32(HW_DMA3_CHCR);
279 PSXHW_LOG("DMA PCR 32bit read %x\n", psxHu32(0x10f0));
280 return SWAPu32(HW_DMA_PCR); // dma rest channel
282 PSXHW_LOG("DMA ICR 32bit read %x\n", psxHu32(0x10f4));
283 return SWAPu32(HW_DMA_ICR); // interrupt enabler?*/
286 // time for rootcounters :)
288 hard = psxRcntRcount(0);
290 PSXHW_LOG("T0 count read32: %x\n", hard);
294 hard = psxRcntRmode(0);
296 PSXHW_LOG("T0 mode read32: %x\n", hard);
300 hard = psxRcntRtarget(0);
302 PSXHW_LOG("T0 target read32: %x\n", hard);
306 hard = psxRcntRcount(1);
308 PSXHW_LOG("T1 count read32: %x\n", hard);
312 hard = psxRcntRmode(1);
314 PSXHW_LOG("T1 mode read32: %x\n", hard);
318 hard = psxRcntRtarget(1);
320 PSXHW_LOG("T1 target read32: %x\n", hard);
324 hard = psxRcntRcount(2);
326 PSXHW_LOG("T2 count read32: %x\n", hard);
330 hard = psxRcntRmode(2);
332 PSXHW_LOG("T2 mode read32: %x\n", hard);
336 hard = psxRcntRtarget(2);
338 PSXHW_LOG("T2 target read32: %x\n", hard);
345 PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add);
350 PSXHW_LOG("*Known 32bit read at address %x\n", add);
355 void psxHwWrite8(u32 add, u8 value) {
357 case 0x1f801040: sioWrite8(value); break;
\r
358 #ifdef ENABLE_SIO1API
359 case 0x1f801050: SIO1_writeData8(value); break;
\r
361 case 0x1f801800: cdrWrite0(value); break;
362 case 0x1f801801: cdrWrite1(value); break;
363 case 0x1f801802: cdrWrite2(value); break;
364 case 0x1f801803: cdrWrite3(value); break;
369 PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
375 PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
379 void psxHwWrite16(u32 add, u16 value) {
382 sioWrite8((unsigned char)value);
383 sioWrite8((unsigned char)(value>>8));
385 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
389 sioWriteStat16(value);
391 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
395 sioWriteMode16(value);
397 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
400 case 0x1f80104a: // control register
401 sioWriteCtrl16(value);
403 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
406 case 0x1f80104e: // baudrate register
407 sioWriteBaud16(value);
409 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
412 #ifdef ENABLE_SIO1API
414 SIO1_writeData16(value);
417 SIO1_writeStat16(value);
420 SIO1_writeCtrl16(value);
423 SIO1_writeBaud16(value);
428 PSXHW_LOG("IREG 16bit write %x\n", value);
430 if (Config.Sio) psxHu16ref(0x1070) |= SWAPu16(0x80);
431 if (Config.SpuIrq) psxHu16ref(0x1070) |= SWAPu16(0x200);
432 psxHu16ref(0x1070) &= SWAPu16((psxHu16(0x1074) & value));
437 PSXHW_LOG("IMASK 16bit write %x\n", value);
439 psxHu16ref(0x1074) = SWAPu16(value);
440 if (psxHu16ref(0x1070) & value)
441 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
446 PSXHW_LOG("COUNTER 0 COUNT 16bit write %x\n", value);
448 psxRcntWcount(0, value); return;
451 PSXHW_LOG("COUNTER 0 MODE 16bit write %x\n", value);
453 psxRcntWmode(0, value); return;
456 PSXHW_LOG("COUNTER 0 TARGET 16bit write %x\n", value);
458 psxRcntWtarget(0, value); return;
462 PSXHW_LOG("COUNTER 1 COUNT 16bit write %x\n", value);
464 psxRcntWcount(1, value); return;
467 PSXHW_LOG("COUNTER 1 MODE 16bit write %x\n", value);
469 psxRcntWmode(1, value); return;
472 PSXHW_LOG("COUNTER 1 TARGET 16bit write %x\n", value);
474 psxRcntWtarget(1, value); return;
478 PSXHW_LOG("COUNTER 2 COUNT 16bit write %x\n", value);
480 psxRcntWcount(2, value); return;
483 PSXHW_LOG("COUNTER 2 MODE 16bit write %x\n", value);
485 psxRcntWmode(2, value); return;
488 PSXHW_LOG("COUNTER 2 TARGET 16bit write %x\n", value);
490 psxRcntWtarget(2, value); return;
493 if (add>=0x1f801c00 && add<0x1f801e00) {
494 SPU_writeRegister(add, value);
498 psxHu16ref(add) = SWAPu16(value);
500 PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
504 psxHu16ref(add) = SWAPu16(value);
506 PSXHW_LOG("*Known 16bit write at address %x value %x\n", add, value);
510 #define DmaExec(n) { \
511 HW_DMA##n##_CHCR = SWAPu32(value); \
513 if (SWAPu32(HW_DMA##n##_CHCR) & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8 << (n * 4))) { \
514 psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), SWAPu32(HW_DMA##n##_CHCR)); \
518 void psxHwWrite32(u32 add, u32 value) {
521 sioWrite8((unsigned char)value);
522 sioWrite8((unsigned char)((value&0xff) >> 8));
523 sioWrite8((unsigned char)((value&0xff) >> 16));
524 sioWrite8((unsigned char)((value&0xff) >> 24));
526 PAD_LOG("sio write32 %x\n", value);
529 #ifdef ENABLE_SIO1API
531 SIO1_writeData32(value);
536 PSXHW_LOG("RAM size write %x\n", value);
537 psxHu32ref(add) = SWAPu32(value);
543 PSXHW_LOG("IREG 32bit write %x\n", value);
545 if (Config.Sio) psxHu32ref(0x1070) |= SWAPu32(0x80);
546 if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAPu32(0x200);
547 psxHu32ref(0x1070) &= SWAPu32((psxHu32(0x1074) & value));
551 PSXHW_LOG("IMASK 32bit write %x\n", value);
553 psxHu32ref(0x1074) = SWAPu32(value);
554 if (psxHu32ref(0x1070) & value)
555 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
560 PSXHW_LOG("DMA0 MADR 32bit write %x\n", value);
561 HW_DMA0_MADR = SWAPu32(value); return; // DMA0 madr
563 PSXHW_LOG("DMA0 BCR 32bit write %x\n", value);
564 HW_DMA0_BCR = SWAPu32(value); return; // DMA0 bcr
568 PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value);
570 DmaExec(0); // DMA0 chcr (MDEC in DMA)
575 PSXHW_LOG("DMA1 MADR 32bit write %x\n", value);
576 HW_DMA1_MADR = SWAPu32(value); return; // DMA1 madr
578 PSXHW_LOG("DMA1 BCR 32bit write %x\n", value);
579 HW_DMA1_BCR = SWAPu32(value); return; // DMA1 bcr
583 PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value);
585 DmaExec(1); // DMA1 chcr (MDEC out DMA)
590 PSXHW_LOG("DMA2 MADR 32bit write %x\n", value);
591 HW_DMA2_MADR = SWAPu32(value); return; // DMA2 madr
593 PSXHW_LOG("DMA2 BCR 32bit write %x\n", value);
594 HW_DMA2_BCR = SWAPu32(value); return; // DMA2 bcr
598 PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value);
600 DmaExec(2); // DMA2 chcr (GPU DMA)
605 PSXHW_LOG("DMA3 MADR 32bit write %x\n", value);
606 HW_DMA3_MADR = SWAPu32(value); return; // DMA3 madr
608 PSXHW_LOG("DMA3 BCR 32bit write %x\n", value);
609 HW_DMA3_BCR = SWAPu32(value); return; // DMA3 bcr
613 PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value);
615 DmaExec(3); // DMA3 chcr (CDROM DMA)
621 PSXHW_LOG("DMA4 MADR 32bit write %x\n", value);
622 HW_DMA4_MADR = SWAPu32(value); return; // DMA4 madr
624 PSXHW_LOG("DMA4 BCR 32bit write %x\n", value);
625 HW_DMA4_BCR = SWAPu32(value); return; // DMA4 bcr
629 PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value);
631 DmaExec(4); // DMA4 chcr (SPU DMA)
635 case 0x1f8010d0: break; //DMA5write_madr();
636 case 0x1f8010d4: break; //DMA5write_bcr();
637 case 0x1f8010d8: break; //DMA5write_chcr(); // Not needed
642 PSXHW_LOG("DMA6 MADR 32bit write %x\n", value);
643 HW_DMA6_MADR = SWAPu32(value); return; // DMA6 bcr
645 PSXHW_LOG("DMA6 BCR 32bit write %x\n", value);
646 HW_DMA6_BCR = SWAPu32(value); return; // DMA6 bcr
650 PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value);
652 DmaExec(6); // DMA6 chcr (OT clear)
657 PSXHW_LOG("DMA PCR 32bit write %x\n", value);
658 HW_DMA_PCR = SWAPu32(value);
664 PSXHW_LOG("DMA ICR 32bit write %x\n", value);
667 u32 tmp = value & 0x00ff803f;
668 tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
669 if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
670 || tmp & HW_DMA_ICR_BUS_ERROR) {
671 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
672 psxHu32ref(0x1070) |= SWAP32(8);
673 tmp |= HW_DMA_ICR_IRQ_SENT;
675 HW_DMA_ICR = SWAPu32(tmp);
681 PSXHW_LOG("GPU DATA 32bit write %x\n", value);
683 GPU_writeData(value); return;
686 PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
688 GPU_writeStatus(value);
693 mdecWrite0(value); break;
695 mdecWrite1(value); break;
699 PSXHW_LOG("COUNTER 0 COUNT 32bit write %x\n", value);
701 psxRcntWcount(0, value & 0xffff); return;
704 PSXHW_LOG("COUNTER 0 MODE 32bit write %x\n", value);
706 psxRcntWmode(0, value); return;
709 PSXHW_LOG("COUNTER 0 TARGET 32bit write %x\n", value);
711 psxRcntWtarget(0, value & 0xffff); return; // HW_DMA_ICR&= SWAP32((~value)&0xff000000);
715 PSXHW_LOG("COUNTER 1 COUNT 32bit write %x\n", value);
717 psxRcntWcount(1, value & 0xffff); return;
720 PSXHW_LOG("COUNTER 1 MODE 32bit write %x\n", value);
722 psxRcntWmode(1, value); return;
725 PSXHW_LOG("COUNTER 1 TARGET 32bit write %x\n", value);
727 psxRcntWtarget(1, value & 0xffff); return;
731 PSXHW_LOG("COUNTER 2 COUNT 32bit write %x\n", value);
733 psxRcntWcount(2, value & 0xffff); return;
736 PSXHW_LOG("COUNTER 2 MODE 32bit write %x\n", value);
738 psxRcntWmode(2, value); return;
741 PSXHW_LOG("COUNTER 2 TARGET 32bit write %x\n", value);
743 psxRcntWtarget(2, value & 0xffff); return;
746 // Dukes of Hazard 2 - car engine noise
747 if (add>=0x1f801c00 && add<0x1f801e00) {
748 SPU_writeRegister(add, value&0xffff);
749 SPU_writeRegister(add + 2, value>>16);
753 psxHu32ref(add) = SWAPu32(value);
755 PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
759 psxHu32ref(add) = SWAPu32(value);
761 PSXHW_LOG("*Known 32bit write at address %x value %x\n", add, value);
765 int psxHwFreeze(gzFile f, int Mode) {