1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Functions for PSX hardware control.
30 //#define PSXHW_LOG printf
33 if (Config.Sio) psxHu32ref(0x1070) |= SWAP32(0x80);
34 if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAP32(0x200);
36 memset(psxH, 0, 0x10000);
38 mdecInit(); // initialize mdec decoder
41 HW_GPU_STATUS = 0x14802000;
44 u8 psxHwRead8(u32 add) {
48 case 0x1f801040: hard = sioRead8();break;
\r
50 case 0x1f801050: hard = SIO1_readData8(); break;
\r
52 case 0x1f801800: hard = cdrRead0(); break;
53 case 0x1f801801: hard = cdrRead1(); break;
54 case 0x1f801802: hard = cdrRead2(); break;
55 case 0x1f801803: hard = cdrRead3(); break;
59 PSXHW_LOG("*Unkwnown 8bit read at address %x\n", add);
65 PSXHW_LOG("*Known 8bit read at address %x value %x\n", add, hard);
70 u16 psxHwRead16(u32 add) {
75 case 0x1f801070: PSXHW_LOG("IREG 16bit read %x\n", psxHu16(0x1070));
76 return psxHu16(0x1070);
79 case 0x1f801074: PSXHW_LOG("IMASK 16bit read %x\n", psxHu16(0x1074));
80 return psxHu16(0x1074);
85 hard|= sioRead8() << 8;
87 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
91 hard = sioReadStat16();
93 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
97 hard = sioReadMode16();
99 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
103 hard = sioReadCtrl16();
105 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
109 hard = sioReadBaud16();
111 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
114 #ifdef ENABLE_SIO1API
116 hard = SIO1_readData16();
119 hard = SIO1_readStat16();
122 hard = SIO1_readCtrl16();
125 hard = SIO1_readBaud16();
129 hard = psxRcntRcount(0);
131 PSXHW_LOG("T0 count read16: %x\n", hard);
135 hard = psxRcntRmode(0);
137 PSXHW_LOG("T0 mode read16: %x\n", hard);
141 hard = psxRcntRtarget(0);
143 PSXHW_LOG("T0 target read16: %x\n", hard);
147 hard = psxRcntRcount(1);
149 PSXHW_LOG("T1 count read16: %x\n", hard);
153 hard = psxRcntRmode(1);
155 PSXHW_LOG("T1 mode read16: %x\n", hard);
159 hard = psxRcntRtarget(1);
161 PSXHW_LOG("T1 target read16: %x\n", hard);
165 hard = psxRcntRcount(2);
167 PSXHW_LOG("T2 count read16: %x\n", hard);
171 hard = psxRcntRmode(2);
173 PSXHW_LOG("T2 mode read16: %x\n", hard);
177 hard = psxRcntRtarget(2);
179 PSXHW_LOG("T2 target read16: %x\n", hard);
183 //case 0x1f802030: hard = //int_2000????
184 //case 0x1f802040: hard =//dip switches...??
187 if (add >= 0x1f801c00 && add < 0x1f801e00) {
188 hard = SPU_readRegister(add);
192 PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add);
199 PSXHW_LOG("*Known 16bit read at address %x value %x\n", add, hard);
204 u32 psxHwRead32(u32 add) {
210 hard |= sioRead8() << 8;
211 hard |= sioRead8() << 16;
212 hard |= sioRead8() << 24;
214 PAD_LOG("sio read32 ;ret = %x\n", hard);
217 #ifdef ENABLE_SIO1API
219 hard = SIO1_readData32();
224 PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060));
225 return psxHu32(0x1060);
228 case 0x1f801070: PSXHW_LOG("IREG 32bit read %x\n", psxHu32(0x1070));
229 return psxHu32(0x1070);
232 case 0x1f801074: PSXHW_LOG("IMASK 32bit read %x\n", psxHu32(0x1074));
233 return psxHu32(0x1074);
237 hard = GPU_readData();
239 PSXHW_LOG("GPU DATA 32bit read %x\n", hard);
244 hard = HW_GPU_STATUS;
245 if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
246 hard |= PSXGPU_LCF & (psxRegs.cycle << 20);
248 PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
252 case 0x1f801820: hard = mdecRead0(); break;
253 case 0x1f801824: hard = mdecRead1(); break;
257 PSXHW_LOG("DMA2 MADR 32bit read %x\n", psxHu32(0x10a0));
258 return SWAPu32(HW_DMA2_MADR);
260 PSXHW_LOG("DMA2 BCR 32bit read %x\n", psxHu32(0x10a4));
261 return SWAPu32(HW_DMA2_BCR);
263 PSXHW_LOG("DMA2 CHCR 32bit read %x\n", psxHu32(0x10a8));
264 return SWAPu32(HW_DMA2_CHCR);
269 PSXHW_LOG("DMA3 MADR 32bit read %x\n", psxHu32(0x10b0));
270 return SWAPu32(HW_DMA3_MADR);
272 PSXHW_LOG("DMA3 BCR 32bit read %x\n", psxHu32(0x10b4));
273 return SWAPu32(HW_DMA3_BCR);
275 PSXHW_LOG("DMA3 CHCR 32bit read %x\n", psxHu32(0x10b8));
276 return SWAPu32(HW_DMA3_CHCR);
281 PSXHW_LOG("DMA PCR 32bit read %x\n", psxHu32(0x10f0));
282 return SWAPu32(HW_DMA_PCR); // dma rest channel
284 PSXHW_LOG("DMA ICR 32bit read %x\n", psxHu32(0x10f4));
285 return SWAPu32(HW_DMA_ICR); // interrupt enabler?*/
288 // time for rootcounters :)
290 hard = psxRcntRcount(0);
292 PSXHW_LOG("T0 count read32: %x\n", hard);
296 hard = psxRcntRmode(0);
298 PSXHW_LOG("T0 mode read32: %x\n", hard);
302 hard = psxRcntRtarget(0);
304 PSXHW_LOG("T0 target read32: %x\n", hard);
308 hard = psxRcntRcount(1);
310 PSXHW_LOG("T1 count read32: %x\n", hard);
314 hard = psxRcntRmode(1);
316 PSXHW_LOG("T1 mode read32: %x\n", hard);
320 hard = psxRcntRtarget(1);
322 PSXHW_LOG("T1 target read32: %x\n", hard);
326 hard = psxRcntRcount(2);
328 PSXHW_LOG("T2 count read32: %x\n", hard);
332 hard = psxRcntRmode(2);
334 PSXHW_LOG("T2 mode read32: %x\n", hard);
338 hard = psxRcntRtarget(2);
340 PSXHW_LOG("T2 target read32: %x\n", hard);
347 PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add);
352 PSXHW_LOG("*Known 32bit read at address %x\n", add);
357 void psxHwWrite8(u32 add, u8 value) {
359 case 0x1f801040: sioWrite8(value); break;
\r
360 #ifdef ENABLE_SIO1API
361 case 0x1f801050: SIO1_writeData8(value); break;
\r
363 case 0x1f801800: cdrWrite0(value); break;
364 case 0x1f801801: cdrWrite1(value); break;
365 case 0x1f801802: cdrWrite2(value); break;
366 case 0x1f801803: cdrWrite3(value); break;
371 PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
377 PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
381 void psxHwWrite16(u32 add, u16 value) {
384 sioWrite8((unsigned char)value);
385 sioWrite8((unsigned char)(value>>8));
387 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
391 sioWriteStat16(value);
393 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
397 sioWriteMode16(value);
399 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
402 case 0x1f80104a: // control register
403 sioWriteCtrl16(value);
405 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
408 case 0x1f80104e: // baudrate register
409 sioWriteBaud16(value);
411 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
414 #ifdef ENABLE_SIO1API
416 SIO1_writeData16(value);
419 SIO1_writeStat16(value);
422 SIO1_writeCtrl16(value);
425 SIO1_writeBaud16(value);
430 PSXHW_LOG("IREG 16bit write %x\n", value);
432 if (Config.Sio) psxHu16ref(0x1070) |= SWAPu16(0x80);
433 if (Config.SpuIrq) psxHu16ref(0x1070) |= SWAPu16(0x200);
434 psxHu16ref(0x1070) &= SWAPu16(value);
439 PSXHW_LOG("IMASK 16bit write %x\n", value);
441 psxHu16ref(0x1074) = SWAPu16(value);
442 if (psxHu16ref(0x1070) & value)
443 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
448 PSXHW_LOG("COUNTER 0 COUNT 16bit write %x\n", value);
450 psxRcntWcount(0, value); return;
453 PSXHW_LOG("COUNTER 0 MODE 16bit write %x\n", value);
455 psxRcntWmode(0, value); return;
458 PSXHW_LOG("COUNTER 0 TARGET 16bit write %x\n", value);
460 psxRcntWtarget(0, value); return;
464 PSXHW_LOG("COUNTER 1 COUNT 16bit write %x\n", value);
466 psxRcntWcount(1, value); return;
469 PSXHW_LOG("COUNTER 1 MODE 16bit write %x\n", value);
471 psxRcntWmode(1, value); return;
474 PSXHW_LOG("COUNTER 1 TARGET 16bit write %x\n", value);
476 psxRcntWtarget(1, value); return;
480 PSXHW_LOG("COUNTER 2 COUNT 16bit write %x\n", value);
482 psxRcntWcount(2, value); return;
485 PSXHW_LOG("COUNTER 2 MODE 16bit write %x\n", value);
487 psxRcntWmode(2, value); return;
490 PSXHW_LOG("COUNTER 2 TARGET 16bit write %x\n", value);
492 psxRcntWtarget(2, value); return;
495 if (add>=0x1f801c00 && add<0x1f801e00) {
496 SPU_writeRegister(add, value, psxRegs.cycle);
500 psxHu16ref(add) = SWAPu16(value);
502 PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
506 psxHu16ref(add) = SWAPu16(value);
508 PSXHW_LOG("*Known 16bit write at address %x value %x\n", add, value);
512 #define DmaExec(n) { \
513 HW_DMA##n##_CHCR = SWAPu32(value); \
515 if (SWAPu32(HW_DMA##n##_CHCR) & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8 << (n * 4))) { \
516 psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), SWAPu32(HW_DMA##n##_CHCR)); \
520 void psxHwWrite32(u32 add, u32 value) {
523 sioWrite8((unsigned char)value);
524 sioWrite8((unsigned char)((value&0xff) >> 8));
525 sioWrite8((unsigned char)((value&0xff) >> 16));
526 sioWrite8((unsigned char)((value&0xff) >> 24));
528 PAD_LOG("sio write32 %x\n", value);
531 #ifdef ENABLE_SIO1API
533 SIO1_writeData32(value);
538 PSXHW_LOG("RAM size write %x\n", value);
539 psxHu32ref(add) = SWAPu32(value);
545 PSXHW_LOG("IREG 32bit write %x\n", value);
547 if (Config.Sio) psxHu32ref(0x1070) |= SWAPu32(0x80);
548 if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAPu32(0x200);
549 psxHu32ref(0x1070) &= SWAPu32(value);
553 PSXHW_LOG("IMASK 32bit write %x\n", value);
555 psxHu32ref(0x1074) = SWAPu32(value);
556 if (psxHu32ref(0x1070) & value)
557 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
562 PSXHW_LOG("DMA0 MADR 32bit write %x\n", value);
563 HW_DMA0_MADR = SWAPu32(value); return; // DMA0 madr
565 PSXHW_LOG("DMA0 BCR 32bit write %x\n", value);
566 HW_DMA0_BCR = SWAPu32(value); return; // DMA0 bcr
570 PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value);
572 DmaExec(0); // DMA0 chcr (MDEC in DMA)
577 PSXHW_LOG("DMA1 MADR 32bit write %x\n", value);
578 HW_DMA1_MADR = SWAPu32(value); return; // DMA1 madr
580 PSXHW_LOG("DMA1 BCR 32bit write %x\n", value);
581 HW_DMA1_BCR = SWAPu32(value); return; // DMA1 bcr
585 PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value);
587 DmaExec(1); // DMA1 chcr (MDEC out DMA)
592 PSXHW_LOG("DMA2 MADR 32bit write %x\n", value);
593 HW_DMA2_MADR = SWAPu32(value); return; // DMA2 madr
595 PSXHW_LOG("DMA2 BCR 32bit write %x\n", value);
596 HW_DMA2_BCR = SWAPu32(value); return; // DMA2 bcr
600 PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value);
602 DmaExec(2); // DMA2 chcr (GPU DMA)
607 PSXHW_LOG("DMA3 MADR 32bit write %x\n", value);
608 HW_DMA3_MADR = SWAPu32(value); return; // DMA3 madr
610 PSXHW_LOG("DMA3 BCR 32bit write %x\n", value);
611 HW_DMA3_BCR = SWAPu32(value); return; // DMA3 bcr
615 PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value);
617 DmaExec(3); // DMA3 chcr (CDROM DMA)
623 PSXHW_LOG("DMA4 MADR 32bit write %x\n", value);
624 HW_DMA4_MADR = SWAPu32(value); return; // DMA4 madr
626 PSXHW_LOG("DMA4 BCR 32bit write %x\n", value);
627 HW_DMA4_BCR = SWAPu32(value); return; // DMA4 bcr
631 PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value);
633 DmaExec(4); // DMA4 chcr (SPU DMA)
637 case 0x1f8010d0: break; //DMA5write_madr();
638 case 0x1f8010d4: break; //DMA5write_bcr();
639 case 0x1f8010d8: break; //DMA5write_chcr(); // Not needed
644 PSXHW_LOG("DMA6 MADR 32bit write %x\n", value);
645 HW_DMA6_MADR = SWAPu32(value); return; // DMA6 bcr
647 PSXHW_LOG("DMA6 BCR 32bit write %x\n", value);
648 HW_DMA6_BCR = SWAPu32(value); return; // DMA6 bcr
652 PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value);
654 DmaExec(6); // DMA6 chcr (OT clear)
659 PSXHW_LOG("DMA PCR 32bit write %x\n", value);
660 HW_DMA_PCR = SWAPu32(value);
666 PSXHW_LOG("DMA ICR 32bit write %x\n", value);
669 u32 tmp = value & 0x00ff803f;
670 tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
671 if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
672 || tmp & HW_DMA_ICR_BUS_ERROR) {
673 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
674 psxHu32ref(0x1070) |= SWAP32(8);
675 tmp |= HW_DMA_ICR_IRQ_SENT;
677 HW_DMA_ICR = SWAPu32(tmp);
683 PSXHW_LOG("GPU DATA 32bit write %x\n", value);
685 GPU_writeData(value); return;
688 PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
690 GPU_writeStatus(value);
695 mdecWrite0(value); break;
697 mdecWrite1(value); break;
701 PSXHW_LOG("COUNTER 0 COUNT 32bit write %x\n", value);
703 psxRcntWcount(0, value & 0xffff); return;
706 PSXHW_LOG("COUNTER 0 MODE 32bit write %x\n", value);
708 psxRcntWmode(0, value); return;
711 PSXHW_LOG("COUNTER 0 TARGET 32bit write %x\n", value);
713 psxRcntWtarget(0, value & 0xffff); return; // HW_DMA_ICR&= SWAP32((~value)&0xff000000);
717 PSXHW_LOG("COUNTER 1 COUNT 32bit write %x\n", value);
719 psxRcntWcount(1, value & 0xffff); return;
722 PSXHW_LOG("COUNTER 1 MODE 32bit write %x\n", value);
724 psxRcntWmode(1, value); return;
727 PSXHW_LOG("COUNTER 1 TARGET 32bit write %x\n", value);
729 psxRcntWtarget(1, value & 0xffff); return;
733 PSXHW_LOG("COUNTER 2 COUNT 32bit write %x\n", value);
735 psxRcntWcount(2, value & 0xffff); return;
738 PSXHW_LOG("COUNTER 2 MODE 32bit write %x\n", value);
740 psxRcntWmode(2, value); return;
743 PSXHW_LOG("COUNTER 2 TARGET 32bit write %x\n", value);
745 psxRcntWtarget(2, value & 0xffff); return;
748 // Dukes of Hazard 2 - car engine noise
749 if (add>=0x1f801c00 && add<0x1f801e00) {
750 SPU_writeRegister(add, value&0xffff, psxRegs.cycle);
751 SPU_writeRegister(add + 2, value>>16, psxRegs.cycle);
755 psxHu32ref(add) = SWAPu32(value);
757 PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
761 psxHu32ref(add) = SWAPu32(value);
763 PSXHW_LOG("*Known 32bit write at address %x value %x\n", add, value);
767 int psxHwFreeze(void *f, int Mode) {