2 * basic, incomplete SSP160x (SSP1601?) interpreter
3 * with SVP memory controller emu
5 * Copyright (c) GraÅžvydas "notaz" Ignotas, 2008
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
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18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 //#define USE_DEBUGGER
31 /* detect ops with unimplemented/invalid fields.
32 * Useful for homebrew or if a new VR revision pops up. */
40 * desc: Constant register with all bits set (0xffff).
44 * desc: Generic register. When set, updates P (P = X * Y * 2)
48 * desc: Generic register. When set, updates P (P = X * Y * 2)
56 * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
58 * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively
59 * modulo-increment and modulo-decrement. The value shows which
60 * power of 2 to use, i.e. 4 means modulo by 16.
61 * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC)
63 * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?).
64 * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after.
65 * datasheet says these (5,6) bits correspond to hardware pins.
66 * 7 - IE (?) Not directly used by SVP code (never set, but preserved)?
67 * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value
68 * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff))
69 * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
70 * a - GPI_0 Interrupt 0 enable/status?
71 * b - GPI_1 Interrupt 1 enable/status?
72 * c - L L flag. Carry?
74 * e - OV Overflow flag.
75 * f - N Negative flag.
76 * seen directly changing code sequences:
77 * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
78 * ldi ST, 60h ori A, 60h and A, E8h and A, E8h
79 * ld ST, A ld ST, A ori 3
84 * desc: hw stack of 6 levels (according to datasheet)
88 * desc: Program counter.
92 * desc: multiply result register. P = X * Y * 2
93 * probably affected by MACS bit in ST.
95 * 8. "PM0" (PM from PMAR name from Tasco's docs)
97 * desc: Programmable Memory access register.
98 * On reset, or when one (both?) GP0 bits are clear,
99 * acts as status for XST, mapped at 015004 at 68k side:
100 * bit0: ssp has written something to XST (cleared when 015004 is read)
101 * bit1: 68k has written something through a1500{0|2} (cleared on PM0 read)
105 * desc: Programmable Memory access register.
106 * This reg. is only used as PMAR.
110 * desc: Programmable Memory access register.
111 * This reg. is only used as PMAR.
115 * desc: eXternal STate. Mapped to a15000 and a15002 at 68k side.
116 * Can be programmed as PMAR? (only seen in test mode code)
117 * Affects PM0 when written to?
121 * desc: Programmable Memory access register.
122 * This reg. is only used as PMAR. The most used PMAR by VR.
126 * 14. "PMC" (PMC from PMAC name from Tasco's docs)
128 * desc: Programmable Memory access Control. Set using 2 16bit writes,
129 * first address, then mode word. After setting PMAC, PMAR sould
130 * be blind accessed (ld -, PMx or ld PMx, -) to program it for
131 * reading and writing respectively.
132 * Reading the register also shifts it's state (from "waiting for
133 * address" to "waiting for mode" and back). Reads always return
134 * address related to last PMx register accressed.
135 * (note: addresses do not wrap).
139 * desc: Accumulator Low. 16 least significant bits of accumulator.
140 * (normally reading acc (ld X, A) you get 16 most significant bits).
143 * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
144 * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ],
145 * which work similar to * and ** operators in C, only they use different memory banks and
146 * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses
147 * program memory at address read from (rX), and increments value in (rX).
149 * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
150 * 3 modifiers can be applied (optional):
151 * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST.
152 * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure).
153 * +!: post-increment, unaffected by RPL (probably).
154 * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
155 * ar probably invalid.
157 * r3 and r7 are special and can not be changed (at least Samsung samples and VR code never do).
158 * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
159 * Samsung's old DSP page claims that).
160 * 1 of these 4 modifiers must be used (short form direct addressing?):
161 * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
163 * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
169 * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc)
171 * mld (rj), (ri) [, b]
172 * operation: A = 0; P = (rj) * (ri)
173 * notes: based on IIR_4B.SC sample. flags? what is b???
175 * mpya (rj), (ri) [, b]
176 * name: multiply and add?
177 * operation: A += P; P = (rj) * (ri)
180 * name: multiply and subtract?
181 * notes: not used by VR code.
184 * mod cond, shr does arithmetic shift
186 * 'ld -, AL' and probably 'ld AL, -' are for dummy assigns
189 * 000000 - 1fffff ROM, accessable by both
190 * 200000 - 2fffff unused?
191 * 300000 - 31ffff DRAM, both
192 * 320000 - 38ffff unused?
193 * 390000 - 3907ff IRAM. can only be accessed by ssp?
194 * 390000 - 39ffff similar mapping to "cell arrange" in Sega CD, 68k only?
195 * 3a0000 - 3affff similar mapping to "cell arrange" in Sega CD, a bit different
197 * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
198 * 30fe06 - also sync related.
199 * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by VR.
201 * Assumptions and limitations in this code
202 * only Z and N status flags are emulated (others unused by VR)
203 * so all condition checks except N and Z are ignored (not used by VR)
204 * modifiers for 'OP a, ri' and ((ri)) are ignored (not used by VR)
205 * loop repeat mode when (ri) is destination is ignored
206 * ops not used by VR are not implemented
209 #include "../../pico_int.h"
211 #define u32 unsigned int
214 #define rX ssp->gr[SSP_X].h
215 #define rY ssp->gr[SSP_Y].h
216 #define rA ssp->gr[SSP_A].h
217 #define rST ssp->gr[SSP_ST].h // 4
218 #define rSTACK ssp->gr[SSP_STACK].h
219 #define rPC ssp->gr[SSP_PC].h
220 #define rP ssp->gr[SSP_P]
221 #define rPM0 ssp->gr[SSP_PM0].h // 8
222 #define rPM1 ssp->gr[SSP_PM1].h
223 #define rPM2 ssp->gr[SSP_PM2].h
224 #define rXST ssp->gr[SSP_XST].h
225 #define rPM4 ssp->gr[SSP_PM4].h // 12
227 #define rPMC ssp->gr[SSP_PMC] // will keep addr in .l, mode in .h
228 #define rAL ssp->gr[SSP_A].l
230 #define rA32 ssp->gr[SSP_A].v
233 #define IJind (((op>>6)&4)|(op&3))
235 #define GET_PC() (PC - (unsigned short *)svp->iram_rom)
236 #define GET_PPC_OFFS() ((unsigned char *)PC - svp->iram_rom - 2)
237 #define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
239 #define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
240 #define REG_WRITE(r,d) { \
242 if (r1 >= 4) write_handlers[r1](d); \
243 else if (r1 > 0) ssp->gr[r1].h = d; \
247 #define SSP_FLAG_L (1<<0xc)
248 #define SSP_FLAG_Z (1<<0xd)
249 #define SSP_FLAG_V (1<<0xe)
250 #define SSP_FLAG_N (1<<0xf)
252 // update ZN according to 32bit ACC.
254 rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \
255 if (!rA32) rST |= SSP_FLAG_Z; \
256 else rST |= (rA32>>16)&SSP_FLAG_N;
258 // it seems SVP code never checks for L and OV, so we leave them out.
259 // rST |= (t>>4)&SSP_FLAG_L;
261 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
262 if (!rA32) rST |= SSP_FLAG_Z; \
263 else rST |= (rA32>>16)&SSP_FLAG_N;
265 // standard cond processing.
266 // again, only Z and N is checked, as VR doesn't seem to use any other conds.
269 case 0x00: cond = 1; break; /* always true */ \
270 case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
271 case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
272 default:elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
275 // ops with accumulator.
276 // how is low word really affected by these?
277 // nearly sure 'ld A' doesn't affect flags
281 #define OP_LDA32(x) \
284 #define OP_SUBA(x) { \
289 #define OP_SUBA32(x) { \
294 #define OP_CMPA(x) { \
295 u32 t = rA32 - ((x) << 16); \
296 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
297 if (!t) rST |= SSP_FLAG_Z; \
298 else rST |= (t>>16)&SSP_FLAG_N; \
301 #define OP_CMPA32(x) { \
302 u32 t = rA32 - (x); \
303 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
304 if (!t) rST |= SSP_FLAG_Z; \
305 else rST |= (t>>16)&SSP_FLAG_N; \
308 #define OP_ADDA(x) { \
313 #define OP_ADDA32(x) { \
322 #define OP_ANDA32(x) \
330 #define OP_ORA32(x) \
338 #define OP_EORA32(x) \
343 #define OP_CHECK32(OP) { \
344 if ((op & 0x0f) == SSP_P) { /* A <- P */ \
345 read_P(); /* update P */ \
349 if ((op & 0x0f) == SSP_A) { /* A <- A */ \
357 #define CHECK_IMM16() if (op&0x1ff) elprintf(EL_ANOMALY, "imm bits! %04x @ %04x", op, GET_PPC_OFFS())
358 #define CHECK_B_SET() if (op&0x100) elprintf(EL_ANOMALY, "b set! %04x @ %04x", op, GET_PPC_OFFS())
359 #define CHECK_B_CLEAR() if (!(op&0x100)) elprintf(EL_ANOMALY, "b clear! %04x @ %04x", op, GET_PPC_OFFS())
360 #define CHECK_MOD() if (op&0x00c) elprintf(EL_ANOMALY, "mod bits! %04x @ %04x", op, GET_PPC_OFFS())
361 #define CHECK_10f() if (op&0x10f) elprintf(EL_ANOMALY, "bits 10f! %04x @ %04x", op, GET_PPC_OFFS())
362 #define CHECK_008() if (op&0x008) elprintf(EL_ANOMALY, "bits 008! %04x @ %04x", op, GET_PPC_OFFS())
363 #define CHECK_00f() if (op&0x00f) elprintf(EL_ANOMALY, "bits 00f! %04x @ %04x", op, GET_PPC_OFFS())
364 #define CHECK_0f0() if (op&0x0f0) elprintf(EL_ANOMALY, "bits 0f0! %04x @ %04x", op, GET_PPC_OFFS())
365 #define CHECK_1f0() if (op&0x1f0) elprintf(EL_ANOMALY, "bits 1f0! %04x @ %04x", op, GET_PPC_OFFS())
366 #define CHECK_RPL() if (rST&7) elprintf(EL_ANOMALY, "unhandled RPL! %04x @ %04x", op, GET_PPC_OFFS())
367 #define CHECK_ST(d) if((rST^d)&0xf98)elprintf(EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS())
369 #define CHECK_IMM16()
370 #define CHECK_B_SET()
371 #define CHECK_B_CLEAR()
382 ssp1601_t *ssp = NULL;
383 static unsigned short *PC;
387 static int running = 0;
388 static int last_iram = 0;
391 // -----------------------------------------------------
392 // register i/o handlers
395 static u32 read_unknown(void)
397 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown read @ %04x", GET_PPC_OFFS());
401 static void write_unknown(u32 d)
403 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown write @ %04x", GET_PPC_OFFS());
407 static void write_ST(u32 d)
414 static u32 read_STACK(void)
417 if ((short)rSTACK < 0) {
419 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
421 return ssp->stack[rSTACK];
424 static void write_STACK(u32 d)
427 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
430 ssp->stack[rSTACK++] = d;
434 static u32 read_PC(void)
439 static void write_PC(u32 d)
446 static u32 read_P(void)
448 int m1 = (signed short)rX;
449 int m2 = (signed short)rY;
450 rP.v = (m1 * m2 * 2);
454 // -----------------------------------------------------
456 static int get_inc(int mode)
458 int inc = (mode >> 11) & 7;
461 inc = 1 << inc; // 0 1 2 4 8 16 32 128
462 if (mode & 0x8000) inc = -inc; // decrement mode
467 #define overwrite_write(dst, d) \
469 if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
470 if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
471 if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
472 if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
475 static u32 pm_io(int reg, int write, u32 d)
477 if (ssp->emu_status & SSP_PMC_SET)
479 // this MUST be blind r or w
480 if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
481 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
482 reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
483 ssp->emu_status &= ~SSP_PMC_SET;
486 elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
487 ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
488 ssp->emu_status &= ~SSP_PMC_SET;
489 if ((rPMC.v & 0x7fffff) == 0x1c8000 || (rPMC.v & 0x7fffff) == 0x1c8240) {
490 elprintf(EL_SVP, "ssp IRAM copy from %06x to %04x", (ssp->RAM1[0]-1)<<1, (rPMC.v&0x7fff)<<1);
492 last_iram = (ssp->RAM1[0]-1)<<1;
499 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
500 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i (%c) with only addr set @ %04x",
501 reg, write ? 'w' : 'r', GET_PPC_OFFS());
502 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
505 if (reg == 4 || (rST & 0x60))
507 #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
508 unsigned short *dram = (unsigned short *)svp->dram;
511 int mode = ssp->pmac_write[reg]>>16;
512 int addr = ssp->pmac_write[reg]&0xffff;
513 if ((mode & 0xb800) == 0xb800)
514 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: mode %04x", mode);
515 if ((mode & 0x43ff) == 0x0018) // DRAM
517 int inc = get_inc(mode);
518 elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
519 reg, CADDR, d, inc, (mode>>10)&1);
521 overwrite_write(dram[addr], d);
522 } else dram[addr] = d;
523 ssp->pmac_write[reg] += inc;
525 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
527 elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x",
528 reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS());
530 overwrite_write(dram[addr], d);
531 } else dram[addr] = d;
532 ssp->pmac_write[reg] += (addr&1) ? 31 : 1;
534 else if ((mode & 0x47ff) == 0x001c) // IRAM
536 int inc = get_inc(mode);
537 if ((addr&0xfc00) != 0x8000)
538 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
539 elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
540 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
541 ssp->pmac_write[reg] += inc;
545 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
546 reg, mode, CADDR, d, GET_PPC_OFFS());
551 int mode = ssp->pmac_read[reg]>>16;
552 int addr = ssp->pmac_read[reg]&0xffff;
553 if ((mode & 0xfff0) == 0x0800) // ROM, inc 1, verified to be correct
555 elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
556 ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
557 ssp->pmac_read[reg] += 1;
558 d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
560 else if ((mode & 0x47ff) == 0x0018) // DRAM
562 int inc = get_inc(mode);
563 elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr]);
565 ssp->pmac_read[reg] += inc;
569 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled read mode %04x, [%06x] @ %04x",
570 reg, mode, CADDR, GET_PPC_OFFS());
575 // PMC value corresponds to last PMR accessed (not sure).
576 rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
585 static u32 read_PM0(void)
587 u32 d = pm_io(0, 0, 0);
588 if (d != (u32)-1) return d;
589 elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
591 if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
592 ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
598 static void write_PM0(u32 d)
600 u32 r = pm_io(0, 1, d);
601 if (r != (u32)-1) return;
602 elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
607 static u32 read_PM1(void)
609 u32 d = pm_io(1, 0, 0);
610 if (d != (u32)-1) return d;
612 elprintf(EL_SVP|EL_ANOMALY, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
616 static void write_PM1(u32 d)
618 u32 r = pm_io(1, 1, d);
619 if (r != (u32)-1) return;
621 elprintf(EL_SVP|EL_ANOMALY, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
626 static u32 read_PM2(void)
628 u32 d = pm_io(2, 0, 0);
629 if (d != (u32)-1) return d;
631 elprintf(EL_SVP|EL_ANOMALY, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
635 static void write_PM2(u32 d)
637 u32 r = pm_io(2, 1, d);
638 if (r != (u32)-1) return;
640 elprintf(EL_SVP|EL_ANOMALY, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
645 static u32 read_XST(void)
648 u32 d = pm_io(3, 0, 0);
649 if (d != (u32)-1) return d;
651 elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
655 static void write_XST(u32 d)
658 u32 r = pm_io(3, 1, d);
659 if (r != (u32)-1) return;
661 elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
667 static u32 read_PM4(void)
669 u32 d = pm_io(4, 0, 0);
672 switch (GET_PPC_OFFS()) {
673 case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
674 case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
678 if (d != (u32)-1) return d;
680 elprintf(EL_SVP|EL_ANOMALY, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
684 static void write_PM4(u32 d)
686 u32 r = pm_io(4, 1, d);
687 if (r != (u32)-1) return;
689 elprintf(EL_SVP|EL_ANOMALY, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
694 static u32 read_PMC(void)
696 elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.l,
697 (ssp->emu_status & SSP_PMC_HAVE_ADDR) ? 'm' : 'a', GET_PPC_OFFS());
698 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
699 //if (ssp->emu_status & SSP_PMC_SET)
700 // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
701 ssp->emu_status |= SSP_PMC_SET;
702 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
703 return ((rPMC.l << 4) & 0xfff0) | ((rPMC.l >> 4) & 0xf);
705 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
710 static void write_PMC(u32 d)
712 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
713 //if (ssp->emu_status & SSP_PMC_SET)
714 // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
715 ssp->emu_status |= SSP_PMC_SET;
716 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
718 elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.h, GET_PPC_OFFS());
720 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
722 elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.l, GET_PPC_OFFS());
727 static u32 read_AL(void)
729 if (*(PC-1) == 0x000f)
730 elprintf(EL_SVP, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
731 ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
735 static void write_AL(u32 d)
741 typedef u32 (*read_func_t)(void);
742 typedef void (*write_func_t)(u32 d);
744 static read_func_t read_handlers[16] =
746 read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
747 read_unknown, // 4 ST
756 read_unknown, // 13 gr13
761 static write_func_t write_handlers[16] =
763 write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
764 // write_unknown, // 4 ST
765 write_ST, // 4 ST (debug hook)
768 write_unknown, // 7 P
774 write_unknown, // 13 gr13
779 // -----------------------------------------------------
780 // pointer register handlers
783 #define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
785 static u32 ptr1_read_(int ri, int isj2, int modi3)
787 //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
788 u32 mask, add = 0, t = ri | isj2 | modi3;
789 unsigned char *rp = NULL;
795 case 0x02: return ssp->RAM0[ssp->r0[t&3]];
796 case 0x03: return ssp->RAM0[0];
799 case 0x06: return ssp->RAM1[ssp->r1[t&3]];
800 case 0x07: return ssp->RAM1[0];
804 case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
805 case 0x0b: return ssp->RAM0[1];
808 case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
809 case 0x0f: return ssp->RAM1[1];
813 case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
814 if (!(rST&7)) { (*rp)--; return t; }
815 add = -1; goto modulo;
816 case 0x13: return ssp->RAM0[2];
819 case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
820 if (!(rST&7)) { (*rp)--; return t; }
821 add = -1; goto modulo;
822 case 0x17: return ssp->RAM1[2];
826 case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
827 if (!(rST&7)) { (*rp)++; return t; }
828 add = 1; goto modulo;
829 case 0x1b: return ssp->RAM0[3];
832 case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
833 if (!(rST&7)) { (*rp)++; return t; }
834 add = 1; goto modulo;
835 case 0x1f: return ssp->RAM1[3];
841 mask = (1 << (rST&7)) - 1;
842 *rp = (*rp & ~mask) | ((*rp + add) & mask);
846 static void ptr1_write(int op, u32 d)
848 int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
854 case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
855 case 0x03: ssp->RAM0[0] = d; return;
858 case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
859 case 0x07: ssp->RAM1[0] = d; return;
864 case 0x0a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
865 case 0x0b: ssp->RAM0[1] = d; return;
868 case 0x0e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
869 case 0x0f: ssp->RAM1[1] = d; return;
873 case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; CHECK_RPL(); return;
874 case 0x13: ssp->RAM0[2] = d; return;
877 case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; CHECK_RPL(); return;
878 case 0x17: ssp->RAM1[2] = d; return;
882 case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; CHECK_RPL(); return;
883 case 0x1b: ssp->RAM0[3] = d; return;
886 case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; CHECK_RPL(); return;
887 case 0x1f: ssp->RAM1[3] = d; return;
891 static u32 ptr2_read(int op)
893 int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
899 case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
900 case 0x03: mv = ssp->RAM0[0]++; break;
903 case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
904 case 0x07: mv = ssp->RAM1[0]++; break;
906 case 0x0b: mv = ssp->RAM0[1]++; break;
907 case 0x0f: mv = ssp->RAM1[1]++; break;
909 case 0x13: mv = ssp->RAM0[2]++; break;
910 case 0x17: mv = ssp->RAM1[2]++; break;
912 case 0x1b: mv = ssp->RAM0[3]++; break;
913 case 0x1f: mv = ssp->RAM1[3]++; break;
914 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
918 return ((unsigned short *)svp->iram_rom)[mv];
922 // -----------------------------------------------------
924 #if defined(USE_DEBUGGER)
925 static void debug_dump2file(const char *fname, void *mem, int len)
927 FILE *f = fopen(fname, "wb");
928 unsigned short *p = mem;
931 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
932 fwrite(mem, 1, len, f);
934 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
935 printf("dumped to %s\n", fname);
938 printf("dump failed\n");
943 static void debug_dump(void)
945 printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
946 printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, rP.v);
947 printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
948 printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, rPMC.v);
949 printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v',
950 rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
951 printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
952 ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
953 printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
954 elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status);
957 static void debug_dump_mem(void)
961 for (h = 0; h < 32; h++)
963 if (h == 16) printf("RAM1\n");
964 printf("%03x:", h*16);
965 for (i = 0; i < 16; i++)
966 printf(" %04x", ssp->RAM[h*16+i]);
971 static int bpts[10] = { 0, };
973 static void debug(unsigned int pc, unsigned int op)
975 static char buffo[64] = {0,};
976 char buff[64] = {0,};
980 for (i = 0; i < 10; i++)
981 if (pc != 0 && bpts[i] == pc) {
982 printf("breakpoint %i\n", i);
989 printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1);
995 fgets(buff, sizeof(buff), stdin);
996 if (buff[0] == '\n') strcpy(buff, buffo);
997 else strcpy(buffo, buff);
1002 case 'r': running = 1; return;
1005 case 'x': debug_dump(); break;
1006 case 'm': debug_dump_mem(); break;
1008 char *baddr = buff + 2;
1010 if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; }
1011 bpts[i] = strtol(baddr, NULL, 16) >> 1;
1012 printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
1016 sprintf(buff, "iramrom_%04x.bin", last_iram);
1017 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
1018 debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram));
1020 default: printf("unknown command\n"); break;
1024 #endif // USE_DEBUGGER
1027 void ssp1601_reset(ssp1601_t *l_ssp)
1030 ssp->emu_status = 0;
1031 ssp->gr[SSP_GR0].v = 0xffff0000;
1033 rSTACK = 0; // ? using ascending stack
1038 void ssp1601_run(int cycles)
1044 while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
1051 debug(GET_PC()-1, op);
1058 if (op == 0) break; // nop
1059 if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
1060 read_P(); // update P
1065 tmpv = REG_READ(op & 0x0f);
1066 REG_WRITE((op & 0xf0) >> 4, tmpv);
1071 case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1074 case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
1077 case 0x04: CHECK_10f(); tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); g_cycles--; break;
1080 case 0x05: CHECK_MOD(); tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); g_cycles -= 2; break;
1083 case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); g_cycles--; break;
1086 case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
1089 case 0x09: CHECK_MOD(); tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1092 case 0x0a: CHECK_MOD(); rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
1098 case 0x0f: rIJ[(op>>8)&7] = op; break;
1105 if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); SET_PC(new_PC); }
1107 g_cycles--; // always 2 cycles
1114 tmpv = ((unsigned short *)svp->iram_rom)[rA];
1115 REG_WRITE((op & 0xf0) >> 4, tmpv);
1116 g_cycles -= 2; // 3 cycles total
1124 if (cond) { int new_PC = *PC++; SET_PC(new_PC); }
1137 case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
1138 case 3: rA32 <<= 1; break; // shl
1139 case 6: rA32 = -(signed int)rA32; break; // neg
1140 case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
1141 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x",
1142 op&7, GET_PPC_OFFS());
1152 read_P(); // update P
1155 rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
1156 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
1159 // mpya (rj), (ri), b
1162 read_P(); // update P
1165 rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
1166 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
1169 // mld (rj), (ri), b
1175 rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
1176 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
1180 case 0x10: CHECK_1f0(); OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
1181 case 0x30: CHECK_1f0(); OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
1182 case 0x40: CHECK_1f0(); OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
1183 case 0x50: CHECK_1f0(); OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
1184 case 0x60: CHECK_1f0(); OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
1185 case 0x70: CHECK_1f0(); OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
1188 case 0x11: CHECK_0f0(); tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
1189 case 0x31: CHECK_0f0(); tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
1190 case 0x41: CHECK_0f0(); tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
1191 case 0x51: CHECK_0f0(); tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
1192 case 0x61: CHECK_0f0(); tmpv = ptr1_read(op); OP_ORA (tmpv); break;
1193 case 0x71: CHECK_0f0(); tmpv = ptr1_read(op); OP_EORA(tmpv); break;
1196 case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
1197 case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break;
1198 case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break;
1199 case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break;
1200 case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break;
1201 case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break;
1202 case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
1205 case 0x14: CHECK_IMM16(); tmpv = *PC++; OP_SUBA(tmpv); g_cycles--; break;
1206 case 0x34: CHECK_IMM16(); tmpv = *PC++; OP_CMPA(tmpv); g_cycles--; break;
1207 case 0x44: CHECK_IMM16(); tmpv = *PC++; OP_ADDA(tmpv); g_cycles--; break;
1208 case 0x54: CHECK_IMM16(); tmpv = *PC++; OP_ANDA(tmpv); g_cycles--; break;
1209 case 0x64: CHECK_IMM16(); tmpv = *PC++; OP_ORA (tmpv); g_cycles--; break;
1210 case 0x74: CHECK_IMM16(); tmpv = *PC++; OP_EORA(tmpv); g_cycles--; break;
1213 case 0x15: CHECK_MOD(); tmpv = ptr2_read(op); OP_SUBA(tmpv); g_cycles -= 2; break;
1214 case 0x35: CHECK_MOD(); tmpv = ptr2_read(op); OP_CMPA(tmpv); g_cycles -= 2; break;
1215 case 0x45: CHECK_MOD(); tmpv = ptr2_read(op); OP_ADDA(tmpv); g_cycles -= 2; break;
1216 case 0x55: CHECK_MOD(); tmpv = ptr2_read(op); OP_ANDA(tmpv); g_cycles -= 2; break;
1217 case 0x65: CHECK_MOD(); tmpv = ptr2_read(op); OP_ORA (tmpv); g_cycles -= 2; break;
1218 case 0x75: CHECK_MOD(); tmpv = ptr2_read(op); OP_EORA(tmpv); g_cycles -= 2; break;
1221 case 0x19: CHECK_MOD(); tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
1222 case 0x39: CHECK_MOD(); tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
1223 case 0x49: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
1224 case 0x59: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
1225 case 0x69: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
1226 case 0x79: CHECK_MOD(); tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
1229 case 0x1c: CHECK_B_SET(); OP_SUBA(op & 0xff); break;
1230 case 0x3c: CHECK_B_SET(); OP_CMPA(op & 0xff); break;
1231 case 0x4c: CHECK_B_SET(); OP_ADDA(op & 0xff); break;
1232 case 0x5c: CHECK_B_SET(); OP_ANDA(op & 0xff); break;
1233 case 0x6c: CHECK_B_SET(); OP_ORA (op & 0xff); break;
1234 case 0x7c: CHECK_B_SET(); OP_EORA(op & 0xff); break;
1237 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
1244 read_P(); // update P