2 * This software is released into the public domain.
3 * See UNLICENSE file in top level directory.
9 //#pragma GCC diagnostic ignored "-Wunused-function"
11 #define VDP_DATA_PORT 0xC00000
12 #define VDP_CTRL_PORT 0xC00004
13 #define VDP_HV_COUNTER 0xC00008
15 #define TILE_MEM_END 0xB000
18 #define TILE_FONT_BASE (TILE_MEM_END - FONT_LEN * 32)
20 /* note: using ED menu's layout here.. */
21 #define WPLANE (TILE_MEM_END + 0x0000)
22 #define HSCRL (TILE_MEM_END + 0x0800)
23 #define SLIST (TILE_MEM_END + 0x0C00)
24 #define APLANE (TILE_MEM_END + 0x1000)
25 #define BPLANE (TILE_MEM_END + 0x3000)
27 #define write16_z80le(a, d) \
28 ((volatile u8 *)(a))[0] = (u8)(d), \
29 ((volatile u8 *)(a))[1] = ((d) >> 8)
31 static inline u16 read16_z80le(const void *a_)
33 volatile const u8 *a = (volatile const u8 *)a_;
34 return a[0] | ((u16)a[1] << 8);
37 #define CTL_WRITE_VRAM(adr) \
38 (((0x4000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
39 #define CTL_WRITE_VSRAM(adr) \
40 (((0x4000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x10)
41 #define CTL_WRITE_CRAM(adr) \
42 (((0xC000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
43 #define CTL_READ_VRAM(adr) \
44 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
45 #define CTL_READ_VSRAM(adr) \
46 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x10)
47 #define CTL_READ_CRAM(adr) \
48 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x20)
50 #define CTL_WRITE_DMA 0x80
52 #define VDP_setReg(r, v) \
53 write16(VDP_CTRL_PORT, 0x8000 | ((r) << 8) | ((v) & 0xff))
58 VDP_NT_SCROLLA = 0x02,
60 VDP_NT_SCROLLB = 0x04,
75 #define VDP_MODE1_PS 0x04
76 #define VDP_MODE1_IE1 0x10 // h int
77 #define VDP_MODE2_MD 0x04
78 #define VDP_MODE2_PAL 0x08 // 30 col
79 #define VDP_MODE2_DMA 0x10
80 #define VDP_MODE2_IE0 0x20 // v int
81 #define VDP_MODE2_DISP 0x40
82 #define VDP_MODE2_128K 0x80
84 #define SR_PAL (1 << 0)
85 #define SR_DMA (1 << 1)
86 #define SR_HB (1 << 2)
87 #define SR_VB (1 << 3)
88 #define SR_ODD (1 << 4)
90 #define SR_SOVR (1 << 6)
92 #define SR_FULL (1 << 8)
93 #define SR_EMPT (1 << 9)
96 #define LEFT_BORDER 1 /* lame TV */
102 extern const u32 font_base[];
103 extern const u8 z80_test[];
104 extern const u8 z80_test_end[];
108 static noinline void VDP_drawTextML(const char *str, u16 plane_base,
111 const u8 *src = (const u8 *)str;
112 u16 basetile = text_pal << 13;
113 int max_len = 40 - LEFT_BORDER;
119 for (len = 0; str[len] && len < max_len; len++)
121 if (len > (PLANE_W - x))
124 addr = plane_base + ((x + (PLANE_W * y)) << 1);
125 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr));
128 write16(VDP_DATA_PORT,
129 basetile | ((*src++) - 32 + TILE_FONT_BASE / 32));
133 static int printf_ypos;
135 static void printf_line(int x, const char *buf)
140 VDP_drawTextML(buf, APLANE, x, printf_ypos++ & (PLANE_H - 1));
142 if (printf_ypos >= CSCREEN_H) {
143 /* clear next line */
145 addr += (PLANE_W * (printf_ypos & (PLANE_H - 1))) << 1;
146 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr));
147 for (i = 0; i < 40 / 2; i++)
148 write32(VDP_DATA_PORT, 0);
151 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
152 write16(VDP_DATA_PORT, (printf_ypos - CSCREEN_H + 1) * 8);
156 #define PRINTF_LEN 40
158 static int printf_xpos;
160 static noinline int printf(const char *fmt, ...)
162 static const char hexchars[] = "0123456789abcdef";
163 char c, buf[PRINTF_LEN + 11 + 1];
172 for (d = 0; *fmt; ) {
183 printf_line(printf_xpos, buf);
199 while ('1' <= *fmt && *fmt <= '9') {
200 fwidth = fwidth * 10 + *fmt - '0';
210 ival = va_arg(ap, int);
215 for (i = 1000000000; i >= 10; i /= 10)
218 for (; i >= 10; i /= 10) {
219 buf[d++] = '0' + ival / i;
222 buf[d++] = '0' + ival;
225 uval = va_arg(ap, int);
226 while (fwidth > 1 && uval < (1 << (fwidth - 1) * 4)) {
227 buf[d++] = prefix0 ? '0' : ' ';
230 for (j = 1; j < 8 && uval >= (1 << j * 4); j++)
232 for (j--; j >= 0; j--)
233 buf[d++] = hexchars[(uval >> j * 4) & 0x0f];
236 buf[d++] = va_arg(ap, int);
239 s = va_arg(ap, char *);
240 while (*s && d < PRINTF_LEN)
244 // don't handle, for now
255 VDP_drawTextML(buf, APLANE, printf_xpos,
256 printf_ypos & (PLANE_H - 1));
263 static const char *exc_names[] = {
268 "Illegal Instruction",
272 "Privilege Violation", /* 8 8 */
274 "Line 1010 Emulator",
275 "Line 1111 Emulator",
279 "Uninitialized Interrupt",
288 "Spurious Interrupt", /* 18 24 */
301 u16 ecxnum; // from handler
313 } bae _packed; // bus/address error frame
317 void exception(const struct exc_frame *f)
322 while (read16(VDP_CTRL_PORT) & 2)
324 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
325 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DISP);
327 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
328 write16(VDP_DATA_PORT,
329 printf_ypos >= CSCREEN_H ?
330 (printf_ypos - CSCREEN_H + 1) * 8 : 0);
332 printf("exception %i ", f->ecxnum);
333 if (f->ecxnum < ARRAY_SIZE(exc_names) && exc_names[f->ecxnum] != NULL)
334 printf("(%s)", exc_names[f->ecxnum]);
336 printf(" (%s)", (f->bae.fc & 0x10) ? "r" : "w");
340 printf(" PC: %08x SR: %04x \n", f->bae.pc, f->bae.sr);
341 printf("addr: %08x IR: %04x FC: %02x \n",
342 f->bae.addr, f->bae.ir, f->bae.fc);
346 printf(" PC: %08x SR: %04x \n", f->g.pc, f->g.sr);
349 sp = (u32 *)(f->ar[7] + sp_add);
350 for (i = 0; i < 7; i++)
351 printf(" D%d: %08x A%d: %08x \n", i, f->dr[i], i, f->ar[i]);
352 printf(" D%d: %08x SP: %08x \n", i, f->dr[i], (u32)sp);
354 printf(" %08x %08x %08x %08x\n", sp[0], sp[1], sp[2], sp[3]);
355 printf(" %08x %08x %08x %08x\n", sp[4], sp[5], sp[6], sp[7]);
360 static void setup_default_palette(void)
362 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
363 write32(VDP_DATA_PORT, 0);
364 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(15 * 2)); // font normal
365 write16(VDP_DATA_PORT, 0xeee);
366 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(31 * 2)); // green
367 write16(VDP_DATA_PORT, 0x0e0);
368 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(47 * 2)); // red
369 write16(VDP_DATA_PORT, 0x00e);
372 static void do_setup_dma(const void *src_, u16 words)
375 // VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA);
376 VDP_setReg(VDP_DMA_LEN0, words);
377 VDP_setReg(VDP_DMA_LEN1, words >> 8);
378 VDP_setReg(VDP_DMA_SRC0, src >> 1);
379 VDP_setReg(VDP_DMA_SRC1, src >> 9);
380 VDP_setReg(VDP_DMA_SRC2, src >> 17);
381 // write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr) | CTL_WRITE_DMA);
384 static void vdp_wait_for_fifo_empty(void)
386 while (!(read16(VDP_CTRL_PORT) & 0x200))
387 /* fifo not empty */;
390 static void vdp_wait_for_dma_idle(void)
392 while (read16(VDP_CTRL_PORT) & 2)
396 static void vdp_wait_for_line_0(void)
398 // in PAL vcounter reports 0 twice in a frame,
399 // so wait for vblank to clear first
400 while (!(read16(VDP_CTRL_PORT) & 8))
402 while (read16(VDP_CTRL_PORT) & 8)
404 while (read8(VDP_HV_COUNTER) != 0)
408 static void wait_next_vsync(void)
410 while (read16(VDP_CTRL_PORT) & SR_VB)
412 while (!(read16(VDP_CTRL_PORT) & SR_VB))
416 static void t_dma_zero_wrap_early(void)
418 const u32 *src = (const u32 *)0x3c0000;
419 u32 *ram = (u32 *)0xff0000;
421 do_setup_dma(src + 4, 2);
422 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) | CTL_WRITE_DMA);
423 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) | CTL_WRITE_DMA);
425 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
426 ram[0] = read32(VDP_DATA_PORT);
427 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfffc));
428 ram[1] = read32(VDP_DATA_PORT);
431 static void t_dma_zero_fill_early(void)
433 u32 *ram = (u32 *)0xff0000;
435 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
436 write32(VDP_DATA_PORT, 0);
437 write32(VDP_DATA_PORT, 0);
438 write32(VDP_DATA_PORT, 0);
439 write32(VDP_DATA_PORT, 0);
441 VDP_setReg(VDP_AUTOINC, 1);
442 VDP_setReg(VDP_DMA_SRC2, 0x80);
443 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(1) | CTL_WRITE_DMA);
444 write16(VDP_DATA_PORT, 0x1122);
445 ram[2] = read16(VDP_CTRL_PORT);
446 vdp_wait_for_dma_idle();
448 VDP_setReg(VDP_AUTOINC, 2);
449 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
450 ram[3] = read32(VDP_DATA_PORT);
453 #define R_SKIP 0x5a5a
455 #define expect(ok_, v0_, v1_) \
456 do { if ((v0_) != (v1_)) { \
457 printf("%s: %08x %08x\n", #v0_, v0_, v1_); \
461 #define expect_sh2(ok_, sh2_, v0_, v1_) \
462 do { if ((v0_) != (v1_)) { \
463 printf("%csh2: %08x %08x\n", sh2_ ? 's' : 'm', v0_, v1_); \
467 #define expect_range(ok_, v0_, vmin_, vmax_) \
468 do { if ((v0_) < (vmin_) || (v0_) > (vmax_)) { \
469 printf("%s: %02x /%02x-%02x\n", #v0_, v0_, vmin_, vmax_); \
473 #define expect_bits(ok_, v0_, val_, mask_) \
474 do { if (((v0_) & (mask_)) != (val_)) { \
475 printf("%s: %04x & %04x != %04x\n", #v0_, v0_, mask_, val_); \
479 static int t_dma_zero_wrap(void)
481 const u32 *src = (const u32 *)0x3c0000;
482 const u32 *ram = (const u32 *)0xff0000;
485 expect(ok, ram[0], src[5 + 0x10000/4]);
486 expect(ok, ram[1], src[4]);
490 static int t_dma_zero_fill(void)
492 const u32 *ram = (const u32 *)0xff0000;
497 expect(ok, ram[3], 0x11111111);
501 static int t_dma_ram_wrap(void)
503 u32 *ram = (u32 *)0xff0000;
507 saved = read32(&ram[0x10000/4 - 1]);
508 ram[0x10000/4 - 1] = 0x01020304;
510 do_setup_dma(&ram[0x10000/4 - 1], 4);
512 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
515 write32(&ram[0x10000/4 - 1], saved);
517 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
518 v0 = read32(VDP_DATA_PORT);
519 v1 = read32(VDP_DATA_PORT);
521 expect(ok, v0, 0x01020304);
522 expect(ok, v1, 0x05060708);
526 // test no src reprogram, only len0
527 static int t_dma_multi(void)
529 const u32 *src = (const u32 *)0x3c0000;
533 do_setup_dma(src, 2);
534 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
535 VDP_setReg(VDP_DMA_LEN0, 2);
536 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x104) | CTL_WRITE_DMA);
538 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
539 v0 = read32(VDP_DATA_PORT);
540 v1 = read32(VDP_DATA_PORT);
542 expect(ok, v0, src[0]);
543 expect(ok, v1, src[1]);
547 static int t_dma_cram_wrap(void)
549 u32 *ram = (u32 *)0xff0000;
553 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
554 write32(VDP_DATA_PORT, 0);
559 do_setup_dma(ram, 4);
560 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0x7c | 0xff81) | CTL_WRITE_DMA);
562 write32(VDP_CTRL_PORT, CTL_READ_CRAM(0x7c));
563 v0 = read32(VDP_DATA_PORT) & 0x0eee0eee;
564 write32(VDP_CTRL_PORT, CTL_READ_CRAM(0));
565 v1 = read32(VDP_DATA_PORT) & 0x0eee0eee;
567 setup_default_palette();
569 expect(ok, v0, ram[0]);
570 expect(ok, v1, ram[1]);
574 static int t_dma_vsram_wrap(void)
576 u32 *ram32 = (u32 *)0xff0000;
577 u16 *ram16 = (u16 *)0xff0000;
582 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
583 write32(VDP_DATA_PORT, 0);
585 for (i = 0; i < 0x48/2; i++)
588 do_setup_dma(ram16, 0x48/2);
589 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0x3c | 0xff81) | CTL_WRITE_DMA);
591 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0x3c));
592 v0 = read32(VDP_DATA_PORT) & 0x03ff03ff;
593 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0));
594 v1 = read32(VDP_DATA_PORT) & 0x03ff03ff;
596 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
597 write32(VDP_DATA_PORT, 0);
599 expect(ok, v0, ram32[0]);
600 expect(ok, v1, ram32[0x48/4 - 1]);
604 static int t_dma_and_data(void)
606 const u32 *src = (const u32 *)0x3c0000;
610 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
611 write32(VDP_DATA_PORT, 0);
613 do_setup_dma(src, 2);
614 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfc) | CTL_WRITE_DMA);
615 write32(VDP_DATA_PORT, 0x5ec8a248);
617 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfc));
618 v0 = read32(VDP_DATA_PORT);
619 v1 = read32(VDP_DATA_PORT);
621 expect(ok, v0, src[0]);
622 expect(ok, v1, 0x5ec8a248);
626 static int t_dma_short_cmd(void)
628 const u32 *src = (const u32 *)0x3c0000;
632 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x3ff4));
633 write32(VDP_DATA_PORT, 0x10111213);
634 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfff0));
635 write32(VDP_DATA_PORT, 0x20212223);
636 write32(VDP_DATA_PORT, 0x30313233);
637 vdp_wait_for_fifo_empty();
639 do_setup_dma(src, 2);
640 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfff0) | CTL_WRITE_DMA);
641 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x3ff4) >> 16);
642 write32(VDP_DATA_PORT, 0x40414243);
644 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x3ff4));
645 v0 = read32(VDP_DATA_PORT);
646 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfff0));
647 v1 = read32(VDP_DATA_PORT);
648 v2 = read32(VDP_DATA_PORT);
650 expect(ok, v0, 0x10111213);
651 expect(ok, v1, src[0]);
652 expect(ok, v2, 0x40414243);
656 static int t_dma_fill3_odd(void)
661 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
662 write32(VDP_DATA_PORT, 0);
663 write32(VDP_DATA_PORT, 0);
664 write32(VDP_DATA_PORT, 0);
665 vdp_wait_for_fifo_empty();
667 VDP_setReg(VDP_AUTOINC, 3);
668 VDP_setReg(VDP_DMA_LEN0, 3);
669 VDP_setReg(VDP_DMA_SRC2, 0x80);
670 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x101) | CTL_WRITE_DMA);
671 write16(VDP_DATA_PORT, 0x1122);
672 vdp_wait_for_dma_idle();
674 VDP_setReg(VDP_AUTOINC, 2);
675 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
676 v0 = read32(VDP_DATA_PORT);
677 v1 = read32(VDP_DATA_PORT);
678 v2 = read32(VDP_DATA_PORT);
680 expect(ok, v0, 0x22110000);
681 expect(ok, v1, 0x00111100);
682 expect(ok, v2, 0x00000011);
686 static int t_dma_fill3_even(void)
691 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
692 write32(VDP_DATA_PORT, 0);
693 write32(VDP_DATA_PORT, 0);
694 write32(VDP_DATA_PORT, 0);
695 vdp_wait_for_fifo_empty();
697 VDP_setReg(VDP_AUTOINC, 3);
698 VDP_setReg(VDP_DMA_LEN0, 3);
699 VDP_setReg(VDP_DMA_SRC2, 0x80);
700 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
701 write16(VDP_DATA_PORT, 0x1122);
702 vdp_wait_for_dma_idle();
704 VDP_setReg(VDP_AUTOINC, 2);
705 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
706 v0 = read32(VDP_DATA_PORT);
707 v1 = read32(VDP_DATA_PORT);
708 v2 = read32(VDP_DATA_PORT);
710 expect(ok, v0, 0x11221100);
711 expect(ok, v1, 0x00000011);
712 expect(ok, v2, 0x11000000);
716 static unused int t_dma_fill3_vsram(void)
721 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
722 write32(VDP_DATA_PORT, 0);
723 write32(VDP_DATA_PORT, 0);
724 write32(VDP_DATA_PORT, 0);
726 write16(VDP_DATA_PORT, 0x0111);
727 write16(VDP_DATA_PORT, 0x0222);
728 write16(VDP_DATA_PORT, 0x0333);
729 vdp_wait_for_fifo_empty();
731 VDP_setReg(VDP_AUTOINC, 3);
732 VDP_setReg(VDP_DMA_LEN0, 3);
733 VDP_setReg(VDP_DMA_SRC2, 0x80);
734 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(1) | CTL_WRITE_DMA);
735 write16(VDP_DATA_PORT, 0x0102);
736 vdp_wait_for_dma_idle();
738 VDP_setReg(VDP_AUTOINC, 2);
739 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0));
740 v0 = read32(VDP_DATA_PORT);
741 v1 = read32(VDP_DATA_PORT);
742 v2 = read32(VDP_DATA_PORT);
744 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
745 write32(VDP_DATA_PORT, 0);
747 expect(ok, v0, 0x01020000);
748 expect(ok, v1, 0x01110111);
749 expect(ok, v2, 0x00000111);
753 static int t_dma_fill_dis(void)
758 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
759 write32(VDP_DATA_PORT, 0);
760 write32(VDP_DATA_PORT, 0);
762 VDP_setReg(VDP_DMA_LEN0, 1);
763 VDP_setReg(VDP_DMA_SRC2, 0x80);
764 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
765 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
766 write16(VDP_DATA_PORT, 0x1122);
767 vdp_wait_for_dma_idle();
769 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
770 write16(VDP_DATA_PORT, 0x3344);
771 vdp_wait_for_dma_idle();
773 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
774 v0 = read32(VDP_DATA_PORT);
775 v1 = read32(VDP_DATA_PORT);
782 static int t_dma_fill_src(void)
784 const u32 *src = (const u32 *)0x3c0000;
788 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
789 write32(VDP_DATA_PORT, 0);
791 // do_setup_dma(src, 2); // hang, can't write src2 twice
792 VDP_setReg(VDP_DMA_LEN0, 2);
793 VDP_setReg(VDP_DMA_SRC0, (u32)src >> 1);
794 VDP_setReg(VDP_DMA_SRC1, (u32)src >> 9);
795 VDP_setReg(VDP_DMA_SRC2, 0x80);
796 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
797 write16(VDP_DATA_PORT, 0x1122);
798 vdp_wait_for_dma_idle();
800 VDP_setReg(VDP_DMA_LEN0, 2);
801 VDP_setReg(VDP_DMA_SRC2, (u32)src >> 17);
802 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x104) | CTL_WRITE_DMA);
804 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
805 v0 = read32(VDP_DATA_PORT);
806 v1 = read32(VDP_DATA_PORT);
808 expect(ok, v0, 0x11220011);
809 expect(ok, v1, src[1]);
813 // should not see the busy flag
814 static int t_dma_busy_vram(void)
816 const u32 *src = (const u32 *)0x3c0000;
820 vdp_wait_for_line_0();
822 do_setup_dma(src, 1);
823 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
824 sr[0] = read16(VDP_CTRL_PORT);
826 do_setup_dma(src, 4);
827 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
828 sr[1] = read16(VDP_CTRL_PORT);
830 VDP_setReg(VDP_DMA_LEN0, 8);
831 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
832 sr[2] = read16(VDP_CTRL_PORT);
834 expect_bits(ok, sr[0], 0, SR_DMA);
835 expect_bits(ok, sr[1], 0, SR_DMA);
836 expect_bits(ok, sr[2], 0, SR_DMA);
840 // (((a & 2) >> 1) ^ 1) | ((a & $400) >> 9) | (a & $3FC) | ((a & $1F800) >> 1)
841 static int t_dma_128k(void)
843 u16 *ram = (u16 *)0xff0000;
851 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
852 write32(VDP_DATA_PORT, 0x01020304);
853 write32(VDP_DATA_PORT, 0x05060708);
854 vdp_wait_for_fifo_empty();
857 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
858 do_setup_dma(ram, 3);
859 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
860 vdp_wait_for_fifo_empty();
862 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
863 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
864 v0 = read32(VDP_DATA_PORT);
865 v1 = read32(VDP_DATA_PORT);
867 expect(ok, v0, 0x22110304);
868 expect(ok, v1, 0x05330708);
872 static int t_vdp_128k_b16(void)
877 VDP_setReg(VDP_AUTOINC, 0);
878 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8100));
879 write32(VDP_DATA_PORT, 0x01020304);
880 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x10100));
881 write32(VDP_DATA_PORT, 0x05060708);
882 vdp_wait_for_fifo_empty();
884 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
885 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) >> 16); // note: upper cmd
886 write32(VDP_DATA_PORT, 0x11223344);
887 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x10102));
888 write32(VDP_DATA_PORT, 0x55667788);
889 vdp_wait_for_fifo_empty();
891 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
892 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x8100));
893 v0 = read16(VDP_DATA_PORT);
894 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x0100));
895 v1 = read16(VDP_DATA_PORT);
897 VDP_setReg(VDP_AUTOINC, 2);
899 expect(ok, v0, 0x8844);
900 expect(ok, v1, 0x0708);
904 static unused int t_vdp_128k_b16_inc(void)
909 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
910 write32(VDP_DATA_PORT, 0x01020304);
911 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8000));
912 write32(VDP_DATA_PORT, 0x05060708);
913 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfffe));
914 write32(VDP_DATA_PORT, 0x090a0b0c);
915 vdp_wait_for_fifo_empty();
917 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
918 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) >> 16); // note: upper cmd
919 write16(VDP_DATA_PORT, 0x1122);
920 vdp_wait_for_fifo_empty();
922 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
923 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
924 v0 = read32(VDP_DATA_PORT);
925 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x8000));
926 v1 = read32(VDP_DATA_PORT);
927 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
928 write32(VDP_DATA_PORT, 0);
929 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8000));
930 write32(VDP_DATA_PORT, 0);
932 expect(ok, v0, 0x0b0c0304); // XXX: no 22 anywhere?
933 expect(ok, v1, 0x05060708);
937 static int t_vdp_reg_cmd(void)
942 VDP_setReg(VDP_AUTOINC, 0);
943 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
944 write32(VDP_DATA_PORT, 0x01020304);
945 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
946 write32(VDP_DATA_PORT, 0x05060708);
948 VDP_setReg(VDP_AUTOINC, 2);
949 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x0100));
950 v0 = read16(VDP_DATA_PORT);
952 expect(ok, v0, 0x0304);
956 static int t_vdp_sr_vb(void)
961 while (read8(VDP_HV_COUNTER) != 242)
963 sr[0] = read16(VDP_CTRL_PORT);
964 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
965 sr[1] = read16(VDP_CTRL_PORT);
966 while (read8(VDP_HV_COUNTER) != 4)
968 sr[2] = read16(VDP_CTRL_PORT);
969 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
970 sr[3] = read16(VDP_CTRL_PORT);
972 expect_bits(ok, sr[0], SR_VB, SR_VB);
973 expect_bits(ok, sr[1], SR_VB, SR_VB);
974 expect_bits(ok, sr[2], SR_VB, SR_VB);
975 expect_bits(ok, sr[3], 0, SR_VB);
979 /* z80 tests assume busreq state */
980 static int t_z80mem_long_mirror(void)
982 u8 *zram = (u8 *)0xa00000;
985 write8(&zram[0x1100], 0x11);
986 write8(&zram[0x1101], 0x22);
987 write8(&zram[0x1102], 0x33);
988 write8(&zram[0x1103], 0x44);
990 write32(&zram[0x3100], 0x55667788);
993 expect(ok, zram[0x1100], 0x55);
994 expect(ok, zram[0x1101], 0x22);
995 expect(ok, zram[0x1102], 0x77);
996 expect(ok, zram[0x1103], 0x44);
1000 static int t_z80mem_noreq_w(void)
1002 u8 *zram = (u8 *)0xa00000;
1005 write8(&zram[0x1100], 0x11);
1007 write16(0xa11100, 0x000);
1008 write8(&zram[0x1100], 0x22);
1011 write16(0xa11100, 0x100);
1012 while (read16(0xa11100) & 0x100)
1015 expect(ok, zram[0x1100], 0x11);
1019 #define Z80_C_DISPATCH 113 // see z80_test.s80
1020 #define Z80_C_END 17
1021 #define Z80_C_END_VCNT 67
1023 #define Z80_CYLES_TEST1(b) (Z80_C_DISPATCH + ((b) - 1) * 21 + 26 + Z80_C_END)
1025 static int t_z80mem_vdp_r(void)
1027 u8 *zram = (u8 *)0xa00000;
1030 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
1031 write32(VDP_DATA_PORT, 0x11223344);
1032 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
1034 zram[0x1000] = 1; // cp
1035 write16_z80le(&zram[0x1002], 0x7f00); // src
1036 write16_z80le(&zram[0x1004], 0x1100); // dst
1037 write16_z80le(&zram[0x1006], 2); // len
1038 zram[0x1100] = zram[0x1101] = zram[0x1102] = 0x5a;
1040 write16(0xa11100, 0x000);
1041 burn10(Z80_CYLES_TEST1(2) * 15 / 7 / 10);
1043 write16(0xa11100, 0x100);
1044 while (read16(0xa11100) & 0x100)
1047 expect(ok, zram[0x1000], 0);
1048 expect(ok, zram[0x1100], 0x11);
1049 expect(ok, zram[0x1101], 0x44);
1050 expect(ok, zram[0x1102], 0x5a);
1054 static unused int t_z80mem_vdp_w(void)
1056 u8 *zram = (u8 *)0xa00000;
1060 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
1061 write32(VDP_DATA_PORT, 0x11223344);
1062 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
1063 vdp_wait_for_fifo_empty();
1065 zram[0x1000] = 1; // cp
1066 write16_z80le(&zram[0x1002], 0x1100); // src
1067 write16_z80le(&zram[0x1004], 0x7f00); // dst
1068 write16_z80le(&zram[0x1006], 2); // len
1069 zram[0x1100] = 0x55;
1070 zram[0x1101] = 0x66;
1072 write16(0xa11100, 0x000);
1073 burn10(Z80_CYLES_TEST1(2) * 15 / 7 / 10);
1075 write16(0xa11100, 0x100);
1076 while (read16(0xa11100) & 0x100)
1079 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
1080 v0 = read32(VDP_DATA_PORT);
1082 expect(ok, zram[0x1000], 0);
1083 expect(ok, v0, 0x55556666);
1087 static int t_tim_loop(void)
1092 vdp_wait_for_line_0();
1094 vcnt = read8(VDP_HV_COUNTER);
1097 //expect_range(ok, vcnt, 0x80, 0x80);
1098 expect(ok, vcnt, 223);
1102 static int t_tim_z80_loop(void)
1104 u8 pal = read8(0xa10001) & 0x40;
1105 u8 *zram = (u8 *)0xa00000;
1106 u16 z80_loops = pal ? 3420*(313*2+1)/15/100 : 3420*(262*2+1)/15/100; // 2fr + 1ln
1107 u16 _68k_loops = pal ? 3420*(313*2+1)/7/10 : 3420*(262*2+1)/7/10;
1110 zram[0x1000] = 3; // idle loop, save vcnt
1111 write16_z80le(&zram[0x1002], 0); // src (unused)
1112 write16_z80le(&zram[0x1004], 0x1100); // vcnt dst
1113 write16_z80le(&zram[0x1006], z80_loops); // x100 cycles
1117 vdp_wait_for_line_0();
1118 write16(0xa11100, 0x000);
1119 burn10(_68k_loops + (Z80_C_DISPATCH + Z80_C_END_VCNT) * 15 / 7 / 10);
1121 write16(0xa11100, 0x100);
1122 while (read16(0xa11100) & 0x100)
1124 expect(ok, zram[0x1000], 0);
1125 expect(ok, zram[0x1100], 1);
1129 #define Z80_CYCLES_TEST2(b) (Z80_C_DISPATCH + (b) * 38 + Z80_C_END_VCNT)
1132 static void z80_read_loop(u8 *zram, u16 src)
1134 const int pairs = 512 + 256;
1136 zram[0x1000] = 2; // read loop, save vcnt
1137 write16_z80le(&zram[0x1002], src); // src
1138 write16_z80le(&zram[0x1004], 0x1100); // vcnt dst
1139 write16_z80le(&zram[0x1006], pairs); // reads/2
1143 vdp_wait_for_line_0();
1144 write16(0xa11100, 0x000);
1145 burn10(Z80_CYCLES_TEST2(pairs) * 15 / 7 * 2 / 10);
1147 write16(0xa11100, 0x100);
1148 while (read16(0xa11100) & 0x100)
1152 static int t_tim_z80_ram(void)
1154 u8 *zram = (u8 *)0xa00000;
1157 z80_read_loop(zram, 0);
1159 expect(ok, zram[0x1000], 0);
1160 expect_range(ok, zram[0x1100], 0x80, 0x80);
1164 static int t_tim_z80_ym(void)
1166 u8 *zram = (u8 *)0xa00000;
1169 z80_read_loop(zram, 0x4000);
1171 expect(ok, zram[0x1000], 0);
1172 expect_range(ok, zram[0x1100], 0x80, 0x80);
1176 static int t_tim_z80_vdp(void)
1178 u8 *zram = (u8 *)0xa00000;
1181 z80_read_loop(zram, 0x7f08);
1183 expect(ok, zram[0x1000], 0);
1184 expect_range(ok, zram[0x1100], 0x91, 0x91);
1188 static int t_tim_z80_bank_rom(void)
1190 u8 *zram = (u8 *)0xa00000;
1193 for (i = 0; i < 17; i++)
1194 write8(0xa06000, 0); // bank 0
1196 z80_read_loop(zram, 0x8000);
1198 expect(ok, zram[0x1000], 0);
1199 expect_range(ok, zram[0x1100], 0x95, 0x96);
1203 /* borderline too slow */
1205 static void test_vcnt_vb(void)
1207 const u32 *srhv = (u32 *)0xc00006; // to read SR and HV counter
1208 u32 *ram = (u32 *)0xff0000;
1209 u16 vcnt, vcnt_expect = 0;
1213 vdp_wait_for_line_0();
1218 vcnt = val & 0xff00;
1219 if (vcnt == vcnt_expect)
1222 if (vcnt == 0 && !(sr & SR_VB)) // not VB
1223 break; // wrapped to start of frame
1225 vcnt_expect += 0x100;
1226 if (vcnt == vcnt_expect && !((sr ^ (old >> 16)) & SR_VB)) {
1230 // should have a vcnt jump here
1242 static int t_tim_vcnt(void)
1244 const u32 *ram32 = (u32 *)0xff0000;
1245 const u8 *ram = (u8 *)0xff0000;
1246 u8 pal = read8(0xa10001) & 0x40;
1247 u8 vc_jmp_b = pal ? 0x02 : 0xea;
1248 u8 vc_jmp_a = pal ? 0xca : 0xe5;
1249 u16 lines = pal ? 313 : 262;
1253 expect(ok, ram[0*4+2], 0); // line 0
1254 expect_bits(ok, ram[0*4+1], 0, SR_VB);
1255 expect(ok, ram[1*4+2], 223); // last no blank
1256 expect_bits(ok, ram[1*4+1], 0, SR_VB);
1257 expect(ok, ram[2*4+2], 224); // 1st blank
1258 expect_bits(ok, ram[2*4+1], SR_VB, SR_VB);
1259 expect(ok, ram[3*4+2], vc_jmp_b); // before jump
1260 expect_bits(ok, ram[3*4+1], SR_VB, SR_VB);
1261 expect(ok, ram[4*4+2], vc_jmp_a); // after jump
1262 expect_bits(ok, ram[4*4+1], SR_VB, SR_VB);
1263 expect(ok, ram[5*4+2], 0xfe); // before vb clear
1264 expect_bits(ok, ram[5*4+1], SR_VB, SR_VB);
1265 expect(ok, ram[6*4+2], 0xff); // after vb clear
1266 expect_bits(ok, ram[6*4+1], 0, SR_VB);
1267 expect(ok, ram[7*4+2], 0); // next line 0
1268 expect_bits(ok, ram[7*4+1], 0, SR_VB);
1269 expect(ok, ram32[8], lines - 1);
1273 static int t_tim_vcnt_loops(void)
1275 const u16 *ram16 = (u16 *)0xfff004;
1276 u8 pal = read8(0xa10001) & 0x40;
1277 u16 i, lines = pal ? 313 : 262;
1281 expect(ok, ram16[-1*2+0], 0xff);
1282 expect_range(ok, ram16[-1*2+1], 21, 22);
1283 for (i = 0; i < lines; i++)
1284 expect_range(ok, ram16[i*2+1], 19, 21);
1285 expect(ok, ram16[lines*2+0], 0);
1286 expect_range(ok, ram16[lines*2+1], 19, 21);
1290 static int t_tim_hblank_h40(void)
1292 const u8 *r = (u8 *)0xff0000;
1298 expect_bits(ok, r[2], SR_HB, SR_HB);
1299 expect_bits(ok, r[5], SR_HB, SR_HB);
1301 expect_bits(ok, r[7], SR_HB, SR_HB);
1303 expect_bits(ok, r[12], 0, SR_HB);
1307 static int t_tim_hblank_h32(void)
1309 const u8 *r = (u8 *)0xff0000;
1312 VDP_setReg(VDP_MODE4, 0x00);
1314 VDP_setReg(VDP_MODE4, 0x81);
1316 expect_bits(ok, r[0], 0, SR_HB);
1318 expect_bits(ok, r[4], SR_HB, SR_HB);
1319 expect_bits(ok, r[5], SR_HB, SR_HB);
1321 expect_bits(ok, r[8], SR_HB, SR_HB);
1323 expect_bits(ok, r[12], 0, SR_HB);
1327 static int t_tim_vdp_as_vram_w(void)
1332 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
1333 vdp_wait_for_line_0();
1334 write16_x16(VDP_DATA_PORT, 112*18 / 16, 0);
1335 vcnt = read8(VDP_HV_COUNTER);
1338 expect(ok, vcnt, 112*2-1);
1342 static int t_tim_vdp_as_cram_w(void)
1347 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
1348 vdp_wait_for_line_0();
1349 write16_x16(VDP_DATA_PORT, 112*18 / 16, 0);
1350 vcnt = read8(VDP_HV_COUNTER);
1353 setup_default_palette();
1355 expect(ok, vcnt, 112);
1359 static const u8 hcnt2tm[] =
1361 0x0a, 0x1d, 0x31, 0x44, 0x58, 0x6b, 0x7f, 0x92,
1362 0xa6, 0xb9, 0xcc, 0x00, 0x00, 0x00, 0xe2, 0xf6
1365 static int t_tim_ym_timer_z80(int is_b)
1367 u8 pal = read8(0xa10001) & 0x40;
1368 u8 *zram = (u8 *)0xa00000;
1370 u16 _68k_loops = 3420*(302+5+1)/7/10; // ~ (72*1024*2)/(3420./7)
1371 u16 start, end, diff;
1374 zram[0x1000] = 4 + is_b; // ym2612 timer a/b test
1375 zram[0x1100] = zram[0x1101] = zram[0x1102] = zram[0x1103] = 0;
1378 vdp_wait_for_line_0();
1379 write16(0xa11100, 0x000);
1381 burn10(_68k_loops + (Z80_C_DISPATCH + Z80_C_END_VCNT) * 15 / 7 / 10);
1383 write16(0xa11100, 0x100);
1384 while (read16(0xa11100) & 0x100)
1387 expect(ok, zram[0x1000], 0);
1389 //start = ((u16)zram[0x1102] << 8) | hcnt2tm[zram[0x1103] >> 4];
1390 //end = ((u16)zram[0x1100] << 8) | hcnt2tm[zram[0x1101] >> 4];
1391 start = zram[0x1102];
1395 expect_range(ok, diff, 0xf4, 0xf6);
1397 expect_range(ok, diff, 0x27, 0x29);
1398 write8(&z80[0x4001], 0); // stop, but should keep the flag
1400 burn10(32*6/10); // busy bit, 32 FM ticks (M/7/6)
1402 expect(ok, z80[0x4000], 2);
1403 write8(&z80[0x4001], 0x20); // reset flag (reg 0x27, set up by z80)
1406 expect(ok, z80[0x4000], 1);
1407 write8(&z80[0x4001], 0x10);
1411 expect(ok, z80[0x4000], 0);
1415 static int t_tim_ym_timera_z80(void)
1417 return t_tim_ym_timer_z80(0);
1420 static int t_tim_ym_timerb_z80(void)
1422 return t_tim_ym_timer_z80(1);
1425 static int t_tim_ym_timerb_stop(void)
1436 } *t = (void *)0xfff000;
1437 u8 *z80 = (u8 *)0xa00000;
1440 write16(0xa11100, 0x100);
1441 while (read16(0xa11100) & 0x100)
1443 test_ym_stopped_tick();
1445 //start = ((u16)t->vcnt_start << 8) | hcnt2tm[t->hcnt_start >> 4];
1446 //end = ((u16)t->vcnt_end << 8) | hcnt2tm[t->hcnt_end >> 4];
1447 //diff = end - start;
1448 diff = t->vcnt_end - t->vcnt_start;
1449 //expect_range(ok, diff, 0x492, 0x5c2); // why so much variation?
1450 expect_range(ok, diff, 4, 5);
1451 expect(ok, t->stat0, 0);
1452 expect(ok, t->stat1, 2);
1453 expect(ok, z80[0x4000], 2);
1454 write8(&z80[0x4001], 0x30);
1458 static int t_tim_ym_timer_ab_sync(void)
1460 u16 v1, v2, v3, v4, v5, ln0, ln1, ln2;
1463 vdp_wait_for_line_0();
1464 v1 = test_ym_ab_sync();
1467 burn10(3420*15/7/10); // ~15 scanlines
1468 write8(0xa04001, 0x3f); // clear, no reload
1469 burn10(12); // wait for busy to clear
1470 v2 = read8(0xa04000);
1471 v3 = test_ym_ab_sync2();
1474 burn10(3420*15/7/10); // ~15 scanlines
1475 v4 = test_ym_ab_sync2();
1478 burn10(3420*30/7/10); // ~35 scanlines
1479 v5 = read8(0xa04000);
1486 expect_range(ok, ln1-ln0, 18, 19);
1487 expect_range(ok, ln2-ln1, 32, 34); // almost always 33
1500 // broken on fresh boot due to uknown reasons
1501 static int t_irq_hint(void)
1503 struct irq_test *it = (void *)0xfff000;
1504 struct irq_test *itv = it + 1;
1507 memset_(it, 0, sizeof(*it) * 2);
1508 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1509 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1511 // without this, tests fail after cold boot
1512 while (!(read16(VDP_CTRL_PORT) & 8))
1515 // for more fun, disable the display
1516 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
1519 while (read8(VDP_HV_COUNTER) != 100)
1521 while (read8(VDP_HV_COUNTER) != 229)
1523 // take the pending irq
1524 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1526 burn10(488 * 2 / 10);
1528 expect(ok, it->first.v, 229); // pending irq trigger
1529 expect(ok, it->cnt, 1);
1530 expect(ok, itv->cnt, 0);
1533 it->cnt = it->first.hv = it->last.hv = 0;
1535 while (read8(VDP_HV_COUNTER) != 4)
1537 while (read8(VDP_HV_COUNTER) != 228)
1540 expect(ok, it->cnt, 225);
1541 expect(ok, it->first.v, 0);
1542 expect(ok, it->last.v, 224);
1544 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1546 // detect reload line
1547 it->cnt = it->first.hv = it->last.hv = 0;
1550 while (read16(VDP_CTRL_PORT) & 8)
1552 VDP_setReg(10, 255);
1553 while (read8(VDP_HV_COUNTER) != 228)
1556 expect(ok, it->cnt, 1);
1557 expect(ok, it->first.v, 17);
1558 expect(ok, it->last.v, 17);
1560 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1565 static int t_irq_both_cpu_unmask(void)
1567 struct irq_test *ith = (void *)0xfff000;
1568 struct irq_test *itv = ith + 1;
1572 memset_(ith, 0, sizeof(*ith) * 2);
1573 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1574 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1576 while (read8(VDP_HV_COUNTER) != 100)
1578 while (read8(VDP_HV_COUNTER) != 226)
1581 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1582 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP);
1583 /* go to active display line 100 */
1584 while (read8(VDP_HV_COUNTER) != 100)
1586 s0 = read16(VDP_CTRL_PORT);
1587 s1 = move_sr_and_read(0x2000, VDP_CTRL_PORT);
1589 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1590 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1592 expect(ok, itv->cnt, 1); // vint count
1593 expect(ok, itv->first.v, 100); // vint line
1594 expect(ok, ith->cnt, 1); // hint count
1595 expect(ok, ith->first.v, 100); // hint line
1596 expect_bits(ok, s0, SR_F, SR_F);
1597 expect_bits(ok, s1, 0, SR_F);
1601 static int t_irq_ack_v_h(void)
1603 struct irq_test *ith = (void *)0xfff000;
1604 struct irq_test *itv = ith + 1;
1608 memset_(ith, 0, sizeof(*ith) * 2);
1609 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1610 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1612 /* ensure hcnt reload */
1613 while (!(read16(VDP_CTRL_PORT) & 8))
1615 while (read16(VDP_CTRL_PORT) & 8)
1617 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1618 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0);
1619 while (read8(VDP_HV_COUNTER) != 100)
1621 while (read8(VDP_HV_COUNTER) != 226)
1623 s0 = read16(VDP_CTRL_PORT);
1624 s1 = move_sr_and_read(0x2500, VDP_CTRL_PORT);
1626 s2 = move_sr_and_read(0x2000, VDP_CTRL_PORT);
1629 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1630 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1632 expect(ok, itv->cnt, 1); // vint count
1633 expect(ok, itv->first.v, 226); // vint line
1634 expect(ok, ith->cnt, 1); // hint count
1635 expect(ok, ith->first.v, 228); // hint line
1636 expect_bits(ok, s0, SR_F, SR_F);
1637 expect_bits(ok, s1, 0, SR_F);
1638 expect_bits(ok, s2, 0, SR_F);
1642 static int t_irq_ack_v_h_2(void)
1644 struct irq_test *ith = (void *)0xfff000;
1645 struct irq_test *itv = ith + 1;
1649 memset_(ith, 0, sizeof(*ith) * 2);
1650 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1651 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1653 while (read8(VDP_HV_COUNTER) != 100)
1655 while (read8(VDP_HV_COUNTER) != 226)
1657 s0 = read16(VDP_CTRL_PORT);
1659 s1 = read16(VDP_CTRL_PORT);
1660 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1661 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1663 expect(ok, itv->cnt, 2); // vint count
1664 expect(ok, itv->first.v, 226); // vint line
1665 expect(ok, ith->cnt, 1); // hint count
1666 expect(ok, ith->first.v, 227); // hint line
1667 expect_bits(ok, s0, SR_F, SR_F);
1668 expect_bits(ok, s1, 0, SR_F);
1672 static int t_irq_ack_h_v(void)
1674 u16 *ram = (u16 *)0xfff000;
1675 u8 *ram8 = (u8 *)0xfff000;
1679 ram[0] = ram[1] = ram[2] =
1680 ram[4] = ram[5] = ram[6] = 0;
1681 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1682 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1684 while (read8(VDP_HV_COUNTER) != 100)
1686 while (read8(VDP_HV_COUNTER) != 226)
1688 s0 = read16(VDP_CTRL_PORT);
1689 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1692 s1 = read16(VDP_CTRL_PORT);
1693 write_and_read1(VDP_CTRL_PORT, 0x8000 | (VDP_MODE2 << 8)
1694 | VDP_MODE2_MD | VDP_MODE2_IE0, s);
1696 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1697 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1699 expect(ok, ram[0], 1); // hint count
1700 expect(ok, ram8[2], 226); // hint line
1701 expect(ok, ram[4], 1); // vint count
1702 expect(ok, ram8[10], 228); // vint line
1703 expect_bits(ok, s0, SR_F, SR_F);
1704 expect_bits(ok, s1, SR_F, SR_F);
1705 expect_bits(ok, s[0], SR_F, SR_F);
1706 expect_bits(ok, s[1], SR_F, SR_F);
1707 expect_bits(ok, s[2], 0, SR_F);
1708 expect_bits(ok, s[3], 0, SR_F);
1712 static int t_irq_ack_h_v_2(void)
1714 u16 *ram = (u16 *)0xfff000;
1715 u8 *ram8 = (u8 *)0xfff000;
1719 ram[0] = ram[1] = ram[2] =
1720 ram[4] = ram[5] = ram[6] = 0;
1721 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1722 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1724 while (read8(VDP_HV_COUNTER) != 100)
1726 while (read8(VDP_HV_COUNTER) != 226)
1728 s0 = read16(VDP_CTRL_PORT);
1730 s1 = read16(VDP_CTRL_PORT);
1731 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1732 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1734 expect(ok, ram[0], 2); // hint count
1735 expect(ok, ram8[2], 226); // hint first line
1736 expect(ok, ram8[4], 226); // hint last line
1737 expect(ok, ram[4], 0); // vint count
1738 expect(ok, ram8[10], 0); // vint line
1739 expect_bits(ok, s0, SR_F, SR_F);
1740 expect_bits(ok, s1, 0, SR_F);
1744 static void t_irq_f_flag(void)
1746 memcpy_((void *)0xff0140, test_f_vint, test_f_vint_end - test_f_vint);
1747 memset_((void *)0xff0000, 0, 10);
1748 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP);
1750 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1753 static int t_irq_f_flag_h40(void)
1755 u8 f, *r = (u8 *)0xff0000;
1760 expect_bits(ok, r[0], 0, SR_F);
1761 expect_bits(ok, r[1], 0, SR_F);
1762 expect_bits(ok, r[2], 0, SR_F);
1763 // hits 1-3 times in range 3-9, usually ~5
1764 f = r[3] | r[4] | r[5] | r[6] | r[7];
1766 expect_bits(ok, r[10], 0, SR_F);
1767 expect_bits(ok, r[11], 0, SR_F);
1768 expect_bits(ok, f, SR_F, SR_F);
1772 static int t_irq_f_flag_h32(void)
1774 u8 f, *r = (u8 *)0xff0000;
1777 VDP_setReg(VDP_MODE4, 0x00);
1779 VDP_setReg(VDP_MODE4, 0x81);
1781 expect_bits(ok, r[0], 0, SR_F);
1782 expect_bits(ok, r[1], 0, SR_F);
1783 // hits 1-3 times in range 2-7, usually 3
1784 f = r[2] | r[3] | r[4] | r[5] | r[6] | r[7];
1786 expect_bits(ok, r[8], 0, SR_F);
1787 expect_bits(ok, r[9], 0, SR_F);
1788 expect_bits(ok, r[10], 0, SR_F);
1789 expect_bits(ok, r[11], 0, SR_F);
1790 expect_bits(ok, f, SR_F, SR_F);
1796 #define IRQ_CNT_FB_BASE 0x1ff00
1799 static void x32_cmd(enum x32x_cmd cmd, u32 a0, u32 a1, u16 is_slave)
1801 u16 v, *r = (u16 *)0xa15120;
1803 u16 cmd_s = cmd | (is_slave << 15);
1806 write32(&r[4/2], a0);
1807 write32(&r[8/2], a1);
1811 for (i = 0; i < 10000 && (v = read16(r)) == cmd_s; i++)
1814 printf("cmd clr: %x\n", v);
1816 printf("exc m s: %02x %02x\n", r8[0x0e], r8[0x0f]);
1821 printf("cmd err: %x\n", v);
1826 static int t_32x_reset_btn(void)
1828 void (*do_32x_disable)(void) = (void *)0xff0040;
1829 u32 *fbl_icnt = (u32 *)(0x840000 + IRQ_CNT_FB_BASE);
1830 u16 *m_icnt = (u16 *)fbl_icnt;
1831 u16 *s_icnt = m_icnt + 8;
1832 u32 *r32 = (u32 *)0xa15100;
1833 u16 *r16 = (u16 *)r32, i, s;
1838 if (!(read16(r16) & 1))
1841 expect(ok, r16[0x00/2], 0x8083);
1843 write8(r8, 0x00); // FM=0
1845 expect(ok, r16[0x00/2], 0x83);
1846 expect(ok, r16[0x02/2], 0);
1847 expect(ok, r16[0x04/2], 3);
1848 expect(ok, r16[0x06/2], 1); // RV (set in sega_gcc.s reset handler)
1849 expect(ok, r32[0x08/4], 0x5a5a08);
1850 expect(ok, r32[0x0c/4], 0x5a5a0c);
1851 expect(ok, r16[0x10/2], 0x5a10);
1852 expect(ok, r32[0x14/4], 0);
1853 expect(ok, r32[0x18/4], 0);
1854 expect(ok, r32[0x1c/4], 0);
1855 expect(ok, r32[0x20/4], 0x00005a20);
1856 expect(ok, r32[0x24/4], 0x5a5a5a24);
1857 expect(ok, r32[0x28/4], 0x5a5a5a28);
1858 expect(ok, r32[0x2c/4], 0x075a5a2c); // 7 - last_irq_vec
1859 if (!(r16[0x00/2] & 0x8000)) {
1860 expect(ok, r8 [0x81], 1);
1861 expect(ok, r16[0x82/2], 1);
1862 expect(ok, r16[0x84/2], 0xff);
1863 expect(ok, r16[0x86/2], 0xffff);
1864 expect(ok, r16[0x88/2], 0);
1865 expect(ok, r8 [0x8b] & ~2, 0); // FEN toggles periodically?
1866 expect(ok, r16[0x8c/2], 0);
1867 expect(ok, r16[0x8e/2], 0);
1868 // setup vdp for t_32x_init
1870 r16[0x82/2] = r16[0x84/2] = r16[0x86/2] = 0;
1872 r32[0x20/4] = r32[0x24/4] = r32[0x28/4] = r32[0x2c/4] = 0;
1873 for (s = 0; s < 2; s++)
1875 x32_cmd(CMD_READ32, 0x20004000, 0, s); // not cleared by hw
1876 expect_sh2(ok, s, r32[0x24/4], 0x02020000); // ADEN | cmd
1877 // t_32x_sh_defaults will test the other bits
1879 // setup for t_32x_sh_defaults
1880 x32_cmd(CMD_WRITE8, 0x20004001, 0, 0);
1881 x32_cmd(CMD_WRITE8, 0x20004001, 0, 1);
1883 for (i = 0; i < 7; i++) {
1884 expect(ok, m_icnt[i], 0x100);
1885 expect(ok, s_icnt[i], 0x100);
1887 expect(ok, m_icnt[7], 0x101); // VRES happened
1888 expect(ok, s_icnt[7], 0x100); // masked on slave
1890 x32_cmd(CMD_GETSR, 0, 0, 1);
1891 expect_sh2(ok, 1, r32[0x24/4] & ~1, 0xf0); // still masked
1892 x32_cmd(CMD_SETSR, 0x10, 0, 1);
1893 expect(ok, r16[0x00/2], 0x8083);
1894 write8(r8, 0x00); // FM=0
1896 expect(ok, m_icnt[7], 0x101);
1897 expect(ok, s_icnt[7], 0x101);
1898 expect(ok, r32[0x2c/4], 0x00070000); // 7 - last_irq_vec
1901 memcpy_(do_32x_disable, x32x_disable,
1902 x32x_disable_end - x32x_disable);
1905 expect(ok, r16[0x00/2], 0x82);
1906 expect(ok, r16[0x02/2], 0);
1907 expect(ok, r16[0x04/2], 3);
1908 expect(ok, r16[0x06/2], 0); // RV cleared by x32x_disable
1909 expect(ok, r32[0x08/4], 0x5a5a08);
1910 expect(ok, r32[0x0c/4], 0x5a5a0c);
1911 expect(ok, r16[0x10/2], 0x5a10);
1912 expect(ok, rl[0x04/4], 0x000800);
1914 // setup for t_32x_init, t_32x_sh_defaults
1916 r16[0x10/2] = 0x1234; // warm reset indicator
1918 expect(ok, r16[0x06/2], 0); // RV
1922 static int t_32x_init(void)
1924 void (*do_32x_enable)(void) = (void *)0xff0040;
1925 u32 M_OK = MKLONG('M','_','O','K');
1926 u32 S_OK = MKLONG('S','_','O','K');
1927 u32 *r32 = (u32 *)0xa15100;
1928 u16 *r16 = (u16 *)r32;
1932 //v1070 = read32(0x1070);
1934 /* what does REN mean exactly?
1935 * Seems to be sometimes clear after reset */
1936 for (i = 0; i < 1000000; i++)
1937 if (read16(r16) & 0x80)
1939 expect(ok, r16[0x00/2], 0x82);
1940 expect(ok, r16[0x02/2], 0);
1941 expect(ok, r16[0x04/2], 0);
1942 expect(ok, r16[0x06/2], 0);
1943 expect(ok, r8 [0x08], 0);
1944 //expect(ok, r32[0x08/4], 0); // garbage 24bit
1945 expect(ok, r8 [0x0c], 0);
1946 //expect(ok, r32[0x0c/4], 0); // garbage 24bit
1947 if (r16[0x10/2] != 0x1234) // warm reset
1948 expect(ok, r16[0x10/2], 0xffff);
1949 expect(ok, r16[0x12/2], 0);
1950 expect(ok, r32[0x14/4], 0);
1951 expect(ok, r32[0x18/4], 0);
1952 expect(ok, r32[0x1c/4], 0);
1953 //expect(ok, r8 [0x81], 0); // VDP; hangs without ADEN
1954 r32[0x20/4] = 0; // master resp
1955 r32[0x24/4] = 0; // slave resp
1959 // check writable bits without ADEN
1960 // 08,0c have garbage or old values (survive MD's power cycle)
1961 write16(&r16[0x00/2], 0);
1963 expect(ok, r16[0x00/2], 0x80);
1964 write16(&r16[0x00/2], 0xfffe);
1966 expect(ok, r16[0x00/2], 0x8082);
1968 r16[0x02/2] = 0xffff;
1969 r32[0x04/4] = 0xffffffff;
1970 r32[0x08/4] = 0xffffffff;
1971 r32[0x0c/4] = 0xffffffff;
1972 r16[0x10/2] = 0xffff;
1973 r32[0x14/4] = 0xffffffff;
1974 r32[0x18/4] = 0xffffffff;
1975 r32[0x1c/4] = 0xffffffff;
1977 expect(ok, r16[0x00/2], 0x82);
1978 expect(ok, r16[0x02/2], 0x03);
1979 expect(ok, r16[0x04/2], 0x03);
1980 expect(ok, r16[0x06/2], 0x07);
1981 expect(ok, r32[0x08/4], 0x00fffffe);
1982 expect(ok, r32[0x0c/4], 0x00ffffff);
1983 expect(ok, r16[0x10/2], 0xfffc);
1984 expect(ok, r32[0x14/4], 0);
1985 expect(ok, r16[0x18/2], 0);
1986 expect(ok, r16[0x1a/2], 0x0101);
1987 expect(ok, r32[0x1c/4], 0);
1994 // could just set RV, but BIOS reads ROM, so can't
1995 memcpy_(do_32x_enable, x32x_enable,
1996 x32x_enable_end - x32x_enable);
1999 expect(ok, r16[0x00/2], 0x83);
2000 expect(ok, r16[0x02/2], 0);
2001 expect(ok, r16[0x04/2], 0);
2002 expect(ok, r16[0x06/2], 1); // RV
2003 expect(ok, r32[0x14/4], 0);
2004 expect(ok, r32[0x18/4], 0);
2005 expect(ok, r32[0x1c/4], 0);
2006 expect(ok, r32[0x20/4], M_OK);
2007 while (!read16(&r16[0x24/2]))
2009 expect(ok, r32[0x24/4], S_OK);
2010 write32(&r32[0x20/4], 0);
2011 if (!(r16[0x00/2] & 0x8000)) {
2012 expect(ok, r8 [0x81], 0);
2013 expect(ok, r16[0x82/2], 0);
2014 expect(ok, r16[0x84/2], 0);
2015 expect(ok, r16[0x86/2], 0);
2016 //expect(ok, r16[0x88/2], 0); // triggers fill?
2017 expect(ok, r8 [0x8b] & ~2, 0);
2018 expect(ok, r16[0x8c/2], 0);
2019 expect(ok, r16[0x8e/2], 0);
2024 static int t_32x_echo(void)
2026 u16 *r16 = (u16 *)0xa15100;
2029 r16[0x2c/2] = r16[0x2e/2] = 0;
2030 x32_cmd(CMD_ECHO, 0x12340000, 0, 0);
2031 expect_sh2(ok, 0, r16[0x26/2], 0x1234);
2032 x32_cmd(CMD_ECHO, 0x23450000, 0, 1);
2033 expect_sh2(ok, 1, r16[0x26/2], 0xa345);
2034 expect(ok, r16[0x2c/2], 0); // no last_irq_vec
2035 expect(ok, r16[0x2e/2], 0); // no exception_index
2039 static int t_32x_sh_defaults(void)
2041 u32 *r32 = (u32 *)0xa15120;
2044 for (s = 0; s < 2; s++)
2046 x32_cmd(CMD_READ32, 0x20004000, 0, s);
2047 expect_sh2(ok, s, r32[0x04/4], 0x02000000); // ADEN
2048 x32_cmd(CMD_READ32, 0x20004004, 0, s);
2049 expect_sh2(ok, s, r32[0x04/4], 0x00004001); // Empty Rv
2050 x32_cmd(CMD_READ32, 0x20004008, 0, s);
2051 expect_sh2(ok, s, r32[0x04/4], 0);
2052 x32_cmd(CMD_READ32, 0x2000400c, 0, s);
2053 expect_sh2(ok, s, r32[0x04/4], 0);
2054 x32_cmd(CMD_GETGBR, 0, 0, s);
2055 expect_sh2(ok, s, r32[0x04/4], 0x20004000);
2060 static int t_32x_md_bios(void)
2062 void (*do_call_c0)(int a, int d) = (void *)0xff0040;
2063 u8 *rmb = (u8 *)0xff0000;
2067 memcpy_(do_call_c0, test_32x_b_c0,
2068 test_32x_b_c0_end - test_32x_b_c0);
2070 do_call_c0(0xff0000, 0x5a);
2072 expect(ok, rmb[0], 0x5a);
2073 expect(ok, rl[0x04/4], 0x880200);
2074 expect(ok, rl[0x10/4], 0x880212);
2075 expect(ok, rl[0x94/4], 0x8802d8);
2079 static int t_32x_md_rom(void)
2084 expect(ok, rl[0x004/4], 0x880200);
2085 expect(ok, rl[0x100/4], 0x53454741);
2086 expect(ok, rl[0x70/4], 0);
2087 write32(&rl[0x70/4], 0xa5123456);
2088 write32(&rl[0x78/4], ~0);
2090 expect(ok, rl[0x78/4], 0x8802ae);
2091 expect(ok, rl[0x70/4], 0xa5123456);
2092 //expect(ok, rl[0x1070/4], v1070);
2093 write32(&rl[0x70/4], 0);
2094 // with RV 0x880000/0x900000 hangs, can't test
2098 static int t_32x_md_fb(void)
2100 u8 *fbb = (u8 *)0x840000;
2101 u16 *fbw = (u16 *)fbb;
2102 u32 *fbl = (u32 *)fbb;
2103 u8 *fob = (u8 *)0x860000;
2104 u16 *fow = (u16 *)fob;
2105 u32 *fol = (u32 *)fob;
2108 fbl[0] = 0x12345678;
2109 fol[1] = 0x89abcdef;
2111 expect(ok, fbw[1], 0x5678);
2112 expect(ok, fow[2], 0x89ab);
2121 expect(ok, fol[0], 0x12340000);
2122 expect(ok, fbl[1], 0x89ab0201);
2126 static int t_32x_sh_fb(void)
2128 u32 *fbl = (u32 *)0x840000;
2129 u8 *r8 = (u8 *)0xa15100;
2132 if (read8(r8) & 0x80)
2133 write8(r8, 0x00); // FM=0
2134 fbl[0] = 0x12345678;
2135 fbl[1] = 0x89abcdef;
2137 write8(r8, 0x80); // FM=1
2138 x32_cmd(CMD_WRITE8, 0x24000000, 0, 0); // should ignore
2139 x32_cmd(CMD_WRITE8, 0x24020001, 0, 0); // ignore
2140 x32_cmd(CMD_WRITE16, 0x24000002, 0, 0); // ok
2141 x32_cmd(CMD_WRITE16, 0x24020000, 0, 0); // ignore
2142 x32_cmd(CMD_WRITE32, 0x24020004, 0x5a0000a5, 1);
2143 write8(r8, 0x00); // FM=0
2145 expect(ok, fbl[0], 0x12340000);
2146 expect(ok, fbl[1], 0x5aabcda5);
2150 static int t_32x_irq(void)
2152 u32 *fbl_icnt = (u32 *)(0x840000 + IRQ_CNT_FB_BASE);
2153 u16 *m_icnt = (u16 *)fbl_icnt;
2154 u16 *s_icnt = m_icnt + 8;
2155 u32 *r = (u32 *)0xa15100;
2156 u16 *r16 = (u16 *)r;
2160 write8(r, 0x00); // FM=0
2163 for (i = 0; i < 8; i++)
2164 write32(&fbl_icnt[i], 0);
2166 write16(&r16[0x02/2], 0xfffd); // INTM+unused_bits
2168 expect(ok, r16[0x02/2], 1);
2169 x32_cmd(CMD_WRITE8, 0x20004001, 2, 0); // unmask cmd
2170 x32_cmd(CMD_WRITE8, 0x20004001, 2, 1); // unmask cmd slave
2172 write8(r, 0x00); // FM=0 (hangs without)
2174 expect(ok, r16[0x02/2], 0);
2175 expect(ok, r8 [0x2c], 4);
2176 expect(ok, r8 [0x2d], 0);
2177 expect(ok, r16[0x2e/2], 0); // no exception_index
2178 expect(ok, m_icnt[4], 1);
2179 expect(ok, s_icnt[4], 0);
2180 write16(&r16[0x02/2], 0xaaaa); // INTS+unused_bits
2182 expect(ok, r16[0x02/2], 2);
2185 expect(ok, r16[0x02/2], 0);
2186 expect(ok, r8 [0x2c], 4);
2187 expect(ok, r8 [0x2d], 4);
2188 expect(ok, r16[0x2e/2], 0); // no exception_index
2189 write8(r, 0x00); // FM=0
2191 expect(ok, m_icnt[4], 1);
2192 expect(ok, s_icnt[4], 1);
2193 for (i = 0; i < 8; i++) {
2196 expect(ok, m_icnt[i], 0);
2197 expect(ok, s_icnt[i], 0);
2202 static int t_32x_reg_w(void)
2204 u32 *r32 = (u32 *)0xa15100;
2205 u16 *r16 = (u16 *)r32, old;
2212 expect(ok, r32[0x08/4], 0xfffffe);
2213 expect(ok, r32[0x0c/4], 0xffffff);
2214 expect(ok, r16[0x10/2], 0xfffc);
2216 r32[0x08/4] = r32[0x0c/4] = 0;
2219 x32_cmd(CMD_WRITE16, 0x20004006, ~old, 0);
2220 expect(ok, r16[0x06/2], old);
2224 // prepare for reset btn press tests
2225 static int t_32x_reset_prep(void)
2227 u32 *fbl = (u32 *)0x840000;
2228 u32 *fbl_icnt = fbl + IRQ_CNT_FB_BASE / 4;
2229 u32 *r32 = (u32 *)0xa15100;
2230 u16 *r16 = (u16 *)r32;
2234 expect(ok, r16[0x00/2], 0x83);
2235 write8(r8, 0x00); // FM=0
2238 expect(ok, r8[0x8b] & ~2, 0);
2239 for (i = 0; i < 8; i++)
2240 write32(&fbl_icnt[i], 0x01000100);
2241 x32_cmd(CMD_WRITE8, 0x20004001, 0x02, 0); // unmask cmd
2242 x32_cmd(CMD_WRITE8, 0x20004001, 0x02, 1); // unmask slave
2243 x32_cmd(CMD_SETSR, 0xf0, 0, 1); // mask slave irqs (on the cpu)
2245 write8(r8, 0x00); // FM=0
2246 expect(ok, r32[0x2c/4], 0);
2248 for (i = 0; i < 8; i++)
2249 expect(ok, fbl_icnt[i], 0x01000100);
2251 r16[0x04/2] = 0xffff;
2252 r32[0x08/4] = 0x5a5a5a08;
2253 r32[0x0c/4] = 0x5a5a5a0c;
2254 r16[0x10/2] = 0x5a10;
2255 r32[0x20/4] = 0x00005a20; // no x32_cmd
2256 r32[0x24/4] = 0x5a5a5a24;
2257 r32[0x28/4] = 0x5a5a5a28;
2258 r32[0x2c/4] = 0x5a5a5a2c;
2259 if (!(r16[0x00/2] & 0x8000)) {
2261 r16[0x8a/2] = 0x0001;
2263 for (i = 0; i < 220/2; i++)
2264 write32(&fbl[i], 0);
2266 r16[0x82/2] = 0xffff;
2267 r16[0x84/2] = 0xffff;
2268 r16[0x86/2] = 0xffff;
2269 r16[0x8a/2] = 0x0000;
2270 r16[0x8c/2] = 0xffff;
2271 r16[0x8e/2] = 0xffff;
2282 static const struct {
2287 // this must be first to disable the 32x and restore the 68k vector table
2288 { T_32, t_32x_reset_btn, "32x resetbtn" },
2290 { T_MD, t_dma_zero_wrap, "dma zero len + wrap" },
2291 { T_MD, t_dma_zero_fill, "dma zero len + fill" },
2292 { T_MD, t_dma_ram_wrap, "dma ram wrap" },
2293 { T_MD, t_dma_multi, "dma multi" },
2294 { T_MD, t_dma_cram_wrap, "dma cram wrap" },
2295 { T_MD, t_dma_vsram_wrap, "dma vsram wrap" },
2296 { T_MD, t_dma_and_data, "dma and data" },
2297 { T_MD, t_dma_short_cmd, "dma short cmd" },
2298 { T_MD, t_dma_fill3_odd, "dma fill3 odd" },
2299 { T_MD, t_dma_fill3_even, "dma fill3 even" },
2300 { T_MD, t_dma_fill3_vsram, "dma fill3 vsram" },
2301 { T_MD, t_dma_fill_dis, "dma fill disabled" },
2302 { T_MD, t_dma_fill_src, "dma fill src incr" },
2303 { T_MD, t_dma_busy_vram, "dma no busy" },
2304 { T_MD, t_dma_128k, "dma 128k mode" },
2305 { T_MD, t_vdp_128k_b16, "vdp 128k addr bit16" },
2306 // { t_vdp_128k_b16_inc, "vdp 128k bit16 inc" }, // mystery
2307 { T_MD, t_vdp_reg_cmd, "vdp reg w cmd reset" },
2308 { T_MD, t_vdp_sr_vb, "vdp status reg vb" },
2309 { T_MD, t_z80mem_long_mirror, "z80 ram long mirror" },
2310 { T_MD, t_z80mem_noreq_w, "z80 ram noreq write" },
2311 { T_MD, t_z80mem_vdp_r, "z80 vdp read" },
2312 // { t_z80mem_vdp_w, "z80 vdp write" }, // hang
2313 { T_MD, t_tim_loop, "time loop" },
2314 { T_MD, t_tim_z80_loop, "time z80 loop" },
2315 { T_MD, t_tim_z80_ram, "time z80 ram" },
2316 { T_MD, t_tim_z80_ym, "time z80 ym2612" },
2317 { T_MD, t_tim_z80_vdp, "time z80 vdp" },
2318 { T_MD, t_tim_z80_bank_rom, "time z80 bank rom" },
2319 { T_MD, t_tim_vcnt, "time V counter" },
2320 { T_MD, t_tim_vcnt_loops, "time vcnt loops" },
2321 { T_MD, t_tim_hblank_h40, "time hblank h40" },
2322 { T_MD, t_tim_hblank_h32, "time hblank h32" },
2323 { T_MD, t_tim_vdp_as_vram_w, "time vdp vram w" },
2324 { T_MD, t_tim_vdp_as_cram_w, "time vdp cram w" },
2325 { T_MD, t_tim_ym_timera_z80, "time timer a z80" },
2326 { T_MD, t_tim_ym_timerb_z80, "time timer b z80" },
2327 { T_MD, t_tim_ym_timerb_stop, "timer b stop" },
2328 { T_MD, t_tim_ym_timer_ab_sync,"timer ab sync" },
2329 { T_MD, t_irq_hint, "irq4 / line" },
2330 { T_MD, t_irq_both_cpu_unmask, "irq both umask" },
2331 { T_MD, t_irq_ack_v_h, "irq ack v-h" },
2332 { T_MD, t_irq_ack_v_h_2, "irq ack v-h 2" },
2333 { T_MD, t_irq_ack_h_v, "irq ack h-v" },
2334 { T_MD, t_irq_ack_h_v_2, "irq ack h-v 2" },
2335 { T_MD, t_irq_f_flag_h40, "irq f flag h40" },
2336 { T_MD, t_irq_f_flag_h32, "irq f flag h32" },
2338 // the first one enables 32X, so must be kept
2339 // all tests assume RV=1 FM=0
2340 { T_32, t_32x_init, "32x init" },
2341 { T_32, t_32x_echo, "32x echo" },
2342 { T_32, t_32x_sh_defaults, "32x sh def" },
2343 { T_32, t_32x_md_bios, "32x md bios" },
2344 { T_32, t_32x_md_rom, "32x md rom" },
2345 { T_32, t_32x_md_fb, "32x md fb" },
2346 { T_32, t_32x_sh_fb, "32x sh fb" },
2347 { T_32, t_32x_irq, "32x irq" },
2348 { T_32, t_32x_reg_w, "32x reg w" },
2349 { T_32, t_32x_reset_prep, "32x rstprep" }, // must be last 32x
2352 static void setup_z80(void)
2354 u8 *zram = (u8 *)0xa00000;
2358 write16(0xa11100, 0x100);
2359 write16(0xa11200, 0x100);
2361 while (read16(0xa11100) & 0x100)
2364 // load the default test program, clear it's data
2365 len = z80_test_end - z80_test;
2366 for (i = 0; i < len; i++)
2367 write8(&zram[i], z80_test[i]);
2368 for (i = 0x1000; i < 0x1007; i++)
2369 write8(&zram[i], 0);
2372 write16(0xa11200, 0x000);
2373 write16(0xa11100, 0x000);
2375 write16(0xa11200, 0x100);
2377 burn10(50 * 15 / 7 / 10); // see z80_test.s80
2379 // take back the bus
2380 write16(0xa11100, 0x100);
2381 while (read16(0xa11100) & 0x100)
2385 static unused int hexinc(char *c)
2399 void (*px32x_switch_rv)(short rv);
2400 short (*pget_input)(void) = get_input;
2412 write8(0xa10009, 0x40);
2415 while (read16(VDP_CTRL_PORT) & 2)
2418 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
2419 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA);
2420 VDP_setReg(VDP_MODE3, 0x00);
2421 VDP_setReg(VDP_MODE4, 0x81);
2422 VDP_setReg(VDP_NT_SCROLLA, APLANE >> 10);
2423 VDP_setReg(VDP_NT_SCROLLB, BPLANE >> 13);
2424 VDP_setReg(VDP_SAT_BASE, SLIST >> 9);
2425 VDP_setReg(VDP_HSCROLL, HSCRL >> 10);
2426 VDP_setReg(VDP_AUTOINC, 2);
2427 VDP_setReg(VDP_SCROLLSZ, 0x01);
2428 VDP_setReg(VDP_BACKDROP, 0);
2431 t_dma_zero_wrap_early();
2432 t_dma_zero_fill_early();
2435 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
2436 for (i = 0; i < 32 / 4; i++)
2437 write32(VDP_DATA_PORT, 0);
2439 /* clear name tables */
2440 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(APLANE));
2441 for (i = 0; i < PLANE_W * PLANE_H / 2; i++)
2442 write32(VDP_DATA_PORT, 0);
2444 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(BPLANE));
2445 for (i = 0; i < PLANE_W * PLANE_H / 2; i++)
2446 write32(VDP_DATA_PORT, 0);
2448 /* SAT, h. scroll */
2449 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(SLIST));
2450 write32(VDP_DATA_PORT, 0);
2452 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(HSCRL));
2453 write32(VDP_DATA_PORT, 0);
2455 /* scroll plane vscroll */
2456 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
2457 write32(VDP_DATA_PORT, 0);
2461 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(TILE_FONT_BASE));
2462 for (i = 0; i < FONT_LEN * 32 / 4; i++)
2463 write32(VDP_DATA_PORT, font_base[i]);
2466 setup_default_palette();
2468 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
2470 have_32x = read32(0xa130ec) == MKLONG('M','A','R','S');
2471 en_32x = have_32x && (read16(0xa15100) & 1);
2472 v8 = read8(0xa10001);
2473 printf("MD version: %02x %s %s %s%s\n", v8,
2474 (v8 & 0x80) ? "world" : "jap",
2475 (v8 & 0x40) ? "pal" : "ntsc",
2476 have_32x ? "32X" : "",
2478 printf("reset hvc %04x->%04x\n", read16(-4), read16(-2));
2481 extern u32 sh2_test[];
2482 if (sh2_test[0] != read32(0x3e0) || sh2_test[0x200/4] != read32(0x3e4))
2483 printf("bad 0x3c0 tab\n");
2485 for (i = 0; i < ARRAY_SIZE(g_tests); i++) {
2486 // print test number if we haven't scrolled away
2487 if (printf_ypos < CSCREEN_H) {
2488 int old_ypos = printf_ypos;
2490 printf("%02d/%02d", i, ARRAY_SIZE(g_tests));
2491 printf_ypos = old_ypos;
2494 if ((g_tests[i].type & T_32) && !have_32x) {
2498 ret = g_tests[i].test();
2499 if (ret == R_SKIP) {
2505 printf("failed %d: %s\n", i, g_tests[i].name);
2513 printf("%d/%d passed, %d skipped.\n",
2514 passed, ARRAY_SIZE(g_tests), skipped);
2519 if (have_32x && (read16(0xa15100) & 1)) {
2520 u8 *p = (u8 *)0xff0040;
2521 u32 len = x32x_switch_rv_end - x32x_switch_rv;
2522 px32x_switch_rv = (void *)p; p += len;
2523 memcpy_(px32x_switch_rv, x32x_switch_rv, len);
2525 len = get_input_end - get_input_s;
2526 pget_input = (void *)p; p += len;
2527 memcpy_(pget_input, get_input_s, len);
2529 // prepare for reset - run from 880xxx as the reset vector points there
2530 // todo: broken printf
2533 for (i = 0; i < 60*60 && !(pget_input() & BTNM_A); i++) {
2534 while (read16(VDP_CTRL_PORT) & SR_VB)
2535 write16(-4, read16(VDP_HV_COUNTER)); /* blanking */
2536 while (!(read16(VDP_CTRL_PORT) & SR_VB))
2537 write16(-4, read16(VDP_HV_COUNTER)); /* not blanking */;
2540 // blank due to my lame tv being burn-in prone
2541 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
2543 while (!(pget_input() & BTNM_A))
2544 write16(-4, read16(VDP_HV_COUNTER));
2545 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
2549 char c[3] = { '0', '0', '0' };
2550 short hscroll = 0, vscroll = 0;
2551 short hsz = 1, vsz = 0;
2554 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(APLANE));
2557 for (i = 0, c[0] = 'a'; i < 8 * 1024 / 2; i++) {
2558 write16(VDP_DATA_PORT, (u16)c[0] - 32 + TILE_FONT_BASE / 32);
2560 if (c[0] == 'z' + 1)
2564 for (i = 0; i < 8 * 1024 / 2 / 4; i++) {
2565 write16(VDP_DATA_PORT, (u16)'.' - 32 + TILE_FONT_BASE / 32);
2566 write16(VDP_DATA_PORT, (u16)c[2] - 32 + TILE_FONT_BASE / 32);
2567 write16(VDP_DATA_PORT, (u16)c[1] - 32 + TILE_FONT_BASE / 32);
2568 write16(VDP_DATA_PORT, (u16)c[0] - 32 + TILE_FONT_BASE / 32);
2574 while (pget_input() & BTNM_A)
2579 int b = pget_input();
2582 hscroll = 1, vscroll = -1;
2585 } while (pget_input() & BTNM_C);
2588 if (b & (BTNM_L | BTNM_R | BTNM_C)) {
2589 hscroll += (b & BTNM_L) ? 1 : -1;
2590 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(HSCRL));
2591 write16(VDP_DATA_PORT, hscroll);
2593 if (b & (BTNM_U | BTNM_D | BTNM_C)) {
2594 vscroll += (b & BTNM_U) ? -1 : 1;
2595 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
2597 int end = (int)vscroll + 21;
2598 for (i = vscroll; i < end; i++)
2599 write32(VDP_DATA_PORT, i << 17);
2600 VDP_setReg(VDP_MODE3, 0x04);
2603 write16(VDP_DATA_PORT, vscroll);
2604 VDP_setReg(VDP_MODE3, 0x00);
2608 hsz = (hsz + 1) & 3;
2611 } while (pget_input() & BTNM_A);
2614 vsz = (vsz + 1) & 3;
2617 } while (pget_input() & BTNM_B);
2619 VDP_setReg(VDP_SCROLLSZ, (vsz << 4) | hsz);
2624 printf(" %d %d ", hsz, vsz);
2636 // vim:ts=4:sw=4:expandtab