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testpico: show that vres clear is separate
[megadrive.git] / testpico / main.c
CommitLineData
ffd4b35c 1/*
2 * This software is released into the public domain.
3 * See UNLICENSE file in top level directory.
4 */
5#include <stdlib.h>
6#include <stdarg.h>
9d39a80e 7#include "common.h"
ffd4b35c 8#include "asmtools.h"
5073ab5a 9//#pragma GCC diagnostic ignored "-Wunused-function"
ffd4b35c 10
11#define VDP_DATA_PORT 0xC00000
12#define VDP_CTRL_PORT 0xC00004
a385208c 13#define VDP_HV_COUNTER 0xC00008
ffd4b35c 14
15#define TILE_MEM_END 0xB000
16
17#define FONT_LEN 128
a385208c 18#define TILE_FONT_BASE (TILE_MEM_END - FONT_LEN * 32)
ffd4b35c 19
20/* note: using ED menu's layout here.. */
21#define WPLANE (TILE_MEM_END + 0x0000)
22#define HSCRL (TILE_MEM_END + 0x0800)
23#define SLIST (TILE_MEM_END + 0x0C00)
24#define APLANE (TILE_MEM_END + 0x1000)
25#define BPLANE (TILE_MEM_END + 0x3000)
26
ffd4b35c 27#define write16_z80le(a, d) \
28 ((volatile u8 *)(a))[0] = (u8)(d), \
29 ((volatile u8 *)(a))[1] = ((d) >> 8)
30
31static inline u16 read16_z80le(const void *a_)
32{
33 volatile const u8 *a = (volatile const u8 *)a_;
34 return a[0] | ((u16)a[1] << 8);
35}
36
37#define CTL_WRITE_VRAM(adr) \
38 (((0x4000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
39#define CTL_WRITE_VSRAM(adr) \
40 (((0x4000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x10)
41#define CTL_WRITE_CRAM(adr) \
42 (((0xC000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
43#define CTL_READ_VRAM(adr) \
44 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
45#define CTL_READ_VSRAM(adr) \
46 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x10)
47#define CTL_READ_CRAM(adr) \
48 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x20)
49
50#define CTL_WRITE_DMA 0x80
51
52#define VDP_setReg(r, v) \
53 write16(VDP_CTRL_PORT, 0x8000 | ((r) << 8) | ((v) & 0xff))
54
55enum {
56 VDP_MODE1 = 0x00,
57 VDP_MODE2 = 0x01,
58 VDP_NT_SCROLLA = 0x02,
59 VDP_NT_WIN = 0x03,
60 VDP_NT_SCROLLB = 0x04,
61 VDP_SAT_BASE = 0x05,
62 VDP_BACKDROP = 0x07,
63 VDP_MODE3 = 0x0b,
64 VDP_MODE4 = 0x0c,
65 VDP_HSCROLL = 0x0d,
66 VDP_AUTOINC = 0x0f,
67 VDP_SCROLLSZ = 0x10,
68 VDP_DMA_LEN0 = 0x13,
69 VDP_DMA_LEN1 = 0x14,
70 VDP_DMA_SRC0 = 0x15,
71 VDP_DMA_SRC1 = 0x16,
72 VDP_DMA_SRC2 = 0x17,
73};
74
75#define VDP_MODE1_PS 0x04
76#define VDP_MODE1_IE1 0x10 // h int
77#define VDP_MODE2_MD 0x04
78#define VDP_MODE2_PAL 0x08 // 30 col
79#define VDP_MODE2_DMA 0x10
80#define VDP_MODE2_IE0 0x20 // v int
81#define VDP_MODE2_DISP 0x40
a385208c 82#define VDP_MODE2_128K 0x80
83
84#define SR_PAL (1 << 0)
85#define SR_DMA (1 << 1)
86#define SR_HB (1 << 2)
87#define SR_VB (1 << 3)
88#define SR_ODD (1 << 4)
89#define SR_C (1 << 5)
90#define SR_SOVR (1 << 6)
91#define SR_F (1 << 7)
92#define SR_FULL (1 << 8)
93#define SR_EMPT (1 << 9)
ffd4b35c 94
95/* cell counts */
96#define LEFT_BORDER 1 /* lame TV */
97#define PLANE_W 64
98#define PLANE_H 32
99#define CSCREEN_H 28
100
101/* data.s */
102extern const u32 font_base[];
103extern const u8 z80_test[];
104extern const u8 z80_test_end[];
105
106static int text_pal;
107
108static noinline void VDP_drawTextML(const char *str, u16 plane_base,
109 u16 x, u16 y)
110{
111 const u8 *src = (const u8 *)str;
112 u16 basetile = text_pal << 13;
113 int max_len = 40 - LEFT_BORDER;
114 int len;
115 u32 addr;
116
117 x += LEFT_BORDER;
118
119 for (len = 0; str[len] && len < max_len; len++)
120 ;
121 if (len > (PLANE_W - x))
122 len = PLANE_W - x;
123
124 addr = plane_base + ((x + (PLANE_W * y)) << 1);
125 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr));
126
127 while (len-- > 0) {
128 write16(VDP_DATA_PORT,
129 basetile | ((*src++) - 32 + TILE_FONT_BASE / 32));
130 }
131}
132
133static int printf_ypos;
134
135static void printf_line(int x, const char *buf)
136{
137 u32 addr;
138 int i;
139
140 VDP_drawTextML(buf, APLANE, x, printf_ypos++ & (PLANE_H - 1));
141
142 if (printf_ypos >= CSCREEN_H) {
143 /* clear next line */
144 addr = APLANE;
145 addr += (PLANE_W * (printf_ypos & (PLANE_H - 1))) << 1;
146 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr));
147 for (i = 0; i < 40 / 2; i++)
148 write32(VDP_DATA_PORT, 0);
149
150 /* scroll plane */
151 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
152 write16(VDP_DATA_PORT, (printf_ypos - CSCREEN_H + 1) * 8);
153 }
154}
155
156#define PRINTF_LEN 40
157
158static int printf_xpos;
159
160static noinline int printf(const char *fmt, ...)
161{
162 static const char hexchars[] = "0123456789abcdef";
163 char c, buf[PRINTF_LEN + 11 + 1];
164 const char *s;
165 va_list ap;
166 int ival;
167 u32 uval;
168 int d = 0;
169 int i, j;
170
171 va_start(ap, fmt);
172 for (d = 0; *fmt; ) {
173 int prefix0 = 0;
174 int fwidth = 0;
175
176 c = *fmt++;
177 if (d < PRINTF_LEN)
178 buf[d] = c;
179
180 if (c != '%') {
181 if (c == '\n') {
182 buf[d] = 0;
183 printf_line(printf_xpos, buf);
184 d = 0;
185 printf_xpos = 0;
186 continue;
187 }
188 d++;
189 continue;
190 }
191 if (d >= PRINTF_LEN)
192 continue;
193
194 if (*fmt == '0') {
195 prefix0 = 1;
196 fmt++;
197 }
198
199 while ('1' <= *fmt && *fmt <= '9') {
200 fwidth = fwidth * 10 + *fmt - '0';
201 fmt++;
202 }
203
204 switch (*fmt++) {
205 case '%':
206 d++;
207 break;
208 case 'd':
209 case 'i':
210 ival = va_arg(ap, int);
211 if (ival < 0) {
212 buf[d++] = '-';
213 ival = -ival;
214 }
215 for (i = 1000000000; i >= 10; i /= 10)
216 if (ival >= i)
217 break;
218 for (; i >= 10; i /= 10) {
219 buf[d++] = '0' + ival / i;
220 ival %= i;
221 }
222 buf[d++] = '0' + ival;
223 break;
224 case 'x':
225 uval = va_arg(ap, int);
226 while (fwidth > 1 && uval < (1 << (fwidth - 1) * 4)) {
227 buf[d++] = prefix0 ? '0' : ' ';
228 fwidth--;
229 }
230 for (j = 1; j < 8 && uval >= (1 << j * 4); j++)
231 ;
232 for (j--; j >= 0; j--)
233 buf[d++] = hexchars[(uval >> j * 4) & 0x0f];
234 break;
5073ab5a 235 case 'c':
236 buf[d++] = va_arg(ap, int);
237 break;
ffd4b35c 238 case 's':
239 s = va_arg(ap, char *);
240 while (*s && d < PRINTF_LEN)
241 buf[d++] = *s++;
242 break;
243 default:
244 // don't handle, for now
245 d++;
246 va_arg(ap, void *);
247 break;
248 }
249 }
250 buf[d] = 0;
251 va_end(ap);
252
253 if (d != 0) {
254 // line without \n
255 VDP_drawTextML(buf, APLANE, printf_xpos,
256 printf_ypos & (PLANE_H - 1));
257 printf_xpos += d;
258 }
259
260 return d; // wrong..
261}
262
263static const char *exc_names[] = {
264 NULL,
265 NULL,
266 "Bus Error",
267 "Address Error",
268 "Illegal Instruction",
269 "Zero Divide",
270 "CHK Instruction",
271 "TRAPV Instruction",
272 "Privilege Violation", /* 8 8 */
273 "Trace",
274 "Line 1010 Emulator",
275 "Line 1111 Emulator",
276 NULL,
277 NULL,
278 NULL,
279 "Uninitialized Interrupt",
280 NULL, /* 10 16 */
281 NULL,
282 NULL,
283 NULL,
284 NULL,
285 NULL,
286 NULL,
287 NULL,
288 "Spurious Interrupt", /* 18 24 */
289 "l1 irq",
290 "l2 irq",
291 "l3 irq",
292 "l4 irq",
293 "l5 irq",
294 "l6 irq",
295 "l7 irq",
296};
297
298struct exc_frame {
299 u32 dr[8];
300 u32 ar[8];
301 u16 ecxnum; // from handler
302 union {
303 struct {
304 u16 sr;
305 u32 pc;
306 } g _packed;
307 struct {
308 u16 fc;
309 u32 addr;
310 u16 ir;
311 u16 sr;
312 u32 pc;
313 } bae _packed; // bus/address error frame
314 };
315} _packed;
316
ffd4b35c 317void exception(const struct exc_frame *f)
318{
234c4556 319 u32 *sp, sp_add;
ffd4b35c 320 int i;
321
322 while (read16(VDP_CTRL_PORT) & 2)
323 ;
324 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
325 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DISP);
326 /* adjust scroll */
327 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
328 write16(VDP_DATA_PORT,
329 printf_ypos >= CSCREEN_H ?
330 (printf_ypos - CSCREEN_H + 1) * 8 : 0);
331
332 printf("exception %i ", f->ecxnum);
333 if (f->ecxnum < ARRAY_SIZE(exc_names) && exc_names[f->ecxnum] != NULL)
334 printf("(%s)", exc_names[f->ecxnum]);
335 if (f->ecxnum < 4)
336 printf(" (%s)", (f->bae.fc & 0x10) ? "r" : "w");
337 printf(" \n");
338
339 if (f->ecxnum < 4) {
234c4556 340 printf(" PC: %08x SR: %04x \n", f->bae.pc, f->bae.sr);
ffd4b35c 341 printf("addr: %08x IR: %04x FC: %02x \n",
342 f->bae.addr, f->bae.ir, f->bae.fc);
234c4556 343 sp_add = 14;
ffd4b35c 344 }
345 else {
234c4556 346 printf(" PC: %08x SR: %04x \n", f->g.pc, f->g.sr);
347 sp_add = 6;
ffd4b35c 348 }
7449b889 349 sp = (u32 *)(f->ar[7] + sp_add);
350 for (i = 0; i < 7; i++)
ffd4b35c 351 printf(" D%d: %08x A%d: %08x \n", i, f->dr[i], i, f->ar[i]);
7449b889 352 printf(" D%d: %08x SP: %08x \n", i, f->dr[i], (u32)sp);
234c4556 353 printf(" \n");
234c4556 354 printf(" %08x %08x %08x %08x\n", sp[0], sp[1], sp[2], sp[3]);
355 printf(" %08x %08x %08x %08x\n", sp[4], sp[5], sp[6], sp[7]);
ffd4b35c 356}
357
358// ---
359
360static void setup_default_palette(void)
361{
362 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
363 write32(VDP_DATA_PORT, 0);
364 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(15 * 2)); // font normal
365 write16(VDP_DATA_PORT, 0xeee);
366 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(31 * 2)); // green
367 write16(VDP_DATA_PORT, 0x0e0);
368 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(47 * 2)); // red
369 write16(VDP_DATA_PORT, 0x00e);
370}
371
372static void do_setup_dma(const void *src_, u16 words)
373{
374 u32 src = (u32)src_;
375 // VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA);
376 VDP_setReg(VDP_DMA_LEN0, words);
377 VDP_setReg(VDP_DMA_LEN1, words >> 8);
378 VDP_setReg(VDP_DMA_SRC0, src >> 1);
379 VDP_setReg(VDP_DMA_SRC1, src >> 9);
380 VDP_setReg(VDP_DMA_SRC2, src >> 17);
381 // write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr) | CTL_WRITE_DMA);
382}
383
a385208c 384static void vdp_wait_for_fifo_empty(void)
385{
386 while (!(read16(VDP_CTRL_PORT) & 0x200))
387 /* fifo not empty */;
388}
389
390static void vdp_wait_for_dma_idle(void)
391{
392 while (read16(VDP_CTRL_PORT) & 2)
393 /* dma busy */;
394}
395
396static void vdp_wait_for_line_0(void)
397{
398 // in PAL vcounter reports 0 twice in a frame,
399 // so wait for vblank to clear first
400 while (!(read16(VDP_CTRL_PORT) & 8))
401 /* not blanking */;
402 while (read16(VDP_CTRL_PORT) & 8)
403 /* blanking */;
404 while (read8(VDP_HV_COUNTER) != 0)
405 ;
406}
407
7449b889 408static void wait_next_vsync(void)
409{
410 while (read16(VDP_CTRL_PORT) & SR_VB)
411 /* blanking */;
412 while (!(read16(VDP_CTRL_PORT) & SR_VB))
413 /* not blanking */;
414}
415
ffd4b35c 416static void t_dma_zero_wrap_early(void)
417{
418 const u32 *src = (const u32 *)0x3c0000;
419 u32 *ram = (u32 *)0xff0000;
420
421 do_setup_dma(src + 4, 2);
422 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) | CTL_WRITE_DMA);
423 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) | CTL_WRITE_DMA);
424
425 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
426 ram[0] = read32(VDP_DATA_PORT);
427 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfffc));
428 ram[1] = read32(VDP_DATA_PORT);
429}
430
431static void t_dma_zero_fill_early(void)
432{
433 u32 *ram = (u32 *)0xff0000;
434
435 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
436 write32(VDP_DATA_PORT, 0);
437 write32(VDP_DATA_PORT, 0);
438 write32(VDP_DATA_PORT, 0);
439 write32(VDP_DATA_PORT, 0);
440
441 VDP_setReg(VDP_AUTOINC, 1);
442 VDP_setReg(VDP_DMA_SRC2, 0x80);
443 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(1) | CTL_WRITE_DMA);
444 write16(VDP_DATA_PORT, 0x1122);
445 ram[2] = read16(VDP_CTRL_PORT);
a385208c 446 vdp_wait_for_dma_idle();
ffd4b35c 447
448 VDP_setReg(VDP_AUTOINC, 2);
449 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
450 ram[3] = read32(VDP_DATA_PORT);
451}
452
5073ab5a 453#define R_SKIP 0x5a5a
454
ffd4b35c 455#define expect(ok_, v0_, v1_) \
e71680d5 456do { if ((v0_) != (v1_)) { \
ffd4b35c 457 printf("%s: %08x %08x\n", #v0_, v0_, v1_); \
458 ok_ = 0; \
e71680d5 459}} while (0)
ffd4b35c 460
5073ab5a 461#define expect_sh2(ok_, sh2_, v0_, v1_) \
462do { if ((v0_) != (v1_)) { \
463 printf("%csh2: %08x %08x\n", sh2_ ? 's' : 'm', v0_, v1_); \
464 ok_ = 0; \
465}} while (0)
466
a385208c 467#define expect_range(ok_, v0_, vmin_, vmax_) \
e71680d5 468do { if ((v0_) < (vmin_) || (v0_) > (vmax_)) { \
a385208c 469 printf("%s: %02x /%02x-%02x\n", #v0_, v0_, vmin_, vmax_); \
470 ok_ = 0; \
e71680d5 471}} while (0)
a385208c 472
473#define expect_bits(ok_, v0_, val_, mask_) \
e71680d5 474do { if (((v0_) & (mask_)) != (val_)) { \
a385208c 475 printf("%s: %04x & %04x != %04x\n", #v0_, v0_, mask_, val_); \
476 ok_ = 0; \
e71680d5 477}} while (0)
a385208c 478
ffd4b35c 479static int t_dma_zero_wrap(void)
480{
481 const u32 *src = (const u32 *)0x3c0000;
482 const u32 *ram = (const u32 *)0xff0000;
483 int ok = 1;
484
485 expect(ok, ram[0], src[5 + 0x10000/4]);
486 expect(ok, ram[1], src[4]);
487 return ok;
488}
489
490static int t_dma_zero_fill(void)
491{
492 const u32 *ram = (const u32 *)0xff0000;
493 u32 v0 = ram[2] & 2;
494 int ok = 1;
495
496 expect(ok, v0, 2);
497 expect(ok, ram[3], 0x11111111);
498 return ok;
499}
500
501static int t_dma_ram_wrap(void)
502{
503 u32 *ram = (u32 *)0xff0000;
504 u32 saved, v0, v1;
505 int ok = 1;
506
507 saved = read32(&ram[0x10000/4 - 1]);
508 ram[0x10000/4 - 1] = 0x01020304;
509 ram[0] = 0x05060708;
510 do_setup_dma(&ram[0x10000/4 - 1], 4);
511 mem_barrier();
512 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
513
514 mem_barrier();
515 write32(&ram[0x10000/4 - 1], saved);
516
517 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
518 v0 = read32(VDP_DATA_PORT);
519 v1 = read32(VDP_DATA_PORT);
520
521 expect(ok, v0, 0x01020304);
522 expect(ok, v1, 0x05060708);
523 return ok;
524}
525
526// test no src reprogram, only len0
527static int t_dma_multi(void)
528{
529 const u32 *src = (const u32 *)0x3c0000;
530 u32 v0, v1;
531 int ok = 1;
532
533 do_setup_dma(src, 2);
534 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
535 VDP_setReg(VDP_DMA_LEN0, 2);
536 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x104) | CTL_WRITE_DMA);
537
538 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
539 v0 = read32(VDP_DATA_PORT);
540 v1 = read32(VDP_DATA_PORT);
541
542 expect(ok, v0, src[0]);
543 expect(ok, v1, src[1]);
544 return ok;
545}
546
547static int t_dma_cram_wrap(void)
548{
549 u32 *ram = (u32 *)0xff0000;
550 u32 v0, v1;
551 int ok = 1;
552
553 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
554 write32(VDP_DATA_PORT, 0);
555
556 ram[0] = 0x0ec20ec4;
557 ram[1] = 0x0ec60ec8;
558 mem_barrier();
559 do_setup_dma(ram, 4);
560 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0x7c | 0xff81) | CTL_WRITE_DMA);
561
562 write32(VDP_CTRL_PORT, CTL_READ_CRAM(0x7c));
563 v0 = read32(VDP_DATA_PORT) & 0x0eee0eee;
564 write32(VDP_CTRL_PORT, CTL_READ_CRAM(0));
565 v1 = read32(VDP_DATA_PORT) & 0x0eee0eee;
566
567 setup_default_palette();
568
569 expect(ok, v0, ram[0]);
570 expect(ok, v1, ram[1]);
571 return ok;
572}
573
574static int t_dma_vsram_wrap(void)
575{
576 u32 *ram32 = (u32 *)0xff0000;
577 u16 *ram16 = (u16 *)0xff0000;
578 u32 v0, v1;
579 int ok = 1;
580 int i;
581
582 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
583 write32(VDP_DATA_PORT, 0);
584
585 for (i = 0; i < 0x48/2; i++)
586 ram16[i] = i + 1;
587 mem_barrier();
588 do_setup_dma(ram16, 0x48/2);
589 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0x3c | 0xff81) | CTL_WRITE_DMA);
590
591 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0x3c));
592 v0 = read32(VDP_DATA_PORT) & 0x03ff03ff;
593 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0));
594 v1 = read32(VDP_DATA_PORT) & 0x03ff03ff;
595
596 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
597 write32(VDP_DATA_PORT, 0);
598
599 expect(ok, v0, ram32[0]);
600 expect(ok, v1, ram32[0x48/4 - 1]);
601 return ok;
602}
603
604static int t_dma_and_data(void)
605{
606 const u32 *src = (const u32 *)0x3c0000;
a385208c 607 u32 v0, v1;
ffd4b35c 608 int ok = 1;
609
610 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
611 write32(VDP_DATA_PORT, 0);
612
613 do_setup_dma(src, 2);
614 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfc) | CTL_WRITE_DMA);
615 write32(VDP_DATA_PORT, 0x5ec8a248);
616
a385208c 617 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfc));
ffd4b35c 618 v0 = read32(VDP_DATA_PORT);
a385208c 619 v1 = read32(VDP_DATA_PORT);
ffd4b35c 620
a385208c 621 expect(ok, v0, src[0]);
622 expect(ok, v1, 0x5ec8a248);
623 return ok;
624}
625
626static int t_dma_short_cmd(void)
627{
628 const u32 *src = (const u32 *)0x3c0000;
629 u32 v0, v1, v2;
630 int ok = 1;
631
632 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x3ff4));
633 write32(VDP_DATA_PORT, 0x10111213);
634 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfff0));
635 write32(VDP_DATA_PORT, 0x20212223);
636 write32(VDP_DATA_PORT, 0x30313233);
cc7e5122 637 vdp_wait_for_fifo_empty();
a385208c 638
639 do_setup_dma(src, 2);
640 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfff0) | CTL_WRITE_DMA);
641 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x3ff4) >> 16);
642 write32(VDP_DATA_PORT, 0x40414243);
643
644 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x3ff4));
645 v0 = read32(VDP_DATA_PORT);
646 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfff0));
647 v1 = read32(VDP_DATA_PORT);
648 v2 = read32(VDP_DATA_PORT);
649
650 expect(ok, v0, 0x10111213);
651 expect(ok, v1, src[0]);
652 expect(ok, v2, 0x40414243);
ffd4b35c 653 return ok;
654}
655
656static int t_dma_fill3_odd(void)
657{
658 u32 v0, v1, v2;
659 int ok = 1;
660
661 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
662 write32(VDP_DATA_PORT, 0);
663 write32(VDP_DATA_PORT, 0);
664 write32(VDP_DATA_PORT, 0);
cc7e5122 665 vdp_wait_for_fifo_empty();
ffd4b35c 666
667 VDP_setReg(VDP_AUTOINC, 3);
668 VDP_setReg(VDP_DMA_LEN0, 3);
669 VDP_setReg(VDP_DMA_SRC2, 0x80);
670 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x101) | CTL_WRITE_DMA);
671 write16(VDP_DATA_PORT, 0x1122);
a385208c 672 vdp_wait_for_dma_idle();
ffd4b35c 673
674 VDP_setReg(VDP_AUTOINC, 2);
675 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
676 v0 = read32(VDP_DATA_PORT);
677 v1 = read32(VDP_DATA_PORT);
678 v2 = read32(VDP_DATA_PORT);
679
680 expect(ok, v0, 0x22110000);
681 expect(ok, v1, 0x00111100);
682 expect(ok, v2, 0x00000011);
683 return ok;
684}
685
686static int t_dma_fill3_even(void)
687{
688 u32 v0, v1, v2;
689 int ok = 1;
690
691 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
692 write32(VDP_DATA_PORT, 0);
693 write32(VDP_DATA_PORT, 0);
694 write32(VDP_DATA_PORT, 0);
cc7e5122 695 vdp_wait_for_fifo_empty();
ffd4b35c 696
697 VDP_setReg(VDP_AUTOINC, 3);
698 VDP_setReg(VDP_DMA_LEN0, 3);
699 VDP_setReg(VDP_DMA_SRC2, 0x80);
700 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
701 write16(VDP_DATA_PORT, 0x1122);
a385208c 702 vdp_wait_for_dma_idle();
ffd4b35c 703
704 VDP_setReg(VDP_AUTOINC, 2);
705 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
706 v0 = read32(VDP_DATA_PORT);
707 v1 = read32(VDP_DATA_PORT);
708 v2 = read32(VDP_DATA_PORT);
709
710 expect(ok, v0, 0x11221100);
711 expect(ok, v1, 0x00000011);
712 expect(ok, v2, 0x11000000);
713 return ok;
714}
715
716static unused int t_dma_fill3_vsram(void)
717{
718 u32 v0, v1, v2;
719 int ok = 1;
720
721 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
722 write32(VDP_DATA_PORT, 0);
723 write32(VDP_DATA_PORT, 0);
724 write32(VDP_DATA_PORT, 0);
725
726 write16(VDP_DATA_PORT, 0x0111);
727 write16(VDP_DATA_PORT, 0x0222);
728 write16(VDP_DATA_PORT, 0x0333);
a385208c 729 vdp_wait_for_fifo_empty();
ffd4b35c 730
731 VDP_setReg(VDP_AUTOINC, 3);
732 VDP_setReg(VDP_DMA_LEN0, 3);
733 VDP_setReg(VDP_DMA_SRC2, 0x80);
734 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(1) | CTL_WRITE_DMA);
735 write16(VDP_DATA_PORT, 0x0102);
a385208c 736 vdp_wait_for_dma_idle();
ffd4b35c 737
738 VDP_setReg(VDP_AUTOINC, 2);
739 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0));
740 v0 = read32(VDP_DATA_PORT);
741 v1 = read32(VDP_DATA_PORT);
742 v2 = read32(VDP_DATA_PORT);
743
744 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
745 write32(VDP_DATA_PORT, 0);
746
747 expect(ok, v0, 0x01020000);
748 expect(ok, v1, 0x01110111);
749 expect(ok, v2, 0x00000111);
750 return ok;
751}
752
753static int t_dma_fill_dis(void)
754{
755 u32 v0, v1;
756 int ok = 1;
757
758 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
759 write32(VDP_DATA_PORT, 0);
760 write32(VDP_DATA_PORT, 0);
761
762 VDP_setReg(VDP_DMA_LEN0, 1);
763 VDP_setReg(VDP_DMA_SRC2, 0x80);
764 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
765 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
766 write16(VDP_DATA_PORT, 0x1122);
a385208c 767 vdp_wait_for_dma_idle();
ffd4b35c 768
769 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
770 write16(VDP_DATA_PORT, 0x3344);
a385208c 771 vdp_wait_for_dma_idle();
ffd4b35c 772
773 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
774 v0 = read32(VDP_DATA_PORT);
775 v1 = read32(VDP_DATA_PORT);
776
777 expect(ok, v0, 0);
778 expect(ok, v1, 0);
779 return ok;
780}
781
782static int t_dma_fill_src(void)
783{
784 const u32 *src = (const u32 *)0x3c0000;
785 u32 v0, v1;
786 int ok = 1;
787
788 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
789 write32(VDP_DATA_PORT, 0);
790
791 // do_setup_dma(src, 2); // hang, can't write src2 twice
792 VDP_setReg(VDP_DMA_LEN0, 2);
793 VDP_setReg(VDP_DMA_SRC0, (u32)src >> 1);
794 VDP_setReg(VDP_DMA_SRC1, (u32)src >> 9);
795 VDP_setReg(VDP_DMA_SRC2, 0x80);
796 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
797 write16(VDP_DATA_PORT, 0x1122);
a385208c 798 vdp_wait_for_dma_idle();
ffd4b35c 799
800 VDP_setReg(VDP_DMA_LEN0, 2);
801 VDP_setReg(VDP_DMA_SRC2, (u32)src >> 17);
802 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x104) | CTL_WRITE_DMA);
803
804 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
805 v0 = read32(VDP_DATA_PORT);
806 v1 = read32(VDP_DATA_PORT);
807
808 expect(ok, v0, 0x11220011);
809 expect(ok, v1, src[1]);
810 return ok;
811}
812
a385208c 813// (((a & 2) >> 1) ^ 1) | ((a & $400) >> 9) | (a & $3FC) | ((a & $1F800) >> 1)
814static int t_dma_128k(void)
815{
816 u16 *ram = (u16 *)0xff0000;
817 u32 v0, v1;
818 int ok = 1;
819
820 ram[0] = 0x5a11;
821 ram[1] = 0x5a22;
822 ram[2] = 0x5a33;
823
824 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
825 write32(VDP_DATA_PORT, 0x01020304);
826 write32(VDP_DATA_PORT, 0x05060708);
827 vdp_wait_for_fifo_empty();
828
829 mem_barrier();
830 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
831 do_setup_dma(ram, 3);
832 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
833 vdp_wait_for_fifo_empty();
834
835 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
836 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
837 v0 = read32(VDP_DATA_PORT);
838 v1 = read32(VDP_DATA_PORT);
839
840 expect(ok, v0, 0x22110304);
841 expect(ok, v1, 0x05330708);
842 return ok;
843}
844
845static int t_vdp_128k_b16(void)
846{
847 u32 v0, v1;
848 int ok = 1;
849
850 VDP_setReg(VDP_AUTOINC, 0);
851 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8100));
852 write32(VDP_DATA_PORT, 0x01020304);
853 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x10100));
854 write32(VDP_DATA_PORT, 0x05060708);
855 vdp_wait_for_fifo_empty();
856
857 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
858 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) >> 16); // note: upper cmd
859 write32(VDP_DATA_PORT, 0x11223344);
860 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x10102));
861 write32(VDP_DATA_PORT, 0x55667788);
862 vdp_wait_for_fifo_empty();
863
864 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
865 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x8100));
866 v0 = read16(VDP_DATA_PORT);
867 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x0100));
868 v1 = read16(VDP_DATA_PORT);
869
870 VDP_setReg(VDP_AUTOINC, 2);
871
872 expect(ok, v0, 0x8844);
873 expect(ok, v1, 0x0708);
874 return ok;
875}
876
877static unused int t_vdp_128k_b16_inc(void)
878{
879 u32 v0, v1;
880 int ok = 1;
881
882 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
883 write32(VDP_DATA_PORT, 0x01020304);
884 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8000));
885 write32(VDP_DATA_PORT, 0x05060708);
886 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfffe));
887 write32(VDP_DATA_PORT, 0x090a0b0c);
888 vdp_wait_for_fifo_empty();
889
890 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
891 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) >> 16); // note: upper cmd
892 write16(VDP_DATA_PORT, 0x1122);
893 vdp_wait_for_fifo_empty();
894
895 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
896 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
897 v0 = read32(VDP_DATA_PORT);
898 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x8000));
899 v1 = read32(VDP_DATA_PORT);
900 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
901 write32(VDP_DATA_PORT, 0);
902 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8000));
903 write32(VDP_DATA_PORT, 0);
904
905 expect(ok, v0, 0x0b0c0304); // XXX: no 22 anywhere?
906 expect(ok, v1, 0x05060708);
907 return ok;
908}
909
910static int t_vdp_reg_cmd(void)
911{
912 u32 v0;
913 int ok = 1;
914
915 VDP_setReg(VDP_AUTOINC, 0);
916 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
917 write32(VDP_DATA_PORT, 0x01020304);
918 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
919 write32(VDP_DATA_PORT, 0x05060708);
920
921 VDP_setReg(VDP_AUTOINC, 2);
922 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x0100));
923 v0 = read16(VDP_DATA_PORT);
924
925 expect(ok, v0, 0x0304);
926 return ok;
927}
928
cc7e5122 929static int t_vdp_sr_vb(void)
930{
931 u16 sr[4];
932 int ok = 1;
933
934 while (read8(VDP_HV_COUNTER) != 242)
935 ;
936 sr[0] = read16(VDP_CTRL_PORT);
937 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
938 sr[1] = read16(VDP_CTRL_PORT);
939 while (read8(VDP_HV_COUNTER) != 4)
940 ;
941 sr[2] = read16(VDP_CTRL_PORT);
942 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
943 sr[3] = read16(VDP_CTRL_PORT);
944
945 expect_bits(ok, sr[0], SR_VB, SR_VB);
946 expect_bits(ok, sr[1], SR_VB, SR_VB);
947 expect_bits(ok, sr[2], SR_VB, SR_VB);
948 expect_bits(ok, sr[3], 0, SR_VB);
949 return ok;
950}
951
ffd4b35c 952/* z80 tests assume busreq state */
953static int t_z80mem_long_mirror(void)
954{
955 u8 *zram = (u8 *)0xa00000;
956 int ok = 1;
957
958 write8(&zram[0x1100], 0x11);
959 write8(&zram[0x1101], 0x22);
960 write8(&zram[0x1102], 0x33);
961 write8(&zram[0x1103], 0x44);
962 mem_barrier();
963 write32(&zram[0x3100], 0x55667788);
964 mem_barrier();
965
966 expect(ok, zram[0x1100], 0x55);
967 expect(ok, zram[0x1101], 0x22);
968 expect(ok, zram[0x1102], 0x77);
969 expect(ok, zram[0x1103], 0x44);
970 return ok;
971}
972
a385208c 973static int t_z80mem_noreq_w(void)
974{
975 u8 *zram = (u8 *)0xa00000;
976 int ok = 1;
977
978 write8(&zram[0x1100], 0x11);
979 mem_barrier();
980 write16(0xa11100, 0x000);
981 write8(&zram[0x1100], 0x22);
982 mem_barrier();
983
984 write16(0xa11100, 0x100);
985 while (read16(0xa11100) & 0x100)
986 ;
987
988 expect(ok, zram[0x1100], 0x11);
989 return ok;
990}
991
e71680d5 992#define Z80_C_DISPATCH 113 // see z80_test.s80
993#define Z80_C_END 17
994#define Z80_C_END_VCNT 67
995
996#define Z80_CYLES_TEST1(b) (Z80_C_DISPATCH + ((b) - 1) * 21 + 26 + Z80_C_END)
a385208c 997
ffd4b35c 998static int t_z80mem_vdp_r(void)
999{
1000 u8 *zram = (u8 *)0xa00000;
1001 int ok = 1;
1002
1003 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
1004 write32(VDP_DATA_PORT, 0x11223344);
1005 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
1006
1007 zram[0x1000] = 1; // cp
ffd4b35c 1008 write16_z80le(&zram[0x1002], 0x7f00); // src
a385208c 1009 write16_z80le(&zram[0x1004], 0x1100); // dst
1010 write16_z80le(&zram[0x1006], 2); // len
1011 zram[0x1100] = zram[0x1101] = zram[0x1102] = 0x5a;
ffd4b35c 1012 mem_barrier();
1013 write16(0xa11100, 0x000);
e71680d5 1014 burn10(Z80_CYLES_TEST1(2) * 15 / 7 / 10);
ffd4b35c 1015
1016 write16(0xa11100, 0x100);
1017 while (read16(0xa11100) & 0x100)
1018 ;
1019
1020 expect(ok, zram[0x1000], 0);
a385208c 1021 expect(ok, zram[0x1100], 0x11);
1022 expect(ok, zram[0x1101], 0x44);
1023 expect(ok, zram[0x1102], 0x5a);
ffd4b35c 1024 return ok;
1025}
1026
1027static unused int t_z80mem_vdp_w(void)
1028{
1029 u8 *zram = (u8 *)0xa00000;
1030 u32 v0;
1031 int ok = 1;
1032
1033 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
1034 write32(VDP_DATA_PORT, 0x11223344);
1035 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
a385208c 1036 vdp_wait_for_fifo_empty();
ffd4b35c 1037
1038 zram[0x1000] = 1; // cp
a385208c 1039 write16_z80le(&zram[0x1002], 0x1100); // src
ffd4b35c 1040 write16_z80le(&zram[0x1004], 0x7f00); // dst
a385208c 1041 write16_z80le(&zram[0x1006], 2); // len
1042 zram[0x1100] = 0x55;
1043 zram[0x1101] = 0x66;
ffd4b35c 1044 mem_barrier();
1045 write16(0xa11100, 0x000);
e71680d5 1046 burn10(Z80_CYLES_TEST1(2) * 15 / 7 / 10);
ffd4b35c 1047
1048 write16(0xa11100, 0x100);
1049 while (read16(0xa11100) & 0x100)
1050 ;
1051
1052 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
1053 v0 = read32(VDP_DATA_PORT);
1054
1055 expect(ok, zram[0x1000], 0);
1056 expect(ok, v0, 0x55556666);
1057 return ok;
1058}
1059
a385208c 1060static int t_tim_loop(void)
1061{
1062 u8 vcnt;
1063 int ok = 1;
1064
1065 vdp_wait_for_line_0();
1066 burn10(488*220/10);
1067 vcnt = read8(VDP_HV_COUNTER);
1068 mem_barrier();
1069
1070 //expect_range(ok, vcnt, 0x80, 0x80);
1071 expect(ok, vcnt, 223);
1072 return ok;
1073}
1074
e71680d5 1075static int t_tim_z80_loop(void)
1076{
1077 u8 pal = read8(0xa10001) & 0x40;
1078 u8 *zram = (u8 *)0xa00000;
1079 u16 z80_loops = pal ? 3420*(313*2+1)/15/100 : 3420*(262*2+1)/15/100; // 2fr + 1ln
1080 u16 _68k_loops = pal ? 3420*(313*2+1)/7/10 : 3420*(262*2+1)/7/10;
1081 int ok = 1;
1082
1083 zram[0x1000] = 3; // idle loop, save vcnt
1084 write16_z80le(&zram[0x1002], 0); // src (unused)
1085 write16_z80le(&zram[0x1004], 0x1100); // vcnt dst
1086 write16_z80le(&zram[0x1006], z80_loops); // x100 cycles
1087 zram[0x1100] = 0;
1088 mem_barrier();
1089
1090 vdp_wait_for_line_0();
1091 write16(0xa11100, 0x000);
1092 burn10(_68k_loops + (Z80_C_DISPATCH + Z80_C_END_VCNT) * 15 / 7 / 10);
1093
1094 write16(0xa11100, 0x100);
1095 while (read16(0xa11100) & 0x100)
1096 ;
1097 expect(ok, zram[0x1000], 0);
1098 expect(ok, zram[0x1100], 1);
1099 return ok;
1100}
1101
1102#define Z80_CYCLES_TEST2(b) (Z80_C_DISPATCH + (b) * 38 + Z80_C_END_VCNT)
a385208c 1103
1104// 80 80 91 95-96
1105static void z80_read_loop(u8 *zram, u16 src)
1106{
1107 const int pairs = 512 + 256;
1108
1109 zram[0x1000] = 2; // read loop, save vcnt
1110 write16_z80le(&zram[0x1002], src); // src
1111 write16_z80le(&zram[0x1004], 0x1100); // vcnt dst
1112 write16_z80le(&zram[0x1006], pairs); // reads/2
1113 zram[0x1100] = 0;
1114 mem_barrier();
1115
1116 vdp_wait_for_line_0();
1117 write16(0xa11100, 0x000);
e71680d5 1118 burn10(Z80_CYCLES_TEST2(pairs) * 15 / 7 * 2 / 10);
a385208c 1119
1120 write16(0xa11100, 0x100);
1121 while (read16(0xa11100) & 0x100)
1122 ;
1123}
1124
1125static int t_tim_z80_ram(void)
1126{
1127 u8 *zram = (u8 *)0xa00000;
1128 int ok = 1;
1129
1130 z80_read_loop(zram, 0);
1131
1132 expect(ok, zram[0x1000], 0);
1133 expect_range(ok, zram[0x1100], 0x80, 0x80);
1134 return ok;
1135}
1136
1137static int t_tim_z80_ym(void)
1138{
1139 u8 *zram = (u8 *)0xa00000;
1140 int ok = 1;
1141
1142 z80_read_loop(zram, 0x4000);
1143
1144 expect(ok, zram[0x1000], 0);
1145 expect_range(ok, zram[0x1100], 0x80, 0x80);
1146 return ok;
1147}
1148
1149static int t_tim_z80_vdp(void)
1150{
1151 u8 *zram = (u8 *)0xa00000;
1152 int ok = 1;
1153
1154 z80_read_loop(zram, 0x7f08);
1155
1156 expect(ok, zram[0x1000], 0);
a385208c 1157 expect_range(ok, zram[0x1100], 0x91, 0x91);
a385208c 1158 return ok;
1159}
1160
1161static int t_tim_z80_bank_rom(void)
1162{
1163 u8 *zram = (u8 *)0xa00000;
1164 int i, ok = 1;
1165
1166 for (i = 0; i < 17; i++)
1167 write8(0xa06000, 0); // bank 0
1168
1169 z80_read_loop(zram, 0x8000);
1170
1171 expect(ok, zram[0x1000], 0);
a385208c 1172 expect_range(ok, zram[0x1100], 0x95, 0x96);
a385208c 1173 return ok;
1174}
1175
1176/* borderline too slow */
1177#if 0
cc7e5122 1178static void test_vcnt_vb(void)
a385208c 1179{
1180 const u32 *srhv = (u32 *)0xc00006; // to read SR and HV counter
1181 u32 *ram = (u32 *)0xff0000;
1182 u16 vcnt, vcnt_expect = 0;
1183 u16 sr, count = 0;
1184 u32 val, old;
1185
1186 vdp_wait_for_line_0();
1187 old = read32(srhv);
1188 *ram++ = old;
1189 for (;;) {
1190 val = read32(srhv);
1191 vcnt = val & 0xff00;
1192 if (vcnt == vcnt_expect)
1193 continue;
1194 sr = val >> 16;
1195 if (vcnt == 0 && !(sr & SR_VB)) // not VB
1196 break; // wrapped to start of frame
1197// count++;
1198 vcnt_expect += 0x100;
1199 if (vcnt == vcnt_expect && !((sr ^ (old >> 16)) & SR_VB)) {
1200 old = val;
1201 continue;
1202 }
1203 // should have a vcnt jump here
1204 *ram++ = old;
1205 *ram++ = val;
1206 vcnt_expect = vcnt;
1207 old = val;
1208 }
1209 *ram++ = val;
1210 *ram = count;
1211 mem_barrier();
1212}
1213#endif
1214
1215static int t_tim_vcnt(void)
1216{
1217 const u32 *ram32 = (u32 *)0xff0000;
1218 const u8 *ram = (u8 *)0xff0000;
1219 u8 pal = read8(0xa10001) & 0x40;
1220 u8 vc_jmp_b = pal ? 0x02 : 0xea;
1221 u8 vc_jmp_a = pal ? 0xca : 0xe5;
1222 u16 lines = pal ? 313 : 262;
1223 int ok = 1;
1224
cc7e5122 1225 test_vcnt_vb();
a385208c 1226 expect(ok, ram[0*4+2], 0); // line 0
1227 expect_bits(ok, ram[0*4+1], 0, SR_VB);
1228 expect(ok, ram[1*4+2], 223); // last no blank
1229 expect_bits(ok, ram[1*4+1], 0, SR_VB);
1230 expect(ok, ram[2*4+2], 224); // 1st blank
1231 expect_bits(ok, ram[2*4+1], SR_VB, SR_VB);
1232 expect(ok, ram[3*4+2], vc_jmp_b); // before jump
1233 expect_bits(ok, ram[3*4+1], SR_VB, SR_VB);
1234 expect(ok, ram[4*4+2], vc_jmp_a); // after jump
1235 expect_bits(ok, ram[4*4+1], SR_VB, SR_VB);
1236 expect(ok, ram[5*4+2], 0xfe); // before vb clear
1237 expect_bits(ok, ram[5*4+1], SR_VB, SR_VB);
1238 expect(ok, ram[6*4+2], 0xff); // after vb clear
1239 expect_bits(ok, ram[6*4+1], 0, SR_VB);
1240 expect(ok, ram[7*4+2], 0); // next line 0
1241 expect_bits(ok, ram[7*4+1], 0, SR_VB);
1242 expect(ok, ram32[8], lines - 1);
1243 return ok;
1244}
1245
e71680d5 1246static int t_tim_vcnt_loops(void)
1247{
1248 const u16 *ram16 = (u16 *)0xfff004;
1249 u8 pal = read8(0xa10001) & 0x40;
1250 u16 i, lines = pal ? 313 : 262;
1251 int ok = 1;
1252
1253 test_vcnt_loops();
1254 expect(ok, ram16[-1*2+0], 0xff);
1255 expect_range(ok, ram16[-1*2+1], 21, 22);
1256 for (i = 0; i < lines; i++)
1257 expect_range(ok, ram16[i*2+1], 19, 21);
1258 expect(ok, ram16[lines*2+0], 0);
635f2450 1259 expect_range(ok, ram16[lines*2+1], 19, 21);
e71680d5 1260 return ok;
1261}
1262
cc7e5122 1263static int t_tim_hblank_h40(void)
1264{
1265 const u8 *r = (u8 *)0xff0000;
1266 int ok = 1;
1267
1268 test_hb();
1269
1270 // set: 0-2
1271 expect_bits(ok, r[2], SR_HB, SR_HB);
1272 expect_bits(ok, r[5], SR_HB, SR_HB);
1273 // <wait>
1274 expect_bits(ok, r[7], SR_HB, SR_HB);
1275 // clear: 8-11
1276 expect_bits(ok, r[12], 0, SR_HB);
1277 return ok;
1278}
1279
1280static int t_tim_hblank_h32(void)
1281{
1282 const u8 *r = (u8 *)0xff0000;
1283 int ok = 1;
1284
1285 VDP_setReg(VDP_MODE4, 0x00);
1286 test_hb();
1287 VDP_setReg(VDP_MODE4, 0x81);
1288
cc7e5122 1289 expect_bits(ok, r[0], 0, SR_HB);
cc7e5122 1290 // set: 1-4
1291 expect_bits(ok, r[4], SR_HB, SR_HB);
1292 expect_bits(ok, r[5], SR_HB, SR_HB);
1293 // <wait>
1294 expect_bits(ok, r[8], SR_HB, SR_HB);
1295 // clear: 9-11
1296 expect_bits(ok, r[12], 0, SR_HB);
1297 return ok;
1298}
1299
a385208c 1300static int t_tim_vdp_as_vram_w(void)
1301{
1302 int ok = 1;
1303 u8 vcnt;
1304
1305 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
1306 vdp_wait_for_line_0();
1307 write16_x16(VDP_DATA_PORT, 112*18 / 16, 0);
1308 vcnt = read8(VDP_HV_COUNTER);
1309 mem_barrier();
1310
1311 expect(ok, vcnt, 112*2-1);
1312 return ok;
1313}
1314
1315static int t_tim_vdp_as_cram_w(void)
1316{
1317 int ok = 1;
1318 u8 vcnt;
1319
1320 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
1321 vdp_wait_for_line_0();
1322 write16_x16(VDP_DATA_PORT, 112*18 / 16, 0);
1323 vcnt = read8(VDP_HV_COUNTER);
1324 mem_barrier();
1325
1326 setup_default_palette();
1327
a385208c 1328 expect(ok, vcnt, 112);
a385208c 1329 return ok;
1330}
1331
e71680d5 1332static const u8 hcnt2tm[] =
1333{
1334 0x0a, 0x1d, 0x31, 0x44, 0x58, 0x6b, 0x7f, 0x92,
1335 0xa6, 0xb9, 0xcc, 0x00, 0x00, 0x00, 0xe2, 0xf6
1336};
1337
1338static int t_tim_ym_timer_z80(int is_b)
1339{
1340 u8 pal = read8(0xa10001) & 0x40;
1341 u8 *zram = (u8 *)0xa00000;
1342 u8 *z80 = zram;
1343 u16 _68k_loops = 3420*(302+5+1)/7/10; // ~ (72*1024*2)/(3420./7)
1344 u16 start, end, diff;
1345 int ok = 1;
1346
1347 zram[0x1000] = 4 + is_b; // ym2612 timer a/b test
1348 zram[0x1100] = zram[0x1101] = zram[0x1102] = zram[0x1103] = 0;
1349 mem_barrier();
1350
1351 vdp_wait_for_line_0();
1352 write16(0xa11100, 0x000);
1353
1354 burn10(_68k_loops + (Z80_C_DISPATCH + Z80_C_END_VCNT) * 15 / 7 / 10);
1355
1356 write16(0xa11100, 0x100);
1357 while (read16(0xa11100) & 0x100)
1358 ;
1359 mem_barrier();
1360 expect(ok, zram[0x1000], 0);
1361 (void)hcnt2tm;
1362 //start = ((u16)zram[0x1102] << 8) | hcnt2tm[zram[0x1103] >> 4];
1363 //end = ((u16)zram[0x1100] << 8) | hcnt2tm[zram[0x1101] >> 4];
1364 start = zram[0x1102];
1365 end = zram[0x1100];
1366 diff = end - start;
1367 if (pal)
1368 expect_range(ok, diff, 0xf4, 0xf6);
1369 else
1370 expect_range(ok, diff, 0x27, 0x29);
1371 write8(&z80[0x4001], 0); // stop, but should keep the flag
1372 mem_barrier();
1373 burn10(32*6/10); // busy bit, 32 FM ticks (M/7/6)
1374 if (is_b) {
1375 expect(ok, z80[0x4000], 2);
1376 write8(&z80[0x4001], 0x20); // reset flag (reg 0x27, set up by z80)
1377 }
1378 else {
1379 expect(ok, z80[0x4000], 1);
1380 write8(&z80[0x4001], 0x10);
1381 }
1382 mem_barrier();
1383 burn10(32*6/10);
1384 expect(ok, z80[0x4000], 0);
1385 return ok;
1386}
1387
1388static int t_tim_ym_timera_z80(void)
1389{
1390 return t_tim_ym_timer_z80(0);
1391}
1392
1393static int t_tim_ym_timerb_z80(void)
1394{
1395 return t_tim_ym_timer_z80(1);
1396}
1397
1398static int t_tim_ym_timerb_stop(void)
1399{
1400 const struct {
1401 //u8 vcnt_start;
1402 //u8 hcnt_start;
1403 u16 vcnt_start;
1404 u16 stat0;
1405 //u8 vcnt_end;
1406 //u8 hcnt_end;
1407 u16 vcnt_end;
1408 u16 stat1;
1409 } *t = (void *)0xfff000;
1410 u8 *z80 = (u8 *)0xa00000;
1411 u16 diff;
1412 int ok = 1;
1413 write16(0xa11100, 0x100);
1414 while (read16(0xa11100) & 0x100)
1415 ;
1416 test_ym_stopped_tick();
1417 mem_barrier();
1418 //start = ((u16)t->vcnt_start << 8) | hcnt2tm[t->hcnt_start >> 4];
1419 //end = ((u16)t->vcnt_end << 8) | hcnt2tm[t->hcnt_end >> 4];
1420 //diff = end - start;
1421 diff = t->vcnt_end - t->vcnt_start;
1422 //expect_range(ok, diff, 0x492, 0x5c2); // why so much variation?
1423 expect_range(ok, diff, 4, 5);
1424 expect(ok, t->stat0, 0);
1425 expect(ok, t->stat1, 2);
1426 expect(ok, z80[0x4000], 2);
1427 write8(&z80[0x4001], 0x30);
1428 return ok;
1429}
1430
1431static int t_tim_ym_timer_ab_sync(void)
1432{
3d80f940 1433 u16 v1, v2, v3, v4, v5, ln0, ln1, ln2;
e71680d5 1434 int ok = 1;
3d80f940 1435
1436 vdp_wait_for_line_0();
635f2450 1437 v1 = test_ym_ab_sync();
3d80f940 1438
1439 ln0 = get_line();
1440 burn10(3420*15/7/10); // ~15 scanlines
1441 write8(0xa04001, 0x3f); // clear, no reload
1442 burn10(12); // wait for busy to clear
635f2450 1443 v2 = read8(0xa04000);
1444 v3 = test_ym_ab_sync2();
3d80f940 1445
1446 ln1 = get_line();
1447 burn10(3420*15/7/10); // ~15 scanlines
1448 v4 = test_ym_ab_sync2();
1449
1450 ln2 = get_line();
1451 burn10(3420*30/7/10); // ~35 scanlines
1452 v5 = read8(0xa04000);
1453
635f2450 1454 expect(ok, v1, 3);
1455 expect(ok, v2, 0);
1456 expect(ok, v3, 3);
3d80f940 1457 expect(ok, v4, 2);
1458 expect(ok, v5, 0);
1459 expect_range(ok, ln1-ln0, 18, 19);
1460 expect_range(ok, ln2-ln1, 32, 34); // almost always 33
e71680d5 1461 return ok;
1462}
1463
4f936a9c 1464struct irq_test {
1465 u16 cnt;
1466 union {
1467 u16 hv;
1468 u8 v;
1469 } first, last;
8517a6df 1470 u16 pad;
4f936a9c 1471};
1472
e71680d5 1473// broken on fresh boot due to uknown reasons
6c839579 1474static int t_irq_hint(void)
1475{
4f936a9c 1476 struct irq_test *it = (void *)0xfff000;
e71680d5 1477 struct irq_test *itv = it + 1;
6c839579 1478 int ok = 1;
1479
e71680d5 1480 memset_(it, 0, sizeof(*it) * 2);
1481 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1482 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1483
1484 // without this, tests fail after cold boot
1485 while (!(read16(VDP_CTRL_PORT) & 8))
1486 /* not blanking */;
1487
6c839579 1488 // for more fun, disable the display
1489 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
1490
6c839579 1491 VDP_setReg(10, 0);
1492 while (read8(VDP_HV_COUNTER) != 100)
1493 ;
1494 while (read8(VDP_HV_COUNTER) != 229)
1495 ;
1496 // take the pending irq
1497 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1498 move_sr(0x2000);
1499 burn10(488 * 2 / 10);
1500 move_sr(0x2700);
4f936a9c 1501 expect(ok, it->first.v, 229); // pending irq trigger
1502 expect(ok, it->cnt, 1);
e71680d5 1503 expect(ok, itv->cnt, 0);
4f936a9c 1504
6c839579 1505 // count irqs
4f936a9c 1506 it->cnt = it->first.hv = it->last.hv = 0;
6c839579 1507 move_sr(0x2000);
cc7e5122 1508 while (read8(VDP_HV_COUNTER) != 4)
6c839579 1509 ;
1510 while (read8(VDP_HV_COUNTER) != 228)
1511 ;
1512 move_sr(0x2700);
4f936a9c 1513 expect(ok, it->cnt, 225);
1514 expect(ok, it->first.v, 0);
1515 expect(ok, it->last.v, 224);
1516
6c839579 1517 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1518
4f936a9c 1519 // detect reload line
1520 it->cnt = it->first.hv = it->last.hv = 0;
1521 VDP_setReg(10, 17);
1522 move_sr(0x2000);
1523 while (read16(VDP_CTRL_PORT) & 8)
1524 /* blanking */;
1525 VDP_setReg(10, 255);
1526 while (read8(VDP_HV_COUNTER) != 228)
1527 ;
1528 move_sr(0x2700);
1529 expect(ok, it->cnt, 1);
1530 expect(ok, it->first.v, 17);
1531 expect(ok, it->last.v, 17);
1532
1533 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1534
6c839579 1535 return ok;
1536}
1537
8517a6df 1538static int t_irq_both_cpu_unmask(void)
1539{
1540 struct irq_test *ith = (void *)0xfff000;
1541 struct irq_test *itv = ith + 1;
1542 u16 s0, s1;
1543 int ok = 1;
1544
1545 memset_(ith, 0, sizeof(*ith) * 2);
1546 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1547 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1548 VDP_setReg(10, 0);
1549 while (read8(VDP_HV_COUNTER) != 100)
1550 ;
1551 while (read8(VDP_HV_COUNTER) != 226)
1552 ;
1553 VDP_setReg(10, 99);
1554 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1555 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP);
1556 /* go to active display line 100 */
1557 while (read8(VDP_HV_COUNTER) != 100)
1558 ;
1559 s0 = read16(VDP_CTRL_PORT);
1560 s1 = move_sr_and_read(0x2000, VDP_CTRL_PORT);
1561 move_sr(0x2700);
1562 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1563 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1564
1565 expect(ok, itv->cnt, 1); // vint count
1566 expect(ok, itv->first.v, 100); // vint line
1567 expect(ok, ith->cnt, 1); // hint count
1568 expect(ok, ith->first.v, 100); // hint line
1569 expect_bits(ok, s0, SR_F, SR_F);
1570 expect_bits(ok, s1, 0, SR_F);
1571 return ok;
1572}
1573
6c839579 1574static int t_irq_ack_v_h(void)
1575{
8517a6df 1576 struct irq_test *ith = (void *)0xfff000;
1577 struct irq_test *itv = ith + 1;
6c839579 1578 u16 s0, s1, s2;
1579 int ok = 1;
1580
8517a6df 1581 memset_(ith, 0, sizeof(*ith) * 2);
6c839579 1582 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1583 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1584 VDP_setReg(10, 0);
4f936a9c 1585 /* ensure hcnt reload */
1586 while (!(read16(VDP_CTRL_PORT) & 8))
1587 /* not blanking */;
1588 while (read16(VDP_CTRL_PORT) & 8)
1589 /* blanking */;
6c839579 1590 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1591 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0);
1592 while (read8(VDP_HV_COUNTER) != 100)
1593 ;
1594 while (read8(VDP_HV_COUNTER) != 226)
1595 ;
1596 s0 = read16(VDP_CTRL_PORT);
1597 s1 = move_sr_and_read(0x2500, VDP_CTRL_PORT);
1598 burn10(666 / 10);
1599 s2 = move_sr_and_read(0x2000, VDP_CTRL_PORT);
1600 burn10(488 / 10);
1601 move_sr(0x2700);
1602 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1603 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1604
8517a6df 1605 expect(ok, itv->cnt, 1); // vint count
1606 expect(ok, itv->first.v, 226); // vint line
1607 expect(ok, ith->cnt, 1); // hint count
1608 expect(ok, ith->first.v, 228); // hint line
6c839579 1609 expect_bits(ok, s0, SR_F, SR_F);
1610 expect_bits(ok, s1, 0, SR_F);
1611 expect_bits(ok, s2, 0, SR_F);
1612 return ok;
1613}
1614
cc7e5122 1615static int t_irq_ack_v_h_2(void)
1616{
8517a6df 1617 struct irq_test *ith = (void *)0xfff000;
1618 struct irq_test *itv = ith + 1;
cc7e5122 1619 u16 s0, s1;
1620 int ok = 1;
1621
8517a6df 1622 memset_(ith, 0, sizeof(*ith) * 2);
cc7e5122 1623 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1624 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1625 VDP_setReg(10, 0);
1626 while (read8(VDP_HV_COUNTER) != 100)
1627 ;
1628 while (read8(VDP_HV_COUNTER) != 226)
1629 ;
1630 s0 = read16(VDP_CTRL_PORT);
1631 test_v_h_2();
1632 s1 = read16(VDP_CTRL_PORT);
1633 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1634 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1635
8517a6df 1636 expect(ok, itv->cnt, 2); // vint count
1637 expect(ok, itv->first.v, 226); // vint line
1638 expect(ok, ith->cnt, 1); // hint count
1639 expect(ok, ith->first.v, 227); // hint line
cc7e5122 1640 expect_bits(ok, s0, SR_F, SR_F);
1641 expect_bits(ok, s1, 0, SR_F);
1642 return ok;
1643}
1644
6c839579 1645static int t_irq_ack_h_v(void)
1646{
1647 u16 *ram = (u16 *)0xfff000;
1648 u8 *ram8 = (u8 *)0xfff000;
1649 u16 s0, s1, s[4];
1650 int ok = 1;
1651
1652 ram[0] = ram[1] = ram[2] =
1653 ram[4] = ram[5] = ram[6] = 0;
1654 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1655 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1656 VDP_setReg(10, 0);
1657 while (read8(VDP_HV_COUNTER) != 100)
1658 ;
1659 while (read8(VDP_HV_COUNTER) != 226)
1660 ;
1661 s0 = read16(VDP_CTRL_PORT);
1662 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1663 move_sr(0x2000);
1664 burn10(666 / 10);
1665 s1 = read16(VDP_CTRL_PORT);
1666 write_and_read1(VDP_CTRL_PORT, 0x8000 | (VDP_MODE2 << 8)
1667 | VDP_MODE2_MD | VDP_MODE2_IE0, s);
6c839579 1668 move_sr(0x2700);
1669 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1670 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1671
1672 expect(ok, ram[0], 1); // hint count
1673 expect(ok, ram8[2], 226); // hint line
1674 expect(ok, ram[4], 1); // vint count
1675 expect(ok, ram8[10], 228); // vint line
1676 expect_bits(ok, s0, SR_F, SR_F);
1677 expect_bits(ok, s1, SR_F, SR_F);
1678 expect_bits(ok, s[0], SR_F, SR_F);
1679 expect_bits(ok, s[1], SR_F, SR_F);
1680 expect_bits(ok, s[2], 0, SR_F);
1681 expect_bits(ok, s[3], 0, SR_F);
1682 return ok;
1683}
1684
cc7e5122 1685static int t_irq_ack_h_v_2(void)
1686{
1687 u16 *ram = (u16 *)0xfff000;
1688 u8 *ram8 = (u8 *)0xfff000;
1689 u16 s0, s1;
1690 int ok = 1;
1691
1692 ram[0] = ram[1] = ram[2] =
1693 ram[4] = ram[5] = ram[6] = 0;
1694 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1695 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1696 VDP_setReg(10, 0);
1697 while (read8(VDP_HV_COUNTER) != 100)
1698 ;
1699 while (read8(VDP_HV_COUNTER) != 226)
1700 ;
1701 s0 = read16(VDP_CTRL_PORT);
1702 test_h_v_2();
1703 s1 = read16(VDP_CTRL_PORT);
1704 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1705 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1706
1707 expect(ok, ram[0], 2); // hint count
1708 expect(ok, ram8[2], 226); // hint first line
1709 expect(ok, ram8[4], 226); // hint last line
1710 expect(ok, ram[4], 0); // vint count
1711 expect(ok, ram8[10], 0); // vint line
1712 expect_bits(ok, s0, SR_F, SR_F);
1713 expect_bits(ok, s1, 0, SR_F);
1714 return ok;
1715}
1716
1717static void t_irq_f_flag(void)
1718{
1719 memcpy_((void *)0xff0140, test_f_vint, test_f_vint_end - test_f_vint);
1720 memset_((void *)0xff0000, 0, 10);
1721 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP);
1722 test_f();
1723 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1724}
1725
1726static int t_irq_f_flag_h40(void)
1727{
1728 u8 f, *r = (u8 *)0xff0000;
1729 int ok = 1;
1730
1731 t_irq_f_flag();
1732
1733 expect_bits(ok, r[0], 0, SR_F);
1734 expect_bits(ok, r[1], 0, SR_F);
1735 expect_bits(ok, r[2], 0, SR_F);
1736 // hits 1-3 times in range 3-9, usually ~5
1737 f = r[3] | r[4] | r[5] | r[6] | r[7];
1738
1739 expect_bits(ok, r[10], 0, SR_F);
1740 expect_bits(ok, r[11], 0, SR_F);
1741 expect_bits(ok, f, SR_F, SR_F);
1742 return ok;
1743}
1744
1745static int t_irq_f_flag_h32(void)
1746{
1747 u8 f, *r = (u8 *)0xff0000;
1748 int ok = 1;
1749
1750 VDP_setReg(VDP_MODE4, 0x00);
1751 t_irq_f_flag();
1752 VDP_setReg(VDP_MODE4, 0x81);
1753
1754 expect_bits(ok, r[0], 0, SR_F);
1755 expect_bits(ok, r[1], 0, SR_F);
1756 // hits 1-3 times in range 2-7, usually 3
1757 f = r[2] | r[3] | r[4] | r[5] | r[6] | r[7];
1758
1759 expect_bits(ok, r[8], 0, SR_F);
1760 expect_bits(ok, r[9], 0, SR_F);
1761 expect_bits(ok, r[10], 0, SR_F);
1762 expect_bits(ok, r[11], 0, SR_F);
1763 expect_bits(ok, f, SR_F, SR_F);
1764 return ok;
1765}
1766
9d39a80e 1767// 32X
1768
5073ab5a 1769#define IRQ_CNT_FB_BASE 0x1ff00
1770
6474d733 1771// see do_cmd()
5073ab5a 1772static void x32_cmd(enum x32x_cmd cmd, u32 a0, u32 a1, u16 is_slave)
1773{
1774 u16 v, *r = (u16 *)0xa15120;
6474d733 1775 u8 *r8 = (u8 *)r;
5073ab5a 1776 u16 cmd_s = cmd | (is_slave << 15);
1777 int i;
1778
1779 write32(&r[4/2], a0);
1780 write32(&r[8/2], a1);
1781 mem_barrier();
1782 write16(r, cmd_s);
1783 mem_barrier();
1784 for (i = 0; i < 10000 && (v = read16(r)) == cmd_s; i++)
1785 burn10(1);
1786 if (v != 0) {
1787 printf("cmd clr: %x\n", v);
1788 mem_barrier();
6474d733 1789 printf("exc m s: %02x %02x\n", r8[0x0e], r8[0x0f]);
5073ab5a 1790 write16(r, 0);
1791 }
1792 v = read16(&r[1]);
1793 if (v != 0) {
1794 printf("cmd err: %x\n", v);
1795 write16(&r[1], 0);
1796 }
1797}
1798
1799static int t_32x_reset_btn(void)
1800{
1801 void (*do_32x_disable)(void) = (void *)0xff0040;
1802 u32 *fbl_icnt = (u32 *)(0x840000 + IRQ_CNT_FB_BASE);
1803 u16 *m_icnt = (u16 *)fbl_icnt;
1804 u16 *s_icnt = m_icnt + 8;
1805 u32 *r32 = (u32 *)0xa15100;
1806 u16 *r16 = (u16 *)r32, i, s;
1807 u8 *r8 = (u8 *)r32;
1808 u32 *rl = (u32 *)0;
1809 int ok = 1;
1810
1811 if (!(read16(r16) & 1))
1812 return R_SKIP;
1813
1814 expect(ok, r16[0x00/2], 0x8083);
1815
1816 write8(r8, 0x00); // FM=0
1817 mem_barrier();
1818 expect(ok, r16[0x00/2], 0x83);
1819 expect(ok, r16[0x02/2], 0);
1820 expect(ok, r16[0x04/2], 3);
1821 expect(ok, r16[0x06/2], 1); // RV (set in sega_gcc.s reset handler)
1822 expect(ok, r32[0x08/4], 0x5a5a08);
1823 expect(ok, r32[0x0c/4], 0x5a5a0c);
1824 expect(ok, r16[0x10/2], 0x5a10);
1825 expect(ok, r32[0x14/4], 0);
1826 expect(ok, r32[0x18/4], 0);
1827 expect(ok, r32[0x1c/4], 0);
1828 expect(ok, r32[0x20/4], 0x00005a20);
1829 expect(ok, r32[0x24/4], 0x5a5a5a24);
1830 expect(ok, r32[0x28/4], 0x5a5a5a28);
ec8170d9 1831 expect(ok, r32[0x2c/4], 0x075a5a2c); // 7 - last_irq_vec
5073ab5a 1832 if (!(r16[0x00/2] & 0x8000)) {
7449b889 1833 expect(ok, r8 [0x81], 1);
1834 expect(ok, r16[0x82/2], 1);
1835 expect(ok, r16[0x84/2], 0xff);
1836 expect(ok, r16[0x86/2], 0xffff);
1837 expect(ok, r16[0x88/2], 0);
5073ab5a 1838 expect(ok, r8 [0x8b] & ~2, 0); // FEN toggles periodically?
1839 expect(ok, r16[0x8c/2], 0);
1840 expect(ok, r16[0x8e/2], 0);
7449b889 1841 // setup vdp for t_32x_init
1842 r8 [0x81] = 0;
1843 r16[0x82/2] = r16[0x84/2] = r16[0x86/2] = 0;
5073ab5a 1844 }
1845 r32[0x20/4] = r32[0x24/4] = r32[0x28/4] = r32[0x2c/4] = 0;
1846 for (s = 0; s < 2; s++)
1847 {
1848 x32_cmd(CMD_READ32, 0x20004000, 0, s); // not cleared by hw
1849 expect_sh2(ok, s, r32[0x24/4], 0x02020000); // ADEN | cmd
1850 // t_32x_sh_defaults will test the other bits
1851 }
1852 // setup for t_32x_sh_defaults
1853 x32_cmd(CMD_WRITE8, 0x20004001, 0, 0);
1854 x32_cmd(CMD_WRITE8, 0x20004001, 0, 1);
1855
1856 for (i = 0; i < 7; i++) {
1857 expect(ok, m_icnt[i], 0x100);
1858 expect(ok, s_icnt[i], 0x100);
1859 }
1860 expect(ok, m_icnt[7], 0x101); // VRES happened
ec8170d9 1861 expect(ok, s_icnt[7], 0x100); // masked on slave
1862
1863 x32_cmd(CMD_GETSR, 0, 0, 1);
1864 expect_sh2(ok, 1, r32[0x24/4] & ~1, 0xf0); // still masked
1865 x32_cmd(CMD_SETSR, 0x10, 0, 1);
1866 expect(ok, r16[0x00/2], 0x8083);
1867 write8(r8, 0x00); // FM=0
1868 mem_barrier();
1869 expect(ok, m_icnt[7], 0x101);
5073ab5a 1870 expect(ok, s_icnt[7], 0x101);
ec8170d9 1871 expect(ok, r32[0x2c/4], 0x00070000); // 7 - last_irq_vec
1872 r32[0x2c/4] = 0;
5073ab5a 1873
1874 memcpy_(do_32x_disable, x32x_disable,
1875 x32x_disable_end - x32x_disable);
1876 do_32x_disable();
1877
1878 expect(ok, r16[0x00/2], 0x82);
1879 expect(ok, r16[0x02/2], 0);
1880 expect(ok, r16[0x04/2], 3);
c8abdf56 1881 expect(ok, r16[0x06/2], 0); // RV cleared by x32x_disable
5073ab5a 1882 expect(ok, r32[0x08/4], 0x5a5a08);
1883 expect(ok, r32[0x0c/4], 0x5a5a0c);
1884 expect(ok, r16[0x10/2], 0x5a10);
1885 expect(ok, rl[0x04/4], 0x000800);
1886
1887 // setup for t_32x_init, t_32x_sh_defaults
1888 r16[0x04/2] = 0;
5073ab5a 1889 r16[0x10/2] = 0x1234; // warm reset indicator
1890 mem_barrier();
1891 expect(ok, r16[0x06/2], 0); // RV
1892 return ok;
1893}
1894
9d39a80e 1895static int t_32x_init(void)
1896{
1897 void (*do_32x_enable)(void) = (void *)0xff0040;
1898 u32 M_OK = MKLONG('M','_','O','K');
1899 u32 S_OK = MKLONG('S','_','O','K');
5073ab5a 1900 u32 *r32 = (u32 *)0xa15100;
1901 u16 *r16 = (u16 *)r32;
1902 u8 *r8 = (u8 *)r32;
71b41fdd 1903 int i, ok = 1;
9d39a80e 1904
71b41fdd 1905 //v1070 = read32(0x1070);
1906
1907 /* what does REN mean exactly?
1908 * Seems to be sometimes clear after reset */
1909 for (i = 0; i < 1000000; i++)
1910 if (read16(r16) & 0x80)
1911 break;
9d39a80e 1912 expect(ok, r16[0x00/2], 0x82);
1913 expect(ok, r16[0x02/2], 0);
1914 expect(ok, r16[0x04/2], 0);
1915 expect(ok, r16[0x06/2], 0);
5073ab5a 1916 expect(ok, r8 [0x08], 0);
1917 //expect(ok, r32[0x08/4], 0); // garbage 24bit
1918 expect(ok, r8 [0x0c], 0);
1919 //expect(ok, r32[0x0c/4], 0); // garbage 24bit
1920 if (r16[0x10/2] != 0x1234) // warm reset
1921 expect(ok, r16[0x10/2], 0xffff);
1922 expect(ok, r16[0x12/2], 0);
1923 expect(ok, r32[0x14/4], 0);
1924 expect(ok, r32[0x18/4], 0);
1925 expect(ok, r32[0x1c/4], 0);
1926 //expect(ok, r8 [0x81], 0); // VDP; hangs without ADEN
1927 r32[0x20/4] = 0; // master resp
1928 r32[0x24/4] = 0; // slave resp
1929 r32[0x28/4] = 0;
1930 r32[0x2c/4] = 0;
1931
c8abdf56 1932 // check writable bits without ADEN
1933 // 08,0c have garbage or old values (survive MD's power cycle)
1934 write16(&r16[0x00/2], 0);
1935 mem_barrier();
1936 expect(ok, r16[0x00/2], 0x80);
1937 write16(&r16[0x00/2], 0xfffe);
1938 mem_barrier();
1939 expect(ok, r16[0x00/2], 0x8082);
1940 r16[0x00/2] = 0x82;
1941 r16[0x02/2] = 0xffff;
1942 r32[0x04/4] = 0xffffffff;
1943 r32[0x08/4] = 0xffffffff;
1944 r32[0x0c/4] = 0xffffffff;
1945 r16[0x10/2] = 0xffff;
1946 r32[0x14/4] = 0xffffffff;
1947 r32[0x18/4] = 0xffffffff;
1948 r32[0x1c/4] = 0xffffffff;
1949 mem_barrier();
1950 expect(ok, r16[0x00/2], 0x82);
1951 expect(ok, r16[0x02/2], 0x03);
1952 expect(ok, r16[0x04/2], 0x03);
1953 expect(ok, r16[0x06/2], 0x07);
1954 expect(ok, r32[0x08/4], 0x00fffffe);
1955 expect(ok, r32[0x0c/4], 0x00ffffff);
1956 expect(ok, r16[0x10/2], 0xfffc);
1957 expect(ok, r32[0x14/4], 0);
1958 expect(ok, r16[0x18/2], 0);
1959 expect(ok, r16[0x1a/2], 0x0101);
1960 expect(ok, r32[0x1c/4], 0);
1961 r16[0x02/2] = 0;
1962 r32[0x04/4] = 0;
5073ab5a 1963 r32[0x08/4] = 0;
1964 r32[0x0c/4] = 0;
c8abdf56 1965 r16[0x1a/2] = 0;
9d39a80e 1966
1967 // could just set RV, but BIOS reads ROM, so can't
1968 memcpy_(do_32x_enable, x32x_enable,
1969 x32x_enable_end - x32x_enable);
1970 do_32x_enable();
1971
1972 expect(ok, r16[0x00/2], 0x83);
1973 expect(ok, r16[0x02/2], 0);
1974 expect(ok, r16[0x04/2], 0);
1975 expect(ok, r16[0x06/2], 1); // RV
5073ab5a 1976 expect(ok, r32[0x14/4], 0);
1977 expect(ok, r32[0x18/4], 0);
1978 expect(ok, r32[0x1c/4], 0);
1979 expect(ok, r32[0x20/4], M_OK);
9d39a80e 1980 while (!read16(&r16[0x24/2]))
1981 ;
5073ab5a 1982 expect(ok, r32[0x24/4], S_OK);
1983 write32(&r32[0x20/4], 0);
1984 if (!(r16[0x00/2] & 0x8000)) {
1985 expect(ok, r8 [0x81], 0);
1986 expect(ok, r16[0x82/2], 0);
1987 expect(ok, r16[0x84/2], 0);
1988 expect(ok, r16[0x86/2], 0);
1989 //expect(ok, r16[0x88/2], 0); // triggers fill?
1990 expect(ok, r8 [0x8b] & ~2, 0);
1991 expect(ok, r16[0x8c/2], 0);
1992 expect(ok, r16[0x8e/2], 0);
06d7984c 1993 }
5073ab5a 1994 return ok;
9d39a80e 1995}
1996
1997static int t_32x_echo(void)
1998{
6474d733 1999 u16 *r16 = (u16 *)0xa15100;
9d39a80e 2000 int ok = 1;
2001
6474d733 2002 r16[0x2c/2] = r16[0x2e/2] = 0;
06d7984c 2003 x32_cmd(CMD_ECHO, 0x12340000, 0, 0);
6474d733 2004 expect_sh2(ok, 0, r16[0x26/2], 0x1234);
06d7984c 2005 x32_cmd(CMD_ECHO, 0x23450000, 0, 1);
6474d733 2006 expect_sh2(ok, 1, r16[0x26/2], 0xa345);
2007 expect(ok, r16[0x2c/2], 0); // no last_irq_vec
2008 expect(ok, r16[0x2e/2], 0); // no exception_index
5073ab5a 2009 return ok;
2010}
2011
2012static int t_32x_sh_defaults(void)
2013{
2014 u32 *r32 = (u32 *)0xa15120;
2015 int ok = 1, s;
2016
2017 for (s = 0; s < 2; s++)
2018 {
2019 x32_cmd(CMD_READ32, 0x20004000, 0, s);
2020 expect_sh2(ok, s, r32[0x04/4], 0x02000000); // ADEN
2021 x32_cmd(CMD_READ32, 0x20004004, 0, s);
2022 expect_sh2(ok, s, r32[0x04/4], 0x00004001); // Empty Rv
2023 x32_cmd(CMD_READ32, 0x20004008, 0, s);
2024 expect_sh2(ok, s, r32[0x04/4], 0);
2025 x32_cmd(CMD_READ32, 0x2000400c, 0, s);
2026 expect_sh2(ok, s, r32[0x04/4], 0);
2027 x32_cmd(CMD_GETGBR, 0, 0, s);
2028 expect_sh2(ok, s, r32[0x04/4], 0x20004000);
2029 }
06d7984c 2030 return ok;
2031}
2032
2033static int t_32x_md_bios(void)
2034{
2035 void (*do_call_c0)(int a, int d) = (void *)0xff0040;
2036 u8 *rmb = (u8 *)0xff0000;
2037 u32 *rl = (u32 *)0;
2038 int ok = 1;
2039
2040 memcpy_(do_call_c0, test_32x_b_c0,
2041 test_32x_b_c0_end - test_32x_b_c0);
2042 write8(rmb, 0);
2043 do_call_c0(0xff0000, 0x5a);
2044
2045 expect(ok, rmb[0], 0x5a);
2046 expect(ok, rl[0x04/4], 0x880200);
234c4556 2047 expect(ok, rl[0x10/4], 0x880212);
2048 expect(ok, rl[0x94/4], 0x8802d8);
9d39a80e 2049 return ok;
2050}
2051
2052static int t_32x_md_rom(void)
2053{
2054 u32 *rl = (u32 *)0;
2055 int ok = 1;
2056
2057 expect(ok, rl[0x004/4], 0x880200);
2058 expect(ok, rl[0x100/4], 0x53454741);
2059 expect(ok, rl[0x70/4], 0);
71b41fdd 2060 write32(&rl[0x70/4], 0xa5123456);
9d39a80e 2061 write32(&rl[0x78/4], ~0);
2062 mem_barrier();
9d39a80e 2063 expect(ok, rl[0x78/4], 0x8802ae);
71b41fdd 2064 expect(ok, rl[0x70/4], 0xa5123456);
2065 //expect(ok, rl[0x1070/4], v1070);
2066 write32(&rl[0x70/4], 0);
2067 // with RV 0x880000/0x900000 hangs, can't test
9d39a80e 2068 return ok;
2069}
2070
06d7984c 2071static int t_32x_md_fb(void)
2072{
2073 u8 *fbb = (u8 *)0x840000;
2074 u16 *fbw = (u16 *)fbb;
2075 u32 *fbl = (u32 *)fbb;
2076 u8 *fob = (u8 *)0x860000;
2077 u16 *fow = (u16 *)fob;
2078 u32 *fol = (u32 *)fob;
2079 int ok = 1;
2080
2081 fbl[0] = 0x12345678;
2082 fol[1] = 0x89abcdef;
2083 mem_barrier();
2084 expect(ok, fbw[1], 0x5678);
2085 expect(ok, fow[2], 0x89ab);
2086 fbb[0] = 0;
2087 fob[1] = 0;
2088 fbw[1] = 0;
2089 fow[2] = 0;
2090 fow[3] = 1;
2091 mem_barrier();
2092 fow[3] = 0x200;
2093 mem_barrier();
2094 expect(ok, fol[0], 0x12340000);
2095 expect(ok, fbl[1], 0x89ab0201);
2096 return ok;
2097}
2098
2099static int t_32x_sh_fb(void)
2100{
2101 u32 *fbl = (u32 *)0x840000;
5073ab5a 2102 u8 *r8 = (u8 *)0xa15100;
06d7984c 2103 int ok = 1;
2104
5073ab5a 2105 if (read8(r8) & 0x80)
2106 write8(r8, 0x00); // FM=0
06d7984c 2107 fbl[0] = 0x12345678;
2108 fbl[1] = 0x89abcdef;
2109 mem_barrier();
5073ab5a 2110 write8(r8, 0x80); // FM=1
2111 x32_cmd(CMD_WRITE8, 0x24000000, 0, 0); // should ignore
2112 x32_cmd(CMD_WRITE8, 0x24020001, 0, 0); // ignore
2113 x32_cmd(CMD_WRITE16, 0x24000002, 0, 0); // ok
2114 x32_cmd(CMD_WRITE16, 0x24020000, 0, 0); // ignore
06d7984c 2115 x32_cmd(CMD_WRITE32, 0x24020004, 0x5a0000a5, 1);
5073ab5a 2116 write8(r8, 0x00); // FM=0
06d7984c 2117 mem_barrier();
2118 expect(ok, fbl[0], 0x12340000);
2119 expect(ok, fbl[1], 0x5aabcda5);
2120 return ok;
2121}
2122
5073ab5a 2123static int t_32x_irq(void)
234c4556 2124{
5073ab5a 2125 u32 *fbl_icnt = (u32 *)(0x840000 + IRQ_CNT_FB_BASE);
2126 u16 *m_icnt = (u16 *)fbl_icnt;
2127 u16 *s_icnt = m_icnt + 8;
234c4556 2128 u32 *r = (u32 *)0xa15100;
2129 u16 *r16 = (u16 *)r;
6474d733 2130 u8 *r8 = (u8 *)r;
5073ab5a 2131 int ok = 1, i;
234c4556 2132
5073ab5a 2133 write8(r, 0x00); // FM=0
6474d733 2134 r[0x2c/4] = 0;
5073ab5a 2135 mem_barrier();
2136 for (i = 0; i < 8; i++)
2137 write32(&fbl_icnt[i], 0);
2138 mem_barrier();
2139 write16(&r16[0x02/2], 0xfffd); // INTM+unused_bits
2140 mem_barrier();
2141 expect(ok, r16[0x02/2], 1);
2142 x32_cmd(CMD_WRITE8, 0x20004001, 2, 0); // unmask cmd
2143 x32_cmd(CMD_WRITE8, 0x20004001, 2, 1); // unmask cmd slave
2144 burn10(10);
2145 write8(r, 0x00); // FM=0 (hangs without)
2146 mem_barrier();
2147 expect(ok, r16[0x02/2], 0);
6474d733 2148 expect(ok, r8 [0x2c], 4);
2149 expect(ok, r8 [0x2d], 0);
2150 expect(ok, r16[0x2e/2], 0); // no exception_index
5073ab5a 2151 expect(ok, m_icnt[4], 1);
2152 expect(ok, s_icnt[4], 0);
2153 write16(&r16[0x02/2], 0xaaaa); // INTS+unused_bits
2154 mem_barrier();
2155 expect(ok, r16[0x02/2], 2);
2156 burn10(10);
2157 mem_barrier();
2158 expect(ok, r16[0x02/2], 0);
6474d733 2159 expect(ok, r8 [0x2c], 4);
2160 expect(ok, r8 [0x2d], 4);
2161 expect(ok, r16[0x2e/2], 0); // no exception_index
5073ab5a 2162 write8(r, 0x00); // FM=0
2163 mem_barrier();
2164 expect(ok, m_icnt[4], 1);
2165 expect(ok, s_icnt[4], 1);
2166 for (i = 0; i < 8; i++) {
2167 if (i == 4)
2168 continue;
2169 expect(ok, m_icnt[i], 0);
2170 expect(ok, s_icnt[i], 0);
2171 }
2172 return ok;
2173}
234c4556 2174
5073ab5a 2175static int t_32x_reg_w(void)
2176{
2177 u32 *r32 = (u32 *)0xa15100;
2178 u16 *r16 = (u16 *)r32, old;
2179 int ok = 1;
234c4556 2180
5073ab5a 2181 r32[0x08/4] = ~0;
2182 r32[0x0c/4] = ~0;
2183 r16[0x10/2] = ~0;
2184 mem_barrier();
2185 expect(ok, r32[0x08/4], 0xfffffe);
2186 expect(ok, r32[0x0c/4], 0xffffff);
2187 expect(ok, r16[0x10/2], 0xfffc);
2188 mem_barrier();
2189 r32[0x08/4] = r32[0x0c/4] = 0;
2190 r16[0x10/2] = 0;
2191 old = r16[0x06/2];
2192 x32_cmd(CMD_WRITE16, 0x20004006, ~old, 0);
2193 expect(ok, r16[0x06/2], old);
2194 return ok;
2195}
234c4556 2196
5073ab5a 2197// prepare for reset btn press tests
2198static int t_32x_reset_prep(void)
2199{
7449b889 2200 u32 *fbl = (u32 *)0x840000;
2201 u32 *fbl_icnt = fbl + IRQ_CNT_FB_BASE / 4;
5073ab5a 2202 u32 *r32 = (u32 *)0xa15100;
2203 u16 *r16 = (u16 *)r32;
2204 u8 *r8 = (u8 *)r32;
2205 int ok = 1, i;
2206
2207 expect(ok, r16[0x00/2], 0x83);
2208 write8(r8, 0x00); // FM=0
6474d733 2209 r32[0x2c/4] = 0;
234c4556 2210 mem_barrier();
5073ab5a 2211 expect(ok, r8[0x8b] & ~2, 0);
2212 for (i = 0; i < 8; i++)
2213 write32(&fbl_icnt[i], 0x01000100);
2214 x32_cmd(CMD_WRITE8, 0x20004001, 0x02, 0); // unmask cmd
2215 x32_cmd(CMD_WRITE8, 0x20004001, 0x02, 1); // unmask slave
ec8170d9 2216 x32_cmd(CMD_SETSR, 0xf0, 0, 1); // mask slave irqs (on the cpu)
5073ab5a 2217 burn10(10);
2218 write8(r8, 0x00); // FM=0
6474d733 2219 expect(ok, r32[0x2c/4], 0);
5073ab5a 2220 mem_barrier();
2221 for (i = 0; i < 8; i++)
2222 expect(ok, fbl_icnt[i], 0x01000100);
2223
2224 r16[0x04/2] = 0xffff;
2225 r32[0x08/4] = 0x5a5a5a08;
2226 r32[0x0c/4] = 0x5a5a5a0c;
2227 r16[0x10/2] = 0x5a10;
2228 r32[0x20/4] = 0x00005a20; // no x32_cmd
2229 r32[0x24/4] = 0x5a5a5a24;
2230 r32[0x28/4] = 0x5a5a5a28;
2231 r32[0x2c/4] = 0x5a5a5a2c;
7449b889 2232 if (!(r16[0x00/2] & 0x8000)) {
2233 wait_next_vsync();
2234 r16[0x8a/2] = 0x0001;
2235 mem_barrier();
2236 for (i = 0; i < 220/2; i++)
2237 fbl[i] = 0;
2238 r8 [0x81] = 1;
2239 r16[0x82/2] = 0xffff;
2240 r16[0x84/2] = 0xffff;
2241 r16[0x86/2] = 0xffff;
2242 r16[0x8a/2] = 0x0000;
2243 r16[0x8c/2] = 0xffff;
2244 r16[0x8e/2] = 0xffff;
2245 r16[0x100/2] = 0;
2246 }
234c4556 2247 return ok;
2248}
2249
9d39a80e 2250enum {
2251 T_MD = 0,
2252 T_32 = 1, // 32X
2253};
2254
ffd4b35c 2255static const struct {
9d39a80e 2256 u8 type;
ffd4b35c 2257 int (*test)(void);
2258 const char *name;
2259} g_tests[] = {
5073ab5a 2260 // this must be first to disable the 32x and restore the 68k vector table
2261 { T_32, t_32x_reset_btn, "32x resetbtn" },
2262
9d39a80e 2263 { T_MD, t_dma_zero_wrap, "dma zero len + wrap" },
2264 { T_MD, t_dma_zero_fill, "dma zero len + fill" },
2265 { T_MD, t_dma_ram_wrap, "dma ram wrap" },
2266 { T_MD, t_dma_multi, "dma multi" },
2267 { T_MD, t_dma_cram_wrap, "dma cram wrap" },
2268 { T_MD, t_dma_vsram_wrap, "dma vsram wrap" },
2269 { T_MD, t_dma_and_data, "dma and data" },
2270 { T_MD, t_dma_short_cmd, "dma short cmd" },
2271 { T_MD, t_dma_fill3_odd, "dma fill3 odd" },
2272 { T_MD, t_dma_fill3_even, "dma fill3 even" },
9d39a80e 2273 { T_MD, t_dma_fill3_vsram, "dma fill3 vsram" },
9d39a80e 2274 { T_MD, t_dma_fill_dis, "dma fill disabled" },
2275 { T_MD, t_dma_fill_src, "dma fill src incr" },
2276 { T_MD, t_dma_128k, "dma 128k mode" },
2277 { T_MD, t_vdp_128k_b16, "vdp 128k addr bit16" },
a385208c 2278 // { t_vdp_128k_b16_inc, "vdp 128k bit16 inc" }, // mystery
9d39a80e 2279 { T_MD, t_vdp_reg_cmd, "vdp reg w cmd reset" },
2280 { T_MD, t_vdp_sr_vb, "vdp status reg vb" },
2281 { T_MD, t_z80mem_long_mirror, "z80 ram long mirror" },
2282 { T_MD, t_z80mem_noreq_w, "z80 ram noreq write" },
2283 { T_MD, t_z80mem_vdp_r, "z80 vdp read" },
ffd4b35c 2284 // { t_z80mem_vdp_w, "z80 vdp write" }, // hang
9d39a80e 2285 { T_MD, t_tim_loop, "time loop" },
e71680d5 2286 { T_MD, t_tim_z80_loop, "time z80 loop" },
9d39a80e 2287 { T_MD, t_tim_z80_ram, "time z80 ram" },
2288 { T_MD, t_tim_z80_ym, "time z80 ym2612" },
2289 { T_MD, t_tim_z80_vdp, "time z80 vdp" },
2290 { T_MD, t_tim_z80_bank_rom, "time z80 bank rom" },
2291 { T_MD, t_tim_vcnt, "time V counter" },
e71680d5 2292 { T_MD, t_tim_vcnt_loops, "time vcnt loops" },
9d39a80e 2293 { T_MD, t_tim_hblank_h40, "time hblank h40" },
2294 { T_MD, t_tim_hblank_h32, "time hblank h32" },
2295 { T_MD, t_tim_vdp_as_vram_w, "time vdp vram w" },
2296 { T_MD, t_tim_vdp_as_cram_w, "time vdp cram w" },
e71680d5 2297 { T_MD, t_tim_ym_timera_z80, "time timer a z80" },
2298 { T_MD, t_tim_ym_timerb_z80, "time timer b z80" },
2299 { T_MD, t_tim_ym_timerb_stop, "timer b stop" },
2300 { T_MD, t_tim_ym_timer_ab_sync,"timer ab sync" },
9d39a80e 2301 { T_MD, t_irq_hint, "irq4 / line" },
8517a6df 2302 { T_MD, t_irq_both_cpu_unmask, "irq both umask" },
9d39a80e 2303 { T_MD, t_irq_ack_v_h, "irq ack v-h" },
2304 { T_MD, t_irq_ack_v_h_2, "irq ack v-h 2" },
2305 { T_MD, t_irq_ack_h_v, "irq ack h-v" },
2306 { T_MD, t_irq_ack_h_v_2, "irq ack h-v 2" },
2307 { T_MD, t_irq_f_flag_h40, "irq f flag h40" },
9d39a80e 2308 { T_MD, t_irq_f_flag_h32, "irq f flag h32" },
2309
06d7984c 2310 // the first one enables 32X, so must be kept
2311 // all tests assume RV=1 FM=0
9d39a80e 2312 { T_32, t_32x_init, "32x init" },
2313 { T_32, t_32x_echo, "32x echo" },
5073ab5a 2314 { T_32, t_32x_sh_defaults, "32x sh def" },
06d7984c 2315 { T_32, t_32x_md_bios, "32x md bios" },
2316 { T_32, t_32x_md_rom, "32x md rom" },
2317 { T_32, t_32x_md_fb, "32x md fb" },
2318 { T_32, t_32x_sh_fb, "32x sh fb" },
5073ab5a 2319 { T_32, t_32x_irq, "32x irq" },
2320 { T_32, t_32x_reg_w, "32x reg w" },
2321 { T_32, t_32x_reset_prep, "32x rstprep" }, // must be last 32x
ffd4b35c 2322};
2323
2324static void setup_z80(void)
2325{
2326 u8 *zram = (u8 *)0xa00000;
2327 int i, len;
2328
2329 /* z80 */
2330 write16(0xa11100, 0x100);
2331 write16(0xa11200, 0x100);
2332
2333 while (read16(0xa11100) & 0x100)
2334 ;
2335
2336 // load the default test program, clear it's data
2337 len = z80_test_end - z80_test;
2338 for (i = 0; i < len; i++)
2339 write8(&zram[i], z80_test[i]);
2340 for (i = 0x1000; i < 0x1007; i++)
2341 write8(&zram[i], 0);
a385208c 2342
2343 // reset
2344 write16(0xa11200, 0x000);
2345 write16(0xa11100, 0x000);
2346 burn10(1);
2347 write16(0xa11200, 0x100);
e71680d5 2348
2349 burn10(50 * 15 / 7 / 10); // see z80_test.s80
a385208c 2350
2351 // take back the bus
2352 write16(0xa11100, 0x100);
2353 while (read16(0xa11100) & 0x100)
2354 ;
2355}
2356
cc7e5122 2357static unused int hexinc(char *c)
a385208c 2358{
2359 (*c)++;
2360 if (*c > 'f') {
2361 *c = '0';
2362 return 1;
2363 }
2364 if (*c == '9' + 1)
2365 *c = 'a';
2366 return 0;
ffd4b35c 2367}
2368
2369int main()
2370{
5073ab5a 2371 void (*px32x_switch_rv)(short rv);
2372 short (*pget_input)(void) = get_input;
ffd4b35c 2373 int passed = 0;
9d39a80e 2374 int skipped = 0;
2375 int have_32x;
234c4556 2376 int en_32x;
ffd4b35c 2377 int ret;
a385208c 2378 u8 v8;
ffd4b35c 2379 int i;
2380
2381 setup_z80();
2382
a385208c 2383 /* io */
2384 write8(0xa10009, 0x40);
2385
ffd4b35c 2386 /* setup VDP */
2387 while (read16(VDP_CTRL_PORT) & 2)
2388 ;
2389
2390 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
2391 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA);
2392 VDP_setReg(VDP_MODE3, 0x00);
2393 VDP_setReg(VDP_MODE4, 0x81);
2394 VDP_setReg(VDP_NT_SCROLLA, APLANE >> 10);
2395 VDP_setReg(VDP_NT_SCROLLB, BPLANE >> 13);
2396 VDP_setReg(VDP_SAT_BASE, SLIST >> 9);
2397 VDP_setReg(VDP_HSCROLL, HSCRL >> 10);
2398 VDP_setReg(VDP_AUTOINC, 2);
2399 VDP_setReg(VDP_SCROLLSZ, 0x01);
2400 VDP_setReg(VDP_BACKDROP, 0);
2401
2402 // early tests
2403 t_dma_zero_wrap_early();
2404 t_dma_zero_fill_early();
2405
2406 /* pattern 0 */
2407 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
2408 for (i = 0; i < 32 / 4; i++)
2409 write32(VDP_DATA_PORT, 0);
2410
2411 /* clear name tables */
2412 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(APLANE));
2413 for (i = 0; i < PLANE_W * PLANE_H / 2; i++)
2414 write32(VDP_DATA_PORT, 0);
2415
2416 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(BPLANE));
2417 for (i = 0; i < PLANE_W * PLANE_H / 2; i++)
2418 write32(VDP_DATA_PORT, 0);
2419
2420 /* SAT, h. scroll */
2421 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(SLIST));
2422 write32(VDP_DATA_PORT, 0);
2423
2424 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(HSCRL));
2425 write32(VDP_DATA_PORT, 0);
2426
2427 /* scroll plane vscroll */
2428 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
2429 write32(VDP_DATA_PORT, 0);
2430 printf_ypos = 1;
2431
2432 /* load font */
2433 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(TILE_FONT_BASE));
2434 for (i = 0; i < FONT_LEN * 32 / 4; i++)
2435 write32(VDP_DATA_PORT, font_base[i]);
2436
2437 /* set colors */
2438 setup_default_palette();
2439
2440 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
2441
9d39a80e 2442 have_32x = read32(0xa130ec) == MKLONG('M','A','R','S');
5073ab5a 2443 en_32x = have_32x && (read16(0xa15100) & 1);
a385208c 2444 v8 = read8(0xa10001);
234c4556 2445 printf("MD version: %02x %s %s %s%s\n", v8,
a385208c 2446 (v8 & 0x80) ? "world" : "jap",
9d39a80e 2447 (v8 & 0x40) ? "pal" : "ntsc",
234c4556 2448 have_32x ? "32X" : "",
2449 en_32x ? "+" : "");
7449b889 2450 printf("reset hvc %04x->%04x\n", read16(-4), read16(-2));
2451
2452 // sanity check
2453 extern u32 sh2_test[];
2454 if (sh2_test[0] != read32(0x3e0) || sh2_test[0x200/4] != read32(0x3e4))
2455 printf("bad 0x3c0 tab\n");
ffd4b35c 2456
2457 for (i = 0; i < ARRAY_SIZE(g_tests); i++) {
2458 // print test number if we haven't scrolled away
2459 if (printf_ypos < CSCREEN_H) {
2460 int old_ypos = printf_ypos;
2461 printf_ypos = 0;
ffd4b35c 2462 printf("%02d/%02d", i, ARRAY_SIZE(g_tests));
2463 printf_ypos = old_ypos;
2464 printf_xpos = 0;
2465 }
9d39a80e 2466 if ((g_tests[i].type & T_32) && !have_32x) {
2467 skipped++;
2468 continue;
2469 }
ffd4b35c 2470 ret = g_tests[i].test();
5073ab5a 2471 if (ret == R_SKIP) {
2472 skipped++;
2473 continue;
2474 }
a385208c 2475 if (ret != 1) {
2476 text_pal = 2;
ffd4b35c 2477 printf("failed %d: %s\n", i, g_tests[i].name);
a385208c 2478 text_pal = 0;
2479 }
ffd4b35c 2480 else
2481 passed++;
2482 }
2483
2484 text_pal = 0;
9d39a80e 2485 printf("%d/%d passed, %d skipped.\n",
2486 passed, ARRAY_SIZE(g_tests), skipped);
ffd4b35c 2487
2488 printf_ypos = 0;
2489 printf(" ");
2490
7449b889 2491 if (have_32x && (read16(0xa15100) & 1)) {
5073ab5a 2492 u8 *p = (u8 *)0xff0040;
2493 u32 len = x32x_switch_rv_end - x32x_switch_rv;
2494 px32x_switch_rv = (void *)p; p += len;
2495 memcpy_(px32x_switch_rv, x32x_switch_rv, len);
2496
2497 len = get_input_end - get_input_s;
2498 pget_input = (void *)p; p += len;
2499 memcpy_(pget_input, get_input_s, len);
2500
2501 // prepare for reset - run from 880xxx as the reset vector points there
2502 // todo: broken printf
2503 px32x_switch_rv(0);
2504 }
7449b889 2505 for (i = 0; i < 60*60 && !(pget_input() & BTNM_A); i++) {
2506 while (read16(VDP_CTRL_PORT) & SR_VB)
2507 write16(-4, read16(VDP_HV_COUNTER)); /* blanking */
2508 while (!(read16(VDP_CTRL_PORT) & SR_VB))
2509 write16(-4, read16(VDP_HV_COUNTER)); /* not blanking */;
2510 }
e71680d5 2511#ifndef PICO
2512 // blank due to my lame tv being burn-in prone
2513 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
2514#endif
5073ab5a 2515 while (!(pget_input() & BTNM_A))
7449b889 2516 write16(-4, read16(VDP_HV_COUNTER));
e71680d5 2517 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
a385208c 2518
2519
2520 {
2521 char c[3] = { '0', '0', '0' };
2522 short hscroll = 0, vscroll = 0;
2523 short hsz = 1, vsz = 0;
2524 short cellmode = 0;
2525
2526 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(APLANE));
2527
cc7e5122 2528#if 0
2529 for (i = 0, c[0] = 'a'; i < 8 * 1024 / 2; i++) {
2530 write16(VDP_DATA_PORT, (u16)c[0] - 32 + TILE_FONT_BASE / 32);
2531 c[0]++;
2532 if (c[0] == 'z' + 1)
2533 c[0] = 'a';
2534 }
2535#else
a385208c 2536 for (i = 0; i < 8 * 1024 / 2 / 4; i++) {
2537 write16(VDP_DATA_PORT, (u16)'.' - 32 + TILE_FONT_BASE / 32);
2538 write16(VDP_DATA_PORT, (u16)c[2] - 32 + TILE_FONT_BASE / 32);
2539 write16(VDP_DATA_PORT, (u16)c[1] - 32 + TILE_FONT_BASE / 32);
2540 write16(VDP_DATA_PORT, (u16)c[0] - 32 + TILE_FONT_BASE / 32);
2541 if (hexinc(&c[0]))
2542 if (hexinc(&c[1]))
2543 hexinc(&c[2]);
2544 }
cc7e5122 2545#endif
5073ab5a 2546 while (pget_input() & BTNM_A)
a385208c 2547 wait_next_vsync();
2548
2549 wait_next_vsync();
2550 for (;;) {
5073ab5a 2551 int b = pget_input();
a385208c 2552
2553 if (b & BTNM_C) {
2554 hscroll = 1, vscroll = -1;
2555 do {
2556 wait_next_vsync();
5073ab5a 2557 } while (pget_input() & BTNM_C);
a385208c 2558 cellmode ^= 1;
2559 }
2560 if (b & (BTNM_L | BTNM_R | BTNM_C)) {
2561 hscroll += (b & BTNM_L) ? 1 : -1;
2562 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(HSCRL));
2563 write16(VDP_DATA_PORT, hscroll);
2564 }
2565 if (b & (BTNM_U | BTNM_D | BTNM_C)) {
2566 vscroll += (b & BTNM_U) ? -1 : 1;
2567 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
2568 if (cellmode) {
2569 int end = (int)vscroll + 21;
2570 for (i = vscroll; i < end; i++)
2571 write32(VDP_DATA_PORT, i << 17);
2572 VDP_setReg(VDP_MODE3, 0x04);
2573 }
2574 else {
2575 write16(VDP_DATA_PORT, vscroll);
2576 VDP_setReg(VDP_MODE3, 0x00);
2577 }
2578 }
2579 if (b & BTNM_A) {
2580 hsz = (hsz + 1) & 3;
2581 do {
2582 wait_next_vsync();
5073ab5a 2583 } while (pget_input() & BTNM_A);
a385208c 2584 }
2585 if (b & BTNM_B) {
2586 vsz = (vsz + 1) & 3;
2587 do {
2588 wait_next_vsync();
5073ab5a 2589 } while (pget_input() & BTNM_B);
a385208c 2590 }
2591 VDP_setReg(VDP_SCROLLSZ, (vsz << 4) | hsz);
2592
2593 printf_xpos = 1;
2594 printf_ypos = 0;
2595 text_pal = 1;
2596 printf(" %d %d ", hsz, vsz);
2597
2598 wait_next_vsync();
2599 }
2600 }
2601
ffd4b35c 2602 for (;;)
2603 ;
2604
2605 return 0;
2606}
2607
2608// vim:ts=4:sw=4:expandtab
Genesis/MegaDrive related projects