TIMER_REG(0x44) = ((timer_div - 1) << 4) | 2; /* using PLL1 */
TIMER_REG(0x40) = 0x0c; /* clocks on */
TIMER_REG(0x08) = 0x68 | timer_div2; /* run timer, clear irq, latch value */
TIMER_REG(0x44) = ((timer_div - 1) << 4) | 2; /* using PLL1 */
TIMER_REG(0x40) = 0x0c; /* clocks on */
TIMER_REG(0x08) = 0x68 | timer_div2; /* run timer, clear irq, latch value */
plat_target.cpu_clock_set = pollux_cpu_clock_set;
plat_target.bat_capacity_get = pollux_bat_capacity_get;
plat_target.step_volume = step_volume;
plat_target.cpu_clock_set = pollux_cpu_clock_set;
plat_target.bat_capacity_get = pollux_bat_capacity_get;
plat_target.step_volume = step_volume;