optimizations, bugfixes, uae works (but with timing glitches?)

[picodrive.git] / cpu / Cyclone / config.h

diff --git a/cpu/Cyclone/config.h b/cpu/Cyclone/config.h
index ded00b1..24b73a1 100644 (file)
--- a/cpu/Cyclone/config.h
+++ b/cpu/Cyclone/config.h
@@ -18,7 +18,7 @@
  * the write-back phase. That will be emulated, if this option is enabled.\r
  * This option also alters timing slightly.\r
  */\r
-#define CYCLONE_FOR_GENESIS       1\r
+#define CYCLONE_FOR_GENESIS       0\r
 \r
 /*\r
  * This option compresses Cyclone's jumptable. Because of this the executable\r
@@ -35,24 +35,30 @@
  * Using 0xff000000 means that only 24 least significant bits should be used.\r
  * Set to 0 if you want to mask unused address bits in the memory handlers yourself.\r
  */\r
-#define MEMHANDLERS_ADDR_MASK     0xff000000\r
+#define MEMHANDLERS_ADDR_MASK     0\r
 \r
 /*\r
  * Cyclone keeps the 4 least significant bits of SR, PC+membase and it's cycle\r
  * count in ARM registers instead of the context for performance reasons. If you for\r
  * any reason need to access them in your memory handlers, enable the options below,\r
  * otherwise disable them to improve performance.\r
- * PC value will point to start of instruction currently executed.\r
+ * MEMHANDLERS_NEED_PC updates .pc context field with PC value effective at the time\r
+ * when memhandler was called (opcode address + unknown amount).\r
+ * MEMHANDLERS_NEED_PREV_PC updates .prev_pc context field to currently executed\r
+ * opcode address + 2.\r
+ * Note that .pc and .prev_pc values are always real pointers to memory, so you must\r
+ * subtract .membase to get M68k PC value.\r
  * Warning: updating PC in memhandlers is dangerous, as Cyclone may internally\r
  * increment the PC before fetching the next instruction and continue executing\r
  * at wrong location.\r
  */\r
-#define MEMHANDLERS_NEED_PC       0\r
+#define MEMHANDLERS_NEED_PC       1\r
+#define MEMHANDLERS_NEED_PREV_PC  0\r
 #define MEMHANDLERS_NEED_FLAGS    0\r
 #define MEMHANDLERS_NEED_CYCLES   1\r
 #define MEMHANDLERS_CHANGE_PC     0\r
 #define MEMHANDLERS_CHANGE_FLAGS  0\r
-#define MEMHANDLERS_CHANGE_CYCLES 0\r
+#define MEMHANDLERS_CHANGE_CYCLES 1\r
 \r
 /*\r
  * If enabled, Cyclone will call IrqCallback routine from it's context whenever it\r
@@ -73,7 +79,7 @@
  * encountered. All context members are valid and can be changed.\r
  * If disabled, RESET opcode acts as an NOP.\r
  */\r
-#define USE_RESET_CALLBACK        1\r
+#define USE_RESET_CALLBACK        0\r
 \r
 /*\r
  * If enabled, UnrecognizedCallback is called if an invalid opcode is\r
@@ -101,6 +107,19 @@
  */\r
 #define USE_CHECKPC_CALLBACK      1\r
 \r
+/*\r
+ * This determines if checkpc() should be called after jumps when 8 and 16 bit\r
+ * displacement values were used.\r
+ */\r
+#define USE_CHECKPC_OFFSETBITS_16 1\r
+#define USE_CHECKPC_OFFSETBITS_8  0\r
+\r
+/*\r
+ * Call checkpc() after DBcc jumps (which use 16bit displacement). Cyclone prior to\r
+ * 0.0087 never did that.\r
+ */\r
+#define USE_CHECKPC_DBRA          0\r
+\r
 /*\r
  * When this option is enabled Cyclone will do two word writes instead of one\r
  * long write when handling MOVE.L with pre-decrementing destination, as described in\r