Sonic CD runs on GP2X

[libpicofe.git] / gp2x / 940init.s

diff --git a/gp2x/940init.s b/gp2x/940init.s
index e28b453..771511f 100644 (file)
--- a/gp2x/940init.s
+++ b/gp2x/940init.s
@@ -31,9 +31,9 @@ code940:                          @ interrupt table:
     b       .Begin\r
 .b_irq:\r
     mov     r12, #6\r
-       mov     sp, #0x100000       @ reset stack\r
-       sub     sp, sp, #4\r
-    mov     r1, #0xbd000000     @ assume we live @ 0x3000000 bank\r
+    mov     sp, #0x100000       @ reset stack\r
+    sub     sp, sp, #4\r
+    mov     r1, #0xbe000000     @ assume we live @ 0x2000000 bank\r
     orr     r2, r1, #0x3B00\r
     orr     r2, r2, #0x0046\r
     mvn     r3, #0\r
@@ -48,51 +48,51 @@ code940:                          @ interrupt table:
     b       .Begin\r
 \r
 .Begin:\r
-       mov sp, #0x100000           @ set the stack top (1M)\r
-       sub sp, sp, #4              @ minus 4\r
+    mov sp, #0x100000           @ set the stack top (1M)\r
+    sub sp, sp, #4              @ minus 4\r
 \r
-       @ set up memory region 0 -- the whole 4GB address space\r
-       mov r0, #(0x1f<<1)|1        @ region data\r
-       mcr p15, 0, r0, c6, c0, 0   @ opcode2 ~ data/instr\r
-       mcr p15, 0, r0, c6, c0, 1\r
+    @ set up memory region 0 -- the whole 4GB address space\r
+    mov r0, #(0x1f<<1)|1        @ region data\r
+    mcr p15, 0, r0, c6, c0, 0   @ opcode2 ~ data/instr\r
+    mcr p15, 0, r0, c6, c0, 1\r
 \r
     @ set up region 1 which is the first 2 megabytes.\r
-       mov r0, #(0x14<<1)|1        @ region data\r
-       mcr p15, 0, r0, c6, c1, 0\r
-       mcr p15, 0, r0, c6, c1, 1\r
+    mov r0, #(0x14<<1)|1        @ region data\r
+    mcr p15, 0, r0, c6, c1, 0\r
+    mcr p15, 0, r0, c6, c1, 1\r
 \r
     @ set up region 2: 64k 0x200000-0x210000\r
-       mov r0, #(0x0f<<1)|1\r
+    mov r0, #(0x0f<<1)|1\r
     orr r0, r0, #0x200000\r
-       mcr p15, 0, r0, c6, c2, 0\r
-       mcr p15, 0, r0, c6, c2, 1\r
+    mcr p15, 0, r0, c6, c2, 0\r
+    mcr p15, 0, r0, c6, c2, 1\r
 \r
-    @ set up region 3: 64k 0xbd000000-0xbd010000 (hw control registers)\r
-       mov r0, #(0x0f<<1)|1\r
-    orr r0, r0, #0xbd000000\r
-       mcr p15, 0, r0, c6, c3, 0\r
-       mcr p15, 0, r0, c6, c3, 1\r
+    @ set up region 3: 64k 0xbe000000-0xbe010000 (hw control registers)\r
+    mov r0, #(0x0f<<1)|1\r
+    orr r0, r0, #0xbe000000\r
+    mcr p15, 0, r0, c6, c3, 0\r
+    mcr p15, 0, r0, c6, c3, 1\r
 \r
     @ set region 1 to be cacheable (so the first 2M will be cacheable)\r
-       mov r0, #2\r
-       mcr p15, 0, r0, c2, c0, 0\r
-       mcr p15, 0, r0, c2, c0, 1\r
+    mov r0, #2\r
+    mcr p15, 0, r0, c2, c0, 0\r
+    mcr p15, 0, r0, c2, c0, 1\r
 \r
     @ set region 1 to be bufferable too (only data)\r
-       mcr p15, 0, r0, c3, c0, 0\r
+    mcr p15, 0, r0, c3, c0, 0\r
 \r
     @ set protection, allow accsess only to regions 1 and 2\r
-       mov r0, #(3<<6)|(3<<4)|(3<<2)|(0)  @ data: [full, full, full, no access] for regions [3 2 1 0]\r
-       mcr p15, 0, r0, c5, c0, 0\r
-       mov r0, #(0<<6)|(0<<4)|(3<<2)|(0)  @ instructions: [no access, no, full, no]\r
-       mcr p15, 0, r0, c5, c0, 1\r
-\r
-       mrc p15, 0, r0, c1, c0, 0   @ fetch current control reg\r
-       orr r0, r0, #1              @ 0x00000001: enable protection unit\r
-       orr r0, r0, #4              @ 0x00000004: enable D cache\r
-       orr r0, r0, #0x1000         @ 0x00001000: enable I cache\r
-       orr r0, r0, #0xC0000000     @ 0xC0000000: async+fastbus\r
-       mcr p15, 0, r0, c1, c0, 0   @ set control reg\r
+    mov r0, #(3<<6)|(3<<4)|(3<<2)|(0)  @ data: [full, full, full, no access] for regions [3 2 1 0]\r
+    mcr p15, 0, r0, c5, c0, 0\r
+    mov r0, #(0<<6)|(0<<4)|(3<<2)|(0)  @ instructions: [no access, no, full, no]\r
+    mcr p15, 0, r0, c5, c0, 1\r
+\r
+    mrc p15, 0, r0, c1, c0, 0   @ fetch current control reg\r
+    orr r0, r0, #1              @ 0x00000001: enable protection unit\r
+    orr r0, r0, #4              @ 0x00000004: enable D cache\r
+    orr r0, r0, #0x1000         @ 0x00001000: enable I cache\r
+    orr r0, r0, #0xC0000000     @ 0xC0000000: async+fastbus\r
+    mcr p15, 0, r0, c1, c0, 0   @ set control reg\r
 \r
     @ flush (invalidate) the cache (just in case)\r
     mov r0, #0\r
@@ -172,3 +172,5 @@ wait_irq:
     b       .b_reserved\r
 \r
 .pool\r
+\r
+@ vim:filetype=ignored:\r