}
}
- if ((psxHu32(0x1070) & psxHu32(0x1074)) && (Status & 0x401) == 0x401) {
+ if ((psxHu32(0x1070) & psxHu32(0x1074)) && (psxRegs.CP0.n.Status & 0x401) == 0x401) {
psxException(0x400, 0);
pending_exception = 1;
}
evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
MTC0(&psxRegs, reg, val);
gen_interupt();
- if (Cause & Status & 0x0300) // possible sw irq
+ if (psxRegs.CP0.n.Cause & psxRegs.CP0.n.Status & 0x0300) // possible sw irq
pending_exception = 1;
}
//printf("drc: %d block info entries %s\n", size/8, mode ? "saved" : "loaded");
}
-#ifndef DRC_DISABLE
+#if !defined(DRC_DISABLE) && !defined(LIGHTREC)
/* GTE stuff */
void *gte_handlers[64];
}
static void ari64_notify(int note, void *data) {
- /*
- Should be fixed when ARM dynarec has proper icache emulation.
switch (note)
{
- case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
- break;
- case R3000ACPU_NOTIFY_CACHE_ISOLATED:
- Sent from psxDma3().
- case R3000ACPU_NOTIFY_DMA3_EXE_LOAD:
- default:
- break;
+ case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
+ case R3000ACPU_NOTIFY_CACHE_ISOLATED:
+ new_dyna_pcsx_mem_isolate(note == R3000ACPU_NOTIFY_CACHE_ISOLATED);
+ break;
+ default:
+ break;
}
- */
}
static void ari64_apply_config()
int new_dynarec_hacks;
void *psxH_ptr;
void *zeromem_ptr;
-u8 zero_mem[0x1000];
+u32 zero_mem[0x1000/4];
void *mem_rtab;
void *scratch_buf_ptr;
void new_dynarec_init() {}
void new_dyna_pcsx_mem_init(void) {}
void new_dyna_pcsx_mem_reset(void) {}
void new_dyna_pcsx_mem_load_state(void) {}
+void new_dyna_pcsx_mem_isolate(int enable) {}
void new_dyna_pcsx_mem_shutdown(void) {}
int new_dynarec_save_blocks(void *save, int size) { return 0; }
void new_dynarec_load_blocks(const void *save, int size) {}