#include <stdlib.h>
#include <stdint.h> //include for uint64_t
#include <assert.h>
+#include <sys/mman.h>
#include "emu_if.h" //emulator interface
-#include <sys/mman.h>
+//#define DISASM
+//#define assem_debug printf
+//#define inv_debug printf
+#define assem_debug(...)
+#define inv_debug(...)
#ifdef __i386__
#include "assem_x86.h"
static const u_int using_tlb=0;
#endif
static u_int sp_in_mirror;
+ int new_dynarec_did_compile;
u_int stop_after_jal;
extern u_char restore_candidate[512];
extern int cycle_count;
//#define DEBUG_CYCLE_COUNT 1
-void nullf() {}
-//#define assem_debug printf
-//#define inv_debug printf
-#define assem_debug nullf
-#define inv_debug nullf
-
static void tlb_hacks()
{
#ifndef DISABLE_TLB
}
}
-
+#ifndef FORCE32
void div64(int64_t dividend,int64_t divisor)
{
lo=dividend/divisor;
else original=loaded;
return original;
}
+#endif
#ifdef __i386__
#include "assem_x86.c"
void shiftimm_alloc(struct regstat *current,int i)
{
- clear_const(current,rs1[i]);
- clear_const(current,rt1[i]);
if(opcode2[i]<=0x3) // SLL/SRL/SRA
{
if(rt1[i]) {
alloc_reg(current,i,rt1[i]);
current->is32|=1LL<<rt1[i];
dirty_reg(current,rt1[i]);
+ if(is_const(current,rs1[i])) {
+ int v=get_const(current,rs1[i]);
+ if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
+ if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
+ if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
+ }
+ else clear_const(current,rt1[i]);
}
}
+ else
+ {
+ clear_const(current,rs1[i]);
+ clear_const(current,rt1[i]);
+ }
+
if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
{
if(rt1[i]) {
t=get_reg(i_regs->regmap,rt1[i]);
s=get_reg(i_regs->regmap,rs1[i]);
//assert(t>=0);
- if(t>=0){
+ if(t>=0&&!((i_regs->isconst>>t)&1)){
if(rs1[i]==0)
{
emit_zeroreg(t);
}
type=STORED_STUB;
}
+#ifdef PCSX
+ if(jaddr) {
+ // PCSX store handlers don't check invcode again
+ reglist|=1<<addr;
+ add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
+ jaddr=0;
+ }
+#endif
if(!using_tlb) {
if(!c||memtarget) {
#ifdef DESTRUCTIVE_SHIFT
}
}
+#ifdef DISASM
/* disassembly */
void disassemble_inst(int i)
{
printf (" %x: %s\n",start+i*4,insn[i]);
}
}
+#else
+static void disassemble_inst(int i) {}
+#endif // DISASM
// clear the state completely, instead of just marking
// things invalid like invalidate_all_pages() does
//rlist();
start = (u_int)addr&~3;
//assert(((u_int)addr&1)==0);
+ new_dynarec_did_compile=1;
#ifdef PCSX
if(!sp_in_mirror&&(signed int)(psxRegs.GPR.n.sp&0xffe00000)>0x80200000&&
0x10000<=psxRegs.GPR.n.sp&&(psxRegs.GPR.n.sp&~0xe0e00000)<RAM_SIZE) {
case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
case 0x02: gte_rs[i]=1ll<<(gr+32); // CFC2
if(gr==31&&!gte_reads_flags) {
- printf("gte flag read encountered @%08x\n",addr + i*4);
+ assem_debug("gte flag read encountered @%08x\n",addr + i*4);
gte_reads_flags=1;
}
break;
if(itype[slen-1]==SPAN) {
bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
}
-
+
+#ifdef DISASM
/* Debug/disassembly */
- if((void*)assem_debug==(void*)printf)
for(i=0;i<slen;i++)
{
printf("U:");
#endif
}
}
+#endif // DISASM
/* Pass 8 - Assembly */
linkcount=0;stubcount=0;
for(i=0;i<slen;i++)
{
//if(ds) printf("ds: ");
- if((void*)assem_debug==(void*)printf) disassemble_inst(i);
+ disassemble_inst(i);
if(ds) {
ds=0; // Skip delay slot
if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
}
inv_code_start=inv_code_end=~0;
#ifdef PCSX
- // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
+ // for PCSX we need to mark all mirrors too
if(get_page(start)<(RAM_SIZE>>12))
for(i=start>>12;i<=(start+slen*4)>>12;i++)
- invalid_code[((u_int)0x80000000>>12)|i]=0;
+ invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
+ invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
+ invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
#endif
/* Pass 10 - Free memory by expiring oldest blocks */