/*
+ * PicoDrive
+ * (C) notaz, 2009,2010
+ *
+ * This work is licensed under the terms of MAME license.
+ * See COPYING file in the top-level directory.
+ *
* SH2 addr lines:
* iii. .cc. ..xx * // Internal, Cs, x
*
{
a &= 0x3e;
- if (a == 2) // INTM, INTS
- return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
#if 0
if ((a & 0x30) == 0x20)
return sh2_comm_faker(a);
#else
if ((a & 0x30) == 0x20) {
- // evil X-Men proto polls in a dbra loop and expects it to expire..
static u32 dr2 = 0;
+ unsigned int cycles = SekCyclesDoneT();
+ int comreg = 1 << (a & 0x0f) / 2;
+
+ // evil X-Men proto polls in a dbra loop and expects it to expire..
if (SekDar(2) != dr2)
m68k_poll.cnt = 0;
dr2 = SekDar(2);
- if (p32x_poll_detect(&m68k_poll, a, SekCyclesDoneT(), 0)) {
+ if (cycles - msh2.m68krcycles_done > 500)
+ p32x_sync_sh2s(cycles);
+ if (Pico32x.comm_dirty_sh2 & comreg)
+ Pico32x.comm_dirty_sh2 &= ~comreg;
+ else if (p32x_poll_detect(&m68k_poll, a, cycles, 0)) {
SekSetStop(1);
SekEndTimeslice(16);
}
dr2 = SekDar(2);
+ goto out;
}
#endif
+ if (a == 2) { // INTM, INTS
+ unsigned int cycles = SekCyclesDoneT();
+ if (cycles - msh2.m68krcycles_done > 64)
+ p32x_sync_sh2s(cycles);
+ return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
+ }
+
if ((a & 0x30) == 0x30)
return p32x_pwm_read16(a);
+out:
return Pico32x.regs[a / 2];
}
return;
case 3: // irq ctl
if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
+ p32x_sync_sh2s(SekCyclesDoneT());
Pico32x.sh2irqi[0] |= P32XI_CMD;
- p32x_update_irls();
- SekEndRun(16);
+ p32x_update_irls(0);
}
if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
+ p32x_sync_sh2s(SekCyclesDoneT());
Pico32x.sh2irqi[1] |= P32XI_CMD;
- p32x_update_irls();
- SekEndRun(16);
+ p32x_update_irls(0);
}
return;
case 5: // bank
if ((a & 0x30) == 0x20) {
u8 *r8 = (u8 *)r;
+ int cycles = SekCyclesDoneT();
+ int comreg;
+
+ if (r8[a ^ 1] == d)
+ return;
+
+ comreg = 1 << (a & 0x0f) / 2;
+ if (Pico32x.comm_dirty_68k & comreg)
+ p32x_sync_sh2s(cycles);
+
r8[a ^ 1] = d;
p32x_poll_undetect(&sh2_poll[0], 0);
p32x_poll_undetect(&sh2_poll[1], 0);
- // if some SH2 is busy waiting, it needs to see the result ASAP
- if (SekCyclesLeftNoMCD > 32)
- SekEndRun(32);
+ Pico32x.comm_dirty_68k |= comreg;
+
+ if (cycles - (int)msh2.m68krcycles_done > 120)
+ p32x_sync_sh2s(cycles);
return;
}
}
return;
}
// comm port
- else if ((a & 0x30) == 0x20 && r[a / 2] != d) {
+ else if ((a & 0x30) == 0x20) {
+ int cycles = SekCyclesDoneT();
+ int comreg;
+
+ if (r[a / 2] == d)
+ return;
+
+ comreg = 1 << (a & 0x0f) / 2;
+ if (Pico32x.comm_dirty_68k & comreg)
+ p32x_sync_sh2s(cycles);
+
r[a / 2] = d;
p32x_poll_undetect(&sh2_poll[0], 0);
p32x_poll_undetect(&sh2_poll[1], 0);
- // same as for w8
- if (SekCyclesLeftNoMCD > 32)
- SekEndRun(32);
+ Pico32x.comm_dirty_68k |= comreg;
+
+ if (cycles - (int)msh2.m68krcycles_done > 120)
+ p32x_sync_sh2s(cycles);
return;
}
// PWM
Pico32x.dirty_pal = 1;
r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
break;
+ case 0x03: // shift (for pp mode)
+ r[2 / 2] = d & 1;
+ break;
case 0x05: // fill len
r[4 / 2] = d & 0xff;
break;
Pico32x.pending_fb = d;
// if we are blanking and FS bit is changing
if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
- r[0x0a/2] ^= 1;
+ r[0x0a/2] ^= P32XV_FS;
Pico32xSwapDRAM(d ^ 1);
elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
}
}
}
-static void p32x_vdp_write16(u32 a, u32 d)
+static void p32x_vdp_write16(u32 a, u32 d, u32 cycles)
{
a &= 0x0e;
if (a == 6) { // fill start
if (a == 8) { // fill data
u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
int len = Pico32x.vdp_regs[4 / 2] + 1;
+ int len1 = len;
a = Pico32x.vdp_regs[6 / 2];
- while (len--) {
+ while (len1--) {
dram[a] = d;
a = (a & 0xff00) | ((a + 1) & 0xff);
}
- Pico32x.vdp_regs[6 / 2] = a;
- Pico32x.vdp_regs[8 / 2] = d;
+ Pico32x.vdp_regs[0x06 / 2] = a;
+ Pico32x.vdp_regs[0x08 / 2] = d;
+ if (cycles > 0) {
+ Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
+ p32x_event_schedule(P32X_EVENT_FILLEND, cycles, len);
+ }
return;
}
return r[a / 2];
// comm port
if ((a & 0x30) == 0x20) {
- if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
+ int comreg = 1 << (a & 0x0f) / 2;
+ if (Pico32x.comm_dirty_68k & comreg)
+ Pico32x.comm_dirty_68k &= ~comreg;
+ else if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
ash2_end_run(8);
return r[a / 2];
}
Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
Pico32x.sh2_regs[0] &= ~0x80;
Pico32x.sh2_regs[0] |= d & 0x80;
- p32x_update_irls();
+ if (d & 1)
+ p32x_pwm_schedule(sh2s[cpuid].m68krcycles_done); // XXX: timing?
+ p32x_update_irls(1);
return;
case 5: // H count
Pico32x.sh2_regs[4 / 2] = d & 0xff;
if ((a & 0x30) == 0x20) {
u8 *r8 = (u8 *)Pico32x.regs;
+ int comreg;
+ if (r8[a ^ 1] == d)
+ return;
+
r8[a ^ 1] = d;
if (p32x_poll_undetect(&m68k_poll, 0))
SekSetStop(0);
p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
+ comreg = 1 << (a & 0x0f) / 2;
+ Pico32x.comm_dirty_sh2 |= comreg;
return;
}
}
a &= 0xfe;
// comm
- if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) {
+ if ((a & 0x30) == 0x20) {
+ int comreg;
+ if (Pico32x.regs[a / 2] == d)
+ return;
+
Pico32x.regs[a / 2] = d;
if (p32x_poll_undetect(&m68k_poll, 0))
SekSetStop(0);
p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
+ comreg = 1 << (a & 0x0f) / 2;
+ Pico32x.comm_dirty_sh2 |= comreg;
return;
}
// PWM
case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
case 0x1c:
Pico32x.sh2irqs &= ~P32XI_PWM;
- p32x_timers_do(0);
+ if (!(Pico32x.emu_flags & P32XF_PWM_PEND))
+ p32x_pwm_schedule(sh2s[cpuid].m68krcycles_done); // timing?
goto irls;
}
return;
irls:
- p32x_update_irls();
+ p32x_update_irls(1);
}
// ------------------------------------------------------------------
}
if ((a & 0xfff0) == 0x5180) { // a15180
- p32x_vdp_write16(a, d);
+ p32x_vdp_write16(a, d, 0); // FIXME?
return;
}
#ifdef EMU_F68K
// setup FAME fetchmap
for (rs = 0x90; rs < 0xa0; rs++)
- PicoCpuFM68k.Fetch[rs] = (u32)Pico.rom + bank - 0x900000;
+ PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom + bank - 0x900000;
#endif
}
if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
return Pico32xMem->sh2_rom_s[a ^ 1];
- if ((a & 0x3ff00) == 0x4200) {
+ if ((a & 0x3fe00) == 0x4200) {
d = Pico32xMem->pal[(a & 0x1ff) / 2];
goto out_16to8;
}
if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
return *(u16 *)(Pico32xMem->sh2_rom_s + a);
- if ((a & 0x3ff00) == 0x4200) {
+ if ((a & 0x3fe00) == 0x4200) {
d = Pico32xMem->pal[(a & 0x1ff) / 2];
goto out;
}
return sh2_write8_unmapped(a, d, id);
}
+/* quirk: in both normal and overwrite areas only nonzero values go through */
#define sh2_write8_dramN(n) \
- if (!(a & 0x20000) || d) { \
+ if ((d & 0xff) != 0) { \
u8 *dram = (u8 *)Pico32xMem->dram[n]; \
dram[(a & 0x1ffff) ^ 1] = d; \
} \
if ((a & 0x3ff00) == 0x4100) {
sh2_poll[id].cnt = 0; // for poll before VDP accesses
- p32x_vdp_write16(a, d);
+ p32x_vdp_write16(a, d, sh2s[id].m68krcycles_done);
return 0;
}
// M68K ROM
if (p32x_bios_g != NULL) {
elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
- Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, 0x100);
+ Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom));
}
else {
// generate 68k ROM
#endif
}
// fill remaining m68k_rom page with game ROM
- memcpy(Pico32xMem->m68k_rom + 0x100, Pico.rom + 0x100, sizeof(Pico32xMem->m68k_rom) - 0x100);
+ memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom),
+ Pico.rom + sizeof(Pico32xMem->m68k_rom),
+ sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom));
// MSH2
if (p32x_bios_m != NULL) {
unsigned int rs;
int i;
- Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem));
+ Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0);
if (Pico32xMem == NULL) {
elprintf(EL_STATUS, "OOM");
return;
// m68k_map_unmap(0x000000, 0x3fffff);
// MD ROM area
- rs = sizeof(Pico32xMem->m68k_rom);
- cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
- cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
+ rs = sizeof(Pico32xMem->m68k_rom_bank);
+ cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
+ cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
#ifdef EMU_F68K
// setup FAME fetchmap
- PicoCpuFM68k.Fetch[0] = (u32)Pico32xMem->m68k_rom;
+ PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
for (rs = 0x88; rs < 0x90; rs++)
- PicoCpuFM68k.Fetch[rs] = (u32)Pico.rom - 0x880000;
+ PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000;
#endif
// 32X ROM (banked)
msh2.read8_map = ssh2.read8_map = sh2_read8_map;
msh2.read16_map = ssh2.read16_map = sh2_read16_map;
- msh2.write8_tab = ssh2.write8_tab = (const void **)sh2_write8_map;
- msh2.write16_tab = ssh2.write16_tab = (const void **)sh2_write16_map;
+ msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
+ msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
// setup poll detector
m68k_poll.flag = P32XF_68KPOLL;
sh2_poll[0].cyc_max = 21;
sh2_poll[1].flag = P32XF_SSH2POLL;
sh2_poll[1].cyc_max = 16;
+
+#ifdef DRC_SH2
+ sh2_drc_mem_setup(&msh2);
+ sh2_drc_mem_setup(&ssh2);
+#endif
+}
+
+void Pico32xStateLoaded(void)
+{
+ bank_switch(Pico32x.regs[4 / 2]);
+ Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
+ p32x_poll_event(3, 0);
+ Pico32x.dirty_pal = 1;
+ memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
+ p32x_timers_recalc();
+#ifdef DRC_SH2
+ sh2_drc_flush_all();
+#endif
}
-// vim:shiftwidth=2:expandtab
+// vim:shiftwidth=2:ts=2:expandtab
notaz.gp2x.de / picodrive.git / blobdiff