\r
// This file is part of the Cyclone 68000 Emulator\r
\r
-// Copyright (c) 2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2005-2011 GraÅžvydas "notaz" Ignotas (notasas (at) gmail.com)\r
\r
// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
// You can choose the license that has the most advantages for you.\r
\r
// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
\r
+\r
#include "app.h"\r
\r
-static void CheckPc()\r
+// in/out address in r0, trashes all temp regs\r
+static void CheckPc(void)\r
{\r
- ot(";@ Check Memory Base+pc (r4)\n");\r
- ot(" add lr,pc,#4\n");\r
- ot(" mov r0,r4\n");\r
+#if USE_CHECKPC_CALLBACK\r
+ #ifdef MEMHANDLERS_DIRECT_PREFIX\r
+ ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
+ #else\r
+ ot(";@ Check Memory Base+pc\n");\r
+ ot(" mov lr,pc\n");\r
ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
- ot(" mov r4,r0\n");\r
ot("\n");\r
+ #endif\r
+#endif\r
}\r
\r
-// Push 32-bit value in r1 - trashes r0-r3\r
+// Push 32-bit value in r1 - trashes r0-r3,r12,lr\r
void OpPush32()\r
{\r
ot(";@ Push r1 onto stack\n");\r
ot("\n");\r
}\r
\r
-// Push SR - trashes r0-r3\r
+// Push SR - trashes r0-r3,r12,lr\r
void OpPushSr(int high)\r
{\r
ot(";@ Push SR:\n");\r
OpRegToFlags(high);\r
}\r
\r
-// Pop PC - assumes r10=Memory Base - trashes r0-r3\r
+// Pop PC - trashes r0-r3\r
static void PopPc()\r
{\r
ot(";@ Pop PC:\n");\r
ot(" add r1,r0,#4 ;@ Postincrement A7\n");\r
ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r
MemHandler(0,2);\r
- ot(" add r4,r0,r10 ;@ r4=Memory Base+PC\n");\r
+ ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" add r0,r0,r1 ;@ Memory Base+PC\n");\r
ot("\n");\r
CheckPc();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" mov r4,r0\n");\r
+#else\r
+ ot(" bic r4,r0,#1\n");\r
+#endif\r
}\r
\r
int OpTrap(int op)\r
use=op&~0xf;\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(use);\r
+ OpStart(op,0x10);\r
ot(" and r0,r8,#0xf ;@ Get trap number\n");\r
- ot(" orr r0,r0,#0x20\n");\r
- ot(" mov r0,r0,asl #2\n");\r
- ot(" str r0,[r7,#0x50] ;@ Save Exception Vector\n");\r
+ ot(" orr r0,r0,#0x20 ;@ 32+n\n");\r
ot(" bl Exception\n");\r
ot("\n");\r
\r
- Cycles=38; OpEnd();\r
+ Cycles=38; OpEnd(0x10);\r
\r
return 0;\r
}\r
// --------------------- Opcodes 0x4e50+ ---------------------\r
int OpLink(int op)\r
{\r
- int use=0;\r
+ int use=0,reg;\r
\r
use=op&~7;\r
+ reg=op&7;\r
+ if (reg==7) use=op;\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(use);\r
+ OpStart(op,0x10);\r
\r
- ot(";@ Get An\n");\r
- EaCalc(10, 7, 8, 2);\r
- EaRead(10, 1, 8, 2, 1);\r
+ if(reg!=7) {\r
+ ot(";@ Get An\n");\r
+ EaCalc(11, 7, 8, 2, 1);\r
+ EaRead(11, 1, 8, 2, 7, 1);\r
+ }\r
\r
ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
ot(" sub r0,r0,#4 ;@ A7-=4\n");\r
- ot(" mov r11,r0\n");\r
+ ot(" mov r8,r0 ;@ abuse r8\n");\r
+ if(reg==7) ot(" mov r1,r0\n");\r
ot("\n");\r
\r
ot(";@ Write An to Stack\n");\r
MemHandler(1,2);\r
\r
ot(";@ Save to An\n");\r
- EaWrite(10,11, 8, 2, 1);\r
+ if(reg!=7)\r
+ EaWrite(11,8, 8, 2, 7, 1);\r
\r
ot(";@ Get offset:\n");\r
- EaCalc(0,0,0x3c,1);\r
- EaRead(0,0,0x3c,1);\r
+ EaCalc(0,0,0x3c,1); // abused r8 is ok because of imm EA\r
+ EaRead(0,0,0x3c,1,0);\r
\r
- ot(" add r11,r11,r0 ;@ Add offset to A7\n");\r
- ot(" str r11,[r7,#0x3c]\n");\r
+ ot(" add r8,r8,r0 ;@ Add offset to A7\n");\r
+ ot(" str r8,[r7,#0x3c]\n");\r
ot("\n");\r
\r
Cycles=16;\r
- OpEnd();\r
+ OpEnd(0x10);\r
return 0;\r
}\r
\r
use=op&~7;\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(use);\r
+ OpStart(op,0x10);\r
\r
ot(";@ Get An\n");\r
- EaCalc(10, 7, 8, 2);\r
- EaRead(10, 0, 8, 2, 1);\r
+ EaCalc(11, 0xf, 8, 2, 1);\r
+ EaRead(11, 0, 8, 2, 0xf, 1);\r
\r
- ot(" add r11,r0,#4 ;@ A7+=4\n");\r
+ ot(" add r8,r0,#4 ;@ A7+=4, abuse r8\n");\r
ot("\n");\r
ot(";@ Pop An from stack:\n");\r
MemHandler(0,2);\r
ot("\n");\r
- ot(" str r11,[r7,#0x3c] ;@ Save A7\n");\r
+ ot(" str r8,[r7,#0x3c] ;@ Save A7\n");\r
ot("\n");\r
ot(";@ An = value from stack:\n");\r
- EaWrite(10, 0, 8, 2, 1);\r
- \r
+ EaWrite(11, 0, 8, 2, 7, 1);\r
+\r
Cycles=12;\r
- OpEnd();\r
+ OpEnd(0x10);\r
return 0;\r
}\r
\r
// --------------------- Opcodes 0x4e70+ ---------------------\r
+// 01001110 01110ttt\r
int Op4E70(int op)\r
{\r
int type=0;\r
\r
- type=op&7;\r
- // 01001110 01110ttt, reset/nop/stop/rte/rtd/rts/trapv/rtr\r
- if (type==1) { OpStart(op); Cycles=4; OpEnd(); return 0; } // nop\r
+ type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr\r
\r
- if (type==3 || type==7) // rte/rtr\r
+ switch (type)\r
{\r
- OpStart(op); Cycles=20;\r
- PopSr(type==3);\r
- ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
- PopPc();\r
- if (type==3) CheckInterrupt();\r
+ case 1: // nop\r
+ OpStart(op);\r
+ Cycles=4;\r
OpEnd();\r
return 0;\r
- }\r
\r
- if (type==5) // rts\r
- {\r
- OpStart(op); Cycles=16;\r
- ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
+ case 3: // rte\r
+ OpStart(op,0x10,0,0,1); Cycles=20;\r
+ PopSr(1);\r
PopPc();\r
- OpEnd();\r
+ ot(" ldr r1,[r7,#0x44] ;@ reload SR high\n");\r
+ SuperChange(op,1);\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO || EMULATE_HALT\r
+ ot(" ldr r1,[r7,#0x58]\n");\r
+ ot(" bic r1,r1,#0x0c ;@ clear 'not processing instruction' and 'doing addr error' bits\n");\r
+ ot(" str r1,[r7,#0x58]\n");\r
+#endif\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#endif\r
+ opend_check_interrupt = 1;\r
+ opend_check_trace = 1;\r
+ OpEnd(0x10,0);\r
+ return 0;\r
+\r
+ case 5: // rts\r
+ OpStart(op,0x10); Cycles=16;\r
+ PopPc();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#endif\r
+ OpEnd(0x10);\r
+ return 0;\r
+\r
+ case 6: // trapv\r
+ OpStart(op,0x10,0,1); Cycles=4;\r
+ ot(" tst r10,#0x10000000\n");\r
+ ot(" subne r5,r5,#%i\n",34);\r
+ ot(" movne r0,#7 ;@ TRAPV exception\n");\r
+ ot(" blne Exception\n");\r
+ opend_op_changes_cycles = 1;\r
+ OpEnd(0x10,0);\r
return 0;\r
- }\r
\r
- return 1;\r
+ case 7: // rtr\r
+ OpStart(op,0x10); Cycles=20;\r
+ PopSr(0);\r
+ PopPc();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#endif\r
+ OpEnd(0x10);\r
+ return 0;\r
+\r
+ default:\r
+ return 1;\r
+ }\r
}\r
\r
// --------------------- Opcodes 0x4e80+ ---------------------\r
-// Emit a Jsr/Jmp opcode, 01001110 1mEEEeee\r
+// Emit a Jsr/Jmp opcode, 01001110 1meeeeee\r
int OpJsr(int op)\r
{\r
int use=0;\r
// See if we can do this opcode:\r
if (EaCanRead(sea,-1)==0) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,0);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=14; // Correct?\r
+ OpStart(op,(op&0x40)?0:0x10);\r
\r
- ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" ldr r11,[r7,#0x60] ;@ Get Memory base\n");\r
ot("\n");\r
- EaCalc(0,0x003f,sea,0);\r
+ EaCalc(12,0x003f,sea,0);\r
\r
- ot(";@ Jump - Get new PC from r0\n");\r
- if (op&0x40)\r
+ ot(";@ Jump - Get new PC from r12\n");\r
+ ot(" add r0,r12,r11 ;@ Memory Base + New PC\n");\r
+ ot("\n");\r
+ CheckPc();\r
+ if (!(op&0x40))\r
{\r
- // Jmp - Get new PC from r0\r
- ot(" add r4,r0,r10 ;@ r4 = Memory Base + New PC\n");\r
- ot("\n");\r
+ ot(" ldr r2,[r7,#0x3c]\n");\r
+ ot(" sub r1,r4,r11 ;@ r1 = Old PC\n");\r
}\r
- else\r
- {\r
- ot(";@ Jsr - Push old PC first\n");\r
- ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
- ot(" add r4,r0,r10 ;@ r4 = Memory Base + New PC\n");\r
- ot("\n");\r
- OpPush32();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ // jsr prefetches next instruction before pushing old PC,\r
+ // according to http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r
+ ot(" mov r4,r0\n");\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#else\r
+ ot(" bic r4,r0,#1\n");\r
+#endif\r
\r
- Cycles+=8;\r
+ if (!(op&0x40))\r
+ {\r
+ ot(";@ Push old PC onto stack\n");\r
+ ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,2);\r
}\r
\r
- if (Amatch && sea==0x10) Cycles-=2; // (An) Correct?\r
-\r
- CheckPc();\r
+ Cycles=(op&0x40) ? 4 : 12;\r
+ Cycles+=Ea_add_ns((op&0x40) ? g_jmp_cycle_table : g_jsr_cycle_table, sea);\r
\r
- OpEnd();\r
+ OpEnd((op&0x40)?0:0x10);\r
\r
return 0;\r
}\r
// --------------------- Opcodes 0x50c8+ ---------------------\r
\r
// ARM version of 68000 condition codes:\r
-static char *Cond[16]=\r
+static const char * const Cond[16]=\r
{\r
"", "", "hi","ls","cc","cs","ne","eq",\r
"vc","vs","pl","mi","ge","lt","gt","le"\r
cc=(op>>8)&15;\r
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
- OpStart(op); Cycles=10;\r
-\r
- ot(";@ Decrement Dn.w\n");\r
- ot(" and r1,r8,#0x0007\n");\r
- ot(" mov r1,r1,lsl #2\n");\r
- ot(" ldrsh r0,[r7,r1]\n");\r
- ot(" sub r0,r0,#1\n");\r
- ot(" strh r0,[r7,r1]\n");\r
- ot("\n");\r
+ OpStart(op);\r
\r
- if (cc>=2)\r
+ switch (cc)\r
{\r
- ot(";@ Is the condition true?\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");\r
- ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000\n");\r
- ot(";@ If so, don't dbra\n");\r
- ot(" b%s DbraEnd%.4x\n",Cond[cc],op);\r
- ot("\n");\r
+ case 0: // T\r
+ case 1: // F\r
+ break;\r
+ case 2: // hi\r
+ ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
+ ot(" beq DbraTrue\n\n");\r
+ break;\r
+ case 3: // ls\r
+ ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
+ ot(" bne DbraTrue\n\n");\r
+ break;\r
+ default:\r
+ ot(";@ Is the condition true?\n");\r
+ ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
+ ot(";@ If so, don't dbra\n");\r
+ ot(" b%s DbraTrue\n\n",Cond[cc]);\r
+ break;\r
}\r
\r
- ot(";@ Check if Dn.w is -1\n");\r
- ot(" cmps r0,#-1\n");\r
- ot(" beq DbraEnd%.4x\n",op);\r
- ot("\n");\r
+ if (cc!=0)\r
+ {\r
+ ot(";@ Decrement Dn.w\n");\r
+ ot(" and r1,r8,#0x0007\n");\r
+ ot(" mov r1,r1,lsl #2\n");\r
+ ot(" ldrsh r0,[r7,r1]\n");\r
+ ot(" sub r0,r0,#1\n");\r
+ ot(" strh r0,[r7,r1]\n");\r
+ ot("\n");\r
\r
- ot(";@ Get Branch offset:\n");\r
- ot(" ldrsh r0,[r4]\n");\r
- ot(" add r4,r4,r0 ;@ r4 = New PC\n");\r
- ot("\n");\r
- OpEnd();\r
+ ot(";@ Check if Dn.w is -1\n");\r
+ ot(" cmn r0,#1\n");\r
+\r
+#if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" beq DbraMin1\n");\r
+ ot("\n");\r
+\r
+ ot(";@ Get Branch offset:\n");\r
+ ot(" ldrsh r0,[r4]\n");\r
+ ot(" add r0,r4,r0 ;@ r0 = New PC\n");\r
+ CheckPc();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" mov r4,r0\n");\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#else\r
+ ot(" bic r4,r0,#1\n");\r
+#endif\r
+#else\r
+ ot("\n");\r
+ ot(";@ Get Branch offset:\n");\r
+ ot(" ldrnesh r0,[r4]\n");\r
+ ot(" addeq r4,r4,#2 ;@ Skip branch offset\n");\r
+ ot(" subeq r5,r5,#4 ;@ additional cycles\n");\r
+ ot(" addne r4,r4,r0 ;@ r4 = New PC\n");\r
+ ot(" bic r4,r4,#1\n"); // we do not emulate address errors\r
+ ot("\n");\r
+#endif\r
+ Cycles=12-2;\r
+ OpEnd();\r
+ }\r
\r
- ot("DbraEnd%.4x%s\n", op, ms?"":":");\r
- Cycles+=2;\r
- ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
- ot("\n");\r
- OpEnd();\r
+ //if (cc==0||cc>=2)\r
+ if (op==0x50c8)\r
+ {\r
+ ot(";@ condition true:\n");\r
+ ot("DbraTrue%s\n", ms?"":":");\r
+ ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
+ ot("\n");\r
+ Cycles=12;\r
+ OpEnd();\r
+ }\r
+\r
+#if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP\r
+ if (op==0x51c8)\r
+ {\r
+ ot(";@ Dn.w is -1:\n");\r
+ ot("DbraMin1%s\n", ms?"":":");\r
+ ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
+ ot("\n");\r
+ Cycles=12+2;\r
+ OpEnd();\r
+ }\r
+#endif\r
\r
return 0;\r
}\r
// Emit a Branch opcode 0110cccc nn (cccc=condition)\r
int OpBranch(int op)\r
{\r
- int size=0,use=0;\r
+ int size=0,use=0,checkpc=0;\r
int offset=0;\r
int cc=0;\r
+ const char *asr_r11="";\r
\r
offset=(char)(op&0xff);\r
cc=(op>>8)&15;\r
if (offset==0) size=1;\r
if (offset==-1) size=2;\r
\r
+ if (size==2) size=0; // 000 model does not support long displacement\r
if (size) use=op; // 16-bit or 32-bit\r
else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches\r
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
- OpStart(op); Cycles=10; // Assume branch taken\r
+ OpStart(op,size?0x10:0);\r
+ Cycles=10; // Assume branch taken\r
\r
- ot(";@ Get Branch offset:\n");\r
- if (size)\r
+ switch (cc)\r
{\r
- EaCalc(0,0,0x3c,size);\r
- EaRead(0,0,0x3c,size);\r
- if (Amatch && size==1) Cycles-=4;\r
+ case 0: // T\r
+ case 1: // F\r
+ break;\r
+ case 2: // hi\r
+ ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
+ ot(" bne BccDontBranch%i\n\n",8<<size);\r
+ break;\r
+ case 3: // ls\r
+ ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
+ ot(" beq BccDontBranch%i\n\n",8<<size);\r
+ break;\r
+ default:\r
+ ot(";@ Is the condition true?\n");\r
+ ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
+ ot(" b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);\r
+ break;\r
}\r
\r
- if (size==0) ot(" mov r0,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r
-\r
- if (cc>=2)\r
+ if (size) \r
{\r
- ot(";@ Is the condition true?\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");\r
- ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000\n");\r
-\r
- if (size==0) ot(" mov r0,r0,asr #24 ;@ ...shift down\n\n");\r
-\r
- ot(" b%s DontBranch%.4x\n",Cond[cc^1],op);\r
-\r
- ot("\n");\r
+ if (size<2)\r
+ {\r
+ ot(" ldrsh r11,[r4] ;@ Fetch Branch offset\n");\r
+ }\r
+ else\r
+ {\r
+ ot(" ldrh r2,[r4] ;@ Fetch Branch offset\n");\r
+ ot(" ldrh r11,[r4,#2]\n");\r
+ ot(" orr r11,r11,r2,lsl #16\n");\r
+ }\r
}\r
else\r
{\r
- if (size==0) ot(" mov r0,r0,asr #24 ;@ ...shift down\n\n");\r
+ ot(" mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r
+ asr_r11=",asr #24";\r
}\r
\r
ot(";@ Branch taken - Add on r0 to PC\n");\r
if (cc==1)\r
{\r
ot(";@ Bsr - remember old PC\n");\r
- ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
- ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
+ ot(" ldr r12,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" ldr r2,[r7,#0x3c]\n");\r
+ ot(" sub r1,r4,r12 ;@ r1 = Old PC\n");\r
+ if (size) ot(" add r1,r1,#%d\n",1<<size);\r
ot("\n");\r
- if (size) ot(" sub r4,r4,#%d ;@ (Branch is relative to Opcode+2)\n",1<<size);\r
- ot(" add r4,r4,r0 ;@ r4 = New PC\n");\r
- ot("\n");\r
- OpPush32();\r
- Cycles+=8;\r
- }\r
- else\r
- {\r
- if (size) ot(" sub r4,r4,#%d ;@ (Branch is relative to Opcode+2)\n",1<<size);\r
- ot(" add r4,r4,r0 ;@ r4 = New PC\n");\r
+ ot(";@ Push r1 onto stack\n");\r
+ ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,2);\r
ot("\n");\r
+ Cycles=18; // always 18\r
}\r
\r
- if (offset==0 || offset==-1)\r
- {\r
- ot(";@ Branch is quite far, so may be a good idea to check Memory Base+pc\n");\r
- CheckPc();\r
- }\r
+ ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
+\r
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8\r
+ if (offset!=0 && offset!=-1) checkpc=1;\r
+#endif\r
+#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16\r
+ if (offset==0) checkpc=1;\r
+#endif\r
+#if USE_CHECKPC_CALLBACK\r
+ if (offset==-1) checkpc=1;\r
+#endif\r
+ if (checkpc) CheckPc();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" mov r4,r0\n");\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#else\r
+ ot(" bic r4,r0,#1\n");\r
+#endif\r
+ ot("\n");\r
\r
- OpEnd();\r
+ OpEnd(size?0x10:0);\r
\r
- if (cc>=2)\r
+ // since all "DontBranch" code is same for every size, output only once\r
+ if (cc>=2&&(op&0xff00)==0x6700)\r
{\r
- ot("DontBranch%.4x%s\n", op, ms?"":":");\r
- Cycles-=2; // Branch not taken\r
- OpEnd();\r
+ ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");\r
+ if (size) ot(" add r4,r4,#%d\n",1<<size);\r
+ Cycles+=(size==1) ? 2 : -2; // Branch not taken\r
+ OpEnd(0);\r
}\r
\r
return 0;\r
notaz.gp2x.de / cyclone68000.git / blobdiff