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testpico: more timing tests
[megadrive.git] / testpico / main.c
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ffd4b35c 1/*
2 * This software is released into the public domain.
3 * See UNLICENSE file in top level directory.
4 */
5#include <stdlib.h>
6#include <stdarg.h>
9d39a80e 7#include "common.h"
ffd4b35c 8#include "asmtools.h"
9
10#define VDP_DATA_PORT 0xC00000
11#define VDP_CTRL_PORT 0xC00004
a385208c 12#define VDP_HV_COUNTER 0xC00008
ffd4b35c 13
14#define TILE_MEM_END 0xB000
15
16#define FONT_LEN 128
a385208c 17#define TILE_FONT_BASE (TILE_MEM_END - FONT_LEN * 32)
ffd4b35c 18
19/* note: using ED menu's layout here.. */
20#define WPLANE (TILE_MEM_END + 0x0000)
21#define HSCRL (TILE_MEM_END + 0x0800)
22#define SLIST (TILE_MEM_END + 0x0C00)
23#define APLANE (TILE_MEM_END + 0x1000)
24#define BPLANE (TILE_MEM_END + 0x3000)
25
ffd4b35c 26#define write16_z80le(a, d) \
27 ((volatile u8 *)(a))[0] = (u8)(d), \
28 ((volatile u8 *)(a))[1] = ((d) >> 8)
29
30static inline u16 read16_z80le(const void *a_)
31{
32 volatile const u8 *a = (volatile const u8 *)a_;
33 return a[0] | ((u16)a[1] << 8);
34}
35
36#define CTL_WRITE_VRAM(adr) \
37 (((0x4000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
38#define CTL_WRITE_VSRAM(adr) \
39 (((0x4000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x10)
40#define CTL_WRITE_CRAM(adr) \
41 (((0xC000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
42#define CTL_READ_VRAM(adr) \
43 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
44#define CTL_READ_VSRAM(adr) \
45 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x10)
46#define CTL_READ_CRAM(adr) \
47 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x20)
48
49#define CTL_WRITE_DMA 0x80
50
51#define VDP_setReg(r, v) \
52 write16(VDP_CTRL_PORT, 0x8000 | ((r) << 8) | ((v) & 0xff))
53
54enum {
55 VDP_MODE1 = 0x00,
56 VDP_MODE2 = 0x01,
57 VDP_NT_SCROLLA = 0x02,
58 VDP_NT_WIN = 0x03,
59 VDP_NT_SCROLLB = 0x04,
60 VDP_SAT_BASE = 0x05,
61 VDP_BACKDROP = 0x07,
62 VDP_MODE3 = 0x0b,
63 VDP_MODE4 = 0x0c,
64 VDP_HSCROLL = 0x0d,
65 VDP_AUTOINC = 0x0f,
66 VDP_SCROLLSZ = 0x10,
67 VDP_DMA_LEN0 = 0x13,
68 VDP_DMA_LEN1 = 0x14,
69 VDP_DMA_SRC0 = 0x15,
70 VDP_DMA_SRC1 = 0x16,
71 VDP_DMA_SRC2 = 0x17,
72};
73
74#define VDP_MODE1_PS 0x04
75#define VDP_MODE1_IE1 0x10 // h int
76#define VDP_MODE2_MD 0x04
77#define VDP_MODE2_PAL 0x08 // 30 col
78#define VDP_MODE2_DMA 0x10
79#define VDP_MODE2_IE0 0x20 // v int
80#define VDP_MODE2_DISP 0x40
a385208c 81#define VDP_MODE2_128K 0x80
82
83#define SR_PAL (1 << 0)
84#define SR_DMA (1 << 1)
85#define SR_HB (1 << 2)
86#define SR_VB (1 << 3)
87#define SR_ODD (1 << 4)
88#define SR_C (1 << 5)
89#define SR_SOVR (1 << 6)
90#define SR_F (1 << 7)
91#define SR_FULL (1 << 8)
92#define SR_EMPT (1 << 9)
ffd4b35c 93
94/* cell counts */
95#define LEFT_BORDER 1 /* lame TV */
96#define PLANE_W 64
97#define PLANE_H 32
98#define CSCREEN_H 28
99
100/* data.s */
101extern const u32 font_base[];
102extern const u8 z80_test[];
103extern const u8 z80_test_end[];
104
105static int text_pal;
106
107static noinline void VDP_drawTextML(const char *str, u16 plane_base,
108 u16 x, u16 y)
109{
110 const u8 *src = (const u8 *)str;
111 u16 basetile = text_pal << 13;
112 int max_len = 40 - LEFT_BORDER;
113 int len;
114 u32 addr;
115
116 x += LEFT_BORDER;
117
118 for (len = 0; str[len] && len < max_len; len++)
119 ;
120 if (len > (PLANE_W - x))
121 len = PLANE_W - x;
122
123 addr = plane_base + ((x + (PLANE_W * y)) << 1);
124 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr));
125
126 while (len-- > 0) {
127 write16(VDP_DATA_PORT,
128 basetile | ((*src++) - 32 + TILE_FONT_BASE / 32));
129 }
130}
131
132static int printf_ypos;
133
134static void printf_line(int x, const char *buf)
135{
136 u32 addr;
137 int i;
138
139 VDP_drawTextML(buf, APLANE, x, printf_ypos++ & (PLANE_H - 1));
140
141 if (printf_ypos >= CSCREEN_H) {
142 /* clear next line */
143 addr = APLANE;
144 addr += (PLANE_W * (printf_ypos & (PLANE_H - 1))) << 1;
145 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr));
146 for (i = 0; i < 40 / 2; i++)
147 write32(VDP_DATA_PORT, 0);
148
149 /* scroll plane */
150 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
151 write16(VDP_DATA_PORT, (printf_ypos - CSCREEN_H + 1) * 8);
152 }
153}
154
155#define PRINTF_LEN 40
156
157static int printf_xpos;
158
159static noinline int printf(const char *fmt, ...)
160{
161 static const char hexchars[] = "0123456789abcdef";
162 char c, buf[PRINTF_LEN + 11 + 1];
163 const char *s;
164 va_list ap;
165 int ival;
166 u32 uval;
167 int d = 0;
168 int i, j;
169
170 va_start(ap, fmt);
171 for (d = 0; *fmt; ) {
172 int prefix0 = 0;
173 int fwidth = 0;
174
175 c = *fmt++;
176 if (d < PRINTF_LEN)
177 buf[d] = c;
178
179 if (c != '%') {
180 if (c == '\n') {
181 buf[d] = 0;
182 printf_line(printf_xpos, buf);
183 d = 0;
184 printf_xpos = 0;
185 continue;
186 }
187 d++;
188 continue;
189 }
190 if (d >= PRINTF_LEN)
191 continue;
192
193 if (*fmt == '0') {
194 prefix0 = 1;
195 fmt++;
196 }
197
198 while ('1' <= *fmt && *fmt <= '9') {
199 fwidth = fwidth * 10 + *fmt - '0';
200 fmt++;
201 }
202
203 switch (*fmt++) {
204 case '%':
205 d++;
206 break;
207 case 'd':
208 case 'i':
209 ival = va_arg(ap, int);
210 if (ival < 0) {
211 buf[d++] = '-';
212 ival = -ival;
213 }
214 for (i = 1000000000; i >= 10; i /= 10)
215 if (ival >= i)
216 break;
217 for (; i >= 10; i /= 10) {
218 buf[d++] = '0' + ival / i;
219 ival %= i;
220 }
221 buf[d++] = '0' + ival;
222 break;
223 case 'x':
224 uval = va_arg(ap, int);
225 while (fwidth > 1 && uval < (1 << (fwidth - 1) * 4)) {
226 buf[d++] = prefix0 ? '0' : ' ';
227 fwidth--;
228 }
229 for (j = 1; j < 8 && uval >= (1 << j * 4); j++)
230 ;
231 for (j--; j >= 0; j--)
232 buf[d++] = hexchars[(uval >> j * 4) & 0x0f];
233 break;
234 case 's':
235 s = va_arg(ap, char *);
236 while (*s && d < PRINTF_LEN)
237 buf[d++] = *s++;
238 break;
239 default:
240 // don't handle, for now
241 d++;
242 va_arg(ap, void *);
243 break;
244 }
245 }
246 buf[d] = 0;
247 va_end(ap);
248
249 if (d != 0) {
250 // line without \n
251 VDP_drawTextML(buf, APLANE, printf_xpos,
252 printf_ypos & (PLANE_H - 1));
253 printf_xpos += d;
254 }
255
256 return d; // wrong..
257}
258
259static const char *exc_names[] = {
260 NULL,
261 NULL,
262 "Bus Error",
263 "Address Error",
264 "Illegal Instruction",
265 "Zero Divide",
266 "CHK Instruction",
267 "TRAPV Instruction",
268 "Privilege Violation", /* 8 8 */
269 "Trace",
270 "Line 1010 Emulator",
271 "Line 1111 Emulator",
272 NULL,
273 NULL,
274 NULL,
275 "Uninitialized Interrupt",
276 NULL, /* 10 16 */
277 NULL,
278 NULL,
279 NULL,
280 NULL,
281 NULL,
282 NULL,
283 NULL,
284 "Spurious Interrupt", /* 18 24 */
285 "l1 irq",
286 "l2 irq",
287 "l3 irq",
288 "l4 irq",
289 "l5 irq",
290 "l6 irq",
291 "l7 irq",
292};
293
294struct exc_frame {
295 u32 dr[8];
296 u32 ar[8];
297 u16 ecxnum; // from handler
298 union {
299 struct {
300 u16 sr;
301 u32 pc;
302 } g _packed;
303 struct {
304 u16 fc;
305 u32 addr;
306 u16 ir;
307 u16 sr;
308 u32 pc;
309 } bae _packed; // bus/address error frame
310 };
311} _packed;
312
ffd4b35c 313void exception(const struct exc_frame *f)
314{
234c4556 315 u32 *sp, sp_add;
ffd4b35c 316 int i;
317
318 while (read16(VDP_CTRL_PORT) & 2)
319 ;
320 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
321 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DISP);
322 /* adjust scroll */
323 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
324 write16(VDP_DATA_PORT,
325 printf_ypos >= CSCREEN_H ?
326 (printf_ypos - CSCREEN_H + 1) * 8 : 0);
327
328 printf("exception %i ", f->ecxnum);
329 if (f->ecxnum < ARRAY_SIZE(exc_names) && exc_names[f->ecxnum] != NULL)
330 printf("(%s)", exc_names[f->ecxnum]);
331 if (f->ecxnum < 4)
332 printf(" (%s)", (f->bae.fc & 0x10) ? "r" : "w");
333 printf(" \n");
334
335 if (f->ecxnum < 4) {
234c4556 336 printf(" PC: %08x SR: %04x \n", f->bae.pc, f->bae.sr);
ffd4b35c 337 printf("addr: %08x IR: %04x FC: %02x \n",
338 f->bae.addr, f->bae.ir, f->bae.fc);
234c4556 339 sp_add = 14;
ffd4b35c 340 }
341 else {
234c4556 342 printf(" PC: %08x SR: %04x \n", f->g.pc, f->g.sr);
343 sp_add = 6;
ffd4b35c 344 }
345 for (i = 0; i < 8; i++)
346 printf(" D%d: %08x A%d: %08x \n", i, f->dr[i], i, f->ar[i]);
234c4556 347 printf(" \n");
348 sp = (u32 *)(f->ar[7] + sp_add);
349 printf(" %08x %08x %08x %08x\n", sp[0], sp[1], sp[2], sp[3]);
350 printf(" %08x %08x %08x %08x\n", sp[4], sp[5], sp[6], sp[7]);
ffd4b35c 351}
352
353// ---
354
355static void setup_default_palette(void)
356{
357 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
358 write32(VDP_DATA_PORT, 0);
359 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(15 * 2)); // font normal
360 write16(VDP_DATA_PORT, 0xeee);
361 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(31 * 2)); // green
362 write16(VDP_DATA_PORT, 0x0e0);
363 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(47 * 2)); // red
364 write16(VDP_DATA_PORT, 0x00e);
365}
366
367static void do_setup_dma(const void *src_, u16 words)
368{
369 u32 src = (u32)src_;
370 // VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA);
371 VDP_setReg(VDP_DMA_LEN0, words);
372 VDP_setReg(VDP_DMA_LEN1, words >> 8);
373 VDP_setReg(VDP_DMA_SRC0, src >> 1);
374 VDP_setReg(VDP_DMA_SRC1, src >> 9);
375 VDP_setReg(VDP_DMA_SRC2, src >> 17);
376 // write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr) | CTL_WRITE_DMA);
377}
378
a385208c 379static void vdp_wait_for_fifo_empty(void)
380{
381 while (!(read16(VDP_CTRL_PORT) & 0x200))
382 /* fifo not empty */;
383}
384
385static void vdp_wait_for_dma_idle(void)
386{
387 while (read16(VDP_CTRL_PORT) & 2)
388 /* dma busy */;
389}
390
391static void vdp_wait_for_line_0(void)
392{
393 // in PAL vcounter reports 0 twice in a frame,
394 // so wait for vblank to clear first
395 while (!(read16(VDP_CTRL_PORT) & 8))
396 /* not blanking */;
397 while (read16(VDP_CTRL_PORT) & 8)
398 /* blanking */;
399 while (read8(VDP_HV_COUNTER) != 0)
400 ;
401}
402
ffd4b35c 403static void t_dma_zero_wrap_early(void)
404{
405 const u32 *src = (const u32 *)0x3c0000;
406 u32 *ram = (u32 *)0xff0000;
407
408 do_setup_dma(src + 4, 2);
409 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) | CTL_WRITE_DMA);
410 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) | CTL_WRITE_DMA);
411
412 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
413 ram[0] = read32(VDP_DATA_PORT);
414 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfffc));
415 ram[1] = read32(VDP_DATA_PORT);
416}
417
418static void t_dma_zero_fill_early(void)
419{
420 u32 *ram = (u32 *)0xff0000;
421
422 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
423 write32(VDP_DATA_PORT, 0);
424 write32(VDP_DATA_PORT, 0);
425 write32(VDP_DATA_PORT, 0);
426 write32(VDP_DATA_PORT, 0);
427
428 VDP_setReg(VDP_AUTOINC, 1);
429 VDP_setReg(VDP_DMA_SRC2, 0x80);
430 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(1) | CTL_WRITE_DMA);
431 write16(VDP_DATA_PORT, 0x1122);
432 ram[2] = read16(VDP_CTRL_PORT);
a385208c 433 vdp_wait_for_dma_idle();
ffd4b35c 434
435 VDP_setReg(VDP_AUTOINC, 2);
436 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
437 ram[3] = read32(VDP_DATA_PORT);
438}
439
440#define expect(ok_, v0_, v1_) \
e71680d5 441do { if ((v0_) != (v1_)) { \
ffd4b35c 442 printf("%s: %08x %08x\n", #v0_, v0_, v1_); \
443 ok_ = 0; \
e71680d5 444}} while (0)
ffd4b35c 445
a385208c 446#define expect_range(ok_, v0_, vmin_, vmax_) \
e71680d5 447do { if ((v0_) < (vmin_) || (v0_) > (vmax_)) { \
a385208c 448 printf("%s: %02x /%02x-%02x\n", #v0_, v0_, vmin_, vmax_); \
449 ok_ = 0; \
e71680d5 450}} while (0)
a385208c 451
452#define expect_bits(ok_, v0_, val_, mask_) \
e71680d5 453do { if (((v0_) & (mask_)) != (val_)) { \
a385208c 454 printf("%s: %04x & %04x != %04x\n", #v0_, v0_, mask_, val_); \
455 ok_ = 0; \
e71680d5 456}} while (0)
a385208c 457
ffd4b35c 458static int t_dma_zero_wrap(void)
459{
460 const u32 *src = (const u32 *)0x3c0000;
461 const u32 *ram = (const u32 *)0xff0000;
462 int ok = 1;
463
464 expect(ok, ram[0], src[5 + 0x10000/4]);
465 expect(ok, ram[1], src[4]);
466 return ok;
467}
468
469static int t_dma_zero_fill(void)
470{
471 const u32 *ram = (const u32 *)0xff0000;
472 u32 v0 = ram[2] & 2;
473 int ok = 1;
474
475 expect(ok, v0, 2);
476 expect(ok, ram[3], 0x11111111);
477 return ok;
478}
479
480static int t_dma_ram_wrap(void)
481{
482 u32 *ram = (u32 *)0xff0000;
483 u32 saved, v0, v1;
484 int ok = 1;
485
486 saved = read32(&ram[0x10000/4 - 1]);
487 ram[0x10000/4 - 1] = 0x01020304;
488 ram[0] = 0x05060708;
489 do_setup_dma(&ram[0x10000/4 - 1], 4);
490 mem_barrier();
491 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
492
493 mem_barrier();
494 write32(&ram[0x10000/4 - 1], saved);
495
496 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
497 v0 = read32(VDP_DATA_PORT);
498 v1 = read32(VDP_DATA_PORT);
499
500 expect(ok, v0, 0x01020304);
501 expect(ok, v1, 0x05060708);
502 return ok;
503}
504
505// test no src reprogram, only len0
506static int t_dma_multi(void)
507{
508 const u32 *src = (const u32 *)0x3c0000;
509 u32 v0, v1;
510 int ok = 1;
511
512 do_setup_dma(src, 2);
513 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
514 VDP_setReg(VDP_DMA_LEN0, 2);
515 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x104) | CTL_WRITE_DMA);
516
517 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
518 v0 = read32(VDP_DATA_PORT);
519 v1 = read32(VDP_DATA_PORT);
520
521 expect(ok, v0, src[0]);
522 expect(ok, v1, src[1]);
523 return ok;
524}
525
526static int t_dma_cram_wrap(void)
527{
528 u32 *ram = (u32 *)0xff0000;
529 u32 v0, v1;
530 int ok = 1;
531
532 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
533 write32(VDP_DATA_PORT, 0);
534
535 ram[0] = 0x0ec20ec4;
536 ram[1] = 0x0ec60ec8;
537 mem_barrier();
538 do_setup_dma(ram, 4);
539 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0x7c | 0xff81) | CTL_WRITE_DMA);
540
541 write32(VDP_CTRL_PORT, CTL_READ_CRAM(0x7c));
542 v0 = read32(VDP_DATA_PORT) & 0x0eee0eee;
543 write32(VDP_CTRL_PORT, CTL_READ_CRAM(0));
544 v1 = read32(VDP_DATA_PORT) & 0x0eee0eee;
545
546 setup_default_palette();
547
548 expect(ok, v0, ram[0]);
549 expect(ok, v1, ram[1]);
550 return ok;
551}
552
553static int t_dma_vsram_wrap(void)
554{
555 u32 *ram32 = (u32 *)0xff0000;
556 u16 *ram16 = (u16 *)0xff0000;
557 u32 v0, v1;
558 int ok = 1;
559 int i;
560
561 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
562 write32(VDP_DATA_PORT, 0);
563
564 for (i = 0; i < 0x48/2; i++)
565 ram16[i] = i + 1;
566 mem_barrier();
567 do_setup_dma(ram16, 0x48/2);
568 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0x3c | 0xff81) | CTL_WRITE_DMA);
569
570 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0x3c));
571 v0 = read32(VDP_DATA_PORT) & 0x03ff03ff;
572 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0));
573 v1 = read32(VDP_DATA_PORT) & 0x03ff03ff;
574
575 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
576 write32(VDP_DATA_PORT, 0);
577
578 expect(ok, v0, ram32[0]);
579 expect(ok, v1, ram32[0x48/4 - 1]);
580 return ok;
581}
582
583static int t_dma_and_data(void)
584{
585 const u32 *src = (const u32 *)0x3c0000;
a385208c 586 u32 v0, v1;
ffd4b35c 587 int ok = 1;
588
589 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
590 write32(VDP_DATA_PORT, 0);
591
592 do_setup_dma(src, 2);
593 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfc) | CTL_WRITE_DMA);
594 write32(VDP_DATA_PORT, 0x5ec8a248);
595
a385208c 596 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfc));
ffd4b35c 597 v0 = read32(VDP_DATA_PORT);
a385208c 598 v1 = read32(VDP_DATA_PORT);
ffd4b35c 599
a385208c 600 expect(ok, v0, src[0]);
601 expect(ok, v1, 0x5ec8a248);
602 return ok;
603}
604
605static int t_dma_short_cmd(void)
606{
607 const u32 *src = (const u32 *)0x3c0000;
608 u32 v0, v1, v2;
609 int ok = 1;
610
611 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x3ff4));
612 write32(VDP_DATA_PORT, 0x10111213);
613 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfff0));
614 write32(VDP_DATA_PORT, 0x20212223);
615 write32(VDP_DATA_PORT, 0x30313233);
cc7e5122 616 vdp_wait_for_fifo_empty();
a385208c 617
618 do_setup_dma(src, 2);
619 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfff0) | CTL_WRITE_DMA);
620 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x3ff4) >> 16);
621 write32(VDP_DATA_PORT, 0x40414243);
622
623 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x3ff4));
624 v0 = read32(VDP_DATA_PORT);
625 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfff0));
626 v1 = read32(VDP_DATA_PORT);
627 v2 = read32(VDP_DATA_PORT);
628
629 expect(ok, v0, 0x10111213);
630 expect(ok, v1, src[0]);
631 expect(ok, v2, 0x40414243);
ffd4b35c 632 return ok;
633}
634
635static int t_dma_fill3_odd(void)
636{
637 u32 v0, v1, v2;
638 int ok = 1;
639
640 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
641 write32(VDP_DATA_PORT, 0);
642 write32(VDP_DATA_PORT, 0);
643 write32(VDP_DATA_PORT, 0);
cc7e5122 644 vdp_wait_for_fifo_empty();
ffd4b35c 645
646 VDP_setReg(VDP_AUTOINC, 3);
647 VDP_setReg(VDP_DMA_LEN0, 3);
648 VDP_setReg(VDP_DMA_SRC2, 0x80);
649 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x101) | CTL_WRITE_DMA);
650 write16(VDP_DATA_PORT, 0x1122);
a385208c 651 vdp_wait_for_dma_idle();
ffd4b35c 652
653 VDP_setReg(VDP_AUTOINC, 2);
654 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
655 v0 = read32(VDP_DATA_PORT);
656 v1 = read32(VDP_DATA_PORT);
657 v2 = read32(VDP_DATA_PORT);
658
659 expect(ok, v0, 0x22110000);
660 expect(ok, v1, 0x00111100);
661 expect(ok, v2, 0x00000011);
662 return ok;
663}
664
665static int t_dma_fill3_even(void)
666{
667 u32 v0, v1, v2;
668 int ok = 1;
669
670 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
671 write32(VDP_DATA_PORT, 0);
672 write32(VDP_DATA_PORT, 0);
673 write32(VDP_DATA_PORT, 0);
cc7e5122 674 vdp_wait_for_fifo_empty();
ffd4b35c 675
676 VDP_setReg(VDP_AUTOINC, 3);
677 VDP_setReg(VDP_DMA_LEN0, 3);
678 VDP_setReg(VDP_DMA_SRC2, 0x80);
679 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
680 write16(VDP_DATA_PORT, 0x1122);
a385208c 681 vdp_wait_for_dma_idle();
ffd4b35c 682
683 VDP_setReg(VDP_AUTOINC, 2);
684 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
685 v0 = read32(VDP_DATA_PORT);
686 v1 = read32(VDP_DATA_PORT);
687 v2 = read32(VDP_DATA_PORT);
688
689 expect(ok, v0, 0x11221100);
690 expect(ok, v1, 0x00000011);
691 expect(ok, v2, 0x11000000);
692 return ok;
693}
694
695static unused int t_dma_fill3_vsram(void)
696{
697 u32 v0, v1, v2;
698 int ok = 1;
699
700 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
701 write32(VDP_DATA_PORT, 0);
702 write32(VDP_DATA_PORT, 0);
703 write32(VDP_DATA_PORT, 0);
704
705 write16(VDP_DATA_PORT, 0x0111);
706 write16(VDP_DATA_PORT, 0x0222);
707 write16(VDP_DATA_PORT, 0x0333);
a385208c 708 vdp_wait_for_fifo_empty();
ffd4b35c 709
710 VDP_setReg(VDP_AUTOINC, 3);
711 VDP_setReg(VDP_DMA_LEN0, 3);
712 VDP_setReg(VDP_DMA_SRC2, 0x80);
713 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(1) | CTL_WRITE_DMA);
714 write16(VDP_DATA_PORT, 0x0102);
a385208c 715 vdp_wait_for_dma_idle();
ffd4b35c 716
717 VDP_setReg(VDP_AUTOINC, 2);
718 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0));
719 v0 = read32(VDP_DATA_PORT);
720 v1 = read32(VDP_DATA_PORT);
721 v2 = read32(VDP_DATA_PORT);
722
723 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
724 write32(VDP_DATA_PORT, 0);
725
726 expect(ok, v0, 0x01020000);
727 expect(ok, v1, 0x01110111);
728 expect(ok, v2, 0x00000111);
729 return ok;
730}
731
732static int t_dma_fill_dis(void)
733{
734 u32 v0, v1;
735 int ok = 1;
736
737 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
738 write32(VDP_DATA_PORT, 0);
739 write32(VDP_DATA_PORT, 0);
740
741 VDP_setReg(VDP_DMA_LEN0, 1);
742 VDP_setReg(VDP_DMA_SRC2, 0x80);
743 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
744 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
745 write16(VDP_DATA_PORT, 0x1122);
a385208c 746 vdp_wait_for_dma_idle();
ffd4b35c 747
748 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
749 write16(VDP_DATA_PORT, 0x3344);
a385208c 750 vdp_wait_for_dma_idle();
ffd4b35c 751
752 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
753 v0 = read32(VDP_DATA_PORT);
754 v1 = read32(VDP_DATA_PORT);
755
756 expect(ok, v0, 0);
757 expect(ok, v1, 0);
758 return ok;
759}
760
761static int t_dma_fill_src(void)
762{
763 const u32 *src = (const u32 *)0x3c0000;
764 u32 v0, v1;
765 int ok = 1;
766
767 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
768 write32(VDP_DATA_PORT, 0);
769
770 // do_setup_dma(src, 2); // hang, can't write src2 twice
771 VDP_setReg(VDP_DMA_LEN0, 2);
772 VDP_setReg(VDP_DMA_SRC0, (u32)src >> 1);
773 VDP_setReg(VDP_DMA_SRC1, (u32)src >> 9);
774 VDP_setReg(VDP_DMA_SRC2, 0x80);
775 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
776 write16(VDP_DATA_PORT, 0x1122);
a385208c 777 vdp_wait_for_dma_idle();
ffd4b35c 778
779 VDP_setReg(VDP_DMA_LEN0, 2);
780 VDP_setReg(VDP_DMA_SRC2, (u32)src >> 17);
781 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x104) | CTL_WRITE_DMA);
782
783 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
784 v0 = read32(VDP_DATA_PORT);
785 v1 = read32(VDP_DATA_PORT);
786
787 expect(ok, v0, 0x11220011);
788 expect(ok, v1, src[1]);
789 return ok;
790}
791
a385208c 792// (((a & 2) >> 1) ^ 1) | ((a & $400) >> 9) | (a & $3FC) | ((a & $1F800) >> 1)
793static int t_dma_128k(void)
794{
795 u16 *ram = (u16 *)0xff0000;
796 u32 v0, v1;
797 int ok = 1;
798
799 ram[0] = 0x5a11;
800 ram[1] = 0x5a22;
801 ram[2] = 0x5a33;
802
803 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
804 write32(VDP_DATA_PORT, 0x01020304);
805 write32(VDP_DATA_PORT, 0x05060708);
806 vdp_wait_for_fifo_empty();
807
808 mem_barrier();
809 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
810 do_setup_dma(ram, 3);
811 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
812 vdp_wait_for_fifo_empty();
813
814 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
815 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
816 v0 = read32(VDP_DATA_PORT);
817 v1 = read32(VDP_DATA_PORT);
818
819 expect(ok, v0, 0x22110304);
820 expect(ok, v1, 0x05330708);
821 return ok;
822}
823
824static int t_vdp_128k_b16(void)
825{
826 u32 v0, v1;
827 int ok = 1;
828
829 VDP_setReg(VDP_AUTOINC, 0);
830 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8100));
831 write32(VDP_DATA_PORT, 0x01020304);
832 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x10100));
833 write32(VDP_DATA_PORT, 0x05060708);
834 vdp_wait_for_fifo_empty();
835
836 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
837 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) >> 16); // note: upper cmd
838 write32(VDP_DATA_PORT, 0x11223344);
839 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x10102));
840 write32(VDP_DATA_PORT, 0x55667788);
841 vdp_wait_for_fifo_empty();
842
843 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
844 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x8100));
845 v0 = read16(VDP_DATA_PORT);
846 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x0100));
847 v1 = read16(VDP_DATA_PORT);
848
849 VDP_setReg(VDP_AUTOINC, 2);
850
851 expect(ok, v0, 0x8844);
852 expect(ok, v1, 0x0708);
853 return ok;
854}
855
856static unused int t_vdp_128k_b16_inc(void)
857{
858 u32 v0, v1;
859 int ok = 1;
860
861 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
862 write32(VDP_DATA_PORT, 0x01020304);
863 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8000));
864 write32(VDP_DATA_PORT, 0x05060708);
865 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfffe));
866 write32(VDP_DATA_PORT, 0x090a0b0c);
867 vdp_wait_for_fifo_empty();
868
869 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
870 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) >> 16); // note: upper cmd
871 write16(VDP_DATA_PORT, 0x1122);
872 vdp_wait_for_fifo_empty();
873
874 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
875 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
876 v0 = read32(VDP_DATA_PORT);
877 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x8000));
878 v1 = read32(VDP_DATA_PORT);
879 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
880 write32(VDP_DATA_PORT, 0);
881 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8000));
882 write32(VDP_DATA_PORT, 0);
883
884 expect(ok, v0, 0x0b0c0304); // XXX: no 22 anywhere?
885 expect(ok, v1, 0x05060708);
886 return ok;
887}
888
889static int t_vdp_reg_cmd(void)
890{
891 u32 v0;
892 int ok = 1;
893
894 VDP_setReg(VDP_AUTOINC, 0);
895 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
896 write32(VDP_DATA_PORT, 0x01020304);
897 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
898 write32(VDP_DATA_PORT, 0x05060708);
899
900 VDP_setReg(VDP_AUTOINC, 2);
901 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x0100));
902 v0 = read16(VDP_DATA_PORT);
903
904 expect(ok, v0, 0x0304);
905 return ok;
906}
907
cc7e5122 908static int t_vdp_sr_vb(void)
909{
910 u16 sr[4];
911 int ok = 1;
912
913 while (read8(VDP_HV_COUNTER) != 242)
914 ;
915 sr[0] = read16(VDP_CTRL_PORT);
916 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
917 sr[1] = read16(VDP_CTRL_PORT);
918 while (read8(VDP_HV_COUNTER) != 4)
919 ;
920 sr[2] = read16(VDP_CTRL_PORT);
921 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
922 sr[3] = read16(VDP_CTRL_PORT);
923
924 expect_bits(ok, sr[0], SR_VB, SR_VB);
925 expect_bits(ok, sr[1], SR_VB, SR_VB);
926 expect_bits(ok, sr[2], SR_VB, SR_VB);
927 expect_bits(ok, sr[3], 0, SR_VB);
928 return ok;
929}
930
ffd4b35c 931/* z80 tests assume busreq state */
932static int t_z80mem_long_mirror(void)
933{
934 u8 *zram = (u8 *)0xa00000;
935 int ok = 1;
936
937 write8(&zram[0x1100], 0x11);
938 write8(&zram[0x1101], 0x22);
939 write8(&zram[0x1102], 0x33);
940 write8(&zram[0x1103], 0x44);
941 mem_barrier();
942 write32(&zram[0x3100], 0x55667788);
943 mem_barrier();
944
945 expect(ok, zram[0x1100], 0x55);
946 expect(ok, zram[0x1101], 0x22);
947 expect(ok, zram[0x1102], 0x77);
948 expect(ok, zram[0x1103], 0x44);
949 return ok;
950}
951
a385208c 952static int t_z80mem_noreq_w(void)
953{
954 u8 *zram = (u8 *)0xa00000;
955 int ok = 1;
956
957 write8(&zram[0x1100], 0x11);
958 mem_barrier();
959 write16(0xa11100, 0x000);
960 write8(&zram[0x1100], 0x22);
961 mem_barrier();
962
963 write16(0xa11100, 0x100);
964 while (read16(0xa11100) & 0x100)
965 ;
966
967 expect(ok, zram[0x1100], 0x11);
968 return ok;
969}
970
e71680d5 971#define Z80_C_DISPATCH 113 // see z80_test.s80
972#define Z80_C_END 17
973#define Z80_C_END_VCNT 67
974
975#define Z80_CYLES_TEST1(b) (Z80_C_DISPATCH + ((b) - 1) * 21 + 26 + Z80_C_END)
a385208c 976
ffd4b35c 977static int t_z80mem_vdp_r(void)
978{
979 u8 *zram = (u8 *)0xa00000;
980 int ok = 1;
981
982 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
983 write32(VDP_DATA_PORT, 0x11223344);
984 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
985
986 zram[0x1000] = 1; // cp
ffd4b35c 987 write16_z80le(&zram[0x1002], 0x7f00); // src
a385208c 988 write16_z80le(&zram[0x1004], 0x1100); // dst
989 write16_z80le(&zram[0x1006], 2); // len
990 zram[0x1100] = zram[0x1101] = zram[0x1102] = 0x5a;
ffd4b35c 991 mem_barrier();
992 write16(0xa11100, 0x000);
e71680d5 993 burn10(Z80_CYLES_TEST1(2) * 15 / 7 / 10);
ffd4b35c 994
995 write16(0xa11100, 0x100);
996 while (read16(0xa11100) & 0x100)
997 ;
998
999 expect(ok, zram[0x1000], 0);
a385208c 1000 expect(ok, zram[0x1100], 0x11);
1001 expect(ok, zram[0x1101], 0x44);
1002 expect(ok, zram[0x1102], 0x5a);
ffd4b35c 1003 return ok;
1004}
1005
1006static unused int t_z80mem_vdp_w(void)
1007{
1008 u8 *zram = (u8 *)0xa00000;
1009 u32 v0;
1010 int ok = 1;
1011
1012 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
1013 write32(VDP_DATA_PORT, 0x11223344);
1014 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
a385208c 1015 vdp_wait_for_fifo_empty();
ffd4b35c 1016
1017 zram[0x1000] = 1; // cp
a385208c 1018 write16_z80le(&zram[0x1002], 0x1100); // src
ffd4b35c 1019 write16_z80le(&zram[0x1004], 0x7f00); // dst
a385208c 1020 write16_z80le(&zram[0x1006], 2); // len
1021 zram[0x1100] = 0x55;
1022 zram[0x1101] = 0x66;
ffd4b35c 1023 mem_barrier();
1024 write16(0xa11100, 0x000);
e71680d5 1025 burn10(Z80_CYLES_TEST1(2) * 15 / 7 / 10);
ffd4b35c 1026
1027 write16(0xa11100, 0x100);
1028 while (read16(0xa11100) & 0x100)
1029 ;
1030
1031 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
1032 v0 = read32(VDP_DATA_PORT);
1033
1034 expect(ok, zram[0x1000], 0);
1035 expect(ok, v0, 0x55556666);
1036 return ok;
1037}
1038
a385208c 1039static int t_tim_loop(void)
1040{
1041 u8 vcnt;
1042 int ok = 1;
1043
1044 vdp_wait_for_line_0();
1045 burn10(488*220/10);
1046 vcnt = read8(VDP_HV_COUNTER);
1047 mem_barrier();
1048
1049 //expect_range(ok, vcnt, 0x80, 0x80);
1050 expect(ok, vcnt, 223);
1051 return ok;
1052}
1053
e71680d5 1054static int t_tim_z80_loop(void)
1055{
1056 u8 pal = read8(0xa10001) & 0x40;
1057 u8 *zram = (u8 *)0xa00000;
1058 u16 z80_loops = pal ? 3420*(313*2+1)/15/100 : 3420*(262*2+1)/15/100; // 2fr + 1ln
1059 u16 _68k_loops = pal ? 3420*(313*2+1)/7/10 : 3420*(262*2+1)/7/10;
1060 int ok = 1;
1061
1062 zram[0x1000] = 3; // idle loop, save vcnt
1063 write16_z80le(&zram[0x1002], 0); // src (unused)
1064 write16_z80le(&zram[0x1004], 0x1100); // vcnt dst
1065 write16_z80le(&zram[0x1006], z80_loops); // x100 cycles
1066 zram[0x1100] = 0;
1067 mem_barrier();
1068
1069 vdp_wait_for_line_0();
1070 write16(0xa11100, 0x000);
1071 burn10(_68k_loops + (Z80_C_DISPATCH + Z80_C_END_VCNT) * 15 / 7 / 10);
1072
1073 write16(0xa11100, 0x100);
1074 while (read16(0xa11100) & 0x100)
1075 ;
1076 expect(ok, zram[0x1000], 0);
1077 expect(ok, zram[0x1100], 1);
1078 return ok;
1079}
1080
1081#define Z80_CYCLES_TEST2(b) (Z80_C_DISPATCH + (b) * 38 + Z80_C_END_VCNT)
a385208c 1082
1083// 80 80 91 95-96
1084static void z80_read_loop(u8 *zram, u16 src)
1085{
1086 const int pairs = 512 + 256;
1087
1088 zram[0x1000] = 2; // read loop, save vcnt
1089 write16_z80le(&zram[0x1002], src); // src
1090 write16_z80le(&zram[0x1004], 0x1100); // vcnt dst
1091 write16_z80le(&zram[0x1006], pairs); // reads/2
1092 zram[0x1100] = 0;
1093 mem_barrier();
1094
1095 vdp_wait_for_line_0();
1096 write16(0xa11100, 0x000);
e71680d5 1097 burn10(Z80_CYCLES_TEST2(pairs) * 15 / 7 * 2 / 10);
a385208c 1098
1099 write16(0xa11100, 0x100);
1100 while (read16(0xa11100) & 0x100)
1101 ;
1102}
1103
1104static int t_tim_z80_ram(void)
1105{
1106 u8 *zram = (u8 *)0xa00000;
1107 int ok = 1;
1108
1109 z80_read_loop(zram, 0);
1110
1111 expect(ok, zram[0x1000], 0);
1112 expect_range(ok, zram[0x1100], 0x80, 0x80);
1113 return ok;
1114}
1115
1116static int t_tim_z80_ym(void)
1117{
1118 u8 *zram = (u8 *)0xa00000;
1119 int ok = 1;
1120
1121 z80_read_loop(zram, 0x4000);
1122
1123 expect(ok, zram[0x1000], 0);
1124 expect_range(ok, zram[0x1100], 0x80, 0x80);
1125 return ok;
1126}
1127
1128static int t_tim_z80_vdp(void)
1129{
1130 u8 *zram = (u8 *)0xa00000;
1131 int ok = 1;
1132
1133 z80_read_loop(zram, 0x7f08);
1134
1135 expect(ok, zram[0x1000], 0);
a385208c 1136 expect_range(ok, zram[0x1100], 0x91, 0x91);
a385208c 1137 return ok;
1138}
1139
1140static int t_tim_z80_bank_rom(void)
1141{
1142 u8 *zram = (u8 *)0xa00000;
1143 int i, ok = 1;
1144
1145 for (i = 0; i < 17; i++)
1146 write8(0xa06000, 0); // bank 0
1147
1148 z80_read_loop(zram, 0x8000);
1149
1150 expect(ok, zram[0x1000], 0);
a385208c 1151 expect_range(ok, zram[0x1100], 0x95, 0x96);
a385208c 1152 return ok;
1153}
1154
1155/* borderline too slow */
1156#if 0
cc7e5122 1157static void test_vcnt_vb(void)
a385208c 1158{
1159 const u32 *srhv = (u32 *)0xc00006; // to read SR and HV counter
1160 u32 *ram = (u32 *)0xff0000;
1161 u16 vcnt, vcnt_expect = 0;
1162 u16 sr, count = 0;
1163 u32 val, old;
1164
1165 vdp_wait_for_line_0();
1166 old = read32(srhv);
1167 *ram++ = old;
1168 for (;;) {
1169 val = read32(srhv);
1170 vcnt = val & 0xff00;
1171 if (vcnt == vcnt_expect)
1172 continue;
1173 sr = val >> 16;
1174 if (vcnt == 0 && !(sr & SR_VB)) // not VB
1175 break; // wrapped to start of frame
1176// count++;
1177 vcnt_expect += 0x100;
1178 if (vcnt == vcnt_expect && !((sr ^ (old >> 16)) & SR_VB)) {
1179 old = val;
1180 continue;
1181 }
1182 // should have a vcnt jump here
1183 *ram++ = old;
1184 *ram++ = val;
1185 vcnt_expect = vcnt;
1186 old = val;
1187 }
1188 *ram++ = val;
1189 *ram = count;
1190 mem_barrier();
1191}
1192#endif
1193
1194static int t_tim_vcnt(void)
1195{
1196 const u32 *ram32 = (u32 *)0xff0000;
1197 const u8 *ram = (u8 *)0xff0000;
1198 u8 pal = read8(0xa10001) & 0x40;
1199 u8 vc_jmp_b = pal ? 0x02 : 0xea;
1200 u8 vc_jmp_a = pal ? 0xca : 0xe5;
1201 u16 lines = pal ? 313 : 262;
1202 int ok = 1;
1203
cc7e5122 1204 test_vcnt_vb();
a385208c 1205 expect(ok, ram[0*4+2], 0); // line 0
1206 expect_bits(ok, ram[0*4+1], 0, SR_VB);
1207 expect(ok, ram[1*4+2], 223); // last no blank
1208 expect_bits(ok, ram[1*4+1], 0, SR_VB);
1209 expect(ok, ram[2*4+2], 224); // 1st blank
1210 expect_bits(ok, ram[2*4+1], SR_VB, SR_VB);
1211 expect(ok, ram[3*4+2], vc_jmp_b); // before jump
1212 expect_bits(ok, ram[3*4+1], SR_VB, SR_VB);
1213 expect(ok, ram[4*4+2], vc_jmp_a); // after jump
1214 expect_bits(ok, ram[4*4+1], SR_VB, SR_VB);
1215 expect(ok, ram[5*4+2], 0xfe); // before vb clear
1216 expect_bits(ok, ram[5*4+1], SR_VB, SR_VB);
1217 expect(ok, ram[6*4+2], 0xff); // after vb clear
1218 expect_bits(ok, ram[6*4+1], 0, SR_VB);
1219 expect(ok, ram[7*4+2], 0); // next line 0
1220 expect_bits(ok, ram[7*4+1], 0, SR_VB);
1221 expect(ok, ram32[8], lines - 1);
1222 return ok;
1223}
1224
e71680d5 1225static int t_tim_vcnt_loops(void)
1226{
1227 const u16 *ram16 = (u16 *)0xfff004;
1228 u8 pal = read8(0xa10001) & 0x40;
1229 u16 i, lines = pal ? 313 : 262;
1230 int ok = 1;
1231
1232 test_vcnt_loops();
1233 expect(ok, ram16[-1*2+0], 0xff);
1234 expect_range(ok, ram16[-1*2+1], 21, 22);
1235 for (i = 0; i < lines; i++)
1236 expect_range(ok, ram16[i*2+1], 19, 21);
1237 expect(ok, ram16[lines*2+0], 0);
1238 expect_range(ok, ram16[lines*2+1], 20, 21);
1239 return ok;
1240}
1241
cc7e5122 1242static int t_tim_hblank_h40(void)
1243{
1244 const u8 *r = (u8 *)0xff0000;
1245 int ok = 1;
1246
1247 test_hb();
1248
1249 // set: 0-2
1250 expect_bits(ok, r[2], SR_HB, SR_HB);
1251 expect_bits(ok, r[5], SR_HB, SR_HB);
1252 // <wait>
1253 expect_bits(ok, r[7], SR_HB, SR_HB);
1254 // clear: 8-11
1255 expect_bits(ok, r[12], 0, SR_HB);
1256 return ok;
1257}
1258
1259static int t_tim_hblank_h32(void)
1260{
1261 const u8 *r = (u8 *)0xff0000;
1262 int ok = 1;
1263
1264 VDP_setReg(VDP_MODE4, 0x00);
1265 test_hb();
1266 VDP_setReg(VDP_MODE4, 0x81);
1267
cc7e5122 1268 expect_bits(ok, r[0], 0, SR_HB);
cc7e5122 1269 // set: 1-4
1270 expect_bits(ok, r[4], SR_HB, SR_HB);
1271 expect_bits(ok, r[5], SR_HB, SR_HB);
1272 // <wait>
1273 expect_bits(ok, r[8], SR_HB, SR_HB);
1274 // clear: 9-11
1275 expect_bits(ok, r[12], 0, SR_HB);
1276 return ok;
1277}
1278
a385208c 1279static int t_tim_vdp_as_vram_w(void)
1280{
1281 int ok = 1;
1282 u8 vcnt;
1283
1284 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
1285 vdp_wait_for_line_0();
1286 write16_x16(VDP_DATA_PORT, 112*18 / 16, 0);
1287 vcnt = read8(VDP_HV_COUNTER);
1288 mem_barrier();
1289
1290 expect(ok, vcnt, 112*2-1);
1291 return ok;
1292}
1293
1294static int t_tim_vdp_as_cram_w(void)
1295{
1296 int ok = 1;
1297 u8 vcnt;
1298
1299 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
1300 vdp_wait_for_line_0();
1301 write16_x16(VDP_DATA_PORT, 112*18 / 16, 0);
1302 vcnt = read8(VDP_HV_COUNTER);
1303 mem_barrier();
1304
1305 setup_default_palette();
1306
a385208c 1307 expect(ok, vcnt, 112);
a385208c 1308 return ok;
1309}
1310
e71680d5 1311static const u8 hcnt2tm[] =
1312{
1313 0x0a, 0x1d, 0x31, 0x44, 0x58, 0x6b, 0x7f, 0x92,
1314 0xa6, 0xb9, 0xcc, 0x00, 0x00, 0x00, 0xe2, 0xf6
1315};
1316
1317static int t_tim_ym_timer_z80(int is_b)
1318{
1319 u8 pal = read8(0xa10001) & 0x40;
1320 u8 *zram = (u8 *)0xa00000;
1321 u8 *z80 = zram;
1322 u16 _68k_loops = 3420*(302+5+1)/7/10; // ~ (72*1024*2)/(3420./7)
1323 u16 start, end, diff;
1324 int ok = 1;
1325
1326 zram[0x1000] = 4 + is_b; // ym2612 timer a/b test
1327 zram[0x1100] = zram[0x1101] = zram[0x1102] = zram[0x1103] = 0;
1328 mem_barrier();
1329
1330 vdp_wait_for_line_0();
1331 write16(0xa11100, 0x000);
1332
1333 burn10(_68k_loops + (Z80_C_DISPATCH + Z80_C_END_VCNT) * 15 / 7 / 10);
1334
1335 write16(0xa11100, 0x100);
1336 while (read16(0xa11100) & 0x100)
1337 ;
1338 mem_barrier();
1339 expect(ok, zram[0x1000], 0);
1340 (void)hcnt2tm;
1341 //start = ((u16)zram[0x1102] << 8) | hcnt2tm[zram[0x1103] >> 4];
1342 //end = ((u16)zram[0x1100] << 8) | hcnt2tm[zram[0x1101] >> 4];
1343 start = zram[0x1102];
1344 end = zram[0x1100];
1345 diff = end - start;
1346 if (pal)
1347 expect_range(ok, diff, 0xf4, 0xf6);
1348 else
1349 expect_range(ok, diff, 0x27, 0x29);
1350 write8(&z80[0x4001], 0); // stop, but should keep the flag
1351 mem_barrier();
1352 burn10(32*6/10); // busy bit, 32 FM ticks (M/7/6)
1353 if (is_b) {
1354 expect(ok, z80[0x4000], 2);
1355 write8(&z80[0x4001], 0x20); // reset flag (reg 0x27, set up by z80)
1356 }
1357 else {
1358 expect(ok, z80[0x4000], 1);
1359 write8(&z80[0x4001], 0x10);
1360 }
1361 mem_barrier();
1362 burn10(32*6/10);
1363 expect(ok, z80[0x4000], 0);
1364 return ok;
1365}
1366
1367static int t_tim_ym_timera_z80(void)
1368{
1369 return t_tim_ym_timer_z80(0);
1370}
1371
1372static int t_tim_ym_timerb_z80(void)
1373{
1374 return t_tim_ym_timer_z80(1);
1375}
1376
1377static int t_tim_ym_timerb_stop(void)
1378{
1379 const struct {
1380 //u8 vcnt_start;
1381 //u8 hcnt_start;
1382 u16 vcnt_start;
1383 u16 stat0;
1384 //u8 vcnt_end;
1385 //u8 hcnt_end;
1386 u16 vcnt_end;
1387 u16 stat1;
1388 } *t = (void *)0xfff000;
1389 u8 *z80 = (u8 *)0xa00000;
1390 u16 diff;
1391 int ok = 1;
1392 write16(0xa11100, 0x100);
1393 while (read16(0xa11100) & 0x100)
1394 ;
1395 test_ym_stopped_tick();
1396 mem_barrier();
1397 //start = ((u16)t->vcnt_start << 8) | hcnt2tm[t->hcnt_start >> 4];
1398 //end = ((u16)t->vcnt_end << 8) | hcnt2tm[t->hcnt_end >> 4];
1399 //diff = end - start;
1400 diff = t->vcnt_end - t->vcnt_start;
1401 //expect_range(ok, diff, 0x492, 0x5c2); // why so much variation?
1402 expect_range(ok, diff, 4, 5);
1403 expect(ok, t->stat0, 0);
1404 expect(ok, t->stat1, 2);
1405 expect(ok, z80[0x4000], 2);
1406 write8(&z80[0x4001], 0x30);
1407 return ok;
1408}
1409
1410static int t_tim_ym_timer_ab_sync(void)
1411{
1412 u16 v = test_ym_ab_sync();
1413 int ok = 1;
1414 expect(ok, v, 3);
1415 return ok;
1416}
1417
4f936a9c 1418struct irq_test {
1419 u16 cnt;
1420 union {
1421 u16 hv;
1422 u8 v;
1423 } first, last;
8517a6df 1424 u16 pad;
4f936a9c 1425};
1426
e71680d5 1427// broken on fresh boot due to uknown reasons
6c839579 1428static int t_irq_hint(void)
1429{
4f936a9c 1430 struct irq_test *it = (void *)0xfff000;
e71680d5 1431 struct irq_test *itv = it + 1;
6c839579 1432 int ok = 1;
1433
e71680d5 1434 memset_(it, 0, sizeof(*it) * 2);
1435 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1436 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1437
1438 // without this, tests fail after cold boot
1439 while (!(read16(VDP_CTRL_PORT) & 8))
1440 /* not blanking */;
1441
6c839579 1442 // for more fun, disable the display
1443 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
1444
6c839579 1445 VDP_setReg(10, 0);
1446 while (read8(VDP_HV_COUNTER) != 100)
1447 ;
1448 while (read8(VDP_HV_COUNTER) != 229)
1449 ;
1450 // take the pending irq
1451 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1452 move_sr(0x2000);
1453 burn10(488 * 2 / 10);
1454 move_sr(0x2700);
4f936a9c 1455 expect(ok, it->first.v, 229); // pending irq trigger
1456 expect(ok, it->cnt, 1);
e71680d5 1457 expect(ok, itv->cnt, 0);
4f936a9c 1458
6c839579 1459 // count irqs
4f936a9c 1460 it->cnt = it->first.hv = it->last.hv = 0;
6c839579 1461 move_sr(0x2000);
cc7e5122 1462 while (read8(VDP_HV_COUNTER) != 4)
6c839579 1463 ;
1464 while (read8(VDP_HV_COUNTER) != 228)
1465 ;
1466 move_sr(0x2700);
4f936a9c 1467 expect(ok, it->cnt, 225);
1468 expect(ok, it->first.v, 0);
1469 expect(ok, it->last.v, 224);
1470
6c839579 1471 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1472
4f936a9c 1473 // detect reload line
1474 it->cnt = it->first.hv = it->last.hv = 0;
1475 VDP_setReg(10, 17);
1476 move_sr(0x2000);
1477 while (read16(VDP_CTRL_PORT) & 8)
1478 /* blanking */;
1479 VDP_setReg(10, 255);
1480 while (read8(VDP_HV_COUNTER) != 228)
1481 ;
1482 move_sr(0x2700);
1483 expect(ok, it->cnt, 1);
1484 expect(ok, it->first.v, 17);
1485 expect(ok, it->last.v, 17);
1486
1487 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1488
6c839579 1489 return ok;
1490}
1491
8517a6df 1492static int t_irq_both_cpu_unmask(void)
1493{
1494 struct irq_test *ith = (void *)0xfff000;
1495 struct irq_test *itv = ith + 1;
1496 u16 s0, s1;
1497 int ok = 1;
1498
1499 memset_(ith, 0, sizeof(*ith) * 2);
1500 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1501 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1502 VDP_setReg(10, 0);
1503 while (read8(VDP_HV_COUNTER) != 100)
1504 ;
1505 while (read8(VDP_HV_COUNTER) != 226)
1506 ;
1507 VDP_setReg(10, 99);
1508 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1509 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP);
1510 /* go to active display line 100 */
1511 while (read8(VDP_HV_COUNTER) != 100)
1512 ;
1513 s0 = read16(VDP_CTRL_PORT);
1514 s1 = move_sr_and_read(0x2000, VDP_CTRL_PORT);
1515 move_sr(0x2700);
1516 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1517 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1518
1519 expect(ok, itv->cnt, 1); // vint count
1520 expect(ok, itv->first.v, 100); // vint line
1521 expect(ok, ith->cnt, 1); // hint count
1522 expect(ok, ith->first.v, 100); // hint line
1523 expect_bits(ok, s0, SR_F, SR_F);
1524 expect_bits(ok, s1, 0, SR_F);
1525 return ok;
1526}
1527
6c839579 1528static int t_irq_ack_v_h(void)
1529{
8517a6df 1530 struct irq_test *ith = (void *)0xfff000;
1531 struct irq_test *itv = ith + 1;
6c839579 1532 u16 s0, s1, s2;
1533 int ok = 1;
1534
8517a6df 1535 memset_(ith, 0, sizeof(*ith) * 2);
6c839579 1536 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1537 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1538 VDP_setReg(10, 0);
4f936a9c 1539 /* ensure hcnt reload */
1540 while (!(read16(VDP_CTRL_PORT) & 8))
1541 /* not blanking */;
1542 while (read16(VDP_CTRL_PORT) & 8)
1543 /* blanking */;
6c839579 1544 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1545 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0);
1546 while (read8(VDP_HV_COUNTER) != 100)
1547 ;
1548 while (read8(VDP_HV_COUNTER) != 226)
1549 ;
1550 s0 = read16(VDP_CTRL_PORT);
1551 s1 = move_sr_and_read(0x2500, VDP_CTRL_PORT);
1552 burn10(666 / 10);
1553 s2 = move_sr_and_read(0x2000, VDP_CTRL_PORT);
1554 burn10(488 / 10);
1555 move_sr(0x2700);
1556 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1557 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1558
8517a6df 1559 expect(ok, itv->cnt, 1); // vint count
1560 expect(ok, itv->first.v, 226); // vint line
1561 expect(ok, ith->cnt, 1); // hint count
1562 expect(ok, ith->first.v, 228); // hint line
6c839579 1563 expect_bits(ok, s0, SR_F, SR_F);
1564 expect_bits(ok, s1, 0, SR_F);
1565 expect_bits(ok, s2, 0, SR_F);
1566 return ok;
1567}
1568
cc7e5122 1569static int t_irq_ack_v_h_2(void)
1570{
8517a6df 1571 struct irq_test *ith = (void *)0xfff000;
1572 struct irq_test *itv = ith + 1;
cc7e5122 1573 u16 s0, s1;
1574 int ok = 1;
1575
8517a6df 1576 memset_(ith, 0, sizeof(*ith) * 2);
cc7e5122 1577 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1578 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1579 VDP_setReg(10, 0);
1580 while (read8(VDP_HV_COUNTER) != 100)
1581 ;
1582 while (read8(VDP_HV_COUNTER) != 226)
1583 ;
1584 s0 = read16(VDP_CTRL_PORT);
1585 test_v_h_2();
1586 s1 = read16(VDP_CTRL_PORT);
1587 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1588 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1589
8517a6df 1590 expect(ok, itv->cnt, 2); // vint count
1591 expect(ok, itv->first.v, 226); // vint line
1592 expect(ok, ith->cnt, 1); // hint count
1593 expect(ok, ith->first.v, 227); // hint line
cc7e5122 1594 expect_bits(ok, s0, SR_F, SR_F);
1595 expect_bits(ok, s1, 0, SR_F);
1596 return ok;
1597}
1598
6c839579 1599static int t_irq_ack_h_v(void)
1600{
1601 u16 *ram = (u16 *)0xfff000;
1602 u8 *ram8 = (u8 *)0xfff000;
1603 u16 s0, s1, s[4];
1604 int ok = 1;
1605
1606 ram[0] = ram[1] = ram[2] =
1607 ram[4] = ram[5] = ram[6] = 0;
1608 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1609 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1610 VDP_setReg(10, 0);
1611 while (read8(VDP_HV_COUNTER) != 100)
1612 ;
1613 while (read8(VDP_HV_COUNTER) != 226)
1614 ;
1615 s0 = read16(VDP_CTRL_PORT);
1616 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1617 move_sr(0x2000);
1618 burn10(666 / 10);
1619 s1 = read16(VDP_CTRL_PORT);
1620 write_and_read1(VDP_CTRL_PORT, 0x8000 | (VDP_MODE2 << 8)
1621 | VDP_MODE2_MD | VDP_MODE2_IE0, s);
6c839579 1622 move_sr(0x2700);
1623 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1624 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1625
1626 expect(ok, ram[0], 1); // hint count
1627 expect(ok, ram8[2], 226); // hint line
1628 expect(ok, ram[4], 1); // vint count
1629 expect(ok, ram8[10], 228); // vint line
1630 expect_bits(ok, s0, SR_F, SR_F);
1631 expect_bits(ok, s1, SR_F, SR_F);
1632 expect_bits(ok, s[0], SR_F, SR_F);
1633 expect_bits(ok, s[1], SR_F, SR_F);
1634 expect_bits(ok, s[2], 0, SR_F);
1635 expect_bits(ok, s[3], 0, SR_F);
1636 return ok;
1637}
1638
cc7e5122 1639static int t_irq_ack_h_v_2(void)
1640{
1641 u16 *ram = (u16 *)0xfff000;
1642 u8 *ram8 = (u8 *)0xfff000;
1643 u16 s0, s1;
1644 int ok = 1;
1645
1646 ram[0] = ram[1] = ram[2] =
1647 ram[4] = ram[5] = ram[6] = 0;
1648 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1649 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1650 VDP_setReg(10, 0);
1651 while (read8(VDP_HV_COUNTER) != 100)
1652 ;
1653 while (read8(VDP_HV_COUNTER) != 226)
1654 ;
1655 s0 = read16(VDP_CTRL_PORT);
1656 test_h_v_2();
1657 s1 = read16(VDP_CTRL_PORT);
1658 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1659 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1660
1661 expect(ok, ram[0], 2); // hint count
1662 expect(ok, ram8[2], 226); // hint first line
1663 expect(ok, ram8[4], 226); // hint last line
1664 expect(ok, ram[4], 0); // vint count
1665 expect(ok, ram8[10], 0); // vint line
1666 expect_bits(ok, s0, SR_F, SR_F);
1667 expect_bits(ok, s1, 0, SR_F);
1668 return ok;
1669}
1670
1671static void t_irq_f_flag(void)
1672{
1673 memcpy_((void *)0xff0140, test_f_vint, test_f_vint_end - test_f_vint);
1674 memset_((void *)0xff0000, 0, 10);
1675 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP);
1676 test_f();
1677 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1678}
1679
1680static int t_irq_f_flag_h40(void)
1681{
1682 u8 f, *r = (u8 *)0xff0000;
1683 int ok = 1;
1684
1685 t_irq_f_flag();
1686
1687 expect_bits(ok, r[0], 0, SR_F);
1688 expect_bits(ok, r[1], 0, SR_F);
1689 expect_bits(ok, r[2], 0, SR_F);
1690 // hits 1-3 times in range 3-9, usually ~5
1691 f = r[3] | r[4] | r[5] | r[6] | r[7];
1692
1693 expect_bits(ok, r[10], 0, SR_F);
1694 expect_bits(ok, r[11], 0, SR_F);
1695 expect_bits(ok, f, SR_F, SR_F);
1696 return ok;
1697}
1698
1699static int t_irq_f_flag_h32(void)
1700{
1701 u8 f, *r = (u8 *)0xff0000;
1702 int ok = 1;
1703
1704 VDP_setReg(VDP_MODE4, 0x00);
1705 t_irq_f_flag();
1706 VDP_setReg(VDP_MODE4, 0x81);
1707
1708 expect_bits(ok, r[0], 0, SR_F);
1709 expect_bits(ok, r[1], 0, SR_F);
1710 // hits 1-3 times in range 2-7, usually 3
1711 f = r[2] | r[3] | r[4] | r[5] | r[6] | r[7];
1712
1713 expect_bits(ok, r[8], 0, SR_F);
1714 expect_bits(ok, r[9], 0, SR_F);
1715 expect_bits(ok, r[10], 0, SR_F);
1716 expect_bits(ok, r[11], 0, SR_F);
1717 expect_bits(ok, f, SR_F, SR_F);
1718 return ok;
1719}
1720
9d39a80e 1721// 32X
1722
1723static int t_32x_init(void)
1724{
1725 void (*do_32x_enable)(void) = (void *)0xff0040;
1726 u32 M_OK = MKLONG('M','_','O','K');
1727 u32 S_OK = MKLONG('S','_','O','K');
1728 u32 *r = (u32 *)0xa15100;
1729 u16 *r16 = (u16 *)r;
71b41fdd 1730 int i, ok = 1;
9d39a80e 1731
71b41fdd 1732 //v1070 = read32(0x1070);
1733
1734 /* what does REN mean exactly?
1735 * Seems to be sometimes clear after reset */
1736 for (i = 0; i < 1000000; i++)
1737 if (read16(r16) & 0x80)
1738 break;
9d39a80e 1739 expect(ok, r16[0x00/2], 0x82);
1740 expect(ok, r16[0x02/2], 0);
1741 expect(ok, r16[0x04/2], 0);
1742 expect(ok, r16[0x06/2], 0);
1743 expect(ok, r[0x14/4], 0);
1744 expect(ok, r[0x18/4], 0);
1745 expect(ok, r[0x1c/4], 0);
1746 write32(&r[0x20/4], 0); // master resp
1747 write32(&r[0x24/4], 0); // slave resp
71b41fdd 1748 write32(&r[0x28/4], 0);
1749 write32(&r[0x2c/4], 0);
9d39a80e 1750
1751 // could just set RV, but BIOS reads ROM, so can't
1752 memcpy_(do_32x_enable, x32x_enable,
1753 x32x_enable_end - x32x_enable);
1754 do_32x_enable();
1755
1756 expect(ok, r16[0x00/2], 0x83);
1757 expect(ok, r16[0x02/2], 0);
1758 expect(ok, r16[0x04/2], 0);
1759 expect(ok, r16[0x06/2], 1); // RV
1760 expect(ok, r[0x14/4], 0);
1761 expect(ok, r[0x18/4], 0);
1762 expect(ok, r[0x1c/4], 0);
1763 expect(ok, r[0x20/4], M_OK);
1764 while (!read16(&r16[0x24/2]))
1765 ;
1766 expect(ok, r[0x24/4], S_OK);
06d7984c 1767 write32(&r[0x20/4], 0);
9d39a80e 1768 return ok;
1769}
1770
06d7984c 1771static void x32_cmd(enum x32x_cmd cmd, u32 a0, u32 a1, u16 is_slave)
9d39a80e 1772{
1773 u16 v, *r = (u16 *)0xa15120;
1774 u16 cmd_s = cmd | (is_slave << 15);
71b41fdd 1775 int i;
06d7984c 1776
1777 write32(&r[4/2], a0);
1778 write32(&r[8/2], a1);
1779 mem_barrier();
9d39a80e 1780 write16(r, cmd_s);
1781 mem_barrier();
71b41fdd 1782 for (i = 0; i < 10000 && (v = read16(r)) == cmd_s; i++)
9d39a80e 1783 burn10(1);
71b41fdd 1784 if (v != 0) {
9d39a80e 1785 printf("cmd clr: %x\n", v);
06d7984c 1786 mem_barrier();
1787 printf("c, e: %02x %02x\n", r[0x0c/2], r[0x0e/2]);
71b41fdd 1788 write16(r, 0);
1789 }
06d7984c 1790 v = read16(&r[1]);
1791 if (v != 0) {
1792 printf("cmd err: %x\n", v);
1793 write16(&r[1], 0);
1794 }
9d39a80e 1795}
1796
1797static int t_32x_echo(void)
1798{
1799 u16 *r = (u16 *)0xa15120;
1800 int ok = 1;
1801
06d7984c 1802 x32_cmd(CMD_ECHO, 0x12340000, 0, 0);
1803 expect(ok, r[0x06/2], 0x1234);
1804 x32_cmd(CMD_ECHO, 0x23450000, 0, 1);
1805 expect(ok, r[0x06/2], 0xa345);
1806 return ok;
1807}
1808
1809static int t_32x_md_bios(void)
1810{
1811 void (*do_call_c0)(int a, int d) = (void *)0xff0040;
1812 u8 *rmb = (u8 *)0xff0000;
1813 u32 *rl = (u32 *)0;
1814 int ok = 1;
1815
1816 memcpy_(do_call_c0, test_32x_b_c0,
1817 test_32x_b_c0_end - test_32x_b_c0);
1818 write8(rmb, 0);
1819 do_call_c0(0xff0000, 0x5a);
1820
1821 expect(ok, rmb[0], 0x5a);
1822 expect(ok, rl[0x04/4], 0x880200);
234c4556 1823 expect(ok, rl[0x10/4], 0x880212);
1824 expect(ok, rl[0x94/4], 0x8802d8);
9d39a80e 1825 return ok;
1826}
1827
1828static int t_32x_md_rom(void)
1829{
1830 u32 *rl = (u32 *)0;
1831 int ok = 1;
1832
1833 expect(ok, rl[0x004/4], 0x880200);
1834 expect(ok, rl[0x100/4], 0x53454741);
1835 expect(ok, rl[0x70/4], 0);
71b41fdd 1836 write32(&rl[0x70/4], 0xa5123456);
9d39a80e 1837 write32(&rl[0x78/4], ~0);
1838 mem_barrier();
9d39a80e 1839 expect(ok, rl[0x78/4], 0x8802ae);
71b41fdd 1840 expect(ok, rl[0x70/4], 0xa5123456);
1841 //expect(ok, rl[0x1070/4], v1070);
1842 write32(&rl[0x70/4], 0);
1843 // with RV 0x880000/0x900000 hangs, can't test
9d39a80e 1844 return ok;
1845}
1846
06d7984c 1847static int t_32x_md_fb(void)
1848{
1849 u8 *fbb = (u8 *)0x840000;
1850 u16 *fbw = (u16 *)fbb;
1851 u32 *fbl = (u32 *)fbb;
1852 u8 *fob = (u8 *)0x860000;
1853 u16 *fow = (u16 *)fob;
1854 u32 *fol = (u32 *)fob;
1855 int ok = 1;
1856
1857 fbl[0] = 0x12345678;
1858 fol[1] = 0x89abcdef;
1859 mem_barrier();
1860 expect(ok, fbw[1], 0x5678);
1861 expect(ok, fow[2], 0x89ab);
1862 fbb[0] = 0;
1863 fob[1] = 0;
1864 fbw[1] = 0;
1865 fow[2] = 0;
1866 fow[3] = 1;
1867 mem_barrier();
1868 fow[3] = 0x200;
1869 mem_barrier();
1870 expect(ok, fol[0], 0x12340000);
1871 expect(ok, fbl[1], 0x89ab0201);
1872 return ok;
1873}
1874
1875static int t_32x_sh_fb(void)
1876{
1877 u32 *fbl = (u32 *)0x840000;
1878 int ok = 1;
1879
1880 fbl[0] = 0x12345678;
1881 fbl[1] = 0x89abcdef;
1882 mem_barrier();
1883 write8(0xa15100, 0x80); // FM=1
1884 x32_cmd(CMD_WRITE8, 0x24000000, 0, 0);
1885 x32_cmd(CMD_WRITE8, 0x24020001, 0, 0);
1886 x32_cmd(CMD_WRITE16, 0x24000002, 0, 0);
1887 x32_cmd(CMD_WRITE16, 0x24020000, 0, 0);
1888 x32_cmd(CMD_WRITE32, 0x24020004, 0x5a0000a5, 1);
1889 write8(0xa15100, 0x00); // FM=0
1890 mem_barrier();
1891 expect(ok, fbl[0], 0x12340000);
1892 expect(ok, fbl[1], 0x5aabcda5);
1893 return ok;
1894}
1895
234c4556 1896static int t_32x_disable(void)
1897{
1898 void (*do_32x_disable)(void) = (void *)0xff0040;
1899 u32 *r = (u32 *)0xa15100;
1900 u16 *r16 = (u16 *)r;
1901 u32 *rl = (u32 *)0;
1902 int ok = 1;
1903
1904 expect(ok, r16[0x00/2], 0x83);
1905
1906 memcpy_(do_32x_disable, x32x_disable,
1907 x32x_disable_end - x32x_disable);
1908 do_32x_disable();
1909
1910 expect(ok, r16[0x00/2], 0x82);
1911 expect(ok, r16[0x02/2], 0);
1912 expect(ok, r16[0x04/2], 0);
1913 expect(ok, r16[0x06/2], 1); // RV
1914 expect(ok, r[0x14/4], 0);
1915 expect(ok, r[0x18/4], 0);
1916 expect(ok, r[0x1c/4], 0);
1917 expect(ok, rl[0x04/4], 0x000800);
1918
1919 write16(&r16[0x06/2], 0); // can just set without ADEN
1920 mem_barrier();
1921 expect(ok, r16[0x06/2], 0); // RV
1922 return ok;
1923}
1924
9d39a80e 1925enum {
1926 T_MD = 0,
1927 T_32 = 1, // 32X
1928};
1929
ffd4b35c 1930static const struct {
9d39a80e 1931 u8 type;
ffd4b35c 1932 int (*test)(void);
1933 const char *name;
1934} g_tests[] = {
9d39a80e 1935 { T_MD, t_dma_zero_wrap, "dma zero len + wrap" },
1936 { T_MD, t_dma_zero_fill, "dma zero len + fill" },
1937 { T_MD, t_dma_ram_wrap, "dma ram wrap" },
1938 { T_MD, t_dma_multi, "dma multi" },
1939 { T_MD, t_dma_cram_wrap, "dma cram wrap" },
1940 { T_MD, t_dma_vsram_wrap, "dma vsram wrap" },
1941 { T_MD, t_dma_and_data, "dma and data" },
1942 { T_MD, t_dma_short_cmd, "dma short cmd" },
1943 { T_MD, t_dma_fill3_odd, "dma fill3 odd" },
1944 { T_MD, t_dma_fill3_even, "dma fill3 even" },
9d39a80e 1945 { T_MD, t_dma_fill3_vsram, "dma fill3 vsram" },
9d39a80e 1946 { T_MD, t_dma_fill_dis, "dma fill disabled" },
1947 { T_MD, t_dma_fill_src, "dma fill src incr" },
1948 { T_MD, t_dma_128k, "dma 128k mode" },
1949 { T_MD, t_vdp_128k_b16, "vdp 128k addr bit16" },
a385208c 1950 // { t_vdp_128k_b16_inc, "vdp 128k bit16 inc" }, // mystery
9d39a80e 1951 { T_MD, t_vdp_reg_cmd, "vdp reg w cmd reset" },
1952 { T_MD, t_vdp_sr_vb, "vdp status reg vb" },
1953 { T_MD, t_z80mem_long_mirror, "z80 ram long mirror" },
1954 { T_MD, t_z80mem_noreq_w, "z80 ram noreq write" },
1955 { T_MD, t_z80mem_vdp_r, "z80 vdp read" },
ffd4b35c 1956 // { t_z80mem_vdp_w, "z80 vdp write" }, // hang
9d39a80e 1957 { T_MD, t_tim_loop, "time loop" },
e71680d5 1958 { T_MD, t_tim_z80_loop, "time z80 loop" },
9d39a80e 1959 { T_MD, t_tim_z80_ram, "time z80 ram" },
1960 { T_MD, t_tim_z80_ym, "time z80 ym2612" },
1961 { T_MD, t_tim_z80_vdp, "time z80 vdp" },
1962 { T_MD, t_tim_z80_bank_rom, "time z80 bank rom" },
1963 { T_MD, t_tim_vcnt, "time V counter" },
e71680d5 1964 { T_MD, t_tim_vcnt_loops, "time vcnt loops" },
9d39a80e 1965 { T_MD, t_tim_hblank_h40, "time hblank h40" },
1966 { T_MD, t_tim_hblank_h32, "time hblank h32" },
1967 { T_MD, t_tim_vdp_as_vram_w, "time vdp vram w" },
1968 { T_MD, t_tim_vdp_as_cram_w, "time vdp cram w" },
e71680d5 1969 { T_MD, t_tim_ym_timera_z80, "time timer a z80" },
1970 { T_MD, t_tim_ym_timerb_z80, "time timer b z80" },
1971 { T_MD, t_tim_ym_timerb_stop, "timer b stop" },
1972 { T_MD, t_tim_ym_timer_ab_sync,"timer ab sync" },
9d39a80e 1973 { T_MD, t_irq_hint, "irq4 / line" },
8517a6df 1974 { T_MD, t_irq_both_cpu_unmask, "irq both umask" },
9d39a80e 1975 { T_MD, t_irq_ack_v_h, "irq ack v-h" },
1976 { T_MD, t_irq_ack_v_h_2, "irq ack v-h 2" },
1977 { T_MD, t_irq_ack_h_v, "irq ack h-v" },
1978 { T_MD, t_irq_ack_h_v_2, "irq ack h-v 2" },
1979 { T_MD, t_irq_f_flag_h40, "irq f flag h40" },
9d39a80e 1980 { T_MD, t_irq_f_flag_h32, "irq f flag h32" },
1981
06d7984c 1982 // the first one enables 32X, so must be kept
1983 // all tests assume RV=1 FM=0
9d39a80e 1984 { T_32, t_32x_init, "32x init" },
1985 { T_32, t_32x_echo, "32x echo" },
06d7984c 1986 { T_32, t_32x_md_bios, "32x md bios" },
1987 { T_32, t_32x_md_rom, "32x md rom" },
1988 { T_32, t_32x_md_fb, "32x md fb" },
1989 { T_32, t_32x_sh_fb, "32x sh fb" },
234c4556 1990 { T_32, t_32x_disable, "32x disable" }, // must be last 32x
ffd4b35c 1991};
1992
1993static void setup_z80(void)
1994{
1995 u8 *zram = (u8 *)0xa00000;
1996 int i, len;
1997
1998 /* z80 */
1999 write16(0xa11100, 0x100);
2000 write16(0xa11200, 0x100);
2001
2002 while (read16(0xa11100) & 0x100)
2003 ;
2004
2005 // load the default test program, clear it's data
2006 len = z80_test_end - z80_test;
2007 for (i = 0; i < len; i++)
2008 write8(&zram[i], z80_test[i]);
2009 for (i = 0x1000; i < 0x1007; i++)
2010 write8(&zram[i], 0);
a385208c 2011
2012 // reset
2013 write16(0xa11200, 0x000);
2014 write16(0xa11100, 0x000);
2015 burn10(1);
2016 write16(0xa11200, 0x100);
e71680d5 2017
2018 burn10(50 * 15 / 7 / 10); // see z80_test.s80
a385208c 2019
2020 // take back the bus
2021 write16(0xa11100, 0x100);
2022 while (read16(0xa11100) & 0x100)
2023 ;
2024}
2025
2026static void wait_next_vsync(void)
2027{
e71680d5 2028 while (read16(VDP_CTRL_PORT) & SR_VB)
a385208c 2029 /* blanking */;
e71680d5 2030 while (!(read16(VDP_CTRL_PORT) & SR_VB))
a385208c 2031 /* not blanking */;
2032}
2033
cc7e5122 2034static unused int hexinc(char *c)
a385208c 2035{
2036 (*c)++;
2037 if (*c > 'f') {
2038 *c = '0';
2039 return 1;
2040 }
2041 if (*c == '9' + 1)
2042 *c = 'a';
2043 return 0;
ffd4b35c 2044}
2045
2046int main()
2047{
2048 int passed = 0;
9d39a80e 2049 int skipped = 0;
2050 int have_32x;
234c4556 2051 int en_32x;
ffd4b35c 2052 int ret;
a385208c 2053 u8 v8;
ffd4b35c 2054 int i;
2055
2056 setup_z80();
2057
a385208c 2058 /* io */
2059 write8(0xa10009, 0x40);
2060
ffd4b35c 2061 /* setup VDP */
2062 while (read16(VDP_CTRL_PORT) & 2)
2063 ;
2064
2065 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
2066 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA);
2067 VDP_setReg(VDP_MODE3, 0x00);
2068 VDP_setReg(VDP_MODE4, 0x81);
2069 VDP_setReg(VDP_NT_SCROLLA, APLANE >> 10);
2070 VDP_setReg(VDP_NT_SCROLLB, BPLANE >> 13);
2071 VDP_setReg(VDP_SAT_BASE, SLIST >> 9);
2072 VDP_setReg(VDP_HSCROLL, HSCRL >> 10);
2073 VDP_setReg(VDP_AUTOINC, 2);
2074 VDP_setReg(VDP_SCROLLSZ, 0x01);
2075 VDP_setReg(VDP_BACKDROP, 0);
2076
2077 // early tests
2078 t_dma_zero_wrap_early();
2079 t_dma_zero_fill_early();
2080
2081 /* pattern 0 */
2082 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
2083 for (i = 0; i < 32 / 4; i++)
2084 write32(VDP_DATA_PORT, 0);
2085
2086 /* clear name tables */
2087 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(APLANE));
2088 for (i = 0; i < PLANE_W * PLANE_H / 2; i++)
2089 write32(VDP_DATA_PORT, 0);
2090
2091 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(BPLANE));
2092 for (i = 0; i < PLANE_W * PLANE_H / 2; i++)
2093 write32(VDP_DATA_PORT, 0);
2094
2095 /* SAT, h. scroll */
2096 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(SLIST));
2097 write32(VDP_DATA_PORT, 0);
2098
2099 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(HSCRL));
2100 write32(VDP_DATA_PORT, 0);
2101
2102 /* scroll plane vscroll */
2103 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
2104 write32(VDP_DATA_PORT, 0);
2105 printf_ypos = 1;
2106
2107 /* load font */
2108 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(TILE_FONT_BASE));
2109 for (i = 0; i < FONT_LEN * 32 / 4; i++)
2110 write32(VDP_DATA_PORT, font_base[i]);
2111
2112 /* set colors */
2113 setup_default_palette();
2114
2115 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
2116
9d39a80e 2117 have_32x = read32(0xa130ec) == MKLONG('M','A','R','S');
234c4556 2118 en_32x = have_32x && (read32(0xa15100) & 1);
a385208c 2119 v8 = read8(0xa10001);
234c4556 2120 printf("MD version: %02x %s %s %s%s\n", v8,
a385208c 2121 (v8 & 0x80) ? "world" : "jap",
9d39a80e 2122 (v8 & 0x40) ? "pal" : "ntsc",
234c4556 2123 have_32x ? "32X" : "",
2124 en_32x ? "+" : "");
ffd4b35c 2125
2126 for (i = 0; i < ARRAY_SIZE(g_tests); i++) {
2127 // print test number if we haven't scrolled away
2128 if (printf_ypos < CSCREEN_H) {
2129 int old_ypos = printf_ypos;
2130 printf_ypos = 0;
ffd4b35c 2131 printf("%02d/%02d", i, ARRAY_SIZE(g_tests));
2132 printf_ypos = old_ypos;
2133 printf_xpos = 0;
2134 }
9d39a80e 2135 if ((g_tests[i].type & T_32) && !have_32x) {
2136 skipped++;
2137 continue;
2138 }
ffd4b35c 2139 ret = g_tests[i].test();
a385208c 2140 if (ret != 1) {
2141 text_pal = 2;
ffd4b35c 2142 printf("failed %d: %s\n", i, g_tests[i].name);
a385208c 2143 text_pal = 0;
2144 }
ffd4b35c 2145 else
2146 passed++;
2147 }
2148
2149 text_pal = 0;
9d39a80e 2150 printf("%d/%d passed, %d skipped.\n",
2151 passed, ARRAY_SIZE(g_tests), skipped);
ffd4b35c 2152
2153 printf_ypos = 0;
2154 printf(" ");
2155
e71680d5 2156 for (i = 0; i < 60*60 && !(get_input() & BTNM_A); i++)
a385208c 2157 wait_next_vsync();
e71680d5 2158#ifndef PICO
2159 // blank due to my lame tv being burn-in prone
2160 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
2161#endif
2162 while (!(get_input() & BTNM_A))
2163 burn10(488*100/10);
2164 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
a385208c 2165
2166
2167 {
2168 char c[3] = { '0', '0', '0' };
2169 short hscroll = 0, vscroll = 0;
2170 short hsz = 1, vsz = 0;
2171 short cellmode = 0;
2172
2173 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(APLANE));
2174
cc7e5122 2175#if 0
2176 for (i = 0, c[0] = 'a'; i < 8 * 1024 / 2; i++) {
2177 write16(VDP_DATA_PORT, (u16)c[0] - 32 + TILE_FONT_BASE / 32);
2178 c[0]++;
2179 if (c[0] == 'z' + 1)
2180 c[0] = 'a';
2181 }
2182#else
a385208c 2183 for (i = 0; i < 8 * 1024 / 2 / 4; i++) {
2184 write16(VDP_DATA_PORT, (u16)'.' - 32 + TILE_FONT_BASE / 32);
2185 write16(VDP_DATA_PORT, (u16)c[2] - 32 + TILE_FONT_BASE / 32);
2186 write16(VDP_DATA_PORT, (u16)c[1] - 32 + TILE_FONT_BASE / 32);
2187 write16(VDP_DATA_PORT, (u16)c[0] - 32 + TILE_FONT_BASE / 32);
2188 if (hexinc(&c[0]))
2189 if (hexinc(&c[1]))
2190 hexinc(&c[2]);
2191 }
cc7e5122 2192#endif
a385208c 2193 while (get_input() & BTNM_A)
2194 wait_next_vsync();
2195
2196 wait_next_vsync();
2197 for (;;) {
2198 int b = get_input();
2199
2200 if (b & BTNM_C) {
2201 hscroll = 1, vscroll = -1;
2202 do {
2203 wait_next_vsync();
2204 } while (get_input() & BTNM_C);
2205 cellmode ^= 1;
2206 }
2207 if (b & (BTNM_L | BTNM_R | BTNM_C)) {
2208 hscroll += (b & BTNM_L) ? 1 : -1;
2209 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(HSCRL));
2210 write16(VDP_DATA_PORT, hscroll);
2211 }
2212 if (b & (BTNM_U | BTNM_D | BTNM_C)) {
2213 vscroll += (b & BTNM_U) ? -1 : 1;
2214 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
2215 if (cellmode) {
2216 int end = (int)vscroll + 21;
2217 for (i = vscroll; i < end; i++)
2218 write32(VDP_DATA_PORT, i << 17);
2219 VDP_setReg(VDP_MODE3, 0x04);
2220 }
2221 else {
2222 write16(VDP_DATA_PORT, vscroll);
2223 VDP_setReg(VDP_MODE3, 0x00);
2224 }
2225 }
2226 if (b & BTNM_A) {
2227 hsz = (hsz + 1) & 3;
2228 do {
2229 wait_next_vsync();
2230 } while (get_input() & BTNM_A);
2231 }
2232 if (b & BTNM_B) {
2233 vsz = (vsz + 1) & 3;
2234 do {
2235 wait_next_vsync();
2236 } while (get_input() & BTNM_B);
2237 }
2238 VDP_setReg(VDP_SCROLLSZ, (vsz << 4) | hsz);
2239
2240 printf_xpos = 1;
2241 printf_ypos = 0;
2242 text_pal = 1;
2243 printf(" %d %d ", hsz, vsz);
2244
2245 wait_next_vsync();
2246 }
2247 }
2248
ffd4b35c 2249 for (;;)
2250 ;
2251
2252 return 0;
2253}
2254
2255// vim:ts=4:sw=4:expandtab
Genesis/MegaDrive related projects