2 * This software is released into the public domain.
3 * See UNLICENSE file in top level directory.
8 #define u8 unsigned char
9 #define u16 unsigned short
10 #define u32 unsigned int
12 #define noinline __attribute__((noinline))
13 #define unused __attribute__((unused))
14 #define _packed __attribute__((packed))
16 #define mem_barrier() \
17 asm volatile("":::"memory")
19 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
23 #define VDP_DATA_PORT 0xC00000
24 #define VDP_CTRL_PORT 0xC00004
26 #define TILE_MEM_END 0xB000
29 #define TILE_FONT_BASE (TILE_MEM_END / 32 - FONT_LEN)
31 /* note: using ED menu's layout here.. */
32 #define WPLANE (TILE_MEM_END + 0x0000)
33 #define HSCRL (TILE_MEM_END + 0x0800)
34 #define SLIST (TILE_MEM_END + 0x0C00)
35 #define APLANE (TILE_MEM_END + 0x1000)
36 #define BPLANE (TILE_MEM_END + 0x3000)
39 *((volatile u8 *) (a))
41 *((volatile u16 *) (a))
43 *((volatile u32 *) (a))
44 #define write8(a, d) \
45 *((volatile u8 *) (a)) = (d)
46 #define write16(a, d) \
47 *((volatile u16 *) (a)) = (d)
48 #define write32(a, d) \
49 *((volatile u32 *) (a)) = (d)
51 #define write16_z80le(a, d) \
52 ((volatile u8 *)(a))[0] = (u8)(d), \
53 ((volatile u8 *)(a))[1] = ((d) >> 8)
55 static inline u16 read16_z80le(const void *a_)
57 volatile const u8 *a = (volatile const u8 *)a_;
58 return a[0] | ((u16)a[1] << 8);
61 #define CTL_WRITE_VRAM(adr) \
62 (((0x4000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
63 #define CTL_WRITE_VSRAM(adr) \
64 (((0x4000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x10)
65 #define CTL_WRITE_CRAM(adr) \
66 (((0xC000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
67 #define CTL_READ_VRAM(adr) \
68 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
69 #define CTL_READ_VSRAM(adr) \
70 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x10)
71 #define CTL_READ_CRAM(adr) \
72 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x20)
74 #define CTL_WRITE_DMA 0x80
76 #define VDP_setReg(r, v) \
77 write16(VDP_CTRL_PORT, 0x8000 | ((r) << 8) | ((v) & 0xff))
82 VDP_NT_SCROLLA = 0x02,
84 VDP_NT_SCROLLB = 0x04,
99 #define VDP_MODE1_PS 0x04
100 #define VDP_MODE1_IE1 0x10 // h int
101 #define VDP_MODE2_MD 0x04
102 #define VDP_MODE2_PAL 0x08 // 30 col
103 #define VDP_MODE2_DMA 0x10
104 #define VDP_MODE2_IE0 0x20 // v int
105 #define VDP_MODE2_DISP 0x40
108 #define LEFT_BORDER 1 /* lame TV */
114 extern const u32 font_base[];
115 extern const u8 z80_test[];
116 extern const u8 z80_test_end[];
120 static noinline void VDP_drawTextML(const char *str, u16 plane_base,
123 const u8 *src = (const u8 *)str;
124 u16 basetile = text_pal << 13;
125 int max_len = 40 - LEFT_BORDER;
131 for (len = 0; str[len] && len < max_len; len++)
133 if (len > (PLANE_W - x))
136 addr = plane_base + ((x + (PLANE_W * y)) << 1);
137 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr));
140 write16(VDP_DATA_PORT,
141 basetile | ((*src++) - 32 + TILE_FONT_BASE / 32));
145 static int printf_ypos;
147 static void printf_line(int x, const char *buf)
152 VDP_drawTextML(buf, APLANE, x, printf_ypos++ & (PLANE_H - 1));
154 if (printf_ypos >= CSCREEN_H) {
155 /* clear next line */
157 addr += (PLANE_W * (printf_ypos & (PLANE_H - 1))) << 1;
158 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr));
159 for (i = 0; i < 40 / 2; i++)
160 write32(VDP_DATA_PORT, 0);
163 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
164 write16(VDP_DATA_PORT, (printf_ypos - CSCREEN_H + 1) * 8);
168 #define PRINTF_LEN 40
170 static int printf_xpos;
172 static noinline int printf(const char *fmt, ...)
174 static const char hexchars[] = "0123456789abcdef";
175 char c, buf[PRINTF_LEN + 11 + 1];
184 for (d = 0; *fmt; ) {
195 printf_line(printf_xpos, buf);
211 while ('1' <= *fmt && *fmt <= '9') {
212 fwidth = fwidth * 10 + *fmt - '0';
222 ival = va_arg(ap, int);
227 for (i = 1000000000; i >= 10; i /= 10)
230 for (; i >= 10; i /= 10) {
231 buf[d++] = '0' + ival / i;
234 buf[d++] = '0' + ival;
237 uval = va_arg(ap, int);
238 while (fwidth > 1 && uval < (1 << (fwidth - 1) * 4)) {
239 buf[d++] = prefix0 ? '0' : ' ';
242 for (j = 1; j < 8 && uval >= (1 << j * 4); j++)
244 for (j--; j >= 0; j--)
245 buf[d++] = hexchars[(uval >> j * 4) & 0x0f];
248 s = va_arg(ap, char *);
249 while (*s && d < PRINTF_LEN)
253 // don't handle, for now
264 VDP_drawTextML(buf, APLANE, printf_xpos,
265 printf_ypos & (PLANE_H - 1));
272 static const char *exc_names[] = {
277 "Illegal Instruction",
281 "Privilege Violation", /* 8 8 */
283 "Line 1010 Emulator",
284 "Line 1111 Emulator",
288 "Uninitialized Interrupt",
297 "Spurious Interrupt", /* 18 24 */
310 u16 ecxnum; // from handler
322 } bae _packed; // bus/address error frame
326 int xtttt(void) { return sizeof(struct exc_frame); }
328 void exception(const struct exc_frame *f)
332 while (read16(VDP_CTRL_PORT) & 2)
334 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
335 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DISP);
337 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
338 write16(VDP_DATA_PORT,
339 printf_ypos >= CSCREEN_H ?
340 (printf_ypos - CSCREEN_H + 1) * 8 : 0);
342 printf("exception %i ", f->ecxnum);
343 if (f->ecxnum < ARRAY_SIZE(exc_names) && exc_names[f->ecxnum] != NULL)
344 printf("(%s)", exc_names[f->ecxnum]);
346 printf(" (%s)", (f->bae.fc & 0x10) ? "r" : "w");
350 printf(" PC: %08x SR: %04x \n", f->bae.pc, f->bae.sr);
351 printf("addr: %08x IR: %04x FC: %02x \n",
352 f->bae.addr, f->bae.ir, f->bae.fc);
355 printf(" PC: %08x SR: %04x \n", f->g.pc, f->g.sr);
357 for (i = 0; i < 8; i++)
358 printf(" D%d: %08x A%d: %08x \n", i, f->dr[i], i, f->ar[i]);
364 static void setup_default_palette(void)
366 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
367 write32(VDP_DATA_PORT, 0);
368 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(15 * 2)); // font normal
369 write16(VDP_DATA_PORT, 0xeee);
370 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(31 * 2)); // green
371 write16(VDP_DATA_PORT, 0x0e0);
372 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(47 * 2)); // red
373 write16(VDP_DATA_PORT, 0x00e);
376 static void do_setup_dma(const void *src_, u16 words)
379 // VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA);
380 VDP_setReg(VDP_DMA_LEN0, words);
381 VDP_setReg(VDP_DMA_LEN1, words >> 8);
382 VDP_setReg(VDP_DMA_SRC0, src >> 1);
383 VDP_setReg(VDP_DMA_SRC1, src >> 9);
384 VDP_setReg(VDP_DMA_SRC2, src >> 17);
385 // write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr) | CTL_WRITE_DMA);
388 static void t_dma_zero_wrap_early(void)
390 const u32 *src = (const u32 *)0x3c0000;
391 u32 *ram = (u32 *)0xff0000;
393 do_setup_dma(src + 4, 2);
394 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) | CTL_WRITE_DMA);
395 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) | CTL_WRITE_DMA);
397 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
398 ram[0] = read32(VDP_DATA_PORT);
399 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfffc));
400 ram[1] = read32(VDP_DATA_PORT);
403 static void t_dma_zero_fill_early(void)
405 u32 *ram = (u32 *)0xff0000;
407 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
408 write32(VDP_DATA_PORT, 0);
409 write32(VDP_DATA_PORT, 0);
410 write32(VDP_DATA_PORT, 0);
411 write32(VDP_DATA_PORT, 0);
413 VDP_setReg(VDP_AUTOINC, 1);
414 VDP_setReg(VDP_DMA_SRC2, 0x80);
415 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(1) | CTL_WRITE_DMA);
416 write16(VDP_DATA_PORT, 0x1122);
417 ram[2] = read16(VDP_CTRL_PORT);
418 while (read16(VDP_CTRL_PORT) & 2)
421 VDP_setReg(VDP_AUTOINC, 2);
422 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
423 ram[3] = read32(VDP_DATA_PORT);
426 #define expect(ok_, v0_, v1_) \
427 if ((v0_) != (v1_)) { \
428 printf("%s: %08x %08x\n", #v0_, v0_, v1_); \
432 static int t_dma_zero_wrap(void)
434 const u32 *src = (const u32 *)0x3c0000;
435 const u32 *ram = (const u32 *)0xff0000;
438 expect(ok, ram[0], src[5 + 0x10000/4]);
439 expect(ok, ram[1], src[4]);
443 static int t_dma_zero_fill(void)
445 const u32 *ram = (const u32 *)0xff0000;
450 expect(ok, ram[3], 0x11111111);
454 static int t_dma_ram_wrap(void)
456 u32 *ram = (u32 *)0xff0000;
460 saved = read32(&ram[0x10000/4 - 1]);
461 ram[0x10000/4 - 1] = 0x01020304;
463 do_setup_dma(&ram[0x10000/4 - 1], 4);
465 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
468 write32(&ram[0x10000/4 - 1], saved);
470 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
471 v0 = read32(VDP_DATA_PORT);
472 v1 = read32(VDP_DATA_PORT);
474 expect(ok, v0, 0x01020304);
475 expect(ok, v1, 0x05060708);
479 // test no src reprogram, only len0
480 static int t_dma_multi(void)
482 const u32 *src = (const u32 *)0x3c0000;
486 do_setup_dma(src, 2);
487 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
488 VDP_setReg(VDP_DMA_LEN0, 2);
489 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x104) | CTL_WRITE_DMA);
491 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
492 v0 = read32(VDP_DATA_PORT);
493 v1 = read32(VDP_DATA_PORT);
495 expect(ok, v0, src[0]);
496 expect(ok, v1, src[1]);
500 static int t_dma_cram_wrap(void)
502 u32 *ram = (u32 *)0xff0000;
506 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
507 write32(VDP_DATA_PORT, 0);
512 do_setup_dma(ram, 4);
513 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0x7c | 0xff81) | CTL_WRITE_DMA);
515 write32(VDP_CTRL_PORT, CTL_READ_CRAM(0x7c));
516 v0 = read32(VDP_DATA_PORT) & 0x0eee0eee;
517 write32(VDP_CTRL_PORT, CTL_READ_CRAM(0));
518 v1 = read32(VDP_DATA_PORT) & 0x0eee0eee;
520 setup_default_palette();
522 expect(ok, v0, ram[0]);
523 expect(ok, v1, ram[1]);
527 static int t_dma_vsram_wrap(void)
529 u32 *ram32 = (u32 *)0xff0000;
530 u16 *ram16 = (u16 *)0xff0000;
535 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
536 write32(VDP_DATA_PORT, 0);
538 for (i = 0; i < 0x48/2; i++)
541 do_setup_dma(ram16, 0x48/2);
542 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0x3c | 0xff81) | CTL_WRITE_DMA);
544 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0x3c));
545 v0 = read32(VDP_DATA_PORT) & 0x03ff03ff;
546 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0));
547 v1 = read32(VDP_DATA_PORT) & 0x03ff03ff;
549 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
550 write32(VDP_DATA_PORT, 0);
552 expect(ok, v0, ram32[0]);
553 expect(ok, v1, ram32[0x48/4 - 1]);
557 static int t_dma_and_data(void)
559 const u32 *src = (const u32 *)0x3c0000;
563 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
564 write32(VDP_DATA_PORT, 0);
566 do_setup_dma(src, 2);
567 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfc) | CTL_WRITE_DMA);
568 write32(VDP_DATA_PORT, 0x5ec8a248);
570 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
571 v0 = read32(VDP_DATA_PORT);
573 expect(ok, v0, 0x5ec8a248);
577 static int t_dma_fill3_odd(void)
582 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
583 write32(VDP_DATA_PORT, 0);
584 write32(VDP_DATA_PORT, 0);
585 write32(VDP_DATA_PORT, 0);
587 VDP_setReg(VDP_AUTOINC, 3);
588 VDP_setReg(VDP_DMA_LEN0, 3);
589 VDP_setReg(VDP_DMA_SRC2, 0x80);
590 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x101) | CTL_WRITE_DMA);
591 write16(VDP_DATA_PORT, 0x1122);
592 while (read16(VDP_CTRL_PORT) & 2)
595 VDP_setReg(VDP_AUTOINC, 2);
596 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
597 v0 = read32(VDP_DATA_PORT);
598 v1 = read32(VDP_DATA_PORT);
599 v2 = read32(VDP_DATA_PORT);
601 expect(ok, v0, 0x22110000);
602 expect(ok, v1, 0x00111100);
603 expect(ok, v2, 0x00000011);
607 static int t_dma_fill3_even(void)
612 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
613 write32(VDP_DATA_PORT, 0);
614 write32(VDP_DATA_PORT, 0);
615 write32(VDP_DATA_PORT, 0);
617 VDP_setReg(VDP_AUTOINC, 3);
618 VDP_setReg(VDP_DMA_LEN0, 3);
619 VDP_setReg(VDP_DMA_SRC2, 0x80);
620 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
621 write16(VDP_DATA_PORT, 0x1122);
622 while (read16(VDP_CTRL_PORT) & 2)
625 VDP_setReg(VDP_AUTOINC, 2);
626 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
627 v0 = read32(VDP_DATA_PORT);
628 v1 = read32(VDP_DATA_PORT);
629 v2 = read32(VDP_DATA_PORT);
631 expect(ok, v0, 0x11221100);
632 expect(ok, v1, 0x00000011);
633 expect(ok, v2, 0x11000000);
637 static unused int t_dma_fill3_vsram(void)
642 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
643 write32(VDP_DATA_PORT, 0);
644 write32(VDP_DATA_PORT, 0);
645 write32(VDP_DATA_PORT, 0);
647 write16(VDP_DATA_PORT, 0x0111);
648 write16(VDP_DATA_PORT, 0x0222);
649 write16(VDP_DATA_PORT, 0x0333);
651 VDP_setReg(VDP_AUTOINC, 3);
652 VDP_setReg(VDP_DMA_LEN0, 3);
653 VDP_setReg(VDP_DMA_SRC2, 0x80);
654 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(1) | CTL_WRITE_DMA);
655 write16(VDP_DATA_PORT, 0x0102);
656 while (read16(VDP_CTRL_PORT) & 2)
659 VDP_setReg(VDP_AUTOINC, 2);
660 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0));
661 v0 = read32(VDP_DATA_PORT);
662 v1 = read32(VDP_DATA_PORT);
663 v2 = read32(VDP_DATA_PORT);
665 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
666 write32(VDP_DATA_PORT, 0);
668 expect(ok, v0, 0x01020000);
669 expect(ok, v1, 0x01110111);
670 expect(ok, v2, 0x00000111);
674 static int t_dma_fill_dis(void)
679 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
680 write32(VDP_DATA_PORT, 0);
681 write32(VDP_DATA_PORT, 0);
683 VDP_setReg(VDP_DMA_LEN0, 1);
684 VDP_setReg(VDP_DMA_SRC2, 0x80);
685 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
686 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
687 write16(VDP_DATA_PORT, 0x1122);
688 while (read16(VDP_CTRL_PORT) & 2)
691 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
692 write16(VDP_DATA_PORT, 0x3344);
693 while (read16(VDP_CTRL_PORT) & 2)
696 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
697 v0 = read32(VDP_DATA_PORT);
698 v1 = read32(VDP_DATA_PORT);
705 static int t_dma_fill_src(void)
707 const u32 *src = (const u32 *)0x3c0000;
711 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
712 write32(VDP_DATA_PORT, 0);
714 // do_setup_dma(src, 2); // hang, can't write src2 twice
715 VDP_setReg(VDP_DMA_LEN0, 2);
716 VDP_setReg(VDP_DMA_SRC0, (u32)src >> 1);
717 VDP_setReg(VDP_DMA_SRC1, (u32)src >> 9);
718 VDP_setReg(VDP_DMA_SRC2, 0x80);
719 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
720 write16(VDP_DATA_PORT, 0x1122);
721 while (read16(VDP_CTRL_PORT) & 2)
724 VDP_setReg(VDP_DMA_LEN0, 2);
725 VDP_setReg(VDP_DMA_SRC2, (u32)src >> 17);
726 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x104) | CTL_WRITE_DMA);
728 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
729 v0 = read32(VDP_DATA_PORT);
730 v1 = read32(VDP_DATA_PORT);
732 expect(ok, v0, 0x11220011);
733 expect(ok, v1, src[1]);
737 /* z80 tests assume busreq state */
738 static int t_z80mem_long_mirror(void)
740 u8 *zram = (u8 *)0xa00000;
743 write8(&zram[0x1100], 0x11);
744 write8(&zram[0x1101], 0x22);
745 write8(&zram[0x1102], 0x33);
746 write8(&zram[0x1103], 0x44);
748 write32(&zram[0x3100], 0x55667788);
751 expect(ok, zram[0x1100], 0x55);
752 expect(ok, zram[0x1101], 0x22);
753 expect(ok, zram[0x1102], 0x77);
754 expect(ok, zram[0x1103], 0x44);
758 static int t_z80mem_vdp_r(void)
760 u8 *zram = (u8 *)0xa00000;
763 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
764 write32(VDP_DATA_PORT, 0x11223344);
765 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
767 zram[0x1000] = 1; // cp
768 zram[0x1001] = 2; // len
769 write16_z80le(&zram[0x1002], 0x7f00); // src
770 write16_z80le(&zram[0x1004], 0x1006); // dst
771 zram[0x1006] = zram[0x1007] = zram[0x1008] = 0x5a;
773 write16(0xa11100, 0x000);
774 burn10((98 + 40*2 + 27) * 15 / 7 * 2 / 10);
776 write16(0xa11100, 0x100);
777 while (read16(0xa11100) & 0x100)
780 expect(ok, zram[0x1000], 0);
781 expect(ok, zram[0x1006], 0x11);
782 expect(ok, zram[0x1007], 0x44);
783 expect(ok, zram[0x1008], 0x5a);
787 static unused int t_z80mem_vdp_w(void)
789 u8 *zram = (u8 *)0xa00000;
793 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
794 write32(VDP_DATA_PORT, 0x11223344);
795 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
797 zram[0x1000] = 1; // cp
798 zram[0x1001] = 2; // len
799 write16_z80le(&zram[0x1002], 0x1006); // src
800 write16_z80le(&zram[0x1004], 0x7f00); // dst
804 write16(0xa11100, 0x000);
805 burn10((98 + 40*2 + 27) * 15 / 7 * 2 / 10);
807 write16(0xa11100, 0x100);
808 while (read16(0xa11100) & 0x100)
811 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
812 v0 = read32(VDP_DATA_PORT);
814 expect(ok, zram[0x1000], 0);
815 expect(ok, v0, 0x55556666);
819 static const struct {
823 { t_dma_zero_wrap, "dma zero len + wrap" },
824 { t_dma_zero_fill, "dma zero len + fill" },
825 { t_dma_ram_wrap, "dma ram wrap" },
826 { t_dma_multi, "dma multi" },
827 { t_dma_cram_wrap, "dma cram wrap" },
828 { t_dma_vsram_wrap, "dma vsram wrap" },
829 { t_dma_and_data, "dma and data" },
830 { t_dma_fill3_odd, "dma fill3 odd" },
831 { t_dma_fill3_even, "dma fill3 even" },
832 // { t_dma_fill3_vsram, "dma fill3 vsram" }, // later
833 { t_dma_fill_dis, "dma fill disabled" },
834 { t_dma_fill_src, "dma fill src incr" },
835 { t_z80mem_long_mirror, "z80 ram long mirror" },
836 { t_z80mem_vdp_r, "z80 vdp read" },
837 // { t_z80mem_vdp_w, "z80 vdp write" }, // hang
840 static void setup_z80(void)
842 u8 *zram = (u8 *)0xa00000;
846 write16(0xa11100, 0x100);
847 write16(0xa11200, 0x100);
849 while (read16(0xa11100) & 0x100)
852 // load the default test program, clear it's data
853 len = z80_test_end - z80_test;
854 for (i = 0; i < len; i++)
855 write8(&zram[i], z80_test[i]);
856 for (i = 0x1000; i < 0x1007; i++)
869 while (read16(VDP_CTRL_PORT) & 2)
872 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
873 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA);
874 VDP_setReg(VDP_MODE3, 0x00);
875 VDP_setReg(VDP_MODE4, 0x81);
876 VDP_setReg(VDP_NT_SCROLLA, APLANE >> 10);
877 VDP_setReg(VDP_NT_SCROLLB, BPLANE >> 13);
878 VDP_setReg(VDP_SAT_BASE, SLIST >> 9);
879 VDP_setReg(VDP_HSCROLL, HSCRL >> 10);
880 VDP_setReg(VDP_AUTOINC, 2);
881 VDP_setReg(VDP_SCROLLSZ, 0x01);
882 VDP_setReg(VDP_BACKDROP, 0);
885 t_dma_zero_wrap_early();
886 t_dma_zero_fill_early();
889 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
890 for (i = 0; i < 32 / 4; i++)
891 write32(VDP_DATA_PORT, 0);
893 /* clear name tables */
894 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(APLANE));
895 for (i = 0; i < PLANE_W * PLANE_H / 2; i++)
896 write32(VDP_DATA_PORT, 0);
898 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(BPLANE));
899 for (i = 0; i < PLANE_W * PLANE_H / 2; i++)
900 write32(VDP_DATA_PORT, 0);
903 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(SLIST));
904 write32(VDP_DATA_PORT, 0);
906 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(HSCRL));
907 write32(VDP_DATA_PORT, 0);
909 /* scroll plane vscroll */
910 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
911 write32(VDP_DATA_PORT, 0);
915 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(TILE_FONT_BASE));
916 for (i = 0; i < FONT_LEN * 32 / 4; i++)
917 write32(VDP_DATA_PORT, font_base[i]);
920 setup_default_palette();
922 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
925 printf("MD version: %02x\n", read8(0xa10001));
927 for (i = 0; i < ARRAY_SIZE(g_tests); i++) {
928 // print test number if we haven't scrolled away
929 if (printf_ypos < CSCREEN_H) {
930 int old_ypos = printf_ypos;
933 printf("%02d/%02d", i, ARRAY_SIZE(g_tests));
934 printf_ypos = old_ypos;
938 ret = g_tests[i].test();
940 printf("failed %d: %s\n", i, g_tests[i].name);
946 printf("%d/%d passed.\n", passed, ARRAY_SIZE(g_tests));
957 // vim:ts=4:sw=4:expandtab