spu: add asm mixing code for ARMv5 too
[pcsx_rearmed.git] / frontend / plat_pollux.c
CommitLineData
55b0eeea 1/*
2 * (C) GraÅžvydas "notaz" Ignotas, 2009-2011
3 *
4 * This work is licensed under the terms of the GNU GPLv2 or later.
5 * See the COPYING file in the top-level directory.
6 */
7
8#include <stdio.h>
9#include <stdlib.h>
10#include <string.h>
11#include <sys/types.h>
12#include <sys/stat.h>
13#include <fcntl.h>
14#include <sys/ioctl.h>
15#include <unistd.h>
16#include <linux/fb.h>
17#include <sys/mman.h>
18
19#include "common/input.h"
20#include "common/menu.h"
21#include "warm/warm.h"
22#include "plugin_lib.h"
23#include "cspace.h"
02ee7e24 24#include "blit320.h"
faf2b2aa 25#include "in_tsbutton.h"
55b0eeea 26#include "main.h"
27#include "menu.h"
28#include "plat.h"
d3f3bf09 29#include "pcnt.h"
55b0eeea 30
31static int fbdev = -1, memdev = -1, battdev = -1;
32static volatile unsigned short *memregs;
33static volatile unsigned int *memregl;
34static void *fb_vaddrs[2];
35static unsigned int fb_paddrs[2];
36static int fb_work_buf;
02ee7e24 37static int cpu_clock_allowed, have_warm;
0b6c6da8 38static unsigned int saved_video_regs[2][6];
39#define FB_VRAM_SIZE (320*240*2*2*2) // 2 buffers with space for 24bpp mode
55b0eeea 40
41static unsigned short *psx_vram;
42static unsigned int psx_vram_padds[512];
02ee7e24 43static int psx_step, psx_width, psx_height, psx_bpp;
44static int psx_offset_x, psx_offset_y;
41f55c9f 45static int fb_offset_x, fb_offset_y;
55b0eeea 46
47// TODO: get rid of this
48struct vout_fbdev;
49struct vout_fbdev *layer_fb;
50int g_layer_x, g_layer_y, g_layer_w, g_layer_h;
51
52int omap_enable_layer(int enabled)
53{
54 return 0;
55}
56
57static void *fb_flip(void)
58{
0b6c6da8 59 memregl[0x406C>>2] = memregl[0x446C>>2] = fb_paddrs[fb_work_buf];
55b0eeea 60 memregl[0x4058>>2] |= 0x10;
0b6c6da8 61 memregl[0x4458>>2] |= 0x10;
55b0eeea 62 fb_work_buf ^= 1;
63 return fb_vaddrs[fb_work_buf];
64}
65
66static void pollux_changemode(int bpp, int is_bgr)
67{
68 int code = 0, bytes = 2;
69 unsigned int r;
70
71 printf("changemode: %dbpp %s\n", bpp, is_bgr ? "bgr" : "rgb");
72
73 memregl[0x4004>>2] = 0x00ef013f;
74 memregl[0x4000>>2] |= 1 << 3;
75
76 switch (bpp)
77 {
78 case 8:
79 code = 0x443a;
80 bytes = 1;
81 break;
82 case 16:
83 code = is_bgr ? 0xc342 : 0x4432;
84 bytes = 2;
85 break;
86 case 24:
87 code = is_bgr ? 0xc653 : 0x4653;
88 bytes = 3;
89 break;
90 default:
91 printf("unhandled bpp request: %d\n", bpp);
92 return;
93 }
94
0b6c6da8 95 // program both MLCs so that TV-out works
96 memregl[0x405c>>2] = memregl[0x445c>>2] = bytes;
97 memregl[0x4060>>2] = memregl[0x4460>>2] = 320 * bytes;
55b0eeea 98
99 r = memregl[0x4058>>2];
100 r = (r & 0xffff) | (code << 16) | 0x10;
101 memregl[0x4058>>2] = r;
0b6c6da8 102
103 r = memregl[0x4458>>2];
104 r = (r & 0xffff) | (code << 16) | 0x10;
105 memregl[0x4458>>2] = r;
55b0eeea 106}
107
108/* note: both PLLs are programmed the same way,
109 * the databook incorrectly states that PLL1 differs */
110static int decode_pll(unsigned int reg)
111{
112 long long v;
113 int p, m, s;
114
115 p = (reg >> 18) & 0x3f;
116 m = (reg >> 8) & 0x3ff;
117 s = reg & 0xff;
118
119 if (p == 0)
120 p = 1;
121
122 v = 27000000; // master clock
123 v = v * m / (p << s);
124 return v;
125}
126
127int plat_cpu_clock_get(void)
128{
129 return decode_pll(memregl[0xf004>>2]) / 1000000;
130}
131
132int plat_cpu_clock_apply(int mhz)
133{
134 int adiv, mdiv, pdiv, sdiv = 0;
135 int i, vf000, vf004;
136
137 if (!cpu_clock_allowed)
138 return -1;
139 if (mhz == plat_cpu_clock_get())
140 return 0;
141
142 // m = MDIV, p = PDIV, s = SDIV
143 #define SYS_CLK_FREQ 27
144 pdiv = 9;
145 mdiv = (mhz * pdiv) / SYS_CLK_FREQ;
146 if (mdiv & ~0x3ff)
147 return -1;
148 vf004 = (pdiv<<18) | (mdiv<<8) | sdiv;
149
150 // attempt to keep the AHB divider close to 250, but not higher
151 for (adiv = 1; mhz / adiv > 250; adiv++)
152 ;
153
154 vf000 = memregl[0xf000>>2];
155 vf000 = (vf000 & ~0x3c0) | ((adiv - 1) << 6);
156 memregl[0xf000>>2] = vf000;
157 memregl[0xf004>>2] = vf004;
158 memregl[0xf07c>>2] |= 0x8000;
159 for (i = 0; (memregl[0xf07c>>2] & 0x8000) && i < 0x100000; i++)
160 ;
161
162 printf("clock set to %dMHz, AHB set to %dMHz\n", mhz, mhz / adiv);
163
164 // stupid pll share hack - must restart audio
165 extern long SPUopen(void);
166 extern long SPUclose(void);
167 SPUclose();
168 SPUopen();
169
170 return 0;
171}
172
173int plat_get_bat_capacity(void)
174{
175 unsigned short magic_val = 0;
176
177 if (battdev < 0)
178 return -1;
179 if (read(battdev, &magic_val, sizeof(magic_val)) != sizeof(magic_val))
180 return -1;
181 switch (magic_val) {
182 default:
183 case 1: return 100;
184 case 2: return 66;
185 case 3: return 40;
186 case 4: return 0;
187 }
188}
189
190#define TIMER_BASE3 0x1980
191#define TIMER_REG(x) memregl[(TIMER_BASE3 + x) >> 2]
192
193static __attribute__((unused)) unsigned int timer_get(void)
194{
195 TIMER_REG(0x08) |= 0x48; /* run timer, latch value */
196 return TIMER_REG(0);
197}
198
199static void timer_cleanup(void)
200{
201 TIMER_REG(0x40) = 0x0c; /* be sure clocks are on */
202 TIMER_REG(0x08) = 0x23; /* stop the timer, clear irq in case it's pending */
203 TIMER_REG(0x00) = 0; /* clear counter */
204 TIMER_REG(0x40) = 0; /* clocks off */
205 TIMER_REG(0x44) = 0; /* dividers back to default */
206}
207
208void plat_video_menu_enter(int is_rom_loaded)
209{
210 if (pl_vout_buf != NULL) {
211 if (psx_bpp == 16)
212 // have to do rgb conversion for menu bg
213 bgr555_to_rgb565(pl_vout_buf, pl_vout_buf, 320*240*2);
214 else
215 memset(pl_vout_buf, 0, 320*240*2);
216 }
217
218 pollux_changemode(16, 0);
219}
220
221void plat_video_menu_begin(void)
222{
223}
224
225void plat_video_menu_end(void)
226{
227 g_menuscreen_ptr = fb_flip();
228}
229
230void plat_video_menu_leave(void)
231{
55b0eeea 232 if (psx_vram == NULL) {
233 fprintf(stderr, "GPU plugin did not provide vram\n");
234 exit(1);
235 }
236
237 in_set_config_int(in_name_to_id("evdev:pollux-analog"),
238 IN_CFG_ABS_DEAD_ZONE, analog_deadzone);
41f55c9f 239
240 memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8);
241 g_menuscreen_ptr = fb_flip();
242 memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8);
243
244 pollux_changemode(psx_bpp, 1);
55b0eeea 245}
246
247static void pl_vout_set_raw_vram(void *vram)
248{
249 int i;
250
251 psx_vram = vram;
252
253 if (vram == NULL)
254 return;
255
256 if ((long)psx_vram & 0x7ff)
257 fprintf(stderr, "GPU plugin did not align vram\n");
258
259 for (i = 0; i < 512; i++) {
260 psx_vram[i * 1024] = 0; // touch
261 psx_vram_padds[i] = warm_virt2phys(&psx_vram[i * 1024]);
262 }
263}
264
55b0eeea 265static void spend_cycles(int loops)
266{
267 asm volatile (
268 " mov r0,%0 ;\n"
269 "0: subs r0,r0,#1 ;\n"
270 " bgt 0b"
271 :: "r" (loops) : "cc", "r0");
272}
273
274#define DMA_BASE6 0x0300
275#define DMA_REG(x) memregl[(DMA_BASE6 + x) >> 2]
276
277/* this takes ~1.5ms, while ldm/stm ~1.95ms */
278static void raw_flip_dma(int x, int y)
279{
41f55c9f 280 unsigned int dst = fb_paddrs[fb_work_buf] +
281 (fb_offset_y * 320 + fb_offset_x) * psx_bpp / 8;
02ee7e24 282 int spsx_line = y + psx_offset_y;
283 int spsx_offset = (x + psx_offset_x) & 0x3f8;
55b0eeea 284 int dst_stride = 320 * psx_bpp / 8;
285 int len = psx_width * psx_bpp / 8;
55b0eeea 286 int i;
287
288 warm_cache_op_all(WOP_D_CLEAN);
d3f3bf09 289 pcnt_start(PCNT_BLIT);
55b0eeea 290
291 dst &= ~7;
292 len &= ~7;
293
294 if (DMA_REG(0x0c) & 0x90000) {
295 printf("already runnig DMA?\n");
296 DMA_REG(0x0c) = 0x100000;
297 }
298 if ((DMA_REG(0x2c) & 0x0f) < 5) {
299 printf("DMA queue busy?\n");
300 DMA_REG(0x24) = 1;
301 }
302
303 for (i = psx_height; i > 0; i--, spsx_line += psx_step, dst += dst_stride) {
304 while ((DMA_REG(0x2c) & 0x0f) < 4)
305 spend_cycles(10);
306
307 // XXX: it seems we must always set all regs, what is autoincrement there for?
308 DMA_REG(0x20) = 1; // queue wait cmd
309 DMA_REG(0x10) = psx_vram_padds[spsx_line & 511] + spsx_offset * 2; // DMA src
310 DMA_REG(0x14) = dst; // DMA dst
311 DMA_REG(0x18) = len - 1; // len
312 DMA_REG(0x1c) = 0x80000; // go
313 }
314
55b0eeea 315 if (psx_bpp == 16) {
316 pl_vout_buf = g_menuscreen_ptr;
41f55c9f 317 pl_print_hud(320, fb_offset_y + psx_height, fb_offset_x);
55b0eeea 318 }
319
320 g_menuscreen_ptr = fb_flip();
321 pl_flip_cnt++;
d3f3bf09 322
323 pcnt_end(PCNT_BLIT);
55b0eeea 324}
325
02ee7e24 326#define make_flip_func(name, blitfunc) \
327static void name(int x, int y) \
328{ \
329 unsigned short *vram = psx_vram; \
330 unsigned char *dst = (unsigned char *)g_menuscreen_ptr + \
331 (fb_offset_y * 320 + fb_offset_x) * psx_bpp / 8; \
332 unsigned int src = (y + psx_offset_y) * 1024 + x + psx_offset_x; \
333 int dst_stride = 320 * psx_bpp / 8; \
334 int len = psx_width * psx_bpp / 8; \
335 int i; \
336 \
337 pcnt_start(PCNT_BLIT); \
338 \
339 for (i = psx_height; i > 0; i--, src += psx_step * 1024, dst += dst_stride) { \
340 src &= 1024*512-1; \
341 blitfunc(dst, vram + src, len); \
342 } \
343 \
344 if (psx_bpp == 16) { \
345 pl_vout_buf = g_menuscreen_ptr; \
346 pl_print_hud(320, fb_offset_y + psx_height, fb_offset_x); \
347 } \
348 \
349 g_menuscreen_ptr = fb_flip(); \
350 pl_flip_cnt++; \
351 \
352 pcnt_end(PCNT_BLIT); \
353}
354
355make_flip_func(raw_flip_soft, memcpy)
356make_flip_func(raw_flip_soft_368, blit320_368)
357make_flip_func(raw_flip_soft_512, blit320_512)
358make_flip_func(raw_flip_soft_640, blit320_640)
359
360static void *pl_vout_set_mode(int w, int h, int bpp)
55b0eeea 361{
02ee7e24 362 static int old_w, old_h, old_bpp;
363 int poff_w, poff_h, w_max;
55b0eeea 364
02ee7e24 365 if (!w || !h || !bpp || (w == old_w && h == old_h && bpp == old_bpp))
366 return NULL;
55b0eeea 367
02ee7e24 368 printf("psx mode: %dx%d@%d\n", w, h, bpp);
55b0eeea 369
02ee7e24 370 switch (w + (bpp != 16)) {
371 case 640:
372 pl_rearmed_cbs.pl_vout_raw_flip = raw_flip_soft_640;
373 w_max = 640;
374 break;
375 case 512:
376 pl_rearmed_cbs.pl_vout_raw_flip = raw_flip_soft_512;
377 w_max = 512;
378 break;
379 case 384:
380 case 368:
381 pl_rearmed_cbs.pl_vout_raw_flip = raw_flip_soft_368;
382 w_max = 368;
383 break;
384 default:
385 pl_rearmed_cbs.pl_vout_raw_flip = have_warm ? raw_flip_dma : raw_flip_soft;
386 w_max = 320;
387 break;
55b0eeea 388 }
389
02ee7e24 390 psx_step = 1;
391 if (h > 256) {
392 psx_step = 2;
393 h /= 2;
394 }
395
396 poff_w = poff_h = 0;
397 if (w > w_max) {
398 poff_w = w / 2 - w_max / 2;
399 w = w_max;
400 }
401 fb_offset_x = 0;
402 if (w < 320)
403 fb_offset_x = 320/2 - w / 2;
404 if (h > 240) {
405 poff_h = h / 2 - 240/2;
406 h = 240;
407 }
408 fb_offset_y = 240/2 - h / 2;
409
410 psx_offset_x = poff_w;
411 psx_offset_y = poff_h;
412 psx_width = w;
413 psx_height = h;
414 psx_bpp = bpp;
415
416 if (fb_offset_x || fb_offset_y) {
417 // not fullscreen, must clear borders
418 memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8);
419 g_menuscreen_ptr = fb_flip();
420 memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8);
421 }
422
423 pollux_changemode(bpp, 1);
424
425 return NULL;
55b0eeea 426}
427
41f55c9f 428static void *pl_vout_flip(void)
429{
430 return NULL;
431}
432
0b6c6da8 433static void save_multiple_regs(unsigned int *dest, int base, int count)
434{
435 const volatile unsigned int *regs = memregl + base / 4;
436 int i;
437
438 for (i = 0; i < count; i++)
439 dest[i] = regs[i];
440}
441
442static void restore_multiple_regs(int base, const unsigned int *src, int count)
443{
444 volatile unsigned int *regs = memregl + base / 4;
445 int i;
446
447 for (i = 0; i < count; i++)
448 regs[i] = src[i];
449}
450
55b0eeea 451void plat_init(void)
452{
453 const char *main_fb_name = "/dev/fb0";
454 struct fb_fix_screeninfo fbfix;
455 int rate, timer_div, timer_div2;
456 int fbdev, ret, warm_ret;
457
458 memdev = open("/dev/mem", O_RDWR);
459 if (memdev == -1) {
460 perror("open(/dev/mem) failed");
461 exit(1);
462 }
463
464 memregs = mmap(0, 0x20000, PROT_READ|PROT_WRITE, MAP_SHARED, memdev, 0xc0000000);
465 if (memregs == MAP_FAILED) {
466 perror("mmap(memregs) failed");
467 exit(1);
468 }
469 memregl = (volatile void *)memregs;
470
0b6c6da8 471 // save video regs of both MLCs
472 save_multiple_regs(saved_video_regs[0], 0x4058, ARRAY_SIZE(saved_video_regs[0]));
473 save_multiple_regs(saved_video_regs[1], 0x4458, ARRAY_SIZE(saved_video_regs[1]));
474
55b0eeea 475 fbdev = open(main_fb_name, O_RDWR);
476 if (fbdev == -1) {
477 fprintf(stderr, "%s: ", main_fb_name);
478 perror("open");
479 exit(1);
480 }
481
482 ret = ioctl(fbdev, FBIOGET_FSCREENINFO, &fbfix);
483 if (ret == -1) {
484 perror("ioctl(fbdev) failed");
485 exit(1);
486 }
487 printf("framebuffer: \"%s\" @ %08lx\n", fbfix.id, fbfix.smem_start);
488 fb_paddrs[0] = fbfix.smem_start;
489 fb_paddrs[1] = fb_paddrs[0] + 320*240*4; // leave space for 24bpp
490
0b6c6da8 491 fb_vaddrs[0] = mmap(0, FB_VRAM_SIZE, PROT_READ|PROT_WRITE,
55b0eeea 492 MAP_SHARED, memdev, fb_paddrs[0]);
493 if (fb_vaddrs[0] == MAP_FAILED) {
494 perror("mmap(fb_vaddrs) failed");
495 exit(1);
496 }
497 fb_vaddrs[1] = (char *)fb_vaddrs[0] + 320*240*4;
498
499 pollux_changemode(16, 0);
500 g_menuscreen_w = 320;
501 g_menuscreen_h = 240;
502 g_menuscreen_ptr = fb_flip();
503
504 g_menubg_ptr = calloc(320*240*2, 1);
505 if (g_menubg_ptr == NULL) {
506 fprintf(stderr, "OOM\n");
507 exit(1);
508 }
509
510 warm_ret = warm_init();
02ee7e24 511 have_warm = warm_ret == 0;
55b0eeea 512 warm_change_cb_upper(WCB_B_BIT, 1);
513
514 /* some firmwares have sys clk on PLL0, we can't adjust CPU clock
515 * by reprogramming the PLL0 then, as it overclocks system bus */
516 if ((memregl[0xf000>>2] & 0x03000030) == 0x01000000)
517 cpu_clock_allowed = 1;
518 else {
519 cpu_clock_allowed = 0;
520 fprintf(stderr, "unexpected PLL config (%08x), overclocking disabled\n",
521 memregl[0xf000>>2]);
522 }
523
524 /* find what PLL1 runs at, for the timer */
525 rate = decode_pll(memregl[0xf008>>2]);
526 printf("PLL1 @ %dHz\n", rate);
527
528 /* setup timer */
529 timer_div = (rate + 500000) / 1000000;
530 timer_div2 = 0;
531 while (timer_div > 256) {
532 timer_div /= 2;
533 timer_div2++;
534 }
535 if (1 <= timer_div && timer_div <= 256 && timer_div2 < 4) {
536 int timer_rate = (rate >> timer_div2) / timer_div;
537 if (TIMER_REG(0x08) & 8) {
538 fprintf(stderr, "warning: timer in use, overriding!\n");
539 timer_cleanup();
540 }
541 if (timer_rate != 1000000)
542 fprintf(stderr, "warning: timer drift %d us\n", timer_rate - 1000000);
543
544 timer_div2 = (timer_div2 + 3) & 3;
545 TIMER_REG(0x44) = ((timer_div - 1) << 4) | 2; /* using PLL1 */
546 TIMER_REG(0x40) = 0x0c; /* clocks on */
547 TIMER_REG(0x08) = 0x68 | timer_div2; /* run timer, clear irq, latch value */
548 }
549 else
550 fprintf(stderr, "warning: could not make use of timer\n");
551
552 /* setup DMA */
553 DMA_REG(0x0c) = 0x20000; // pending IRQ clear
554
555 battdev = open("/dev/pollux_batt", O_RDONLY);
556 if (battdev < 0)
557 perror("Warning: could't open pollux_batt");
558
41f55c9f 559 pl_rearmed_cbs.pl_vout_flip = pl_vout_flip;
02ee7e24 560 pl_rearmed_cbs.pl_vout_raw_flip = have_warm ? raw_flip_dma : raw_flip_soft;
55b0eeea 561 pl_rearmed_cbs.pl_vout_set_mode = pl_vout_set_mode;
562 pl_rearmed_cbs.pl_vout_set_raw_vram = pl_vout_set_raw_vram;
563
564 psx_width = 320;
565 psx_height = 240;
566 psx_bpp = 16;
faf2b2aa 567
568 in_tsbutton_init();
55b0eeea 569}
570
571void plat_finish(void)
572{
573 warm_finish();
574 timer_cleanup();
0b6c6da8 575
576 memset(fb_vaddrs[0], 0, FB_VRAM_SIZE);
577 restore_multiple_regs(0x4058, saved_video_regs[0], ARRAY_SIZE(saved_video_regs[0]));
578 restore_multiple_regs(0x4458, saved_video_regs[1], ARRAY_SIZE(saved_video_regs[1]));
579 memregl[0x4058>>2] |= 0x10;
580 memregl[0x4458>>2] |= 0x10;
581 munmap(fb_vaddrs[0], FB_VRAM_SIZE);
582 close(fbdev);
55b0eeea 583
584 if (battdev >= 0)
585 close(battdev);
55b0eeea 586 munmap((void *)memregs, 0x20000);
587 close(memdev);
588}
589
590void in_update_analogs(void)
591{
592}
593
594/* Caanoo stuff, perhaps move later */
595#include <linux/input.h>
596
597struct in_default_bind in_evdev_defbinds[] = {
598 { KEY_UP, IN_BINDTYPE_PLAYER12, DKEY_UP },
599 { KEY_DOWN, IN_BINDTYPE_PLAYER12, DKEY_DOWN },
600 { KEY_LEFT, IN_BINDTYPE_PLAYER12, DKEY_LEFT },
601 { KEY_RIGHT, IN_BINDTYPE_PLAYER12, DKEY_RIGHT },
602 { BTN_TOP, IN_BINDTYPE_PLAYER12, DKEY_TRIANGLE },
603 { BTN_THUMB, IN_BINDTYPE_PLAYER12, DKEY_CROSS },
604 { BTN_THUMB2, IN_BINDTYPE_PLAYER12, DKEY_CIRCLE },
605 { BTN_TRIGGER, IN_BINDTYPE_PLAYER12, DKEY_SQUARE },
606 { BTN_BASE3, IN_BINDTYPE_PLAYER12, DKEY_START },
607 { BTN_BASE4, IN_BINDTYPE_PLAYER12, DKEY_SELECT },
608 { BTN_TOP2, IN_BINDTYPE_PLAYER12, DKEY_L1 },
609 { BTN_PINKIE, IN_BINDTYPE_PLAYER12, DKEY_R1 },
610 { BTN_BASE, IN_BINDTYPE_EMU, SACTION_ENTER_MENU },
611 { 0, 0, 0 },
612};
613
614static const char * const caanoo_keys[KEY_MAX + 1] = {
615 [0 ... KEY_MAX] = NULL,
616 [KEY_UP] = "Up",
617 [KEY_LEFT] = "Left",
618 [KEY_RIGHT] = "Right",
619 [KEY_DOWN] = "Down",
620 [BTN_TRIGGER] = "A",
621 [BTN_THUMB] = "X",
622 [BTN_THUMB2] = "B",
623 [BTN_TOP] = "Y",
624 [BTN_TOP2] = "L",
625 [BTN_PINKIE] = "R",
626 [BTN_BASE] = "Home",
627 [BTN_BASE2] = "Lock",
628 [BTN_BASE3] = "I",
629 [BTN_BASE4] = "II",
630 [BTN_BASE5] = "Push",
631};
632
633int plat_rescan_inputs(void)
634{
635 in_probe();
636 in_set_config(in_name_to_id("evdev:pollux-analog"), IN_CFG_KEY_NAMES,
637 caanoo_keys, sizeof(caanoo_keys));
638 return 0;
639}