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drc: starting arm64 support
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / emu_if.h
CommitLineData
7139f3c8 1#include "new_dynarec.h"
3d624f89 2#include "../r3000a.h"
3
4extern char invalid_code[0x100000];
5
6/* weird stuff */
7#define EAX 0
8#define ECX 1
9
be516ebe 10extern int dynarec_local[];
11
3d624f89 12/* same as psxRegs */
13extern int reg[];
14
15/* same as psxRegs.GPR.n.* */
16extern int hi, lo;
17
18/* same as psxRegs.CP0.n.* */
7139f3c8 19extern int reg_cop0[];
3d624f89 20#define Status psxRegs.CP0.n.Status
21#define Cause psxRegs.CP0.n.Cause
22#define EPC psxRegs.CP0.n.EPC
23#define BadVAddr psxRegs.CP0.n.BadVAddr
24#define Context psxRegs.CP0.n.Context
25#define EntryHi psxRegs.CP0.n.EntryHi
822b27d1 26#define Count psxRegs.cycle // psxRegs.CP0.n.Count
3d624f89 27
b9b61529 28/* COP2/GTE */
054175e9 29enum gte_opcodes {
30 GTE_RTPS = 0x01,
31 GTE_NCLIP = 0x06,
32 GTE_OP = 0x0c,
33 GTE_DPCS = 0x10,
34 GTE_INTPL = 0x11,
35 GTE_MVMVA = 0x12,
36 GTE_NCDS = 0x13,
37 GTE_CDP = 0x14,
38 GTE_NCDT = 0x16,
39 GTE_NCCS = 0x1b,
40 GTE_CC = 0x1c,
41 GTE_NCS = 0x1e,
42 GTE_NCT = 0x20,
43 GTE_SQR = 0x28,
44 GTE_DCPL = 0x29,
45 GTE_DPCT = 0x2a,
46 GTE_AVSZ3 = 0x2d,
47 GTE_AVSZ4 = 0x2e,
48 GTE_RTPT = 0x30,
49 GTE_GPF = 0x3d,
50 GTE_GPL = 0x3e,
51 GTE_NCCT = 0x3f,
52};
53
b9b61529 54extern int reg_cop2d[], reg_cop2c[];
55extern void *gte_handlers[64];
59774ed0 56extern void *gte_handlers_nf[64];
bedfea38 57extern const char *gte_regnames[64];
b9b61529 58extern const char gte_cycletab[64];
2167bef6 59extern const uint64_t gte_reg_reads[64];
60extern const uint64_t gte_reg_writes[64];
b9b61529 61
3d624f89 62/* mem */
c6c3b1b3 63extern void *mem_rtab;
64extern void *mem_wtab;
65
66void jump_handler_read8(u32 addr, u32 *table, u32 cycles);
67void jump_handler_read16(u32 addr, u32 *table, u32 cycles);
68void jump_handler_read32(u32 addr, u32 *table, u32 cycles);
b96d3df7 69void jump_handler_write8(u32 addr, u32 data, u32 cycles, u32 *table);
70void jump_handler_write16(u32 addr, u32 data, u32 cycles, u32 *table);
71void jump_handler_write32(u32 addr, u32 data, u32 cycles, u32 *table);
72void jump_handler_write_h(u32 addr, u32 data, u32 cycles, void *handler);
73void jump_handle_swl(u32 addr, u32 data, u32 cycles);
74void jump_handle_swr(u32 addr, u32 data, u32 cycles);
b1be1eee 75void rcnt0_read_count_m0(u32 addr, u32, u32 cycles);
76void rcnt0_read_count_m1(u32 addr, u32, u32 cycles);
77void rcnt1_read_count_m0(u32 addr, u32, u32 cycles);
78void rcnt1_read_count_m1(u32 addr, u32, u32 cycles);
79void rcnt2_read_count_m0(u32 addr, u32, u32 cycles);
80void rcnt2_read_count_m1(u32 addr, u32, u32 cycles);
c6c3b1b3 81
f95a77f7 82extern unsigned int address;
cbbab9cd 83extern void *psxH_ptr;
054175e9 84extern void *zeromem_ptr;
c6d5790c 85extern void *scratch_buf_ptr;
cbbab9cd 86
9be4ba64 87// same as invalid_code, just a region for ram write checks (inclusive)
01d26796 88// (psx/guest address range)
9be4ba64 89extern u32 inv_code_start, inv_code_end;
90
7139f3c8 91/* cycles/irqs */
3d624f89 92extern unsigned int next_interupt;
7139f3c8 93extern int pending_exception;
3d624f89 94
95/* called by drc */
63cb0298 96void pcsx_mtc0(u32 reg, u32 val);
97void pcsx_mtc0_ds(u32 reg, u32 val);
3d624f89 98
7139f3c8 99/* misc */
c43b5311 100extern void SysPrintf(const char *fmt, ...);
101
a327ad27 102#ifdef RAM_FIXED
01d26796 103#define rdram ((u_char *)0x80000000)
a327ad27 104#else
01d26796 105#define rdram ((u_char *)psxM)
a327ad27 106#endif
ARM optimized PCSX fork