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drc: get rid of SPAN
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / linkage_arm.S
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
7e605697 2 * linkage_arm.s for PCSX *
0bbd1454 3 * Copyright (C) 2009-2011 Ari64 *
b1f89e6f 4 * Copyright (C) 2010-2013 GraÅžvydas "notaz" Ignotas *
57871462 5 * *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
10 * *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
15 * *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
b021ee75 21
665f33e1 22#include "arm_features.h"
d148d265 23#include "new_dynarec_config.h"
b1f89e6f 24#include "linkage_offsets.h"
25
26
27#ifdef __MACH__
28#define dynarec_local ESYM(dynarec_local)
3d680478 29#define add_jump_out ESYM(add_jump_out)
b1f89e6f 30#define new_recompile_block ESYM(new_recompile_block)
398d6924 31#define ndrc_try_restore_block ESYM(ndrc_try_restore_block)
b1f89e6f 32#define get_addr ESYM(get_addr)
33#define get_addr_ht ESYM(get_addr_ht)
b1f89e6f 34#define gen_interupt ESYM(gen_interupt)
b1f89e6f 35#define invalidate_addr ESYM(invalidate_addr)
81dbbf4c 36#define gteCheckStallRaw ESYM(gteCheckStallRaw)
d1150cd6 37#define psxException ESYM(psxException)
b1f89e6f 38#endif
f95a77f7 39
57871462 40 .bss
41 .align 4
b1f89e6f 42 .global dynarec_local
57871462 43 .type dynarec_local, %object
b1f89e6f 44 .size dynarec_local, LO_dynarec_local_size
57871462 45dynarec_local:
b1f89e6f 46 .space LO_dynarec_local_size
47
48#define DRC_VAR_(name, vname, size_) \
49 vname = dynarec_local + LO_##name; \
50 .global vname; \
51 .type vname, %object; \
52 .size vname, size_
53
54#define DRC_VAR(name, size_) \
55 DRC_VAR_(name, ESYM(name), size_)
56
57DRC_VAR(next_interupt, 4)
58DRC_VAR(cycle_count, 4)
59DRC_VAR(last_count, 4)
60DRC_VAR(pending_exception, 4)
61DRC_VAR(stop, 4)
687b4580 62DRC_VAR(branch_target, 4)
b1f89e6f 63DRC_VAR(address, 4)
7f94b097 64DRC_VAR(hack_addr, 4)
b1f89e6f 65DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
f95a77f7 66
67/* psxRegs */
7c3a5182 68@DRC_VAR(reg, 128)
b1f89e6f 69DRC_VAR(lo, 4)
70DRC_VAR(hi, 4)
71DRC_VAR(reg_cop0, 128)
72DRC_VAR(reg_cop2d, 128)
73DRC_VAR(reg_cop2c, 128)
74DRC_VAR(pcaddr, 4)
75@DRC_VAR(code, 4)
76@DRC_VAR(cycle, 4)
77@DRC_VAR(interrupt, 4)
78@DRC_VAR(intCycle, 256)
79
80DRC_VAR(rcnts, 7*4*4)
687b4580 81DRC_VAR(inv_code_start, 4)
82DRC_VAR(inv_code_end, 4)
b1f89e6f 83DRC_VAR(mem_rtab, 4)
84DRC_VAR(mem_wtab, 4)
85DRC_VAR(psxH_ptr, 4)
86DRC_VAR(zeromem_ptr, 4)
687b4580 87DRC_VAR(invc_ptr, 4)
c6d5790c 88DRC_VAR(scratch_buf_ptr, 4)
37387d8b 89DRC_VAR(ram_offset, 4)
b1f89e6f 90DRC_VAR(mini_ht, 256)
63cb0298 91
57871462 92
0e4ad319 93#ifdef TEXRELS_FORBIDDEN
b861c0a9 94 .data
95 .align 2
96ptr_jump_in:
97 .word ESYM(jump_in)
b861c0a9 98ptr_hash_table:
99 .word ESYM(hash_table)
100#endif
101
102
103 .syntax unified
104 .text
105 .align 2
106
665f33e1 107#ifndef HAVE_ARMV5
108.macro blx rd
109 mov lr, pc
110 bx \rd
111.endm
112#endif
113
c67af2ac 114.macro load_varadr reg var
0e4ad319 115#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
1f4e070a 116 movw \reg, #:lower16:(\var-(1678f+8))
117 movt \reg, #:upper16:(\var-(1678f+8))
b861c0a9 1181678:
119 add \reg, pc
0e4ad319 120#elif defined(HAVE_ARMV7) && !defined(__PIC__)
121 movw \reg, #:lower16:\var
122 movt \reg, #:upper16:\var
c67af2ac 123#else
274c4243 124 ldr \reg, =\var
c67af2ac 125#endif
274c4243 126.endm
127
b861c0a9 128.macro load_varadr_ext reg var
0e4ad319 129#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
1f4e070a 130 movw \reg, #:lower16:(ptr_\var-(1678f+8))
131 movt \reg, #:upper16:(ptr_\var-(1678f+8))
b861c0a9 1321678:
133 ldr \reg, [pc, \reg]
134#else
135 load_varadr \reg \var
136#endif
137.endm
138
b1be1eee 139.macro mov_16 reg imm
8f2bb0cb 140#ifdef HAVE_ARMV7
b1be1eee 141 movw \reg, #\imm
c67af2ac 142#else
b1be1eee 143 mov \reg, #(\imm & 0x00ff)
144 orr \reg, #(\imm & 0xff00)
c67af2ac 145#endif
b1be1eee 146.endm
147
148.macro mov_24 reg imm
8f2bb0cb 149#ifdef HAVE_ARMV7
b1be1eee 150 movw \reg, #(\imm & 0xffff)
151 movt \reg, #(\imm >> 16)
c67af2ac 152#else
b1be1eee 153 mov \reg, #(\imm & 0x0000ff)
154 orr \reg, #(\imm & 0x00ff00)
155 orr \reg, #(\imm & 0xff0000)
c67af2ac 156#endif
b1be1eee 157.endm
158
398d6924 159/* r4 = virtual target address */
160/* r5 = instruction to patch */
76f71c27 161.macro dyna_linker_main
d148d265 162#ifndef NO_WRITE_EXEC
b861c0a9 163 load_varadr_ext r3, jump_in
f968d35d 164 /* get_page */
398d6924 165 lsr r2, r4, #12
f968d35d 166 mov r6, #4096
167 bic r2, r2, #0xe0000
57871462 168 sub r6, r6, #1
f968d35d 169 cmp r2, #0x1000
398d6924 170 ldr r7, [r5]
f968d35d 171 biclt r2, #0x0e00
172 and r6, r6, r2
57871462 173 cmp r2, #2048
174 add r12, r7, #2
175 orrcs r2, r6, #2048
398d6924 176 ldr r1, [r3, r2, lsl #2]
57871462 177 lsl r12, r12, #8
398d6924 178 add r6, r5, r12, asr #6 /* old target */
76f71c27 179 mov r8, #0
57871462 180 /* jump_in lookup */
76f71c27 1811:
398d6924 182 movs r0, r1
76f71c27 183 beq 2f
398d6924 184 ldr r3, [r1] /* ll_entry .vaddr */
185 ldrd r0, r1, [r0, #8] /* ll_entry .addr, .next */
186 teq r3, r4
76f71c27 187 bne 1b
398d6924 188 teq r0, r6
189 moveq pc, r0 /* Stale i-cache */
190 mov r8, r0
76f71c27 191 b 1b /* jump_in may have dupes, continue search */
1922:
193 tst r8, r8
398d6924 194 beq 3f /* r4 not in jump_in */
76f71c27 195
398d6924 196 mov r0, r4
76f71c27 197 mov r1, r6
3d680478 198 bl add_jump_out
76f71c27 199 sub r2, r8, r5
57871462 200 and r1, r7, #0xff000000
201 lsl r2, r2, #6
202 sub r1, r1, #2
203 add r1, r1, r2, lsr #8
204 str r1, [r5]
76f71c27 205 mov pc, r8
2063:
398d6924 207 mov r0, r4
208 bl ndrc_try_restore_block
209 tst r0, r0
210 movne pc, r0
d148d265 211#else
212 /* XXX: should be able to do better than this... */
398d6924 213 mov r0, r4
d148d265 214 bl get_addr_ht
215 mov pc, r0
216#endif
76f71c27 217.endm
218
5c6457c3 219
220FUNCTION(dyna_linker):
76f71c27 221 /* r0 = virtual target address */
222 /* r1 = instruction to patch */
57871462 223 mov r4, r0
224 mov r5, r1
398d6924 22510:
226 dyna_linker_main
227
228 mov r0, r4
57871462 229 bl new_recompile_block
230 tst r0, r0
398d6924 231 beq 10b
232
398d6924 233 mov r0, r4
57871462 234 mov r1, r0
b4ab351d 235 mov r2, #(4<<2) /* Address error (fetch) */
5c6457c3 236
57871462 237 /* r0 = instruction pointer */
238 /* r1 = fault address */
b1f89e6f 239 ldr r3, [fp, #LO_reg_cop0+48] /* Status */
b1f89e6f 240 str r0, [fp, #LO_reg_cop0+56] /* EPC */
57871462 241 orr r3, r3, #2
b1f89e6f 242 str r1, [fp, #LO_reg_cop0+32] /* BadVAddr */
b1f89e6f 243 str r3, [fp, #LO_reg_cop0+48] /* Status */
b1f89e6f 244 str r2, [fp, #LO_reg_cop0+52] /* Cause */
57871462 245 mov r0, #0x80000000
b4ab351d 246 orr r0, r0, #0x80
57871462 247 bl get_addr_ht
248 mov pc, r0
4bdc30ab 249 .size dyna_linker, .-dyna_linker
7139f3c8 250
57871462 251 .align 2
5c6457c3 252FUNCTION(jump_vaddr_r0):
57871462 253 eor r2, r0, r0, lsl #16
254 b jump_vaddr
255 .size jump_vaddr_r0, .-jump_vaddr_r0
5c6457c3 256FUNCTION(jump_vaddr_r1):
57871462 257 eor r2, r1, r1, lsl #16
258 mov r0, r1
259 b jump_vaddr
260 .size jump_vaddr_r1, .-jump_vaddr_r1
5c6457c3 261FUNCTION(jump_vaddr_r2):
57871462 262 mov r0, r2
263 eor r2, r2, r2, lsl #16
264 b jump_vaddr
265 .size jump_vaddr_r2, .-jump_vaddr_r2
5c6457c3 266FUNCTION(jump_vaddr_r3):
57871462 267 eor r2, r3, r3, lsl #16
268 mov r0, r3
269 b jump_vaddr
270 .size jump_vaddr_r3, .-jump_vaddr_r3
5c6457c3 271FUNCTION(jump_vaddr_r4):
57871462 272 eor r2, r4, r4, lsl #16
273 mov r0, r4
274 b jump_vaddr
275 .size jump_vaddr_r4, .-jump_vaddr_r4
5c6457c3 276FUNCTION(jump_vaddr_r5):
57871462 277 eor r2, r5, r5, lsl #16
278 mov r0, r5
279 b jump_vaddr
280 .size jump_vaddr_r5, .-jump_vaddr_r5
5c6457c3 281FUNCTION(jump_vaddr_r6):
57871462 282 eor r2, r6, r6, lsl #16
283 mov r0, r6
284 b jump_vaddr
285 .size jump_vaddr_r6, .-jump_vaddr_r6
5c6457c3 286FUNCTION(jump_vaddr_r8):
57871462 287 eor r2, r8, r8, lsl #16
288 mov r0, r8
289 b jump_vaddr
290 .size jump_vaddr_r8, .-jump_vaddr_r8
5c6457c3 291FUNCTION(jump_vaddr_r9):
57871462 292 eor r2, r9, r9, lsl #16
293 mov r0, r9
294 b jump_vaddr
295 .size jump_vaddr_r9, .-jump_vaddr_r9
5c6457c3 296FUNCTION(jump_vaddr_r10):
57871462 297 eor r2, r10, r10, lsl #16
298 mov r0, r10
299 b jump_vaddr
300 .size jump_vaddr_r10, .-jump_vaddr_r10
5c6457c3 301FUNCTION(jump_vaddr_r12):
57871462 302 eor r2, r12, r12, lsl #16
303 mov r0, r12
304 b jump_vaddr
305 .size jump_vaddr_r12, .-jump_vaddr_r12
5c6457c3 306FUNCTION(jump_vaddr_r7):
57871462 307 eor r2, r7, r7, lsl #16
308 add r0, r7, #0
309 .size jump_vaddr_r7, .-jump_vaddr_r7
5c6457c3 310FUNCTION(jump_vaddr):
b861c0a9 311 load_varadr_ext r1, hash_table
57871462 312 mvn r3, #15
313 and r2, r3, r2, lsr #12
314 ldr r2, [r1, r2]!
315 teq r2, r0
df4dc2b1 316 ldreq pc, [r1, #8]
317 ldr r2, [r1, #4]
57871462 318 teq r2, r0
319 ldreq pc, [r1, #12]
b1f89e6f 320 str r10, [fp, #LO_cycle_count]
57871462 321 bl get_addr
b1f89e6f 322 ldr r10, [fp, #LO_cycle_count]
57871462 323 mov pc, r0
324 .size jump_vaddr, .-jump_vaddr
7139f3c8 325
57871462 326 .align 2
5c6457c3 327
5c6457c3 328FUNCTION(verify_code):
57871462 329 /* r1 = source */
330 /* r2 = target */
331 /* r3 = length */
332 tst r3, #4
333 mov r4, #0
334 add r3, r1, r3
335 mov r5, #0
336 ldrne r4, [r1], #4
337 mov r12, #0
338 ldrne r5, [r2], #4
339 teq r1, r3
340 beq .D3
341.D2:
342 ldr r7, [r1], #4
343 eor r9, r4, r5
344 ldr r8, [r2], #4
345 orrs r9, r9, r12
346 bne .D4
347 ldr r4, [r1], #4
348 eor r12, r7, r8
349 ldr r5, [r2], #4
350 cmp r1, r3
351 bcc .D2
352 teq r7, r8
353.D3:
354 teqeq r4, r5
355.D4:
b1f89e6f 356 ldr r8, [fp, #LO_branch_target]
57871462 357 moveq pc, lr
358.D5:
359 bl get_addr
360 mov pc, r0
361 .size verify_code, .-verify_code
7139f3c8 362
57871462 363 .align 2
5c6457c3 364FUNCTION(cc_interrupt):
b1f89e6f 365 ldr r0, [fp, #LO_last_count]
57871462 366 mov r1, #0
57871462 367 add r10, r0, r10
b1f89e6f 368 str r1, [fp, #LO_pending_exception]
b1f89e6f 369 str r10, [fp, #LO_cycle] /* PCSX cycles */
b4ab351d 370@@ str r10, [fp, #LO_reg_cop0+36] /* Count - not on PSX */
57871462 371 mov r10, lr
398d6924 372
57871462 373 bl gen_interupt
374 mov lr, r10
b1f89e6f 375 ldr r10, [fp, #LO_cycle]
376 ldr r0, [fp, #LO_next_interupt]
377 ldr r1, [fp, #LO_pending_exception]
378 ldr r2, [fp, #LO_stop]
379 str r0, [fp, #LO_last_count]
57871462 380 sub r10, r10, r0
381 tst r2, r2
b861c0a9 382 ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
57871462 383 tst r1, r1
384 moveq pc, lr
b1f89e6f 385 ldr r0, [fp, #LO_pcaddr]
57871462 386 bl get_addr_ht
387 mov pc, r0
57871462 388 .size cc_interrupt, .-cc_interrupt
7139f3c8 389
57871462 390 .align 2
5c6457c3 391FUNCTION(fp_exception):
57871462 392 mov r2, #0x10000000
393.E7:
b1f89e6f 394 ldr r1, [fp, #LO_reg_cop0+48] /* Status */
57871462 395 mov r3, #0x80000000
b1f89e6f 396 str r0, [fp, #LO_reg_cop0+56] /* EPC */
57871462 397 orr r1, #2
398 add r2, r2, #0x2c
b1f89e6f 399 str r1, [fp, #LO_reg_cop0+48] /* Status */
400 str r2, [fp, #LO_reg_cop0+52] /* Cause */
7139f3c8 401 add r0, r3, #0x80
57871462 402 bl get_addr_ht
403 mov pc, r0
404 .size fp_exception, .-fp_exception
405 .align 2
5c6457c3 406FUNCTION(fp_exception_ds):
57871462 407 mov r2, #0x90000000 /* Set high bit if delay slot */
408 b .E7
409 .size fp_exception_ds, .-fp_exception_ds
7139f3c8 410
57871462 411 .align 2
d1150cd6 412FUNCTION(jump_break_ds):
413 mov r0, #0x24
414 mov r1, #1
415 b call_psxException
416FUNCTION(jump_break):
417 mov r0, #0x24
418 mov r1, #0
419 b call_psxException
420FUNCTION(jump_syscall_ds):
421 mov r0, #0x20
422 mov r1, #1
423 b call_psxException
5c6457c3 424FUNCTION(jump_syscall):
d1150cd6 425 mov r0, #0x20
426 mov r1, #0
427
428call_psxException:
429 ldr r3, [fp, #LO_last_count]
430 str r2, [fp, #LO_pcaddr]
431 add r10, r3, r10
432 str r10, [fp, #LO_cycle] /* PCSX cycles */
433 bl psxException
7139f3c8 434
b1f89e6f 435 /* note: psxException might do recursive recompiler call from it's HLE code,
7139f3c8 436 * so be ready for this */
3968e69e 437FUNCTION(jump_to_new_pc):
b1f89e6f 438 ldr r1, [fp, #LO_next_interupt]
439 ldr r10, [fp, #LO_cycle]
440 ldr r0, [fp, #LO_pcaddr]
822b27d1 441 sub r10, r10, r1
b1f89e6f 442 str r1, [fp, #LO_last_count]
7139f3c8 443 bl get_addr_ht
444 mov pc, r0
3968e69e 445 .size jump_to_new_pc, .-jump_to_new_pc
0d16cda2 446
7139f3c8 447 .align 2
5c6457c3 448FUNCTION(new_dyna_leave):
b1f89e6f 449 ldr r0, [fp, #LO_last_count]
7139f3c8 450 add r12, fp, #28
451 add r10, r0, r10
b1f89e6f 452 str r10, [fp, #LO_cycle]
b021ee75 453 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
7139f3c8 454 .size new_dyna_leave, .-new_dyna_leave
455
0bbd1454 456 .align 2
5c6457c3 457FUNCTION(invalidate_addr_r0):
5df0e313 458 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
0bbd1454 459 b invalidate_addr_call
460 .size invalidate_addr_r0, .-invalidate_addr_r0
461 .align 2
5c6457c3 462FUNCTION(invalidate_addr_r1):
5df0e313 463 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64 464 mov r0, r1
0bbd1454 465 b invalidate_addr_call
466 .size invalidate_addr_r1, .-invalidate_addr_r1
467 .align 2
5c6457c3 468FUNCTION(invalidate_addr_r2):
5df0e313 469 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64 470 mov r0, r2
0bbd1454 471 b invalidate_addr_call
472 .size invalidate_addr_r2, .-invalidate_addr_r2
473 .align 2
5c6457c3 474FUNCTION(invalidate_addr_r3):
5df0e313 475 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64 476 mov r0, r3
0bbd1454 477 b invalidate_addr_call
478 .size invalidate_addr_r3, .-invalidate_addr_r3
479 .align 2
5c6457c3 480FUNCTION(invalidate_addr_r4):
5df0e313 481 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64 482 mov r0, r4
0bbd1454 483 b invalidate_addr_call
484 .size invalidate_addr_r4, .-invalidate_addr_r4
485 .align 2
5c6457c3 486FUNCTION(invalidate_addr_r5):
5df0e313 487 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64 488 mov r0, r5
0bbd1454 489 b invalidate_addr_call
490 .size invalidate_addr_r5, .-invalidate_addr_r5
491 .align 2
5c6457c3 492FUNCTION(invalidate_addr_r6):
5df0e313 493 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64 494 mov r0, r6
0bbd1454 495 b invalidate_addr_call
496 .size invalidate_addr_r6, .-invalidate_addr_r6
497 .align 2
5c6457c3 498FUNCTION(invalidate_addr_r7):
5df0e313 499 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64 500 mov r0, r7
0bbd1454 501 b invalidate_addr_call
502 .size invalidate_addr_r7, .-invalidate_addr_r7
503 .align 2
5c6457c3 504FUNCTION(invalidate_addr_r8):
5df0e313 505 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64 506 mov r0, r8
0bbd1454 507 b invalidate_addr_call
508 .size invalidate_addr_r8, .-invalidate_addr_r8
509 .align 2
5c6457c3 510FUNCTION(invalidate_addr_r9):
5df0e313 511 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64 512 mov r0, r9
0bbd1454 513 b invalidate_addr_call
514 .size invalidate_addr_r9, .-invalidate_addr_r9
515 .align 2
5c6457c3 516FUNCTION(invalidate_addr_r10):
5df0e313 517 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64 518 mov r0, r10
0bbd1454 519 b invalidate_addr_call
520 .size invalidate_addr_r10, .-invalidate_addr_r10
521 .align 2
5c6457c3 522FUNCTION(invalidate_addr_r12):
5df0e313 523 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64 524 mov r0, r12
0bbd1454 525 .size invalidate_addr_r12, .-invalidate_addr_r12
526 .align 2
b1f89e6f 527invalidate_addr_call:
528 ldr r12, [fp, #LO_inv_code_start]
529 ldr lr, [fp, #LO_inv_code_end]
9be4ba64 530 cmp r0, r12
531 cmpcs lr, r0
532 blcc invalidate_addr
5df0e313 533 ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
0bbd1454 534 .size invalidate_addr_call, .-invalidate_addr_call
535
57871462 536 .align 2
5c6457c3 537FUNCTION(new_dyna_start):
b021ee75 538 /* ip is stored to conform EABI alignment */
539 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
be516ebe 540 mov fp, r0 /* dynarec_local */
b1f89e6f 541 ldr r0, [fp, #LO_pcaddr]
7139f3c8 542 bl get_addr_ht
b1f89e6f 543 ldr r1, [fp, #LO_next_interupt]
544 ldr r10, [fp, #LO_cycle]
545 str r1, [fp, #LO_last_count]
7139f3c8 546 sub r10, r10, r1
547 mov pc, r0
57871462 548 .size new_dyna_start, .-new_dyna_start
7139f3c8 549
7e605697 550/* --------------------------------------- */
7139f3c8 551
7e605697 552.align 2
c6c3b1b3 553
554.macro pcsx_read_mem readop tab_shift
555 /* r0 = address, r1 = handler_tab, r2 = cycles */
556 lsl r3, r0, #20
557 lsr r3, #(20+\tab_shift)
b1f89e6f 558 ldr r12, [fp, #LO_last_count]
c6c3b1b3 559 ldr r1, [r1, r3, lsl #2]
560 add r2, r2, r12
561 lsls r1, #1
562.if \tab_shift == 1
563 lsl r3, #1
564 \readop r0, [r1, r3]
565.else
566 \readop r0, [r1, r3, lsl #\tab_shift]
567.endif
568 movcc pc, lr
b1f89e6f 569 str r2, [fp, #LO_cycle]
c6c3b1b3 570 bx r1
571.endm
572
5c6457c3 573FUNCTION(jump_handler_read8):
c6c3b1b3 574 add r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
b861c0a9 575 pcsx_read_mem ldrbcc, 0
c6c3b1b3 576
5c6457c3 577FUNCTION(jump_handler_read16):
c6c3b1b3 578 add r1, #0x1000/4*4 @ shift to r16 part
10858959 579 pcsx_read_mem ldrhcc, 1
c6c3b1b3 580
5c6457c3 581FUNCTION(jump_handler_read32):
c6c3b1b3 582 pcsx_read_mem ldrcc, 2
583
b96d3df7 584
9b9af0d1 585.macro memhandler_post
586 ldr r0, [fp, #LO_next_interupt]
587 ldr r2, [fp, #LO_cycle] @ memhandlers can modify cc, like dma
588 str r0, [fp, #LO_last_count]
589 sub r0, r2, r0
590.endm
591
b96d3df7 592.macro pcsx_write_mem wrtop tab_shift
593 /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
594 lsl r12,r0, #20
595 lsr r12, #(20+\tab_shift)
596 ldr r3, [r3, r12, lsl #2]
b1f89e6f 597 str r0, [fp, #LO_address] @ some handlers still need it..
b96d3df7 598 lsls r3, #1
9b9af0d1 599 mov r0, r2 @ cycle return in case of direct store
b96d3df7 600.if \tab_shift == 1
601 lsl r12, #1
602 \wrtop r1, [r3, r12]
603.else
604 \wrtop r1, [r3, r12, lsl #\tab_shift]
605.endif
606 movcc pc, lr
b1f89e6f 607 ldr r12, [fp, #LO_last_count]
b96d3df7 608 mov r0, r1
609 add r2, r2, r12
b1f89e6f 610 str r2, [fp, #LO_cycle]
9b9af0d1 611
612 str lr, [fp, #LO_saved_lr]
b96d3df7 613 blx r3
9b9af0d1 614 ldr lr, [fp, #LO_saved_lr]
b96d3df7 615
9b9af0d1 616 memhandler_post
687b4580 617 bx lr
b96d3df7 618.endm
619
5c6457c3 620FUNCTION(jump_handler_write8):
b96d3df7 621 add r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
b861c0a9 622 pcsx_write_mem strbcc, 0
b96d3df7 623
5c6457c3 624FUNCTION(jump_handler_write16):
b96d3df7 625 add r3, #0x1000/4*4 @ shift to r16 part
b861c0a9 626 pcsx_write_mem strhcc, 1
b96d3df7 627
5c6457c3 628FUNCTION(jump_handler_write32):
b96d3df7 629 pcsx_write_mem strcc, 2
630
5c6457c3 631FUNCTION(jump_handler_write_h):
b96d3df7 632 /* r0 = address, r1 = data, r2 = cycles, r3 = handler */
b1f89e6f 633 ldr r12, [fp, #LO_last_count]
634 str r0, [fp, #LO_address] @ some handlers still need it..
b96d3df7 635 add r2, r2, r12
636 mov r0, r1
b1f89e6f 637 str r2, [fp, #LO_cycle]
9b9af0d1 638
639 str lr, [fp, #LO_saved_lr]
b96d3df7 640 blx r3
9b9af0d1 641 ldr lr, [fp, #LO_saved_lr]
b96d3df7 642
9b9af0d1 643 memhandler_post
687b4580 644 bx lr
b96d3df7 645
5c6457c3 646FUNCTION(jump_handle_swl):
b96d3df7 647 /* r0 = address, r1 = data, r2 = cycles */
b1f89e6f 648 ldr r3, [fp, #LO_mem_wtab]
b96d3df7 649 mov r12,r0,lsr #12
650 ldr r3, [r3, r12, lsl #2]
651 lsls r3, #1
652 bcs 4f
653 add r3, r0, r3
654 mov r0, r2
655 tst r3, #2
656 beq 101f
657 tst r3, #1
658 beq 2f
6593:
660 str r1, [r3, #-3]
661 bx lr
6622:
663 lsr r2, r1, #8
664 lsr r1, #24
665 strh r2, [r3, #-2]
666 strb r1, [r3]
667 bx lr
668101:
669 tst r3, #1
670 lsrne r1, #16 @ 1
671 lsreq r12, r1, #24 @ 0
b861c0a9 672 strhne r1, [r3, #-1]
673 strbeq r12, [r3]
b96d3df7 674 bx lr
6754:
676 mov r0, r2
63cb0298 677@ b abort
b96d3df7 678 bx lr @ TODO?
679
680
5c6457c3 681FUNCTION(jump_handle_swr):
b96d3df7 682 /* r0 = address, r1 = data, r2 = cycles */
b1f89e6f 683 ldr r3, [fp, #LO_mem_wtab]
b96d3df7 684 mov r12,r0,lsr #12
685 ldr r3, [r3, r12, lsl #2]
686 lsls r3, #1
687 bcs 4f
688 add r3, r0, r3
689 and r12,r3, #3
690 mov r0, r2
691 cmp r12,#2
b861c0a9 692 strbgt r1, [r3] @ 3
693 strheq r1, [r3] @ 2
b96d3df7 694 cmp r12,#1
695 strlt r1, [r3] @ 0
696 bxne lr
697 lsr r2, r1, #8 @ 1
698 strb r1, [r3]
699 strh r2, [r3, #1]
700 bx lr
7014:
702 mov r0, r2
63cb0298 703@ b abort
b96d3df7 704 bx lr @ TODO?
705
706
b1be1eee 707.macro rcntx_read_mode0 num
708 /* r0 = address, r2 = cycles */
b1f89e6f 709 ldr r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart
b1be1eee 710 mov r0, r2, lsl #16
b861c0a9 711 sub r0, r0, r3, lsl #16
b1be1eee 712 lsr r0, #16
713 bx lr
714.endm
715
5c6457c3 716FUNCTION(rcnt0_read_count_m0):
b1be1eee 717 rcntx_read_mode0 0
718
5c6457c3 719FUNCTION(rcnt1_read_count_m0):
b1be1eee 720 rcntx_read_mode0 1
721
5c6457c3 722FUNCTION(rcnt2_read_count_m0):
b1be1eee 723 rcntx_read_mode0 2
724
5c6457c3 725FUNCTION(rcnt0_read_count_m1):
b1be1eee 726 /* r0 = address, r2 = cycles */
b1f89e6f 727 ldr r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart
b1be1eee 728 mov_16 r1, 0x3334
729 sub r2, r2, r3
730 mul r0, r1, r2 @ /= 5
731 lsr r0, #16
732 bx lr
733
5c6457c3 734FUNCTION(rcnt1_read_count_m1):
b1be1eee 735 /* r0 = address, r2 = cycles */
b1f89e6f 736 ldr r3, [fp, #LO_rcnts+6*4+7*4*1]
b1be1eee 737 mov_24 r1, 0x1e6cde
738 sub r2, r2, r3
739 umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd
740 bx lr
741
5c6457c3 742FUNCTION(rcnt2_read_count_m1):
b1be1eee 743 /* r0 = address, r2 = cycles */
b1f89e6f 744 ldr r3, [fp, #LO_rcnts+6*4+7*4*2]
b1be1eee 745 mov r0, r2, lsl #16-3
b861c0a9 746 sub r0, r0, r3, lsl #16-3
b1be1eee 747 lsr r0, #16 @ /= 8
748 bx lr
749
81dbbf4c 750FUNCTION(call_gteStall):
751 /* r0 = op_cycles, r1 = cycles */
752 ldr r2, [fp, #LO_last_count]
753 str lr, [fp, #LO_saved_lr]
754 add r1, r1, r2
755 str r1, [fp, #LO_cycle]
756 add r1, fp, #LO_psxRegs
757 bl gteCheckStallRaw
758 ldr lr, [fp, #LO_saved_lr]
759 add r10, r10, r0
760 bx lr
761
cdc2da64 762#ifdef HAVE_ARMV6
763
764FUNCTION(get_reg):
765 ldr r12, [r0]
766 and r1, r1, #0xff
767 ldr r2, [r0, #4]
768 orr r1, r1, r1, lsl #8
769 ldr r3, [r0, #8]
770 orr r1, r1, r1, lsl #16 @ searched char in every byte
771 ldrb r0, [r0, #12] @ last byte
772 eor r12, r12, r1
773 eor r2, r2, r1
774 eor r3, r3, r1
775 cmp r0, r1, lsr #24
776 mov r0, #12
777 mvn r1, #0 @ r1=~0
778 bxeq lr
779 orr r3, r3, #0xff000000 @ EXCLUDE_REG
780 uadd8 r0, r12, r1 @ add and set GE bits when not 0 (match)
781 mov r12, #0
782 sel r0, r12, r1 @ 0 if no match, else ff in some byte
783 uadd8 r2, r2, r1
784 sel r2, r12, r1
785 uadd8 r3, r3, r1
786 sel r3, r12, r1
787 mov r12, #3
788 clz r0, r0 @ 0, 8, 16, 24 or 32
789 clz r2, r2
790 clz r3, r3
791 sub r0, r12, r0, lsr #3 @ 3, 2, 1, 0 or -1
792 sub r2, r12, r2, lsr #3
793 sub r3, r12, r3, lsr #3
794 orr r2, r2, #4
795 orr r3, r3, #8
796 and r0, r0, r2
797 and r0, r0, r3
798 bx lr
799
800#endif /* HAVE_ARMV6 */
801
7e605697 802@ vim:filetype=armasm
ARM optimized PCSX fork