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drc: starting arm64 support
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / linkage_arm64.S
CommitLineData
be516ebe 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * linkage_arm.s for PCSX *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2021 notaz *
5 * *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
10 * *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
15 * *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
21
22#include "arm_features.h"
23#include "new_dynarec_config.h"
24#include "assem_arm64.h"
25#include "linkage_offsets.h"
26
27.bss
28 .align 4
29 .global dynarec_local
30 .type dynarec_local, %object
31 .size dynarec_local, LO_dynarec_local_size
32dynarec_local:
33 .space LO_dynarec_local_size
34
35#define DRC_VAR_(name, vname, size_) \
36 vname = dynarec_local + LO_##name; \
37 .global vname; \
38 .type vname, %object; \
39 .size vname, size_
40
41#define DRC_VAR(name, size_) \
42 DRC_VAR_(name, ESYM(name), size_)
43
44DRC_VAR(next_interupt, 4)
45DRC_VAR(cycle_count, 4)
46DRC_VAR(last_count, 4)
47DRC_VAR(pending_exception, 4)
48DRC_VAR(stop, 4)
49DRC_VAR(invc_ptr, 4)
50DRC_VAR(address, 4)
51DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
52
53/* psxRegs */
54DRC_VAR(reg, 128)
55DRC_VAR(lo, 4)
56DRC_VAR(hi, 4)
57DRC_VAR(reg_cop0, 128)
58DRC_VAR(reg_cop2d, 128)
59DRC_VAR(reg_cop2c, 128)
60DRC_VAR(pcaddr, 4)
61#DRC_VAR(code, 4)
62#DRC_VAR(cycle, 4)
63#DRC_VAR(interrupt, 4)
64#DRC_VAR(intCycle, 256)
65
66DRC_VAR(rcnts, 7*4*4)
67DRC_VAR(mem_rtab, 4)
68DRC_VAR(mem_wtab, 4)
69DRC_VAR(psxH_ptr, 4)
70DRC_VAR(zeromem_ptr, 4)
71DRC_VAR(inv_code_start, 4)
72DRC_VAR(inv_code_end, 4)
73DRC_VAR(branch_target, 4)
74DRC_VAR(scratch_buf_ptr, 4)
75#DRC_VAR(align0, 12) /* unused/alignment */
76DRC_VAR(mini_ht, 256)
77DRC_VAR(restore_candidate, 512)
78
79
80 .text
81 .align 2
82
83/* r0 = virtual target address */
84/* r1 = instruction to patch */
85.macro dyna_linker_main
86 /* XXX: should be able to do better than this... */
87 bl get_addr_ht
88 br x0
89.endm
90
91
92FUNCTION(dyna_linker):
93 /* r0 = virtual target address */
94 /* r1 = instruction to patch */
95 dyna_linker_main
96 .size dyna_linker, .-dyna_linker
97
98FUNCTION(exec_pagefault):
99 /* r0 = instruction pointer */
100 /* r1 = fault address */
101 /* r2 = cause */
102 bl abort
103 .size exec_pagefault, .-exec_pagefault
104
105/* Special dynamic linker for the case where a page fault
106 may occur in a branch delay slot */
107FUNCTION(dyna_linker_ds):
108 /* r0 = virtual target address */
109 /* r1 = instruction to patch */
110 dyna_linker_main
111 .size dyna_linker_ds, .-dyna_linker_ds
112
113 .align 2
114
115FUNCTION(jump_vaddr):
116 bl abort
117 .size jump_vaddr, .-jump_vaddr
118
119 .align 2
120
121FUNCTION(verify_code_ds):
122 bl abort
123FUNCTION(verify_code_vm):
124FUNCTION(verify_code):
125 /* r1 = source */
126 /* r2 = target */
127 /* r3 = length */
128 bl abort
129 .size verify_code, .-verify_code
130 .size verify_code_vm, .-verify_code_vm
131
132 .align 2
133FUNCTION(cc_interrupt):
134 bl abort
135 .size cc_interrupt, .-cc_interrupt
136
137 .align 2
138FUNCTION(do_interrupt):
139 bl abort
140 .size do_interrupt, .-do_interrupt
141
142 .align 2
143FUNCTION(fp_exception):
144 mov w2, #0x10000000
1450:
146 ldr w1, [fp, #LO_reg_cop0+48] /* Status */
147 mov w3, #0x80000000
148 str w0, [fp, #LO_reg_cop0+56] /* EPC */
149 orr w1, w1, #2
150 add w2, w2, #0x2c
151 str w1, [fp, #LO_reg_cop0+48] /* Status */
152 str w2, [fp, #LO_reg_cop0+52] /* Cause */
153 add w0, w3, #0x80
154 bl get_addr_ht
155 br x0
156 .size fp_exception, .-fp_exception
157 .align 2
158FUNCTION(fp_exception_ds):
159 mov w2, #0x90000000 /* Set high bit if delay slot */
160 b 0b
161 .size fp_exception_ds, .-fp_exception_ds
162
163 .align 2
164FUNCTION(jump_syscall):
165 ldr w1, [fp, #LO_reg_cop0+48] /* Status */
166 mov w3, #0x80000000
167 str w0, [fp, #LO_reg_cop0+56] /* EPC */
168 orr w1, w1, #2
169 mov w2, #0x20
170 str w1, [fp, #LO_reg_cop0+48] /* Status */
171 str w2, [fp, #LO_reg_cop0+52] /* Cause */
172 add w0, w3, #0x80
173 bl get_addr_ht
174 br x0
175 .size jump_syscall, .-jump_syscall
176 .align 2
177
178 .align 2
179FUNCTION(jump_syscall_hle):
180 bl abort
181
182 /* note: psxException might do recursive recompiler call from it's HLE code,
183 * so be ready for this */
184pcsx_return:
185 bl abort // w10
186 ldr w1, [fp, #LO_next_interupt]
187 ldr w10, [fp, #LO_cycle]
188 ldr w0, [fp, #LO_pcaddr]
189 sub w10, w10, w1
190 str w1, [fp, #LO_last_count]
191 bl get_addr_ht
192 br x0
193 .size jump_syscall_hle, .-jump_syscall_hle
194
195 .align 2
196FUNCTION(jump_hlecall):
197 bl abort
198 .size jump_hlecall, .-jump_hlecall
199
200 .align 2
201FUNCTION(jump_intcall):
202 bl abort
203 .size jump_intcall, .-jump_intcall
204
205 .align 2
206FUNCTION(new_dyna_start):
207 stp x29, x30, [sp, #-96]! // must be aligned by 16
208 ldr w1, [x0, #LO_next_interupt]
209 ldr w2, [x0, #LO_cycle]
210 stp x19, x20, [sp, #16*1]
211 stp x21, x22, [sp, #16*2]
212 stp x23, x24, [sp, #16*3]
213 stp x25, x26, [sp, #16*4]
214 stp x27, x28, [sp, #16*5]
215 mov rFP, x0
216 ldr w0, [rFP, #LO_pcaddr]
217 str w1, [rFP, #LO_last_count]
218 sub rCC, w2, w1
219 bl get_addr_ht
220 br x0
221 .size new_dyna_start, .-new_dyna_start
222
223 .align 2
224FUNCTION(new_dyna_leave):
225 ldr w0, [rFP, #LO_last_count]
226 add rCC, rCC, w0
227 str rCC, [rFP, #LO_cycle]
228 ldp x19, x20, [sp, #16*1]
229 ldp x21, x22, [sp, #16*2]
230 ldp x23, x24, [sp, #16*3]
231 ldp x25, x26, [sp, #16*4]
232 ldp x27, x28, [sp, #16*5]
233 ldp x29, x30, [sp], #96
234 ret
235 .size new_dyna_leave, .-new_dyna_leave
236
237/* --------------------------------------- */
238
239.align 2
240
241FUNCTION(jump_handler_read8):
242 bl abort
243
244FUNCTION(jump_handler_read16):
245 bl abort
246
247FUNCTION(jump_handler_read32):
248 bl abort
249
250FUNCTION(jump_handler_write8):
251 bl abort
252
253FUNCTION(jump_handler_write16):
254 bl abort
255
256FUNCTION(jump_handler_write32):
257 bl abort
258
259FUNCTION(jump_handler_write_h):
260 bl abort
261
262FUNCTION(jump_handle_swl):
263 bl abort
264
265FUNCTION(jump_handle_swr):
266 bl abort
267
ARM optimized PCSX fork