[pcsx_rearmed.git] / libpcsxcore / new_dynarec / patches / trace_intr

diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c
index 2862c546..8af9a27e 100644
--- a/libpcsxcore/new_dynarec/emu_if.c
+++ b/libpcsxcore/new_dynarec/emu_if.c
@@ -322,13 +322,18 @@ static void ari64_shutdown()
 {
 	new_dynarec_cleanup();
 	new_dyna_pcsx_mem_shutdown();
+	(void)ari64_execute;
+	(void)ari64_execute_block;
 }
 
+extern void intExecuteT();
+extern void intExecuteBlockT();
+
 R3000Acpu psxRec = {
 	ari64_init,
 	ari64_reset,
-	ari64_execute,
-	ari64_execute_block,
+	intExecuteT,
+	intExecuteBlockT,
 	ari64_clear,
 	ari64_notify,
 	ari64_apply_config,
@@ -397,7 +402,7 @@ static u32 memcheck_read(u32 a)
 	return *(u32 *)(psxM + (a & 0x1ffffc));
 }
 
-#if 0
+#if 1
 void do_insn_trace(void)
 {
 	static psxRegisters oldregs;
diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c
index 190f8fc7..5feb7a02 100644
--- a/libpcsxcore/new_dynarec/pcsxmem.c
+++ b/libpcsxcore/new_dynarec/pcsxmem.c
@@ -289,6 +289,8 @@ static void write_biu(u32 value)
 		return;
 	}
 
+extern u32 handler_cycle;
+handler_cycle = psxRegs.cycle;
 	memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle);
 	psxRegs.biuReg = value;
 }
diff --git a/libpcsxcore/psxcounters.c b/libpcsxcore/psxcounters.c
index 18bd6a4e..bc2eb3f6 100644
--- a/libpcsxcore/psxcounters.c
+++ b/libpcsxcore/psxcounters.c
@@ -389,9 +389,12 @@ void psxRcntUpdate()
 
 /******************************************************************************/
 
+extern u32 handler_cycle;
+
 void psxRcntWcount( u32 index, u32 value )
 {
     verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
+handler_cycle = psxRegs.cycle;
 
     _psxRcntWcount( index, value );
     psxRcntSet();
@@ -400,6 +403,7 @@ void psxRcntWcount( u32 index, u32 value )
 void psxRcntWmode( u32 index, u32 value )
 {
     verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
+handler_cycle = psxRegs.cycle;
 
     _psxRcntWmode( index, value );
     _psxRcntWcount( index, 0 );
@@ -411,6 +415,7 @@ void psxRcntWmode( u32 index, u32 value )
 void psxRcntWtarget( u32 index, u32 value )
 {
     verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
+handler_cycle = psxRegs.cycle;
 
     rcnts[index].target = value;
 
@@ -423,6 +428,7 @@ void psxRcntWtarget( u32 index, u32 value )
 u32 psxRcntRcount( u32 index )
 {
     u32 count;
+handler_cycle = psxRegs.cycle;
 
     count = _psxRcntRcount( index );
 
diff --git a/libpcsxcore/psxhw.c b/libpcsxcore/psxhw.c
index 27ddfeab..d7c6ff05 100644
--- a/libpcsxcore/psxhw.c
+++ b/libpcsxcore/psxhw.c
@@ -377,13 +377,14 @@ void psxHwWrite8(u32 add, u8 value) {
 		case 0x1f801803: cdrWrite3(value); break;
 
 		default:
+			if (add < 0x1f802000)
 			psxHu8(add) = value;
 #ifdef PSXHW_LOG
 			PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
 #endif
 			return;
 	}
-	psxHu8(add) = value;
+	//psxHu8(add) = value;
 #ifdef PSXHW_LOG
 	PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
 #endif
@@ -506,6 +507,7 @@ void psxHwWrite16(u32 add, u16 value) {
 				return;
 			}
 
+			if (add < 0x1f802000)
 			psxHu16ref(add) = SWAPu16(value);
 #ifdef PSXHW_LOG
 			PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
@@ -701,9 +703,9 @@ void psxHwWrite32(u32 add, u32 value) {
 			return;
 
 		case 0x1f801820:
-			mdecWrite0(value); break;
+			mdecWrite0(value); return;
 		case 0x1f801824:
-			mdecWrite1(value); break;
+			mdecWrite1(value); return;
 
 		case 0x1f801100:
 #ifdef PSXHW_LOG
@@ -761,6 +763,7 @@ void psxHwWrite32(u32 add, u32 value) {
 				return;
 			}
 
+			if (add < 0x1f802000)
 			psxHu32ref(add) = SWAPu32(value);
 #ifdef PSXHW_LOG
 			PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
index e212d8a9..42498e96 100644
--- a/libpcsxcore/psxinterpreter.c
+++ b/libpcsxcore/psxinterpreter.c
@@ -237,7 +237,7 @@ static inline void addCycle(psxRegisters *regs)
 {
 	assert(regs->subCycleStep >= 0x10000);
 	regs->subCycle += regs->subCycleStep;
-	regs->cycle += regs->subCycle >> 16;
+	regs->cycle += 2; //regs->subCycle >> 16;
 	regs->subCycle &= 0xffff;
 }
 
@@ -434,7 +434,9 @@ static void doBranch(psxRegisters *regs, u32 tar, enum R3000Abdt taken) {
 		regs->CP0.n.Target = pc_final;
 	regs->branching = 0;
 
+	psxRegs.cycle += 2;
 	psxBranchTest();
+	psxRegs.cycle -= 2;
 }
 
 static void doBranchReg(psxRegisters *regs, u32 tar) {
@@ -959,7 +961,7 @@ void MTC0(psxRegisters *regs_, int reg, u32 val) {
 	}
 }
 
-OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); }
+OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); psxBranchTest(); }
 
 // no exception
 static inline void psxNULLne(psxRegisters *regs) {
@@ -1167,18 +1169,20 @@ static void intReset() {
 static inline void execI_(u8 **memRLUT, psxRegisters *regs) {
 	u32 pc = regs->pc;
 
-	addCycle(regs);
+	//addCycle(regs);
 	dloadStep(regs);
 
 	regs->pc += 4;
 	regs->code = fetch(regs, memRLUT, pc);
 	psxBSC[regs->code >> 26](regs, regs->code);
+	psxRegs.cycle += 2;
+	fetchNoCache(regs, memRLUT, regs->pc); // bus err check
 }
 
 static inline void execIbp(u8 **memRLUT, psxRegisters *regs) {
 	u32 pc = regs->pc;
 
-	addCycle(regs);
+	//addCycle(regs);
 	dloadStep(regs);
 
 	if (execBreakCheck(regs, pc))
@@ -1187,6 +1191,8 @@ static inline void execIbp(u8 **memRLUT, psxRegisters *regs) {
 	regs->pc += 4;
 	regs->code = fetch(regs, memRLUT, pc);
 	psxBSC[regs->code >> 26](regs, regs->code);
+	psxRegs.cycle += 2;
+	fetchNoCache(regs, memRLUT, regs->pc); // bus err check
 }
 
 static void intExecute() {
@@ -1216,6 +1222,30 @@ void intExecuteBlock(enum blockExecCaller caller) {
 		execI_(memRLUT, regs_);
 }
 
+extern void do_insn_trace(void);
+
+void intExecuteT() {
+	psxRegisters *regs_ = &psxRegs;
+	u8 **memRLUT = psxMemRLUT;
+	extern int stop;
+
+	while (!stop) {
+		do_insn_trace();
+		execIbp(memRLUT, regs_);
+	}
+}
+
+void intExecuteBlockT() {
+	psxRegisters *regs_ = &psxRegs;
+	u8 **memRLUT = psxMemRLUT;
+
+	branchSeen = 0;
+	while (!branchSeen) {
+		do_insn_trace();
+		execIbp(memRLUT, regs_);
+	}
+}
+
 static void intClear(u32 Addr, u32 Size) {
 }
 
@@ -1263,7 +1293,7 @@ void intApplyConfig() {
 	assert(psxSPC[26] == psxDIV   || psxSPC[26] == psxDIV_stall);
 	assert(psxSPC[27] == psxDIVU  || psxSPC[27] == psxDIVU_stall);
 
-	if (Config.DisableStalls) {
+	if (1) {
 		psxBSC[18] = psxCOP2;
 		psxBSC[50] = gteLWC2;
 		psxBSC[58] = gteSWC2;
diff --git a/libpcsxcore/psxmem.c b/libpcsxcore/psxmem.c
index 54219ae0..41168ced 100644
--- a/libpcsxcore/psxmem.c
+++ b/libpcsxcore/psxmem.c
@@ -278,10 +278,13 @@ void psxMemOnIsolate(int enable)
 			: R3000ACPU_NOTIFY_CACHE_UNISOLATED, NULL);
 }
 
+extern u32 last_io_addr;
+
 u8 psxMemRead8(u32 mem) {
 	char *p;
 	u32 t;
 
+	last_io_addr = mem;
 	t = mem >> 16;
 	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
 		if ((mem & 0xffff) < 0x400)
@@ -307,6 +310,7 @@ u16 psxMemRead16(u32 mem) {
 	char *p;
 	u32 t;
 
+	last_io_addr = mem;
 	t = mem >> 16;
 	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
 		if ((mem & 0xffff) < 0x400)
@@ -332,6 +336,7 @@ u32 psxMemRead32(u32 mem) {
 	char *p;
 	u32 t;
 
+	last_io_addr = mem;
 	t = mem >> 16;
 	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
 		if ((mem & 0xffff) < 0x400)
@@ -359,6 +364,7 @@ void psxMemWrite8(u32 mem, u8 value) {
 	char *p;
 	u32 t;
 
+	last_io_addr = mem;
 	t = mem >> 16;
 	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
 		if ((mem & 0xffff) < 0x400)
@@ -386,6 +392,7 @@ void psxMemWrite16(u32 mem, u16 value) {
 	char *p;
 	u32 t;
 
+	last_io_addr = mem;
 	t = mem >> 16;
 	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
 		if ((mem & 0xffff) < 0x400)
@@ -413,6 +420,7 @@ void psxMemWrite32(u32 mem, u32 value) {
 	char *p;
 	u32 t;
 
+	last_io_addr = mem;
 //	if ((mem&0x1fffff) == 0x71E18 || value == 0x48088800) SysPrintf("t2fix!!\n");
 	t = mem >> 16;
 	if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {
@@ -431,6 +439,8 @@ void psxMemWrite32(u32 mem, u32 value) {
 #endif
 		} else {
 			if (mem == 0xfffe0130) {
+extern u32 handler_cycle;
+handler_cycle = psxRegs.cycle;
 				psxRegs.biuReg = value;
 				return;
 			}
diff --git a/libpcsxcore/r3000a.c b/libpcsxcore/r3000a.c
index dffbf6e7..0a3bdb65 100644
--- a/libpcsxcore/r3000a.c
+++ b/libpcsxcore/r3000a.c
@@ -124,6 +124,8 @@ void psxException(u32 cause, enum R3000Abdt bdt, psxCP0Regs *cp0) {
 }
 
 void psxBranchTest() {
+ extern u32 irq_test_cycle;
+ irq_test_cycle = psxRegs.cycle;
 	if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
 		psxRcntUpdate();
Commit	Line	Data
a151a8d8	1	diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c
de6dbc52	2	index 2862c546..8af9a27e 100644
a151a8d8	3	--- a/libpcsxcore/new_dynarec/emu_if.c
a151a8d8	4	+++ b/libpcsxcore/new_dynarec/emu_if.c
de6dbc52	5	@@ -322,13 +322,18 @@ static void ari64_shutdown()
a151a8d8	6	{
	7	new_dynarec_cleanup();
	8	new_dyna_pcsx_mem_shutdown();
	9	+ (void)ari64_execute;
a5cd72d0	10	+ (void)ari64_execute_block;
a151a8d8	11	}
	12
	13	+extern void intExecuteT();
	14	+extern void intExecuteBlockT();
	15	+
	16	R3000Acpu psxRec = {
	17	ari64_init,
	18	ari64_reset,
	19	- ari64_execute,
a5cd72d0	20	- ari64_execute_block,
a151a8d8	21	+ intExecuteT,
	22	+ intExecuteBlockT,
	23	ari64_clear,
a151a8d8	24	ari64_notify,
37387d8b	25	ari64_apply_config,
de6dbc52	26	@@ -397,7 +402,7 @@ static u32 memcheck_read(u32 a)
a151a8d8	27	return (u32 )(psxM + (a & 0x1ffffc));
	28	}
	29
	30	-#if 0
	31	+#if 1
	32	void do_insn_trace(void)
	33	{
	34	static psxRegisters oldregs;
2330734f	35	diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c
a5cd72d0	36	index 190f8fc7..5feb7a02 100644
2330734f	37	--- a/libpcsxcore/new_dynarec/pcsxmem.c
2330734f	38	+++ b/libpcsxcore/new_dynarec/pcsxmem.c
a5cd72d0	39	@@ -289,6 +289,8 @@ static void write_biu(u32 value)
2330734f	40	return;
a5cd72d0	41	}
2330734f	42
	43	+extern u32 handler_cycle;
	44	+handler_cycle = psxRegs.cycle;
a5cd72d0	45	memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle);
	46	psxRegs.biuReg = value;
	47	}
2330734f	48	diff --git a/libpcsxcore/psxcounters.c b/libpcsxcore/psxcounters.c
a5cd72d0	49	index 18bd6a4e..bc2eb3f6 100644
2330734f	50	--- a/libpcsxcore/psxcounters.c
2330734f	51	+++ b/libpcsxcore/psxcounters.c
a5cd72d0	52	@@ -389,9 +389,12 @@ void psxRcntUpdate()
2330734f	53
	54	/******************************************************************************/
	55
	56	+extern u32 handler_cycle;
	57	+
	58	void psxRcntWcount( u32 index, u32 value )
	59	{
	60	verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
	61	+handler_cycle = psxRegs.cycle;
	62
	63	_psxRcntWcount( index, value );
	64	psxRcntSet();
a5cd72d0	65	@@ -400,6 +403,7 @@ void psxRcntWcount( u32 index, u32 value )
2330734f	66	void psxRcntWmode( u32 index, u32 value )
	67	{
	68	verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
	69	+handler_cycle = psxRegs.cycle;
	70
	71	_psxRcntWmode( index, value );
	72	_psxRcntWcount( index, 0 );
a5cd72d0	73	@@ -411,6 +415,7 @@ void psxRcntWmode( u32 index, u32 value )
2330734f	74	void psxRcntWtarget( u32 index, u32 value )
	75	{
	76	verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
	77	+handler_cycle = psxRegs.cycle;
	78
	79	rcnts[index].target = value;
	80
a5cd72d0	81	@@ -423,6 +428,7 @@ void psxRcntWtarget( u32 index, u32 value )
2330734f	82	u32 psxRcntRcount( u32 index )
	83	{
	84	u32 count;
	85	+handler_cycle = psxRegs.cycle;
	86
	87	count = _psxRcntRcount( index );
	88
a151a8d8	89	diff --git a/libpcsxcore/psxhw.c b/libpcsxcore/psxhw.c
a5cd72d0	90	index 27ddfeab..d7c6ff05 100644
a151a8d8	91	--- a/libpcsxcore/psxhw.c
a151a8d8	92	+++ b/libpcsxcore/psxhw.c
a5cd72d0	93	@@ -377,13 +377,14 @@ void psxHwWrite8(u32 add, u8 value) {
a151a8d8	94	case 0x1f801803: cdrWrite3(value); break;
	95
	96	default:
	97	+ if (add < 0x1f802000)
	98	psxHu8(add) = value;
	99	#ifdef PSXHW_LOG
	100	PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
	101	#endif
	102	return;
	103	}
	104	- psxHu8(add) = value;
	105	+ //psxHu8(add) = value;
	106	#ifdef PSXHW_LOG
	107	PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
	108	#endif
a5cd72d0	109	@@ -506,6 +507,7 @@ void psxHwWrite16(u32 add, u16 value) {
a151a8d8	110	return;
	111	}
	112
	113	+ if (add < 0x1f802000)
	114	psxHu16ref(add) = SWAPu16(value);
	115	#ifdef PSXHW_LOG
	116	PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
a5cd72d0	117	@@ -701,9 +703,9 @@ void psxHwWrite32(u32 add, u32 value) {
a151a8d8	118	return;
	119
	120	case 0x1f801820:
	121	- mdecWrite0(value); break;
	122	+ mdecWrite0(value); return;
	123	case 0x1f801824:
	124	- mdecWrite1(value); break;
	125	+ mdecWrite1(value); return;
	126
	127	case 0x1f801100:
	128	#ifdef PSXHW_LOG
a5cd72d0	129	@@ -761,6 +763,7 @@ void psxHwWrite32(u32 add, u32 value) {
a151a8d8	130	return;
	131	}
	132
	133	+ if (add < 0x1f802000)
	134	psxHu32ref(add) = SWAPu32(value);
	135	#ifdef PSXHW_LOG
	136	PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
	137	diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
de6dbc52	138	index e212d8a9..42498e96 100644
a151a8d8	139	--- a/libpcsxcore/psxinterpreter.c
a151a8d8	140	+++ b/libpcsxcore/psxinterpreter.c
a5cd72d0	141	@@ -237,7 +237,7 @@ static inline void addCycle(psxRegisters *regs)
	142	{
	143	assert(regs->subCycleStep >= 0x10000);
	144	regs->subCycle += regs->subCycleStep;
	145	- regs->cycle += regs->subCycle >> 16;
	146	+ regs->cycle += 2; //regs->subCycle >> 16;
	147	regs->subCycle &= 0xffff;
	148	}
a151a8d8	149
a5cd72d0	150	@@ -434,7 +434,9 @@ static void doBranch(psxRegisters *regs, u32 tar, enum R3000Abdt taken) {
	151	regs->CP0.n.Target = pc_final;
	152	regs->branching = 0;
a151a8d8	153
a5cd72d0	154	+ psxRegs.cycle += 2;
2330734f	155	psxBranchTest();
a5cd72d0	156	+ psxRegs.cycle -= 2;
a151a8d8	157	}
a151a8d8	158
a5cd72d0	159	static void doBranchReg(psxRegisters *regs, u32 tar) {
de6dbc52	160	@@ -959,7 +961,7 @@ void MTC0(psxRegisters *regs_, int reg, u32 val) {
a5cd72d0	161	}
a151a8d8	162	}
a151a8d8	163
a5cd72d0	164	-OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); }
	165	+OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); psxBranchTest(); }
	166
	167	// no exception
	168	static inline void psxNULLne(psxRegisters *regs) {
de6dbc52	169	@@ -1167,18 +1169,20 @@ static void intReset() {
a5cd72d0	170	static inline void execI_(u8 *memRLUT, psxRegisters regs) {
	171	u32 pc = regs->pc;
	172
	173	- addCycle(regs);
	174	+ //addCycle(regs);
	175	dloadStep(regs);
	176
	177	regs->pc += 4;
	178	regs->code = fetch(regs, memRLUT, pc);
	179	psxBSC[regs->code >> 26](regs, regs->code);
	180	+ psxRegs.cycle += 2;
de6dbc52	181	+ fetchNoCache(regs, memRLUT, regs->pc); // bus err check
55a695d9	182	}
a151a8d8	183
a5cd72d0	184	static inline void execIbp(u8 *memRLUT, psxRegisters regs) {
	185	u32 pc = regs->pc;
	186
	187	- addCycle(regs);
	188	+ //addCycle(regs);
	189	dloadStep(regs);
	190
	191	if (execBreakCheck(regs, pc))
de6dbc52	192	@@ -1187,6 +1191,8 @@ static inline void execIbp(u8 *memRLUT, psxRegisters regs) {
a5cd72d0	193	regs->pc += 4;
	194	regs->code = fetch(regs, memRLUT, pc);
	195	psxBSC[regs->code >> 26](regs, regs->code);
	196	+ psxRegs.cycle += 2;
de6dbc52	197	+ fetchNoCache(regs, memRLUT, regs->pc); // bus err check
a5cd72d0	198	}
55a695d9	199
a5cd72d0	200	static void intExecute() {
de6dbc52	201	@@ -1216,6 +1222,30 @@ void intExecuteBlock(enum blockExecCaller caller) {
a5cd72d0	202	execI_(memRLUT, regs_);
a151a8d8	203	}
	204
	205	+extern void do_insn_trace(void);
	206	+
	207	+void intExecuteT() {
a5cd72d0	208	+ psxRegisters *regs_ = &psxRegs;
	209	+ u8 **memRLUT = psxMemRLUT;
	210	+ extern int stop;
	211	+
	212	+ while (!stop) {
a151a8d8	213	+ do_insn_trace();
a5cd72d0	214	+ execIbp(memRLUT, regs_);
a151a8d8	215	+ }
	216	+}
	217	+
	218	+void intExecuteBlockT() {
a5cd72d0	219	+ psxRegisters *regs_ = &psxRegs;
	220	+ u8 **memRLUT = psxMemRLUT;
	221	+
	222	+ branchSeen = 0;
	223	+ while (!branchSeen) {
a151a8d8	224	+ do_insn_trace();
a5cd72d0	225	+ execIbp(memRLUT, regs_);
a151a8d8	226	+ }
	227	+}
	228	+
	229	static void intClear(u32 Addr, u32 Size) {
	230	}
	231
de6dbc52	232	@@ -1263,7 +1293,7 @@ void intApplyConfig() {
2330734f	233	assert(psxSPC[26] == psxDIV \|\| psxSPC[26] == psxDIV_stall);
	234	assert(psxSPC[27] == psxDIVU \|\| psxSPC[27] == psxDIVU_stall);
	235
	236	- if (Config.DisableStalls) {
	237	+ if (1) {
	238	psxBSC[18] = psxCOP2;
	239	psxBSC[50] = gteLWC2;
	240	psxBSC[58] = gteSWC2;
a151a8d8	241	diff --git a/libpcsxcore/psxmem.c b/libpcsxcore/psxmem.c
a5cd72d0	242	index 54219ae0..41168ced 100644
a151a8d8	243	--- a/libpcsxcore/psxmem.c
a151a8d8	244	+++ b/libpcsxcore/psxmem.c
a5cd72d0	245	@@ -278,10 +278,13 @@ void psxMemOnIsolate(int enable)
a5cd72d0	246	: R3000ACPU_NOTIFY_CACHE_UNISOLATED, NULL);
a151a8d8	247	}
a151a8d8	248
2330734f	249	+extern u32 last_io_addr;
a5cd72d0	250	+
a151a8d8	251	u8 psxMemRead8(u32 mem) {
	252	char *p;
	253	u32 t;
	254
	255	+ last_io_addr = mem;
	256	t = mem >> 16;
	257	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
	258	if ((mem & 0xffff) < 0x400)
a5cd72d0	259	@@ -307,6 +310,7 @@ u16 psxMemRead16(u32 mem) {
a151a8d8	260	char *p;
	261	u32 t;
	262
	263	+ last_io_addr = mem;
	264	t = mem >> 16;
	265	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
	266	if ((mem & 0xffff) < 0x400)
a5cd72d0	267	@@ -332,6 +336,7 @@ u32 psxMemRead32(u32 mem) {
a151a8d8	268	char *p;
	269	u32 t;
	270
	271	+ last_io_addr = mem;
	272	t = mem >> 16;
	273	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
	274	if ((mem & 0xffff) < 0x400)
a5cd72d0	275	@@ -359,6 +364,7 @@ void psxMemWrite8(u32 mem, u8 value) {
a151a8d8	276	char *p;
	277	u32 t;
	278
	279	+ last_io_addr = mem;
	280	t = mem >> 16;
	281	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
	282	if ((mem & 0xffff) < 0x400)
a5cd72d0	283	@@ -386,6 +392,7 @@ void psxMemWrite16(u32 mem, u16 value) {
a151a8d8	284	char *p;
	285	u32 t;
	286
	287	+ last_io_addr = mem;
	288	t = mem >> 16;
	289	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
	290	if ((mem & 0xffff) < 0x400)
a5cd72d0	291	@@ -413,6 +420,7 @@ void psxMemWrite32(u32 mem, u32 value) {
a151a8d8	292	char *p;
	293	u32 t;
	294
	295	+ last_io_addr = mem;
	296	// if ((mem&0x1fffff) == 0x71E18 \|\| value == 0x48088800) SysPrintf("t2fix!!\n");
	297	t = mem >> 16;
	298	if (t == 0x1f80 \|\| t == 0x9f80 \|\| t == 0xbf80) {
a5cd72d0	299	@@ -431,6 +439,8 @@ void psxMemWrite32(u32 mem, u32 value) {
	300	#endif
	301	} else {
	302	if (mem == 0xfffe0130) {
2330734f	303	+extern u32 handler_cycle;
2330734f	304	+handler_cycle = psxRegs.cycle;
a5cd72d0	305	psxRegs.biuReg = value;
	306	return;
	307	}
2330734f	308	diff --git a/libpcsxcore/r3000a.c b/libpcsxcore/r3000a.c
a5cd72d0	309	index dffbf6e7..0a3bdb65 100644
2330734f	310	--- a/libpcsxcore/r3000a.c
2330734f	311	+++ b/libpcsxcore/r3000a.c
a5cd72d0	312	@@ -124,6 +124,8 @@ void psxException(u32 cause, enum R3000Abdt bdt, psxCP0Regs *cp0) {
2330734f	313	}
	314
	315	void psxBranchTest() {
	316	+ extern u32 irq_test_cycle;
	317	+ irq_test_cycle = psxRegs.cycle;
	318	if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
	319	psxRcntUpdate();
	320