[pcsx_rearmed.git] / libpcsxcore / new_dynarec / pcsxmem.c

/*
 * (C) Gražvydas "notaz" Ignotas, 2010-2011
 *
 * This work is licensed under the terms of GNU GPL version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#include <stdio.h>
#include "../psxhw.h"
#include "../cdrom.h"
#include "../mdec.h"
#include "../gpu.h"
#include "../psxmem_map.h"
#include "emu_if.h"
#include "pcsxmem.h"

#ifdef __thumb__
#error the dynarec is incompatible with Thumb functions,
#error please add -marm to compile flags
#endif

//#define memprintf printf
#define memprintf(...)

static uintptr_t *mem_readtab;
static uintptr_t *mem_writetab;
static uintptr_t mem_iortab[(1+2+4) * 0x1000 / 4];
static uintptr_t mem_iowtab[(1+2+4) * 0x1000 / 4];
static uintptr_t mem_ffrtab[(1+2+4) * 0x1000 / 4];
static uintptr_t mem_ffwtab[(1+2+4) * 0x1000 / 4];
//static uintptr_t mem_unmrtab[(1+2+4) * 0x1000 / 4];
static uintptr_t mem_unmwtab[(1+2+4) * 0x1000 / 4];

static
#ifdef __clang__
// When this is called in a loop, and 'h' is a function pointer, clang will crash.
__attribute__ ((noinline))
#endif
void map_item(uintptr_t *out, const void *h, uintptr_t flag)
{
	uintptr_t hv = (uintptr_t)h;
	if (hv & 1) {
		SysPrintf("FATAL: %p has LSB set\n", h);
		abort();
	}
	*out = (hv >> 1) | (flag << (sizeof(hv) * 8 - 1));
}

// size must be power of 2, at least 4k
#define map_l1_mem(tab, i, addr, size, base) \
	map_item(&tab[((u32)(addr) >> 12) + i], \
		 (u8 *)(base) - (u32)((addr) + ((i << 12) & ~(size - 1))), 0)

#define IOMEM32(a) (((a) & 0xfff) / 4)
#define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
#define IOMEM8(a)  (0x1000/4 + 0x1000/2 + ((a) & 0xfff))

u32 zero_mem[0x1000/4];
static u32 ffff_mem[0x1000/4];

static u32 read_mem_dummy(u32 addr)
{
	// use 'addr' and not 'address', yes the api is weird...
	memprintf("unmapped r %08x @%08x %u\n", addr, psxRegs.pc, psxRegs.cycle);
	return 0xffffffff;
}

static void write_mem_dummy(u32 data)
{
	if (!(psxRegs.CP0.n.SR & (1 << 16)))
		memprintf("unmapped w %08x, %08x @%08x %u\n",
			  address, data, psxRegs.pc, psxRegs.cycle);
}

/* IO handlers */
static u32 io_read_sio16()
{
	return sioRead8() | (sioRead8() << 8);
}

static u32 io_read_sio32()
{
	return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24);
}

static void io_write_sio16(u32 value)
{
	sioWrite8((unsigned char)value);
	sioWrite8((unsigned char)(value>>8));
}

static void io_write_sio32(u32 value)
{
	sioWrite8((unsigned char)value);
	sioWrite8((unsigned char)(value >>  8));
	sioWrite8((unsigned char)(value >> 16));
	sioWrite8((unsigned char)(value >> 24));
}

#if !defined(DRC_DBG) && defined(__arm__)

static void map_rcnt_rcount0(u32 mode)
{
	if (mode & 0x001) { // sync mode
		map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1);
		map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1);
	}
	else if (mode & 0x100) { // pixel clock
		map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
		map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
	}
	else {
		map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
		map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
	}
}

static void map_rcnt_rcount1(u32 mode)
{
	if (mode & 0x001) { // sync mode
		map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1);
		map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1);
	}
	else if (mode & 0x100) { // hcnt
		map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
		map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
	}
	else {
		map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
		map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
	}
}

static void map_rcnt_rcount2(u32 mode)
{
	if ((mode & 7) == 1 || (mode & 7) == 7) { // sync mode
		map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
		map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
	}
	else if (mode & 0x200) { // clk/8
		map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
		map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
	}
	else {
		map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
		map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
	}
}

#else
#define map_rcnt_rcount0(mode)
#define map_rcnt_rcount1(mode)
#define map_rcnt_rcount2(mode)
#endif

#define make_rcnt_funcs(i) \
static u32 io_rcnt_read_mode##i()   { return psxRcntRmode(i); } \
static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
static void io_rcnt_write_count##i(u32 val)  { psxRcntWcount(i, val & 0xffff); } \
static void io_rcnt_write_mode##i(u32 val)   { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }

make_rcnt_funcs(0)
make_rcnt_funcs(1)
make_rcnt_funcs(2)

#define make_dma_func(n) \
static void io_write_chcr##n(u32 value) \
{ \
	HW_DMA##n##_CHCR = value; \
	if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
		psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
	} \
}

make_dma_func(0)
make_dma_func(1)
make_dma_func(2)
make_dma_func(3)
make_dma_func(4)
make_dma_func(6)

static void io_spu_write16(u32 value)
{
	// meh
	SPU_writeRegister(address, value, psxRegs.cycle);
}

static void io_spu_write32(u32 value)
{
	SPUwriteRegister wfunc = SPU_writeRegister;
	u32 a = address;

	wfunc(a, value & 0xffff, psxRegs.cycle);
	wfunc(a + 2, value >> 16, psxRegs.cycle);
}

static u32 io_gpu_read_status(void)
{
	u32 v;

	// meh2, syncing for img bit, might want to avoid it..
	gpuSyncPluginSR();
	v = HW_GPU_STATUS;

	// XXX: because of large timeslices can't use hSyncCount, using rough
	// approximization instead. Perhaps better use hcounter code here or something.
	if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
		v |= PSXGPU_LCF & (psxRegs.cycle << 20);
	return v;
}

static void io_gpu_write_status(u32 value)
{
	GPU_writeStatus(value);
	gpuSyncPluginSR();
}

void new_dyna_pcsx_mem_isolate(int enable)
{
	int i;

	// note: apparently 0xa0000000 uncached access still works,
	// at least read does for sure, so assume write does too
	memprintf("mem isolate %d\n", enable);
	if (enable) {
		for (i = 0; i < (0x800000 >> 12); i++) {
			map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1);
			map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1);
			//map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1);
		}
	}
	else {
		for (i = 0; i < (0x800000 >> 12); i++) {
			map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
			map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
			map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
		}
	}
}

static u32 read_biu(u32 addr)
{
	if (addr != 0xfffe0130)
		return read_mem_dummy(addr);

	memprintf("read_biu  %08x @%08x %u\n",
		psxRegs.biuReg, psxRegs.pc, psxRegs.cycle);
	return psxRegs.biuReg;
}

static void write_biu(u32 value)
{
	if (address != 0xfffe0130) {
		write_mem_dummy(value);
		return;
	}

	memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle);
	psxRegs.biuReg = value;
}

void new_dyna_pcsx_mem_load_state(void)
{
	map_rcnt_rcount0(rcnts[0].mode);
	map_rcnt_rcount1(rcnts[1].mode);
	map_rcnt_rcount2(rcnts[2].mode);
}

int pcsxmem_is_handler_dynamic(unsigned int addr)
{
	if ((addr & 0xfffff000) != 0x1f801000)
		return 0;

	addr &= 0xffff;
	return addr == 0x1100 || addr == 0x1110 || addr == 0x1120;
}

void new_dyna_pcsx_mem_init(void)
{
	int i;

	memset(ffff_mem, 0xff, sizeof(ffff_mem));

	// have to map these further to keep tcache close to .text
	mem_readtab = psxMap(0x08000000, 0x200000 * sizeof(mem_readtab[0]), 0, MAP_TAG_LUTS);
	if (mem_readtab == NULL) {
		SysPrintf("failed to map mem tables\n");
		exit(1);
	}
	mem_writetab = mem_readtab + 0x100000;

	// 1st level lookup:
	//   0: direct mem
	//   1: use 2nd lookup
	// 2nd level lookup:
	//   0: direct mem variable
	//   1: memhandler

	// default/unmapped memhandlers
	for (i = 0; i < 0x100000; i++) {
		//map_item(&mem_readtab[i], mem_unmrtab, 1);
		map_l1_mem(mem_readtab, i, 0, 0x1000, ffff_mem);
		map_item(&mem_writetab[i], mem_unmwtab, 1);
	}

	// RAM and it's mirrors
	for (i = 0; i < (0x800000 >> 12); i++) {
		map_l1_mem(mem_readtab,  i, 0x80000000, 0x200000, psxM);
		map_l1_mem(mem_readtab,  i, 0x00000000, 0x200000, psxM);
		map_l1_mem(mem_readtab,  i, 0xa0000000, 0x200000, psxM);
	}
	new_dyna_pcsx_mem_isolate(0);

	// BIOS and it's mirrors
	for (i = 0; i < (0x80000 >> 12); i++) {
		map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
		map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
	}

	// scratchpad
	map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
	map_l1_mem(mem_readtab, 0, 0x9f800000, 0x1000, psxH);
	map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
	map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH);

	// I/O
	map_item(&mem_readtab[0x1f801000u >> 12], mem_iortab, 1);
	map_item(&mem_readtab[0x9f801000u >> 12], mem_iortab, 1);
	map_item(&mem_readtab[0xbf801000u >> 12], mem_iortab, 1);
	map_item(&mem_writetab[0x1f801000u >> 12], mem_iowtab, 1);
	map_item(&mem_writetab[0x9f801000u >> 12], mem_iowtab, 1);
	map_item(&mem_writetab[0xbf801000u >> 12], mem_iowtab, 1);

	// L2
	// unmapped tables
	for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
		map_item(&mem_unmwtab[i], write_mem_dummy, 1);

	// fill IO tables
	for (i = 0; i < 0x1000/4; i++) {
		map_item(&mem_iortab[i], &psxH[0x1000], 0);
		map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	}
	for (; i < 0x1000/4 + 0x1000/2; i++) {
		map_item(&mem_iortab[i], &psxH[0x1000], 0);
		map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	}
	for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
		map_item(&mem_iortab[i], &psxH[0x1000], 0);
		map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	}

	map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
	map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1);
	map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
	map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
	map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1);
	map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
	map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
	map_item(&mem_iortab[IOMEM32(0x1120)], psxRcntRcount2, 1);
	map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
	map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
//	map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
	map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1);
	map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
	map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);

	map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
	map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
	map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
	map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
	map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
	map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1);
	map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
	map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
	map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1);
	map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
	map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
	map_item(&mem_iortab[IOMEM16(0x1120)], psxRcntRcount2, 1);
	map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
	map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);

	map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
	map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
	map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
	map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
	map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);

	// write(u32 data)
	map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1070)], psxHwWriteIstat, 1);
	map_item(&mem_iowtab[IOMEM32(0x1074)], psxHwWriteImask, 1);
	map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
	map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
	map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
	map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
	map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
	map_item(&mem_iowtab[IOMEM32(0x10f4)], psxHwWriteDmaIcr32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
	map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
	map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
	map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
	map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
	map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
//	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
	map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1);
	map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);

	map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
	map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
	map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1070)], psxHwWriteIstat, 1);
	map_item(&mem_iowtab[IOMEM16(0x1074)], psxHwWriteImask, 1);
	map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
	map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
	map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
	map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
	map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
	map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
	map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
	map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
	map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);

	map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
	map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
	map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
	map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
	map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);

	for (i = 0x1c00; i < 0x2000; i += 2) {
		map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
		map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
	}

	// misc
	map_item(&mem_readtab[0xfffe0130u >> 12], mem_ffrtab, 1);
	map_item(&mem_writetab[0xfffe0130u >> 12], mem_ffwtab, 1);
	for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
		map_item(&mem_ffrtab[i], read_biu, 1);
		map_item(&mem_ffwtab[i], write_biu, 1);
	}

	mem_rtab = mem_readtab;
	mem_wtab = mem_writetab;

	new_dyna_pcsx_mem_load_state();
}

void new_dyna_pcsx_mem_reset(void)
{
	int i;

	// plugins might change so update the pointers
	map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);

	for (i = 0x1c00; i < 0x2000; i += 2)
		map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);

	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
}

void new_dyna_pcsx_mem_shutdown(void)
{
	psxUnmap(mem_readtab, 0x200000 * sizeof(mem_readtab[0]), MAP_TAG_LUTS);
	mem_writetab = mem_readtab = NULL;
}
Commit	Line	Data
7e605697	1	/*
274c4243	2	* (C) Gražvydas "notaz" Ignotas, 2010-2011
7e605697	3	*
	4	* This work is licensed under the terms of GNU GPL version 2 or later.
	5	* See the COPYING file in the top-level directory.
	6	*/
	7
	8	#include <stdio.h>
	9	#include "../psxhw.h"
	10	#include "../cdrom.h"
	11	#include "../mdec.h"
ddbaf678	12	#include "../gpu.h"
87e5b45f	13	#include "../psxmem_map.h"
7e605697	14	#include "emu_if.h"
	15	#include "pcsxmem.h"
	16
5905989e	17	#ifdef __thumb__
9f704290	18	#error the dynarec is incompatible with Thumb functions,
9f704290	19	#error please add -marm to compile flags
5905989e	20	#endif
5905989e	21
7e605697	22	//#define memprintf printf
	23	#define memprintf(...)
	24
be516ebe	25	static uintptr_t *mem_readtab;
	26	static uintptr_t *mem_writetab;
	27	static uintptr_t mem_iortab[(1+2+4) * 0x1000 / 4];
	28	static uintptr_t mem_iowtab[(1+2+4) * 0x1000 / 4];
679d5ee3	29	static uintptr_t mem_ffrtab[(1+2+4) * 0x1000 / 4];
be516ebe	30	static uintptr_t mem_ffwtab[(1+2+4) * 0x1000 / 4];
	31	//static uintptr_t mem_unmrtab[(1+2+4) * 0x1000 / 4];
	32	static uintptr_t mem_unmwtab[(1+2+4) * 0x1000 / 4];
	33
	34	static
578c6882	35	#ifdef __clang__
be516ebe	36	// When this is called in a loop, and 'h' is a function pointer, clang will crash.
be516ebe	37	__attribute__ ((noinline))
578c6882	38	#endif
be516ebe	39	void map_item(uintptr_t out, const void h, uintptr_t flag)
b1be1eee	40	{
be516ebe	41	uintptr_t hv = (uintptr_t)h;
5905989e	42	if (hv & 1) {
f29fbd53	43	SysPrintf("FATAL: %p has LSB set\n", h);
5905989e	44	abort();
5905989e	45	}
be516ebe	46	out = (hv >> 1) \| (flag << (sizeof(hv) 8 - 1));
b1be1eee	47	}
	48
	49	// size must be power of 2, at least 4k
	50	#define map_l1_mem(tab, i, addr, size, base) \
679d5ee3	51	map_item(&tab[((u32)(addr) >> 12) + i], \
e3973c69	52	(u8 *)(base) - (u32)((addr) + ((i << 12) & ~(size - 1))), 0)
b1be1eee	53
	54	#define IOMEM32(a) (((a) & 0xfff) / 4)
	55	#define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
	56	#define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
	57
679d5ee3	58	u32 zero_mem[0x1000/4];
679d5ee3	59	static u32 ffff_mem[0x1000/4];
7a481d40	60
679d5ee3	61	static u32 read_mem_dummy(u32 addr)
7e605697	62	{
679d5ee3	63	// use 'addr' and not 'address', yes the api is weird...
	64	memprintf("unmapped r %08x @%08x %u\n", addr, psxRegs.pc, psxRegs.cycle);
	65	return 0xffffffff;
7e605697	66	}
7e605697	67
b96d3df7	68	static void write_mem_dummy(u32 data)
7e605697	69	{
bc7c5acb	70	if (!(psxRegs.CP0.n.SR & (1 << 16)))
679d5ee3	71	memprintf("unmapped w %08x, %08x @%08x %u\n",
679d5ee3	72	address, data, psxRegs.pc, psxRegs.cycle);
7e605697	73	}
7e605697	74
7e605697	75	/* IO handlers */
	76	static u32 io_read_sio16()
	77	{
	78	return sioRead8() \| (sioRead8() << 8);
	79	}
	80
	81	static u32 io_read_sio32()
	82	{
	83	return sioRead8() \| (sioRead8() << 8) \| (sioRead8() << 16) \| (sioRead8() << 24);
	84	}
	85
	86	static void io_write_sio16(u32 value)
	87	{
	88	sioWrite8((unsigned char)value);
	89	sioWrite8((unsigned char)(value>>8));
	90	}
	91
	92	static void io_write_sio32(u32 value)
	93	{
	94	sioWrite8((unsigned char)value);
b96d3df7	95	sioWrite8((unsigned char)(value >> 8));
	96	sioWrite8((unsigned char)(value >> 16));
	97	sioWrite8((unsigned char)(value >> 24));
7e605697	98	}
7e605697	99
be516ebe	100	#if !defined(DRC_DBG) && defined(__arm__)
19776aef	101
b1be1eee	102	static void map_rcnt_rcount0(u32 mode)
b1be1eee	103	{
11d23573	104	if (mode & 0x001) { // sync mode
	105	map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1);
	106	map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1);
	107	}
	108	else if (mode & 0x100) { // pixel clock
b1be1eee	109	map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
	110	map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
	111	}
	112	else {
	113	map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
	114	map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
	115	}
	116	}
	117
	118	static void map_rcnt_rcount1(u32 mode)
	119	{
11d23573	120	if (mode & 0x001) { // sync mode
	121	map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1);
	122	map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1);
	123	}
	124	else if (mode & 0x100) { // hcnt
b1be1eee	125	map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
	126	map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
	127	}
	128	else {
	129	map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
	130	map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
	131	}
	132	}
	133
	134	static void map_rcnt_rcount2(u32 mode)
	135	{
11d23573	136	if ((mode & 7) == 1 \|\| (mode & 7) == 7) { // sync mode
b1be1eee	137	map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
	138	map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
	139	}
	140	else if (mode & 0x200) { // clk/8
	141	map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
	142	map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
	143	}
	144	else {
	145	map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
	146	map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
	147	}
	148	}
	149
19776aef	150	#else
	151	#define map_rcnt_rcount0(mode)
	152	#define map_rcnt_rcount1(mode)
	153	#define map_rcnt_rcount2(mode)
	154	#endif
	155
7e605697	156	#define make_rcnt_funcs(i) \
7e605697	157	static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \
	158	static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
	159	static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \
b1be1eee	160	static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
7e605697	161	static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
	162
	163	make_rcnt_funcs(0)
	164	make_rcnt_funcs(1)
	165	make_rcnt_funcs(2)
	166
7e605697	167	#define make_dma_func(n) \
	168	static void io_write_chcr##n(u32 value) \
	169	{ \
	170	HW_DMA##n##_CHCR = value; \
	171	if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
	172	psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
	173	} \
	174	}
	175
	176	make_dma_func(0)
	177	make_dma_func(1)
	178	make_dma_func(2)
	179	make_dma_func(3)
	180	make_dma_func(4)
	181	make_dma_func(6)
	182
b96d3df7	183	static void io_spu_write16(u32 value)
	184	{
	185	// meh
650adfd2	186	SPU_writeRegister(address, value, psxRegs.cycle);
b96d3df7	187	}
	188
	189	static void io_spu_write32(u32 value)
	190	{
	191	SPUwriteRegister wfunc = SPU_writeRegister;
	192	u32 a = address;
	193
650adfd2	194	wfunc(a, value & 0xffff, psxRegs.cycle);
650adfd2	195	wfunc(a + 2, value >> 16, psxRegs.cycle);
b96d3df7	196	}
b96d3df7	197
ddbaf678	198	static u32 io_gpu_read_status(void)
ddbaf678	199	{
0486fdc9	200	u32 v;
0486fdc9	201
ddbaf678	202	// meh2, syncing for img bit, might want to avoid it..
ddbaf678	203	gpuSyncPluginSR();
0486fdc9	204	v = HW_GPU_STATUS;
	205
	206	// XXX: because of large timeslices can't use hSyncCount, using rough
	207	// approximization instead. Perhaps better use hcounter code here or something.
	208	if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
	209	v \|= PSXGPU_LCF & (psxRegs.cycle << 20);
	210	return v;
ddbaf678	211	}
	212
	213	static void io_gpu_write_status(u32 value)
	214	{
	215	GPU_writeStatus(value);
	216	gpuSyncPluginSR();
	217	}
	218
679d5ee3	219	void new_dyna_pcsx_mem_isolate(int enable)
b96d3df7	220	{
	221	int i;
	222
679d5ee3	223	// note: apparently 0xa0000000 uncached access still works,
	224	// at least read does for sure, so assume write does too
	225	memprintf("mem isolate %d\n", enable);
	226	if (enable) {
	227	for (i = 0; i < (0x800000 >> 12); i++) {
	228	map_item(&mem_writetab[0x80000\|i], mem_unmwtab, 1);
	229	map_item(&mem_writetab[0x00000\|i], mem_unmwtab, 1);
	230	//map_item(&mem_writetab[0xa0000\|i], mem_unmwtab, 1);
	231	}
	232	}
	233	else {
	234	for (i = 0; i < (0x800000 >> 12); i++) {
	235	map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
	236	map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
	237	map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
	238	}
b96d3df7	239	}
	240	}
	241
679d5ee3	242	static u32 read_biu(u32 addr)
b96d3df7	243	{
679d5ee3	244	if (addr != 0xfffe0130)
	245	return read_mem_dummy(addr);
	246
679d5ee3	247	memprintf("read_biu %08x @%08x %u\n",
	248	psxRegs.biuReg, psxRegs.pc, psxRegs.cycle);
	249	return psxRegs.biuReg;
b96d3df7	250	}
	251
	252	static void write_biu(u32 value)
	253	{
679d5ee3	254	if (address != 0xfffe0130) {
679d5ee3	255	write_mem_dummy(value);
b96d3df7	256	return;
b96d3df7	257	}
679d5ee3	258
	259	memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle);
	260	psxRegs.biuReg = value;
b96d3df7	261	}
b96d3df7	262
b1be1eee	263	void new_dyna_pcsx_mem_load_state(void)
	264	{
	265	map_rcnt_rcount0(rcnts[0].mode);
	266	map_rcnt_rcount1(rcnts[1].mode);
	267	map_rcnt_rcount2(rcnts[2].mode);
	268	}
	269
003cfc63	270	int pcsxmem_is_handler_dynamic(unsigned int addr)
b1be1eee	271	{
	272	if ((addr & 0xfffff000) != 0x1f801000)
	273	return 0;
	274
	275	addr &= 0xffff;
	276	return addr == 0x1100 \|\| addr == 0x1110 \|\| addr == 0x1120;
	277	}
	278
7e605697	279	void new_dyna_pcsx_mem_init(void)
	280	{
	281	int i;
63cb0298	282
679d5ee3	283	memset(ffff_mem, 0xff, sizeof(ffff_mem));
679d5ee3	284
c6c3b1b3	285	// have to map these further to keep tcache close to .text
be516ebe	286	mem_readtab = psxMap(0x08000000, 0x200000 * sizeof(mem_readtab[0]), 0, MAP_TAG_LUTS);
87e5b45f	287	if (mem_readtab == NULL) {
f29fbd53	288	SysPrintf("failed to map mem tables\n");
c6c3b1b3	289	exit(1);
	290	}
	291	mem_writetab = mem_readtab + 0x100000;
	292
	293	// 1st level lookup:
	294	// 0: direct mem
	295	// 1: use 2nd lookup
	296	// 2nd level lookup:
	297	// 0: direct mem variable
	298	// 1: memhandler
	299
	300	// default/unmapped memhandlers
	301	for (i = 0; i < 0x100000; i++) {
	302	//map_item(&mem_readtab[i], mem_unmrtab, 1);
679d5ee3	303	map_l1_mem(mem_readtab, i, 0, 0x1000, ffff_mem);
c6c3b1b3	304	map_item(&mem_writetab[i], mem_unmwtab, 1);
	305	}
	306
	307	// RAM and it's mirrors
	308	for (i = 0; i < (0x800000 >> 12); i++) {
	309	map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM);
c6c3b1b3	310	map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM);
c6c3b1b3	311	map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM);
c6c3b1b3	312	}
679d5ee3	313	new_dyna_pcsx_mem_isolate(0);
c6c3b1b3	314
	315	// BIOS and it's mirrors
	316	for (i = 0; i < (0x80000 >> 12); i++) {
	317	map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
	318	map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
	319	}
	320
	321	// scratchpad
	322	map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
9dd7d179	323	map_l1_mem(mem_readtab, 0, 0x9f800000, 0x1000, psxH);
c6c3b1b3	324	map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
9dd7d179	325	map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH);
c6c3b1b3	326
c6c3b1b3	327	// I/O
679d5ee3	328	map_item(&mem_readtab[0x1f801000u >> 12], mem_iortab, 1);
	329	map_item(&mem_readtab[0x9f801000u >> 12], mem_iortab, 1);
	330	map_item(&mem_readtab[0xbf801000u >> 12], mem_iortab, 1);
	331	map_item(&mem_writetab[0x1f801000u >> 12], mem_iowtab, 1);
	332	map_item(&mem_writetab[0x9f801000u >> 12], mem_iowtab, 1);
	333	map_item(&mem_writetab[0xbf801000u >> 12], mem_iowtab, 1);
7e605697	334
c6c3b1b3	335	// L2
c6c3b1b3	336	// unmapped tables
b96d3df7	337	for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
c6c3b1b3	338	map_item(&mem_unmwtab[i], write_mem_dummy, 1);
	339
	340	// fill IO tables
	341	for (i = 0; i < 0x1000/4; i++) {
	342	map_item(&mem_iortab[i], &psxH[0x1000], 0);
	343	map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	344	}
	345	for (; i < 0x1000/4 + 0x1000/2; i++) {
	346	map_item(&mem_iortab[i], &psxH[0x1000], 0);
	347	map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	348	}
	349	for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
	350	map_item(&mem_iortab[i], &psxH[0x1000], 0);
	351	map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	352	}
	353
	354	map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
11d23573	355	map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1);
c6c3b1b3	356	map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
c6c3b1b3	357	map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
11d23573	358	map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1);
c6c3b1b3	359	map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
c6c3b1b3	360	map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
11d23573	361	map_item(&mem_iortab[IOMEM32(0x1120)], psxRcntRcount2, 1);
c6c3b1b3	362	map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
	363	map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
	364	// map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
ddbaf678	365	map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1);
c6c3b1b3	366	map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
	367	map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
	368
	369	map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
	370	map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
	371	map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
	372	map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
	373	map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
11d23573	374	map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1);
c6c3b1b3	375	map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
c6c3b1b3	376	map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
11d23573	377	map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1);
c6c3b1b3	378	map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
c6c3b1b3	379	map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
11d23573	380	map_item(&mem_iortab[IOMEM16(0x1120)], psxRcntRcount2, 1);
c6c3b1b3	381	map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
	382	map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);
	383
	384	map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
	385	map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
	386	map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
	387	map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
	388	map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
	389
b96d3df7	390	// write(u32 data)
b96d3df7	391	map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
a01b90c3	392	map_item(&mem_iowtab[IOMEM32(0x1070)], psxHwWriteIstat, 1);
a01b90c3	393	map_item(&mem_iowtab[IOMEM32(0x1074)], psxHwWriteImask, 1);
b96d3df7	394	map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
	395	map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
	396	map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
	397	map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
	398	map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
	399	map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
a01b90c3	400	map_item(&mem_iowtab[IOMEM32(0x10f4)], psxHwWriteDmaIcr32, 1);
b96d3df7	401	map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
	402	map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
	403	map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
	404	map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
	405	map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
	406	map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
	407	map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
	408	map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
	409	map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
	410	// map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
ddbaf678	411	map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1);
b96d3df7	412	map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
	413	map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
	414
	415	map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
	416	map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
	417	map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
	418	map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
	419	map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
a01b90c3	420	map_item(&mem_iowtab[IOMEM16(0x1070)], psxHwWriteIstat, 1);
a01b90c3	421	map_item(&mem_iowtab[IOMEM16(0x1074)], psxHwWriteImask, 1);
b96d3df7	422	map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
	423	map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
	424	map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
	425	map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
	426	map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
	427	map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
	428	map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
	429	map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
	430	map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);
	431
	432	map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
	433	map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
	434	map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
	435	map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
	436	map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);
	437
906b1599	438	for (i = 0x1c00; i < 0x2000; i += 2) {
b96d3df7	439	map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
	440	map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
	441	}
	442
	443	// misc
679d5ee3	444	map_item(&mem_readtab[0xfffe0130u >> 12], mem_ffrtab, 1);
	445	map_item(&mem_writetab[0xfffe0130u >> 12], mem_ffwtab, 1);
	446	for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
	447	map_item(&mem_ffrtab[i], read_biu, 1);
b96d3df7	448	map_item(&mem_ffwtab[i], write_biu, 1);
679d5ee3	449	}
b96d3df7	450
c6c3b1b3	451	mem_rtab = mem_readtab;
c6c3b1b3	452	mem_wtab = mem_writetab;
b1be1eee	453
b1be1eee	454	new_dyna_pcsx_mem_load_state();
7e605697	455	}
	456
	457	void new_dyna_pcsx_mem_reset(void)
	458	{
c6c3b1b3	459	int i;
c6c3b1b3	460
7e605697	461	// plugins might change so update the pointers
c6c3b1b3	462	map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
c6c3b1b3	463
906b1599	464	for (i = 0x1c00; i < 0x2000; i += 2)
c6c3b1b3	465	map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);
c6c3b1b3	466
b96d3df7	467	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
7e605697	468	}
92879b62	469
	470	void new_dyna_pcsx_mem_shutdown(void)
	471	{
ed7afeef	472	psxUnmap(mem_readtab, 0x200000 * sizeof(mem_readtab[0]), MAP_TAG_LUTS);
92879b62	473	mem_writetab = mem_readtab = NULL;
92879b62	474	}