[pcsx_rearmed.git] / libpcsxcore / psxcounters.c

/***************************************************************************
 *   Copyright (C) 2010 by Blade_Arma                                      *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
 ***************************************************************************/

/*
 * Internal PSX counters.
 */

#include "psxcounters.h"
#include "gpu.h"
//#include "debug.h"
#define DebugVSync()

/******************************************************************************/

enum
{
    RcSyncModeEnable  = 0x0001, // 0
    Rc01BlankPause    = 0 << 1, // 1,2
    Rc01UnblankReset  = 1 << 1, // 1,2
    Rc01UnblankReset2 = 2 << 1, // 1,2
    Rc2Stop           = 0 << 1, // 1,2
    Rc2Stop2          = 3 << 1, // 1,2
    RcCountToTarget   = 0x0008, // 3
    RcIrqOnTarget     = 0x0010, // 4
    RcIrqOnOverflow   = 0x0020, // 5
    RcIrqRegenerate   = 0x0040, // 6
    RcUnknown7        = 0x0080, // 7    ?
    Rc0PixelClock     = 0x0100, // 8    fake implementation
    Rc1HSyncClock     = 0x0100, // 8
    Rc2Unknown8       = 0x0100, // 8    ?
    Rc0Unknown9       = 0x0200, // 9    ?
    Rc1Unknown9       = 0x0200, // 9    ?
    Rc2OneEighthClock = 0x0200, // 9
    RcUnknown10       = 0x0400, // 10   ?
    RcCountEqTarget   = 0x0800, // 11
    RcOverflow        = 0x1000, // 12
    RcUnknown13       = 0x2000, // 13   ? (always zero)
    RcUnknown14       = 0x4000, // 14   ? (always zero)
    RcUnknown15       = 0x8000, // 15   ? (always zero)
};

#define CounterQuantity           ( 4 )
//static const u32 CounterQuantity  = 4;

static const u32 CountToOverflow  = 0;
static const u32 CountToTarget    = 1;

static const u32 HSyncTotal[]     = { 263, 314 };
#define VBlankStart 240 // todo: depend on the actual GPU setting

#define VERBOSE_LEVEL 0

/******************************************************************************/
#ifdef DRC_DISABLE
Rcnt rcnts[ CounterQuantity ];
#endif
u32 hSyncCount = 0;
u32 frame_counter = 0;
static u32 hsync_steps = 0;

u32 psxNextCounter = 0, psxNextsCounter = 0;

/******************************************************************************/

static inline
u32 lineCycles(void)
{
    if (Config.PsxType)
        return PSXCLK / 50 / HSyncTotal[1];
    else
        return PSXCLK / 60 / HSyncTotal[0];
}

static inline
void setIrq( u32 irq )
{
    psxHu32ref(0x1070) |= SWAPu32(irq);
}

static
void verboseLog( u32 level, const char *str, ... )
{
#if VERBOSE_LEVEL > 0
    if( level <= VERBOSE_LEVEL )
    {
        va_list va;
        char buf[ 4096 ];

        va_start( va, str );
        vsprintf( buf, str, va );
        va_end( va );

        printf( "%s", buf );
        fflush( stdout );
    }
#endif
}

/******************************************************************************/

static inline
void _psxRcntWcount( u32 index, u32 value )
{
    if( value > 0xffff )
    {
        verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
        value &= 0xffff;
    }

    rcnts[index].cycleStart  = psxRegs.cycle;
    rcnts[index].cycleStart -= value * rcnts[index].rate;

    // TODO: <=.
    if( value < rcnts[index].target )
    {
        rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
        rcnts[index].counterState = CountToTarget;
    }
    else
    {
        rcnts[index].cycle = 0x10000 * rcnts[index].rate;
        rcnts[index].counterState = CountToOverflow;
    }
}

static inline
u32 _psxRcntRcount( u32 index )
{
    u32 count;

    count  = psxRegs.cycle;
    count -= rcnts[index].cycleStart;
    if (rcnts[index].rate > 1)
        count /= rcnts[index].rate;

    if( count > 0x10000 )
    {
        verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
    }
    count &= 0xffff;

    return count;
}

static
void _psxRcntWmode( u32 index, u32 value )
{
    rcnts[index].mode = value;

    switch( index )
    {
        case 0:
            if( value & Rc0PixelClock )
            {
                rcnts[index].rate = 5;
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 1:
            if( value & Rc1HSyncClock )
            {
                rcnts[index].rate = lineCycles();
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 2:
            if( value & Rc2OneEighthClock )
            {
                rcnts[index].rate = 8;
            }
            else
            {
                rcnts[index].rate = 1;
            }

            // TODO: wcount must work.
            if( (value & 7) == (RcSyncModeEnable | Rc2Stop) ||
                (value & 7) == (RcSyncModeEnable | Rc2Stop2) )
            {
                rcnts[index].rate = 0xffffffff;
            }
        break;
    }
}

/******************************************************************************/

static
void psxRcntSet()
{
    s32 countToUpdate;
    u32 i;

    psxNextsCounter = psxRegs.cycle;
    psxNextCounter  = 0x7fffffff;

    for( i = 0; i < CounterQuantity; ++i )
    {
        countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);

        if( countToUpdate < 0 )
        {
            psxNextCounter = 0;
            break;
        }

        if( countToUpdate < (s32)psxNextCounter )
        {
            psxNextCounter = countToUpdate;
        }
    }

    psxRegs.interrupt |= (1 << PSXINT_RCNT);
    new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
}

/******************************************************************************/

static
void psxRcntReset( u32 index )
{
    u32 rcycles;

    rcnts[index].mode |= RcUnknown10;

    if( rcnts[index].counterState == CountToTarget )
    {
        rcycles = psxRegs.cycle - rcnts[index].cycleStart;
        if( rcnts[index].mode & RcCountToTarget )
        {
            rcycles -= rcnts[index].target * rcnts[index].rate;
            rcnts[index].cycleStart = psxRegs.cycle - rcycles;
        }
        else
        {
            rcnts[index].cycle = 0x10000 * rcnts[index].rate;
            rcnts[index].counterState = CountToOverflow;
        }

        if( rcnts[index].mode & RcIrqOnTarget )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq\n", index );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcCountEqTarget;

        if( rcycles < 0x10000 * rcnts[index].rate )
            return;
    }

    if( rcnts[index].counterState == CountToOverflow )
    {
        rcycles = psxRegs.cycle - rcnts[index].cycleStart;
        rcycles -= 0x10000 * rcnts[index].rate;

        rcnts[index].cycleStart = psxRegs.cycle - rcycles;

        if( rcycles < rcnts[index].target * rcnts[index].rate )
        {
            rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
            rcnts[index].counterState = CountToTarget;
        }

        if( rcnts[index].mode & RcIrqOnOverflow )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq\n", index );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcOverflow;
    }
}

static void scheduleRcntBase(void)
{
    // Schedule next call, in hsyncs
    if (hSyncCount < VBlankStart)
        hsync_steps = VBlankStart - hSyncCount;
    else
        hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount;

    if (hSyncCount + hsync_steps == HSyncTotal[Config.PsxType])
    {
        rcnts[3].cycle = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
    }
    else
    {
        // clk / 50 / 314 ~= 2157.25
        // clk / 60 / 263 ~= 2146.31
        u32 mult = Config.PsxType ? 8836089 : 8791293;
        rcnts[3].cycle = hsync_steps * mult >> 12;
    }
}

void psxRcntUpdate()
{
    u32 cycle, cycles_passed;

    cycle = psxRegs.cycle;

    // rcnt 0.
    cycles_passed = cycle - rcnts[0].cycleStart;
    while( cycles_passed >= rcnts[0].cycle )
    {
        if (((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
             (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
            && cycles_passed > lineCycles())
        {
            u32 q = cycles_passed / (lineCycles() + 1u);
            rcnts[0].cycleStart += q * lineCycles();
            break;
        }
        else
            psxRcntReset( 0 );

        cycles_passed = cycle - rcnts[0].cycleStart;
    }

    // rcnt 1.
    while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
    {
        psxRcntReset( 1 );
    }

    // rcnt 2.
    while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
    {
        psxRcntReset( 2 );
    }

    // rcnt base.
    if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
    {
        hSyncCount += hsync_steps;

        // VSync irq.
        if( hSyncCount == VBlankStart )
        {
            HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF);
            GPU_vBlank( 1, 0 );
            setIrq( 0x01 );

            EmuUpdate();
            GPU_updateLace();

            if( SPU_async )
            {
                SPU_async( cycle, 1 );
            }
        }
        
        // Update lace.
        if( hSyncCount >= HSyncTotal[Config.PsxType] )
        {
            u32 status, field = 0;
            rcnts[3].cycleStart += Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
            hSyncCount = 0;
            frame_counter++;

            gpuSyncPluginSR();
            status = SWAP32(HW_GPU_STATUS) | PSXGPU_FIELD;
            if ((status & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS) {
                field = frame_counter & 1;
                status |= field << 31;
                status ^= field << 13;
            }
            HW_GPU_STATUS = SWAP32(status);
            GPU_vBlank(0, field);

            if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
                (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
            {
                rcnts[0].cycleStart = rcnts[3].cycleStart;
            }

            if ((rcnts[1].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
                (rcnts[1].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
            {
                rcnts[1].cycleStart = rcnts[3].cycleStart;
            }
            else if (rcnts[1].mode & Rc1HSyncClock)
            {
                // adjust to remove the rounding error
                _psxRcntWcount(1, (psxRegs.cycle - rcnts[1].cycleStart) / rcnts[1].rate);
            }
        }

        scheduleRcntBase();
    }

    psxRcntSet();

#if 0 //ndef NDEBUG
    DebugVSync();
#endif
}

/******************************************************************************/

void psxRcntWcount( u32 index, u32 value )
{
    verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );

    _psxRcntWcount( index, value );
    psxRcntSet();
}

void psxRcntWmode( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );

    _psxRcntWmode( index, value );
    _psxRcntWcount( index, 0 );

    rcnts[index].irqState = 0;
    psxRcntSet();
}

void psxRcntWtarget( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );

    rcnts[index].target = value;

    _psxRcntWcount( index, _psxRcntRcount( index ) );
    psxRcntSet();
}

/******************************************************************************/

u32 psxRcntRcount0()
{
    u32 index = 0;
    u32 count;

    if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
        (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
    {
        count = psxRegs.cycle - rcnts[index].cycleStart;
        //count = ((16u * count) % (16u * PSXCLK / 60 / 263)) / 16u;
        count = count % lineCycles();
        rcnts[index].cycleStart = psxRegs.cycle - count;
    }
    else
        count = _psxRcntRcount( index );

    verboseLog( 2, "[RCNT 0] rcount: %04x m: %04x\n", count, rcnts[index].mode);

    return count;
}

u32 psxRcntRcount1()
{
    u32 index = 1;
    u32 count;

    count = _psxRcntRcount( index );

    verboseLog( 2, "[RCNT 1] rcount: %04x m: %04x\n", count, rcnts[index].mode);

    return count;
}

u32 psxRcntRcount2()
{
    u32 index = 2;
    u32 count;

    count = _psxRcntRcount( index );

    verboseLog( 2, "[RCNT 2] rcount: %04x m: %04x\n", count, rcnts[index].mode);

    return count;
}

u32 psxRcntRmode( u32 index )
{
    u16 mode;

    mode = rcnts[index].mode;
    rcnts[index].mode &= 0xe7ff;

    verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );

    return mode;
}

u32 psxRcntRtarget( u32 index )
{
    verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );

    return rcnts[index].target;
}

/******************************************************************************/

void psxRcntInit()
{
    s32 i;

    // rcnt 0.
    rcnts[0].rate   = 1;
    rcnts[0].irq    = 0x10;

    // rcnt 1.
    rcnts[1].rate   = 1;
    rcnts[1].irq    = 0x20;

    // rcnt 2.
    rcnts[2].rate   = 1;
    rcnts[2].irq    = 0x40;

    // rcnt base.
    rcnts[3].rate   = 1;

    for( i = 0; i < CounterQuantity; ++i )
    {
        _psxRcntWcount( i, 0 );
    }

    hSyncCount = 0;
    hsync_steps = 1;

    scheduleRcntBase();
    psxRcntSet();
}

/******************************************************************************/

s32 psxRcntFreeze( void *f, s32 Mode )
{
    u32 spuSyncCount = 0;
    u32 count;
    s32 i;

    gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity );
    gzfreeze( &hSyncCount, sizeof(hSyncCount) );
    gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
    gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
    gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );

    if (Mode == 0)
    {
        // don't trust things from a savestate
        rcnts[3].rate = 1;
        for( i = 0; i < CounterQuantity; ++i )
        {
            _psxRcntWmode( i, rcnts[i].mode );
            count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
            _psxRcntWcount( i, count );
        }
        scheduleRcntBase();
        psxRcntSet();
    }

    return 0;
}

/******************************************************************************/
// vim:ts=4:shiftwidth=4:expandtab
Commit	Line	Data
ef79bbde P	1	/***************************************************************************
	2	* Copyright (C) 2010 by Blade_Arma *
	3	* *
	4	* This program is free software; you can redistribute it and/or modify *
	5	* it under the terms of the GNU General Public License as published by *
	6	* the Free Software Foundation; either version 2 of the License, or *
	7	* (at your option) any later version. *
	8	* *
	9	* This program is distributed in the hope that it will be useful, *
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	12	* GNU General Public License for more details. *
	13	* *
	14	* You should have received a copy of the GNU General Public License *
	15	* along with this program; if not, write to the *
	16	* Free Software Foundation, Inc., *
	17	* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
	18	***************************************************************************/
	19
	20	/*
	21	* Internal PSX counters.
	22	*/
	23
	24	#include "psxcounters.h"
ddbaf678	25	#include "gpu.h"
7d7672a5	26	//#include "debug.h"
7d7672a5	27	#define DebugVSync()
ef79bbde P	28
	29	/******************************************************************************/
	30
ef79bbde P	31	enum
ef79bbde P	32	{
11d23573	33	RcSyncModeEnable = 0x0001, // 0
	34	Rc01BlankPause = 0 << 1, // 1,2
	35	Rc01UnblankReset = 1 << 1, // 1,2
	36	Rc01UnblankReset2 = 2 << 1, // 1,2
	37	Rc2Stop = 0 << 1, // 1,2
	38	Rc2Stop2 = 3 << 1, // 1,2
ef79bbde P	39	RcCountToTarget = 0x0008, // 3
	40	RcIrqOnTarget = 0x0010, // 4
	41	RcIrqOnOverflow = 0x0020, // 5
	42	RcIrqRegenerate = 0x0040, // 6
	43	RcUnknown7 = 0x0080, // 7 ?
	44	Rc0PixelClock = 0x0100, // 8 fake implementation
	45	Rc1HSyncClock = 0x0100, // 8
	46	Rc2Unknown8 = 0x0100, // 8 ?
	47	Rc0Unknown9 = 0x0200, // 9 ?
	48	Rc1Unknown9 = 0x0200, // 9 ?
	49	Rc2OneEighthClock = 0x0200, // 9
	50	RcUnknown10 = 0x0400, // 10 ?
	51	RcCountEqTarget = 0x0800, // 11
	52	RcOverflow = 0x1000, // 12
	53	RcUnknown13 = 0x2000, // 13 ? (always zero)
	54	RcUnknown14 = 0x4000, // 14 ? (always zero)
	55	RcUnknown15 = 0x8000, // 15 ? (always zero)
	56	};
	57
	58	#define CounterQuantity ( 4 )
	59	//static const u32 CounterQuantity = 4;
	60
	61	static const u32 CountToOverflow = 0;
	62	static const u32 CountToTarget = 1;
	63
1351a8fb	64	static const u32 HSyncTotal[] = { 263, 314 };
1351a8fb	65	#define VBlankStart 240 // todo: depend on the actual GPU setting
ef79bbde	66
9f7ee52e	67	#define VERBOSE_LEVEL 0
ef79bbde P	68
ef79bbde P	69	/******************************************************************************/
41e82ad4	70	#ifdef DRC_DISABLE
b1be1eee	71	Rcnt rcnts[ CounterQuantity ];
41e82ad4	72	#endif
24de2dd4	73	u32 hSyncCount = 0;
24de2dd4	74	u32 frame_counter = 0;
61ef5cf4	75	static u32 hsync_steps = 0;
ef79bbde P	76
	77	u32 psxNextCounter = 0, psxNextsCounter = 0;
	78
	79	/******************************************************************************/
	80
1351a8fb	81	static inline
	82	u32 lineCycles(void)
	83	{
	84	if (Config.PsxType)
	85	return PSXCLK / 50 / HSyncTotal[1];
	86	else
	87	return PSXCLK / 60 / HSyncTotal[0];
	88	}
	89
ef79bbde P	90	static inline
	91	void setIrq( u32 irq )
	92	{
	93	psxHu32ref(0x1070) \|= SWAPu32(irq);
	94	}
	95
	96	static
9f7ee52e	97	void verboseLog( u32 level, const char *str, ... )
ef79bbde	98	{
9f7ee52e	99	#if VERBOSE_LEVEL > 0
3cf51e08	100	if( level <= VERBOSE_LEVEL )
ef79bbde P	101	{
	102	va_list va;
	103	char buf[ 4096 ];
	104
	105	va_start( va, str );
	106	vsprintf( buf, str, va );
	107	va_end( va );
	108
ab948f7e	109	printf( "%s", buf );
ef79bbde P	110	fflush( stdout );
ef79bbde P	111	}
9f7ee52e	112	#endif
ef79bbde P	113	}
	114
	115	/******************************************************************************/
	116
	117	static inline
	118	void _psxRcntWcount( u32 index, u32 value )
	119	{
	120	if( value > 0xffff )
	121	{
	122	verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
	123	value &= 0xffff;
	124	}
	125
	126	rcnts[index].cycleStart = psxRegs.cycle;
	127	rcnts[index].cycleStart -= value * rcnts[index].rate;
	128
	129	// TODO: <=.
	130	if( value < rcnts[index].target )
	131	{
	132	rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
	133	rcnts[index].counterState = CountToTarget;
	134	}
	135	else
	136	{
8ca6b0a6	137	rcnts[index].cycle = 0x10000 * rcnts[index].rate;
ef79bbde P	138	rcnts[index].counterState = CountToOverflow;
	139	}
	140	}
	141
	142	static inline
	143	u32 _psxRcntRcount( u32 index )
	144	{
	145	u32 count;
	146
	147	count = psxRegs.cycle;
	148	count -= rcnts[index].cycleStart;
61ef5cf4	149	if (rcnts[index].rate > 1)
61ef5cf4	150	count /= rcnts[index].rate;
ef79bbde	151
8ca6b0a6	152	if( count > 0x10000 )
ef79bbde	153	{
8ca6b0a6	154	verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
ef79bbde	155	}
8ca6b0a6	156	count &= 0xffff;
ef79bbde P	157
	158	return count;
	159	}
	160
a29f182f	161	static
	162	void _psxRcntWmode( u32 index, u32 value )
	163	{
	164	rcnts[index].mode = value;
	165
	166	switch( index )
	167	{
	168	case 0:
	169	if( value & Rc0PixelClock )
	170	{
	171	rcnts[index].rate = 5;
	172	}
	173	else
	174	{
	175	rcnts[index].rate = 1;
	176	}
	177	break;
	178	case 1:
	179	if( value & Rc1HSyncClock )
	180	{
1351a8fb	181	rcnts[index].rate = lineCycles();
a29f182f	182	}
	183	else
	184	{
	185	rcnts[index].rate = 1;
	186	}
	187	break;
	188	case 2:
	189	if( value & Rc2OneEighthClock )
	190	{
	191	rcnts[index].rate = 8;
	192	}
	193	else
	194	{
	195	rcnts[index].rate = 1;
	196	}
	197
	198	// TODO: wcount must work.
11d23573	199	if( (value & 7) == (RcSyncModeEnable \| Rc2Stop) \|\|
11d23573	200	(value & 7) == (RcSyncModeEnable \| Rc2Stop2) )
a29f182f	201	{
	202	rcnts[index].rate = 0xffffffff;
	203	}
	204	break;
	205	}
	206	}
	207
ef79bbde P	208	/******************************************************************************/
	209
	210	static
	211	void psxRcntSet()
	212	{
	213	s32 countToUpdate;
	214	u32 i;
	215
	216	psxNextsCounter = psxRegs.cycle;
	217	psxNextCounter = 0x7fffffff;
	218
	219	for( i = 0; i < CounterQuantity; ++i )
	220	{
	221	countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
	222
	223	if( countToUpdate < 0 )
	224	{
	225	psxNextCounter = 0;
	226	break;
	227	}
	228
	229	if( countToUpdate < (s32)psxNextCounter )
	230	{
	231	psxNextCounter = countToUpdate;
	232	}
	233	}
5b8c000f	234
	235	psxRegs.interrupt \|= (1 << PSXINT_RCNT);
	236	new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
ef79bbde P	237	}
	238
	239	/******************************************************************************/
	240
	241	static
	242	void psxRcntReset( u32 index )
	243	{
8ca6b0a6	244	u32 rcycles;
ef79bbde	245
53c361f0	246	rcnts[index].mode \|= RcUnknown10;
53c361f0	247
ef79bbde P	248	if( rcnts[index].counterState == CountToTarget )
ef79bbde P	249	{
8ca6b0a6	250	rcycles = psxRegs.cycle - rcnts[index].cycleStart;
ef79bbde	251	if( rcnts[index].mode & RcCountToTarget )
8ca6b0a6	252	{
	253	rcycles -= rcnts[index].target * rcnts[index].rate;
	254	rcnts[index].cycleStart = psxRegs.cycle - rcycles;
	255	}
	256	else
	257	{
	258	rcnts[index].cycle = 0x10000 * rcnts[index].rate;
	259	rcnts[index].counterState = CountToOverflow;
	260	}
ef79bbde P	261
	262	if( rcnts[index].mode & RcIrqOnTarget )
	263	{
	264	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
	265	{
8ca6b0a6	266	verboseLog( 3, "[RCNT %i] irq\n", index );
ef79bbde P	267	setIrq( rcnts[index].irq );
	268	rcnts[index].irqState = 1;
	269	}
	270	}
	271
	272	rcnts[index].mode \|= RcCountEqTarget;
53c361f0	273
8ca6b0a6	274	if( rcycles < 0x10000 * rcnts[index].rate )
53c361f0	275	return;
ef79bbde	276	}
53c361f0	277
53c361f0	278	if( rcnts[index].counterState == CountToOverflow )
ef79bbde	279	{
8ca6b0a6	280	rcycles = psxRegs.cycle - rcnts[index].cycleStart;
	281	rcycles -= 0x10000 * rcnts[index].rate;
	282
	283	rcnts[index].cycleStart = psxRegs.cycle - rcycles;
ef79bbde	284
8ca6b0a6	285	if( rcycles < rcnts[index].target * rcnts[index].rate )
	286	{
	287	rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
	288	rcnts[index].counterState = CountToTarget;
	289	}
ef79bbde P	290
	291	if( rcnts[index].mode & RcIrqOnOverflow )
	292	{
	293	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
	294	{
8ca6b0a6	295	verboseLog( 3, "[RCNT %i] irq\n", index );
ef79bbde P	296	setIrq( rcnts[index].irq );
	297	rcnts[index].irqState = 1;
	298	}
	299	}
	300
	301	rcnts[index].mode \|= RcOverflow;
	302	}
ef79bbde P	303	}
ef79bbde P	304
ff2c2822	305	static void scheduleRcntBase(void)
	306	{
	307	// Schedule next call, in hsyncs
	308	if (hSyncCount < VBlankStart)
	309	hsync_steps = VBlankStart - hSyncCount;
	310	else
	311	hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount;
	312
	313	if (hSyncCount + hsync_steps == HSyncTotal[Config.PsxType])
	314	{
	315	rcnts[3].cycle = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
	316	}
	317	else
	318	{
	319	// clk / 50 / 314 ~= 2157.25
	320	// clk / 60 / 263 ~= 2146.31
	321	u32 mult = Config.PsxType ? 8836089 : 8791293;
	322	rcnts[3].cycle = hsync_steps * mult >> 12;
	323	}
	324	}
	325
ef79bbde P	326	void psxRcntUpdate()
ef79bbde P	327	{
11d23573	328	u32 cycle, cycles_passed;
ef79bbde P	329
	330	cycle = psxRegs.cycle;
	331
	332	// rcnt 0.
11d23573	333	cycles_passed = cycle - rcnts[0].cycleStart;
11d23573	334	while( cycles_passed >= rcnts[0].cycle )
ef79bbde	335	{
11d23573	336	if (((rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset) \|\|
11d23573	337	(rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset2))
1351a8fb	338	&& cycles_passed > lineCycles())
11d23573	339	{
1351a8fb	340	u32 q = cycles_passed / (lineCycles() + 1u);
1351a8fb	341	rcnts[0].cycleStart += q * lineCycles();
11d23573	342	break;
	343	}
	344	else
	345	psxRcntReset( 0 );
	346
	347	cycles_passed = cycle - rcnts[0].cycleStart;
ef79bbde P	348	}
	349
	350	// rcnt 1.
e7851504	351	while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
ef79bbde P	352	{
	353	psxRcntReset( 1 );
	354	}
	355
	356	// rcnt 2.
e7851504	357	while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
ef79bbde P	358	{
	359	psxRcntReset( 2 );
	360	}
	361
	362	// rcnt base.
	363	if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
	364	{
61ef5cf4	365	hSyncCount += hsync_steps;
ef79bbde	366
ef79bbde	367	// VSync irq.
0486fdc9	368	if( hSyncCount == VBlankStart )
ef79bbde	369	{
086adfff	370	HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF);
72e5023f	371	GPU_vBlank( 1, 0 );
8bbbd091	372	setIrq( 0x01 );
	373
	374	EmuUpdate();
	375	GPU_updateLace();
d618a240	376
	377	if( SPU_async )
	378	{
	379	SPU_async( cycle, 1 );
	380	}
ef79bbde P	381	}
ef79bbde P	382
d014a471	383	// Update lace.
d014a471	384	if( hSyncCount >= HSyncTotal[Config.PsxType] )
ef79bbde	385	{
1351a8fb	386	u32 status, field = 0;
ff2c2822	387	rcnts[3].cycleStart += Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
ef79bbde	388	hSyncCount = 0;
ddbaf678	389	frame_counter++;
ef79bbde	390
0486fdc9	391	gpuSyncPluginSR();
db57cbb8	392	status = SWAP32(HW_GPU_STATUS) \| PSXGPU_FIELD;
	393	if ((status & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS) {
	394	field = frame_counter & 1;
	395	status \|= field << 31;
	396	status ^= field << 13;
	397	}
	398	HW_GPU_STATUS = SWAP32(status);
	399	GPU_vBlank(0, field);
11d23573	400
1351a8fb	401	if ((rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset) \|\|
	402	(rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset2))
	403	{
	404	rcnts[0].cycleStart = rcnts[3].cycleStart;
	405	}
	406
	407	if ((rcnts[1].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset) \|\|
	408	(rcnts[1].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset2))
	409	{
	410	rcnts[1].cycleStart = rcnts[3].cycleStart;
	411	}
	412	else if (rcnts[1].mode & Rc1HSyncClock)
11d23573	413	{
1351a8fb	414	// adjust to remove the rounding error
1351a8fb	415	_psxRcntWcount(1, (psxRegs.cycle - rcnts[1].cycleStart) / rcnts[1].rate);
11d23573	416	}
ef79bbde	417	}
61ef5cf4	418
ff2c2822	419	scheduleRcntBase();
ef79bbde P	420	}
ef79bbde P	421
95df1a04	422	psxRcntSet();
95df1a04	423
7a8d521f	424	#if 0 //ndef NDEBUG
ef79bbde	425	DebugVSync();
61ef5cf4	426	#endif
ef79bbde P	427	}
	428
	429	/******************************************************************************/
	430
	431	void psxRcntWcount( u32 index, u32 value )
	432	{
	433	verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
	434
ef79bbde P	435	_psxRcntWcount( index, value );
	436	psxRcntSet();
	437	}
	438
	439	void psxRcntWmode( u32 index, u32 value )
	440	{
	441	verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
	442
a29f182f	443	_psxRcntWmode( index, value );
ef79bbde	444	_psxRcntWcount( index, 0 );
a29f182f	445
a29f182f	446	rcnts[index].irqState = 0;
ef79bbde P	447	psxRcntSet();
	448	}
	449
	450	void psxRcntWtarget( u32 index, u32 value )
	451	{
	452	verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
	453
ef79bbde P	454	rcnts[index].target = value;
	455
	456	_psxRcntWcount( index, _psxRcntRcount( index ) );
	457	psxRcntSet();
	458	}
	459
	460	/******************************************************************************/
	461
11d23573	462	u32 psxRcntRcount0()
	463	{
	464	u32 index = 0;
	465	u32 count;
	466
	467	if ((rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset) \|\|
	468	(rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset2))
	469	{
	470	count = psxRegs.cycle - rcnts[index].cycleStart;
1351a8fb	471	//count = ((16u * count) % (16u * PSXCLK / 60 / 263)) / 16u;
1351a8fb	472	count = count % lineCycles();
11d23573	473	rcnts[index].cycleStart = psxRegs.cycle - count;
	474	}
	475	else
	476	count = _psxRcntRcount( index );
	477
	478	verboseLog( 2, "[RCNT 0] rcount: %04x m: %04x\n", count, rcnts[index].mode);
	479
	480	return count;
	481	}
	482
	483	u32 psxRcntRcount1()
	484	{
	485	u32 index = 1;
	486	u32 count;
	487
	488	count = _psxRcntRcount( index );
	489
	490	verboseLog( 2, "[RCNT 1] rcount: %04x m: %04x\n", count, rcnts[index].mode);
	491
	492	return count;
	493	}
	494
	495	u32 psxRcntRcount2()
ef79bbde	496	{
11d23573	497	u32 index = 2;
ef79bbde P	498	u32 count;
ef79bbde P	499
ef79bbde P	500	count = _psxRcntRcount( index );
ef79bbde P	501
11d23573	502	verboseLog( 2, "[RCNT 2] rcount: %04x m: %04x\n", count, rcnts[index].mode);
ef79bbde P	503
	504	return count;
	505	}
	506
	507	u32 psxRcntRmode( u32 index )
	508	{
	509	u16 mode;
	510
ef79bbde P	511	mode = rcnts[index].mode;
	512	rcnts[index].mode &= 0xe7ff;
	513
	514	verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
	515
	516	return mode;
	517	}
	518
	519	u32 psxRcntRtarget( u32 index )
	520	{
	521	verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
	522
	523	return rcnts[index].target;
	524	}
	525
	526	/******************************************************************************/
	527
	528	void psxRcntInit()
	529	{
	530	s32 i;
	531
	532	// rcnt 0.
	533	rcnts[0].rate = 1;
	534	rcnts[0].irq = 0x10;
	535
	536	// rcnt 1.
	537	rcnts[1].rate = 1;
	538	rcnts[1].irq = 0x20;
	539
	540	// rcnt 2.
	541	rcnts[2].rate = 1;
	542	rcnts[2].irq = 0x40;
	543
	544	// rcnt base.
	545	rcnts[3].rate = 1;
ef79bbde P	546
	547	for( i = 0; i < CounterQuantity; ++i )
	548	{
	549	_psxRcntWcount( i, 0 );
	550	}
	551
c62b43c9	552	hSyncCount = 0;
61ef5cf4	553	hsync_steps = 1;
c62b43c9	554
1351a8fb	555	scheduleRcntBase();
ef79bbde P	556	psxRcntSet();
	557	}
	558
	559	/******************************************************************************/
	560
496d88d4	561	s32 psxRcntFreeze( void *f, s32 Mode )
ef79bbde	562	{
d618a240	563	u32 spuSyncCount = 0;
a29f182f	564	u32 count;
	565	s32 i;
	566
41e82ad4	567	gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity );
ef79bbde P	568	gzfreeze( &hSyncCount, sizeof(hSyncCount) );
	569	gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
	570	gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
	571	gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
	572
61ef5cf4	573	if (Mode == 0)
a29f182f	574	{
a29f182f	575	// don't trust things from a savestate
e43c9382	576	rcnts[3].rate = 1;
a29f182f	577	for( i = 0; i < CounterQuantity; ++i )
	578	{
	579	_psxRcntWmode( i, rcnts[i].mode );
	580	count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
	581	_psxRcntWcount( i, count );
	582	}
ff2c2822	583	scheduleRcntBase();
a29f182f	584	psxRcntSet();
a29f182f	585	}
4f55097d	586
ef79bbde P	587	return 0;
	588	}
	589
	590	/******************************************************************************/
ff2c2822	591	// vim:ts=4:shiftwidth=4:expandtab