[pcsx_rearmed.git] / libpcsxcore / psxdma.c

/***************************************************************************
 *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
 ***************************************************************************/

/*
* Handles PSX DMA functions.
*/

#include "psxdma.h"
#include "gpu.h"

#ifndef min
#define min(a, b) ((b) < (a) ? (b) : (a))
#endif
#ifndef PSXDMA_LOG
#define PSXDMA_LOG(...)
#endif

// Dma0/1 in Mdec.c
// Dma3   in CdRom.c

void spuInterrupt() {
	if (HW_DMA4_CHCR & SWAP32(0x01000000))
	{
		HW_DMA4_CHCR &= SWAP32(~0x01000000);
		DMA_INTERRUPT(4);
	}
}

void psxDma4(u32 madr, u32 bcr, u32 chcr) { // SPU
	u32 words, words_max = 0, words_copy;
	u16 *ptr;

	madr &= ~3;
	ptr = getDmaRam(madr, &words_max);
	if (ptr == INVALID_PTR)
		log_unhandled("bad dma4 madr %x\n", madr);

	words = words_copy = (bcr >> 16) * (bcr & 0xffff);
	if (words_copy > words_max) {
		log_unhandled("bad dma4 madr %x bcr %x\n", madr, bcr);
		words_copy = words_max;
	}

	switch (chcr) {
		case 0x01000201: //cpu to spu transfer
			PSXDMA_LOG("*** DMA4 SPU - mem2spu *** %x addr = %x size = %x\n", chcr, madr, bcr);
			if (ptr == INVALID_PTR)
				break;
			SPU_writeDMAMem(ptr, words_copy * 2, psxRegs.cycle);
			HW_DMA4_MADR = SWAPu32(madr + words_copy * 2);
			// This should be much slower, like 12+ cycles/byte, it's like
			// that because the CPU runs too fast and fifo is not emulated.
			// See also set_dma_end().
			SPUDMA_INT(words * 4);
			return;

		case 0x01000200: //spu to cpu transfer
			PSXDMA_LOG("*** DMA4 SPU - spu2mem *** %x addr = %x size = %x\n", chcr, madr, bcr);
			if (ptr == INVALID_PTR)
				break;
			SPU_readDMAMem(ptr, words_copy * 2, psxRegs.cycle);
			psxCpu->Clear(madr, words_copy);

			HW_DMA4_MADR = SWAPu32(madr + words_copy * 4);
			SPUDMA_INT(words * 4);
			return;

		default:
			log_unhandled("*** DMA4 SPU - unknown *** %x addr = %x size = %x\n", chcr, madr, bcr);
			break;
	}

	HW_DMA4_CHCR &= SWAP32(~0x01000000);
	DMA_INTERRUPT(4);
}

// Taken from PEOPS SOFTGPU
static inline boolean CheckForEndlessLoop(u32 laddr, u32 *lUsedAddr) {
	if (laddr == lUsedAddr[1]) return TRUE;
	if (laddr == lUsedAddr[2]) return TRUE;

	if (laddr < lUsedAddr[0]) lUsedAddr[1] = laddr;
	else lUsedAddr[2] = laddr;

	lUsedAddr[0] = laddr;

	return FALSE;
}

static u32 gpuDmaChainSize(u32 addr) {
	u32 size;
	u32 DMACommandCounter = 0;
	u32 lUsedAddr[3];

	lUsedAddr[0] = lUsedAddr[1] = lUsedAddr[2] = 0xffffff;

	// initial linked list ptr (word)
	size = 1;

	do {
		addr &= 0x1ffffc;

		if (DMACommandCounter++ > 2000000) break;
		if (CheckForEndlessLoop(addr, lUsedAddr)) break;

		// # 32-bit blocks to transfer
		size += psxMu8( addr + 3 );

		// next 32-bit pointer
		addr = psxMu32( addr & ~0x3 ) & 0xffffff;
		size += 1;
	} while (!(addr & 0x800000)); // contrary to some documentation, the end-of-linked-list marker is not actually 0xFF'FFFF
                                  // any pointer with bit 23 set will do.

	return size;
}

void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
	u32 *ptr, madr_next, *madr_next_p, size;
	u32 words, words_left, words_max, words_copy;
	int do_walking;

	madr &= ~3;
	switch (chcr) {
		case 0x01000200: // vram2mem
			PSXDMA_LOG("*** DMA2 GPU - vram2mem *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
			ptr = getDmaRam(madr, &words_max);
			if (ptr == INVALID_PTR) {
				log_unhandled("bad dma2 madr %x\n", madr);
				break;
			}
			// BA blocks * BS words (word = 32-bits)
			words = words_copy = (bcr >> 16) * (bcr & 0xffff);
			if (words > words_max) {
				log_unhandled("bad dma2 madr %x bcr %x\n", madr, bcr);
				words_copy = words_max;
			}
			GPU_readDataMem(ptr, words_copy);
			psxCpu->Clear(madr, words_copy);

			HW_DMA2_MADR = SWAPu32(madr + words_copy * 4);

			// careful: gpu_state_change() also messes with this
			HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
			// already 32-bit word size ((size * 4) / 4)
			GPUDMA_INT(words / 4);
			return;

		case 0x01000201: // mem2vram
			PSXDMA_LOG("*** DMA 2 - GPU mem2vram *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
			words = words_left = (bcr >> 16) * (bcr & 0xffff);
			while (words_left > 0) {
				ptr = getDmaRam(madr, &words_max);
				if (ptr == INVALID_PTR) {
					log_unhandled("bad2 dma madr %x\n", madr);
					break;
				}
				words_copy = min(words_left, words_max);
				GPU_writeDataMem(ptr, words_copy);
				words_left -= words_copy;
				madr += words_copy * 4;
			}

			HW_DMA2_MADR = SWAPu32(madr);

			// careful: gpu_state_change() also messes with this
			HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
			// already 32-bit word size ((size * 4) / 4)
			GPUDMA_INT(words / 4);
			return;

		case 0x01000401: // dma chain
			PSXDMA_LOG("*** DMA 2 - GPU dma chain *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
			// when not emulating walking progress, end immediately
			madr_next = 0xffffff;

			do_walking = Config.GpuListWalking;
			if (do_walking < 0)
				do_walking = Config.hacks.gpu_slow_list_walking;
			madr_next_p = do_walking ? &madr_next : NULL;

			size = GPU_dmaChain((u32 *)psxM, madr & 0x1fffff, madr_next_p);
			if ((int)size <= 0)
				size = gpuDmaChainSize(madr);

			HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
			HW_DMA2_MADR = SWAPu32(madr_next);

			// Tekken 3 = use 1.0 only (not 1.5x)

			// Einhander = parse linked list in pieces (todo)
			// Rebel Assault 2 = parse linked list in pieces (todo)
			GPUDMA_INT(size);
			return;

		default:
			log_unhandled("*** DMA 2 - GPU unknown *** %x addr = %x size = %x\n", chcr, madr, bcr);
			break;
	}

	HW_DMA2_CHCR &= SWAP32(~0x01000000);
	DMA_INTERRUPT(2);
}

// note: this is also (ab)used for non-dma prim command
// to delay gpu returning to idle state, see gpu_state_change()
void gpuInterrupt() {
	if (HW_DMA2_CHCR == SWAP32(0x01000401) && !(HW_DMA2_MADR & SWAP32(0x800000)))
	{
		u32 size, madr_next = 0xffffff;
		size = GPU_dmaChain((u32 *)psxM, HW_DMA2_MADR & 0x1fffff, &madr_next);
		HW_DMA2_MADR = SWAPu32(madr_next);
		GPUDMA_INT(size);
		return;
	}
	if (HW_DMA2_CHCR & SWAP32(0x01000000))
	{
		HW_DMA2_CHCR &= SWAP32(~0x01000000);
		DMA_INTERRUPT(2);
	}
	HW_GPU_STATUS |= SWAP32(PSXGPU_nBUSY); // GPU no longer busy
}

void psxDma6(u32 madr, u32 bcr, u32 chcr) {
	u32 words, words_max;
	u32 *mem;

	PSXDMA_LOG("*** DMA6 OT *** %x addr = %x size = %x\n", chcr, madr, bcr);

	if (chcr == 0x11000002) {
		mem = getDmaRam(madr, &words_max);
		if (mem == INVALID_PTR) {
			log_unhandled("bad6 dma madr %x\n", madr);
			HW_DMA6_CHCR &= SWAP32(~0x11000000);
			DMA_INTERRUPT(6);
			return;
		}

		// already 32-bit size
		words = bcr;

		while (bcr-- && mem > (u32 *)psxM) {
			*mem-- = SWAP32((madr - 4) & 0xffffff);
			madr -= 4;
		}
		*++mem = SWAP32(0xffffff);

		//GPUOTCDMA_INT(size);
		// halted
		psxRegs.cycle += words;
		GPUOTCDMA_INT(16);
		return;
	}
	else {
		// Unknown option
		log_unhandled("*** DMA6 OT - unknown *** %x addr = %x size = %x\n", chcr, madr, bcr);
	}

	HW_DMA6_CHCR &= SWAP32(~0x11000000);
	DMA_INTERRUPT(6);
}

void gpuotcInterrupt()
{
	if (HW_DMA6_CHCR & SWAP32(0x01000000))
	{
		HW_DMA6_CHCR &= SWAP32(~0x11000000);
		DMA_INTERRUPT(6);
	}
}
Commit	Line	Data
ef79bbde P	1	/***************************************************************************
	2	* Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
	3	* *
	4	* This program is free software; you can redistribute it and/or modify *
	5	* it under the terms of the GNU General Public License as published by *
	6	* the Free Software Foundation; either version 2 of the License, or *
	7	* (at your option) any later version. *
	8	* *
	9	* This program is distributed in the hope that it will be useful, *
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	12	* GNU General Public License for more details. *
	13	* *
	14	* You should have received a copy of the GNU General Public License *
	15	* along with this program; if not, write to the *
	16	* Free Software Foundation, Inc., *
	17	* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
	18	***************************************************************************/
	19
	20	/*
	21	* Handles PSX DMA functions.
	22	*/
	23
	24	#include "psxdma.h"
6c036261	25	#include "gpu.h"
ef79bbde	26
b4d5a91d	27	#ifndef min
	28	#define min(a, b) ((b) < (a) ? (b) : (a))
	29	#endif
38266cd6	30	#ifndef PSXDMA_LOG
	31	#define PSXDMA_LOG(...)
	32	#endif
b4d5a91d	33
ef79bbde P	34	// Dma0/1 in Mdec.c
	35	// Dma3 in CdRom.c
	36
	37	void spuInterrupt() {
ad418c19	38	if (HW_DMA4_CHCR & SWAP32(0x01000000))
	39	{
	40	HW_DMA4_CHCR &= SWAP32(~0x01000000);
	41	DMA_INTERRUPT(4);
	42	}
ef79bbde P	43	}
	44
	45	void psxDma4(u32 madr, u32 bcr, u32 chcr) { // SPU
38266cd6	46	u32 words, words_max = 0, words_copy;
ef79bbde	47	u16 *ptr;
ef79bbde	48
38266cd6	49	madr &= ~3;
	50	ptr = getDmaRam(madr, &words_max);
	51	if (ptr == INVALID_PTR)
	52	log_unhandled("bad dma4 madr %x\n", madr);
	53
	54	words = words_copy = (bcr >> 16) * (bcr & 0xffff);
	55	if (words_copy > words_max) {
	56	log_unhandled("bad dma4 madr %x bcr %x\n", madr, bcr);
	57	words_copy = words_max;
	58	}
	59
ef79bbde P	60	switch (chcr) {
ef79bbde P	61	case 0x01000201: //cpu to spu transfer
ef79bbde	62	PSXDMA_LOG("* DMA4 SPU - mem2spu * %x addr = %x size = %x\n", chcr, madr, bcr);
38266cd6	63	if (ptr == INVALID_PTR)
ef79bbde	64	break;
38266cd6	65	SPU_writeDMAMem(ptr, words_copy * 2, psxRegs.cycle);
38266cd6	66	HW_DMA4_MADR = SWAPu32(madr + words_copy * 2);
3c7a8977	67	// This should be much slower, like 12+ cycles/byte, it's like
	68	// that because the CPU runs too fast and fifo is not emulated.
	69	// See also set_dma_end().
4f329f16	70	SPUDMA_INT(words * 4);
ef79bbde P	71	return;
	72
	73	case 0x01000200: //spu to cpu transfer
ef79bbde	74	PSXDMA_LOG("* DMA4 SPU - spu2mem * %x addr = %x size = %x\n", chcr, madr, bcr);
38266cd6	75	if (ptr == INVALID_PTR)
ef79bbde	76	break;
38266cd6	77	SPU_readDMAMem(ptr, words_copy * 2, psxRegs.cycle);
38266cd6	78	psxCpu->Clear(madr, words_copy);
58ebb94c	79
38266cd6	80	HW_DMA4_MADR = SWAPu32(madr + words_copy * 4);
4f329f16	81	SPUDMA_INT(words * 4);
58ebb94c	82	return;
ef79bbde	83
ef79bbde	84	default:
6c9db47c	85	log_unhandled("* DMA4 SPU - unknown * %x addr = %x size = %x\n", chcr, madr, bcr);
ef79bbde	86	break;
ef79bbde P	87	}
	88
	89	HW_DMA4_CHCR &= SWAP32(~0x01000000);
	90	DMA_INTERRUPT(4);
	91	}
	92
57a757ce	93	// Taken from PEOPS SOFTGPU
	94	static inline boolean CheckForEndlessLoop(u32 laddr, u32 *lUsedAddr) {
	95	if (laddr == lUsedAddr[1]) return TRUE;
	96	if (laddr == lUsedAddr[2]) return TRUE;
	97
	98	if (laddr < lUsedAddr[0]) lUsedAddr[1] = laddr;
	99	else lUsedAddr[2] = laddr;
	100
	101	lUsedAddr[0] = laddr;
	102
	103	return FALSE;
	104	}
	105
	106	static u32 gpuDmaChainSize(u32 addr) {
	107	u32 size;
	108	u32 DMACommandCounter = 0;
	109	u32 lUsedAddr[3];
	110
	111	lUsedAddr[0] = lUsedAddr[1] = lUsedAddr[2] = 0xffffff;
	112
	113	// initial linked list ptr (word)
	114	size = 1;
	115
	116	do {
	117	addr &= 0x1ffffc;
	118
	119	if (DMACommandCounter++ > 2000000) break;
	120	if (CheckForEndlessLoop(addr, lUsedAddr)) break;
	121
	122	// # 32-bit blocks to transfer
	123	size += psxMu8( addr + 3 );
	124
	125	// next 32-bit pointer
	126	addr = psxMu32( addr & ~0x3 ) & 0xffffff;
	127	size += 1;
502ea36e	128	} while (!(addr & 0x800000)); // contrary to some documentation, the end-of-linked-list marker is not actually 0xFF'FFFF
502ea36e	129	// any pointer with bit 23 set will do.
57a757ce	130
	131	return size;
	132	}
	133
ef79bbde	134	void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
b4d5a91d	135	u32 ptr, madr_next, madr_next_p, size;
38266cd6	136	u32 words, words_left, words_max, words_copy;
8c84ba5f	137	int do_walking;
ef79bbde	138
38266cd6	139	madr &= ~3;
57a757ce	140	switch (chcr) {
ef79bbde	141	case 0x01000200: // vram2mem
57a757ce	142	PSXDMA_LOG("* DMA2 GPU - vram2mem * %lx addr = %lx size = %lx\n", chcr, madr, bcr);
b4d5a91d	143	ptr = getDmaRam(madr, &words_max);
7a8d521f	144	if (ptr == INVALID_PTR) {
38266cd6	145	log_unhandled("bad dma2 madr %x\n", madr);
ef79bbde P	146	break;
ef79bbde P	147	}
57a757ce	148	// BA blocks * BS words (word = 32-bits)
38266cd6	149	words = words_copy = (bcr >> 16) * (bcr & 0xffff);
	150	if (words > words_max) {
	151	log_unhandled("bad dma2 madr %x bcr %x\n", madr, bcr);
	152	words_copy = words_max;
	153	}
b4d5a91d	154	GPU_readDataMem(ptr, words_copy);
b4d5a91d	155	psxCpu->Clear(madr, words_copy);
58ebb94c	156
38266cd6	157	HW_DMA2_MADR = SWAPu32(madr + words_copy * 4);
57a757ce	158
abf09485	159	// careful: gpu_state_change() also messes with this
abf09485	160	HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
57a757ce	161	// already 32-bit word size ((size * 4) / 4)
58ebb94c	162	GPUDMA_INT(words / 4);
57a757ce	163	return;
ef79bbde P	164
ef79bbde P	165	case 0x01000201: // mem2vram
57a757ce	166	PSXDMA_LOG("* DMA 2 - GPU mem2vram * %lx addr = %lx size = %lx\n", chcr, madr, bcr);
38266cd6	167	words = words_left = (bcr >> 16) * (bcr & 0xffff);
	168	while (words_left > 0) {
	169	ptr = getDmaRam(madr, &words_max);
	170	if (ptr == INVALID_PTR) {
	171	log_unhandled("bad2 dma madr %x\n", madr);
	172	break;
	173	}
	174	words_copy = min(words_left, words_max);
	175	GPU_writeDataMem(ptr, words_copy);
	176	words_left -= words_copy;
	177	madr += words_copy * 4;
ef79bbde	178	}
58ebb94c	179
38266cd6	180	HW_DMA2_MADR = SWAPu32(madr);
57a757ce	181
abf09485	182	// careful: gpu_state_change() also messes with this
abf09485	183	HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
57a757ce	184	// already 32-bit word size ((size * 4) / 4)
58ebb94c	185	GPUDMA_INT(words / 4);
ef79bbde P	186	return;
	187
	188	case 0x01000401: // dma chain
57a757ce	189	PSXDMA_LOG("* DMA 2 - GPU dma chain * %lx addr = %lx size = %lx\n", chcr, madr, bcr);
8c84ba5f	190	// when not emulating walking progress, end immediately
8c84ba5f	191	madr_next = 0xffffff;
57a757ce	192
8c84ba5f	193	do_walking = Config.GpuListWalking;
	194	if (do_walking < 0)
	195	do_walking = Config.hacks.gpu_slow_list_walking;
	196	madr_next_p = do_walking ? &madr_next : NULL;
	197
	198	size = GPU_dmaChain((u32 *)psxM, madr & 0x1fffff, madr_next_p);
b03e0caf	199	if ((int)size <= 0)
b03e0caf	200	size = gpuDmaChainSize(madr);
58ebb94c	201
8c84ba5f	202	HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
8c84ba5f	203	HW_DMA2_MADR = SWAPu32(madr_next);
58ebb94c	204
57a757ce	205	// Tekken 3 = use 1.0 only (not 1.5x)
	206
	207	// Einhander = parse linked list in pieces (todo)
57a757ce	208	// Rebel Assault 2 = parse linked list in pieces (todo)
57a757ce	209	GPUDMA_INT(size);
57a757ce	210	return;
ef79bbde	211
ef79bbde	212	default:
6c9db47c	213	log_unhandled("* DMA 2 - GPU unknown * %x addr = %x size = %x\n", chcr, madr, bcr);
ef79bbde	214	break;
ef79bbde P	215	}
	216
	217	HW_DMA2_CHCR &= SWAP32(~0x01000000);
	218	DMA_INTERRUPT(2);
	219	}
	220
abf09485	221	// note: this is also (ab)used for non-dma prim command
abf09485	222	// to delay gpu returning to idle state, see gpu_state_change()
ef79bbde	223	void gpuInterrupt() {
8c84ba5f	224	if (HW_DMA2_CHCR == SWAP32(0x01000401) && !(HW_DMA2_MADR & SWAP32(0x800000)))
	225	{
	226	u32 size, madr_next = 0xffffff;
	227	size = GPU_dmaChain((u32 *)psxM, HW_DMA2_MADR & 0x1fffff, &madr_next);
	228	HW_DMA2_MADR = SWAPu32(madr_next);
	229	GPUDMA_INT(size);
	230	return;
	231	}
ad418c19	232	if (HW_DMA2_CHCR & SWAP32(0x01000000))
	233	{
	234	HW_DMA2_CHCR &= SWAP32(~0x01000000);
	235	DMA_INTERRUPT(2);
	236	}
086adfff	237	HW_GPU_STATUS \|= SWAP32(PSXGPU_nBUSY); // GPU no longer busy
ef79bbde P	238	}
	239
	240	void psxDma6(u32 madr, u32 bcr, u32 chcr) {
38266cd6	241	u32 words, words_max;
38266cd6	242	u32 *mem;
ef79bbde	243
ef79bbde	244	PSXDMA_LOG("* DMA6 OT * %x addr = %x size = %x\n", chcr, madr, bcr);
ef79bbde P	245
ef79bbde P	246	if (chcr == 0x11000002) {
38266cd6	247	mem = getDmaRam(madr, &words_max);
7a8d521f	248	if (mem == INVALID_PTR) {
38266cd6	249	log_unhandled("bad6 dma madr %x\n", madr);
206a936e	250	HW_DMA6_CHCR &= SWAP32(~0x11000000);
ef79bbde P	251	DMA_INTERRUPT(6);
	252	return;
	253	}
	254
57a757ce	255	// already 32-bit size
fc4803bd	256	words = bcr;
57a757ce	257
38266cd6	258	while (bcr-- && mem > (u32 *)psxM) {
ef79bbde P	259	*mem-- = SWAP32((madr - 4) & 0xffffff);
	260	madr -= 4;
	261	}
086adfff	262	*++mem = SWAP32(0xffffff);
57a757ce	263
fc4803bd	264	//GPUOTCDMA_INT(size);
	265	// halted
	266	psxRegs.cycle += words;
	267	GPUOTCDMA_INT(16);
57a757ce	268	return;
ef79bbde	269	}
ef79bbde P	270	else {
ef79bbde P	271	// Unknown option
6c9db47c	272	log_unhandled("* DMA6 OT - unknown * %x addr = %x size = %x\n", chcr, madr, bcr);
ef79bbde	273	}
ef79bbde	274
206a936e	275	HW_DMA6_CHCR &= SWAP32(~0x11000000);
ef79bbde P	276	DMA_INTERRUPT(6);
	277	}
	278
57a757ce	279	void gpuotcInterrupt()
57a757ce	280	{
ad418c19	281	if (HW_DMA6_CHCR & SWAP32(0x01000000))
ad418c19	282	{
206a936e	283	HW_DMA6_CHCR &= SWAP32(~0x11000000);
ad418c19	284	DMA_INTERRUPT(6);
ad418c19	285	}
57a757ce	286	}