notaz.gp2x.de / pcsx_rearmed.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
psxbios: fix wrong regs in syscall handler
[pcsx_rearmed.git] / libpcsxcore / psxinterpreter.c
CommitLineData
ef79bbde
P		 1/***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
f9ae4f29 3 * Copyright (C) 2023 notaz *
ef79bbde
P		 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
19 ***************************************************************************/
20
21/*
22 * PSX assembly interpreter.
23 */
24
25#include "psxcommon.h"
26#include "r3000a.h"
27#include "gte.h"
28#include "psxhle.h"
3968e69e 29#include "psxinterpreter.h"
4cc373dd 30#include <stddef.h>
32631e6a 31#include <assert.h>
905b7c25 32#include "../include/compiler_features.h"
33
34// these may cause issues: because of poor timing we may step
35// on instructions that real hardware would never reach
36#define DO_EXCEPTION_RESERVEDI
f9ae4f29 37#define HANDLE_LOAD_DELAY
ef79bbde 38
bc7c5acb 39static int branchSeen = 0;
ef79bbde 40
4cc373dd 41#ifdef __i386__
42#define INT_ATTR __attribute__((regparm(2)))
43#else
44#define INT_ATTR
45#endif
46#ifndef INVALID_PTR
47#define INVALID_PTR NULL
48#endif
49
ef79bbde 50// Subsets
4cc373dd 51static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code);
52static void (INT_ATTR *psxSPC[64])(psxRegisters *regs_, u32 code);
53
f9ae4f29 54// load delay
55static void doLoad(psxRegisters *regs, u32 r, u32 val)
56{
57#ifdef HANDLE_LOAD_DELAY
58 int sel = regs->dloadSel ^ 1;
59 assert(regs->dloadReg[sel] == 0);
60 regs->dloadReg[sel] = r;
61 regs->dloadVal[sel] = r ? val : 0;
62 if (regs->dloadReg[sel ^ 1] == r)
63 regs->dloadVal[sel ^ 1] = regs->dloadReg[sel ^ 1] = 0;
64#else
65 regs->GPR.r[r] = r ? val : 0;
66#endif
67}
68
69static void dloadRt(psxRegisters *regs, u32 r, u32 val)
70{
71#ifdef HANDLE_LOAD_DELAY
72 int sel = regs->dloadSel;
73 if (unlikely(regs->dloadReg[sel] == r))
74 regs->dloadVal[sel] = regs->dloadReg[sel] = 0;
75#endif
76 regs->GPR.r[r] = r ? val : 0;
77}
78
79static void dloadStep(psxRegisters *regs)
80{
81#ifdef HANDLE_LOAD_DELAY
82 int sel = regs->dloadSel;
83 regs->GPR.r[regs->dloadReg[sel]] = regs->dloadVal[sel];
84 regs->dloadVal[sel] = regs->dloadReg[sel] = 0;
85 regs->dloadSel ^= 1;
86 assert(regs->GPR.r[0] == 0);
87#endif
88}
89
90static void dloadFlush(psxRegisters *regs)
91{
92#ifdef HANDLE_LOAD_DELAY
93 regs->GPR.r[regs->dloadReg[0]] = regs->dloadVal[0];
94 regs->GPR.r[regs->dloadReg[1]] = regs->dloadVal[1];
95 regs->dloadVal[0] = regs->dloadVal[1] = 0;
96 regs->dloadReg[0] = regs->dloadReg[1] = 0;
97 assert(regs->GPR.r[0] == 0);
98#endif
99}
100
101static void dloadClear(psxRegisters *regs)
102{
103#ifdef HANDLE_LOAD_DELAY
104 regs->dloadVal[0] = regs->dloadVal[1] = 0;
105 regs->dloadReg[0] = regs->dloadReg[1] = 0;
106 regs->dloadSel = 0;
107#endif
108}
109
110static void intException(psxRegisters *regs, u32 pc, u32 cause)
111{
bc7c5acb 112 if (cause != 0x20) {
113 //FILE *f = fopen("/tmp/psx_ram.bin", "wb");
114 //fwrite(psxM, 1, 0x200000, f); fclose(f);
dc4fa8bc 115 log_unhandled("exception %08x @%08x ra=%08x\n",
116 cause, pc, regs->GPR.n.ra);
bc7c5acb 117 }
f9ae4f29 118 dloadFlush(regs);
119 regs->pc = pc;
bc7c5acb 120 psxException(cause, regs->branching, &regs->CP0);
121 regs->branching = R3000A_BRANCH_NONE_OR_EXCEPTION;
122}
123
124// exception caused by current instruction (excluding unkasking)
125static void intExceptionInsn(psxRegisters *regs, u32 cause)
126{
127 cause |= (regs->code & 0x0c000000) << 2;
128 intException(regs, regs->pc - 4, cause);
129}
130
131// 29 Enable for 80000000-ffffffff
132// 30 Enable for 00000000-7fffffff
133// 31 Enable exception
134#define DBR_ABIT(dc, a) ((dc) & (1u << (29+(((a)>>31)^1))))
135#define DBR_EN_EXEC(dc, a) (((dc) & 0x01800000) == 0x01800000 && DBR_ABIT(dc, a))
136#define DBR_EN_LD(dc, a) (((dc) & 0x06800000) == 0x06800000 && DBR_ABIT(dc, a))
137#define DBR_EN_ST(dc, a) (((dc) & 0x0a800000) == 0x0a800000 && DBR_ABIT(dc, a))
138static void intExceptionDebugBp(psxRegisters *regs, u32 pc)
139{
140 psxCP0Regs *cp0 = &regs->CP0;
141 dloadFlush(regs);
142 cp0->n.Cause &= 0x300;
143 cp0->n.Cause |= (regs->branching << 30) | (R3000E_Bp << 2);
144 cp0->n.SR = (cp0->n.SR & ~0x3f) | ((cp0->n.SR & 0x0f) << 2);
145 cp0->n.EPC = regs->branching ? pc - 4 : pc;
146 psxRegs.pc = 0x80000040;
147}
148
149static int execBreakCheck(psxRegisters *regs, u32 pc)
150{
151 if (unlikely(DBR_EN_EXEC(regs->CP0.n.DCIC, pc) &&
152 ((pc ^ regs->CP0.n.BPC) & regs->CP0.n.BPCM) == 0))
153 {
154 regs->CP0.n.DCIC |= 0x03;
155 if (regs->CP0.n.DCIC & (1u << 31)) {
156 intExceptionDebugBp(regs, pc);
157 return 1;
158 }
159 }
160 return 0;
f9ae4f29 161}
162
905b7c25 163// get an opcode without triggering exceptions or affecting cache
164u32 intFakeFetch(u32 pc)
165{
166 u8 *base = psxMemRLUT[pc >> 16];
167 u32 *code;
168 if (unlikely(base == INVALID_PTR))
169 return 0; // nop
170 code = (u32 *)(base + (pc & 0xfffc));
171 return SWAP32(*code);
172
173}
174
175static u32 INT_ATTR fetchNoCache(psxRegisters *regs, u8 **memRLUT, u32 pc)
61ad2a61 176{
4cc373dd 177 u8 *base = memRLUT[pc >> 16];
905b7c25 178 u32 *code;
179 if (unlikely(base == INVALID_PTR)) {
180 SysPrintf("game crash @%08x, ra=%08x\n", pc, regs->GPR.n.ra);
f9ae4f29 181 intException(regs, pc, R3000E_IBE << 2);
905b7c25 182 return 0; // execute as nop
183 }
184 code = (u32 *)(base + (pc & 0xfffc));
4cc373dd 185 return SWAP32(*code);
61ad2a61 186}
187
943a507a 188/*
189Formula One 2001 :
190Use old CPU cache code when the RAM location is updated with new code (affects in-game racing)
191*/
9f84fc93 192static struct cache_entry {
193 u32 tag;
194 u32 data[4];
195} ICache[256];
196
905b7c25 197static u32 INT_ATTR fetchICache(psxRegisters *regs, u8 **memRLUT, u32 pc)
943a507a 198{
9f84fc93 199 // cached?
200 if (pc < 0xa0000000)
943a507a 201 {
9f84fc93 202 // this is not how the hardware works but whatever
203 struct cache_entry *entry = &ICache[(pc & 0xff0) >> 4];
204
205 if (((entry->tag ^ pc) & 0xfffffff0) != 0 || pc < entry->tag)
943a507a 206 {
4cc373dd 207 const u8 *base = memRLUT[pc >> 16];
208 const u32 *code;
905b7c25 209 if (unlikely(base == INVALID_PTR)) {
210 SysPrintf("game crash @%08x, ra=%08x\n", pc, regs->GPR.n.ra);
f9ae4f29 211 intException(regs, pc, R3000E_IBE << 2);
905b7c25 212 return 0; // execute as nop
213 }
4cc373dd 214 code = (u32 *)(base + (pc & 0xfff0));
9f84fc93 215
216 entry->tag = pc;
217 // treat as 4 words, although other configurations are said to be possible
218 switch (pc & 0x0c)
219 {
220 case 0x00: entry->data[0] = SWAP32(code[0]);
221 case 0x04: entry->data[1] = SWAP32(code[1]);
222 case 0x08: entry->data[2] = SWAP32(code[2]);
223 case 0x0c: entry->data[3] = SWAP32(code[3]);
224 }
943a507a 225 }
9f84fc93 226 return entry->data[(pc & 0x0f) >> 2];
943a507a 227 }
228
905b7c25 229 return fetchNoCache(regs, memRLUT, pc);
943a507a 230}
61ad2a61 231
905b7c25 232static u32 (INT_ATTR *fetch)(psxRegisters *regs_, u8 **memRLUT, u32 pc) = fetchNoCache;
943a507a 233
d5aeda23 234// Make the timing events trigger faster as we are currently assuming everything
235// takes one cycle, which is not the case on real hardware.
236// FIXME: count cache misses, memory latencies, stalls to get rid of this
bc7c5acb 237static inline void addCycle(psxRegisters *regs)
d5aeda23 238{
bc7c5acb 239 assert(regs->subCycleStep >= 0x10000);
240 regs->subCycle += regs->subCycleStep;
241 regs->cycle += regs->subCycle >> 16;
242 regs->subCycle &= 0xffff;
d5aeda23 243}
244
4cc373dd 245/**** R3000A Instruction Macros ****/
246#define _PC_ regs_->pc // The next PC to be executed
247
248#define _fOp_(code) ((code >> 26) ) // The opcode part of the instruction register
249#define _fFunct_(code) ((code ) & 0x3F) // The funct part of the instruction register
250#define _fRd_(code) ((code >> 11) & 0x1F) // The rd part of the instruction register
251#define _fRt_(code) ((code >> 16) & 0x1F) // The rt part of the instruction register
252#define _fRs_(code) ((code >> 21) & 0x1F) // The rs part of the instruction register
253#define _fSa_(code) ((code >> 6) & 0x1F) // The sa part of the instruction register
254#define _fIm_(code) ((u16)code) // The immediate part of the instruction register
255#define _fTarget_(code) (code & 0x03ffffff) // The target part of the instruction register
256
257#define _fImm_(code) ((s16)code) // sign-extended immediate
258#define _fImmU_(code) (code&0xffff) // zero-extended immediate
259
260#define _Op_ _fOp_(code)
261#define _Funct_ _fFunct_(code)
262#define _Rd_ _fRd_(code)
263#define _Rt_ _fRt_(code)
264#define _Rs_ _fRs_(code)
265#define _Sa_ _fSa_(code)
266#define _Im_ _fIm_(code)
267#define _Target_ _fTarget_(code)
268
269#define _Imm_ _fImm_(code)
270#define _ImmU_ _fImmU_(code)
271
272#define _rRs_ regs_->GPR.r[_Rs_] // Rs register
273#define _rRt_ regs_->GPR.r[_Rt_] // Rt register
4cc373dd 274#define _rSa_ regs_->GPR.r[_Sa_] // Sa register
4cc373dd 275
276#define _rHi_ regs_->GPR.n.hi // The HI register
277#define _rLo_ regs_->GPR.n.lo // The LO register
278
279#define _JumpTarget_ ((_Target_ * 4) + (_PC_ & 0xf0000000)) // Calculates the target during a jump instruction
280#define _BranchTarget_ ((s16)_Im_ * 4 + _PC_) // Calculates the target during a branch instruction
281
f9ae4f29 282#define _SetLink(x) dloadRt(regs_, x, _PC_ + 4); // Sets the return address in the link register
4cc373dd 283
284#define OP(name) \
285 static inline INT_ATTR void name(psxRegisters *regs_, u32 code)
286
ef79bbde
P		 287// this defines shall be used with the tmp
288// of the next func (instead of _Funct_...)
289#define _tFunct_ ((tmp ) & 0x3F) // The funct part of the instruction register
290#define _tRd_ ((tmp >> 11) & 0x1F) // The rd part of the instruction register
291#define _tRt_ ((tmp >> 16) & 0x1F) // The rt part of the instruction register
292#define _tRs_ ((tmp >> 21) & 0x1F) // The rs part of the instruction register
293#define _tSa_ ((tmp >> 6) & 0x1F) // The sa part of the instruction register
294
4cc373dd 295#define _i32(x) (s32)(x)
296#define _u32(x) (u32)(x)
297
b9698f9d 298#define isBranch(c_) \
299 ((1 <= ((c_) >> 26) && ((c_) >> 26) <= 7) || ((c_) & 0xfc00003e) == 8)
300#define swap_(a_, b_) { u32 t_ = a_; a_ = b_; b_ = t_; }
990cb018 301
b9698f9d 302// tar1 is main branch target, 'code' is opcode in DS
303static u32 psxBranchNoDelay(psxRegisters *regs_, u32 tar1, u32 code, int *taken) {
304 u32 temp, rt;
305
306 assert(isBranch(code));
307 *taken = 1;
308 switch (code >> 26) {
990cb018 309 case 0x00: // SPECIAL
310 switch (_Funct_) {
311 case 0x08: // JR
312 return _u32(_rRs_);
313 case 0x09: // JALR
314 temp = _u32(_rRs_);
b9698f9d 315 if (_Rd_)
316 regs_->GPR.r[_Rd_] = tar1 + 4;
990cb018 317 return temp;
318 }
319 break;
320 case 0x01: // REGIMM
b9698f9d 321 rt = _Rt_;
322 switch (rt) {
323 case 0x10: // BLTZAL
324 regs_->GPR.n.ra = tar1 + 4;
990cb018 325 if (_i32(_rRs_) < 0)
b9698f9d 326 return tar1 + (s16)_Im_ * 4;
990cb018 327 break;
b9698f9d 328 case 0x11: // BGEZAL
329 regs_->GPR.n.ra = tar1 + 4;
990cb018 330 if (_i32(_rRs_) >= 0)
b9698f9d 331 return tar1 + (s16)_Im_ * 4;
990cb018 332 break;
b9698f9d 333 default:
334 if (rt & 1) { // BGEZ
335 if (_i32(_rRs_) >= 0)
336 return tar1 + (s16)_Im_ * 4;
990cb018 337 }
b9698f9d 338 else { // BLTZ
339 if (_i32(_rRs_) < 0)
340 return tar1 + (s16)_Im_ * 4;
990cb018 341 }
342 break;
343 }
344 break;
345 case 0x02: // J
b9698f9d 346 return (tar1 & 0xf0000000u) + _Target_ * 4;
990cb018 347 case 0x03: // JAL
b9698f9d 348 regs_->GPR.n.ra = tar1 + 4;
349 return (tar1 & 0xf0000000u) + _Target_ * 4;
990cb018 350 case 0x04: // BEQ
351 if (_i32(_rRs_) == _i32(_rRt_))
b9698f9d 352 return tar1 + (s16)_Im_ * 4;
990cb018 353 break;
354 case 0x05: // BNE
355 if (_i32(_rRs_) != _i32(_rRt_))
b9698f9d 356 return tar1 + (s16)_Im_ * 4;
990cb018 357 break;
358 case 0x06: // BLEZ
359 if (_i32(_rRs_) <= 0)
b9698f9d 360 return tar1 + (s16)_Im_ * 4;
990cb018 361 break;
362 case 0x07: // BGTZ
363 if (_i32(_rRs_) > 0)
b9698f9d 364 return tar1 + (s16)_Im_ * 4;
990cb018 365 break;
366 }
367
b9698f9d 368 *taken = 0;
369 return tar1;
990cb018 370}
371
b9698f9d 372static void psxDoDelayBranch(psxRegisters *regs, u32 tar1, u32 code1) {
373 u32 tar2, code;
374 int taken, lim;
990cb018 375
b9698f9d 376 tar2 = psxBranchNoDelay(regs, tar1, code1, &taken);
377 regs->pc = tar1;
378 if (!taken)
379 return;
990cb018 380
990cb018 381 /*
b9698f9d 382 * taken branch in delay slot:
990cb018 383 * - execute 1 instruction at tar1
384 * - jump to tar2 (target of branch in delay slot; this branch
385 * has no normal delay slot, instruction at tar1 was fetched instead)
386 */
b9698f9d 387 for (lim = 0; lim < 8; lim++) {
388 regs->code = code = fetch(regs, psxMemRLUT, tar1);
bc7c5acb 389 addCycle(regs);
b9698f9d 390 if (likely(!isBranch(code))) {
f9ae4f29 391 dloadStep(regs);
b9698f9d 392 psxBSC[code >> 26](regs, code);
393 regs->pc = tar2;
394 return;
395 }
396 tar1 = psxBranchNoDelay(regs, tar2, code, &taken);
397 regs->pc = tar2;
398 if (!taken)
399 return;
400 swap_(tar1, tar2);
990cb018 401 }
b9698f9d 402 SysPrintf("Evil chained DS branches @ %08x %08x %08x\n", regs->pc, tar1, tar2);
990cb018 403}
404
bc7c5acb 405static void doBranch(psxRegisters *regs, u32 tar, enum R3000Abdt taken) {
406 u32 code, pc, pc_final;
ef79bbde 407
bc7c5acb 408 branchSeen = regs->branching = taken;
409 pc_final = taken == R3000A_BRANCH_TAKEN ? tar : regs->pc + 4;
990cb018 410
b9698f9d 411 // fetch the delay slot
412 pc = regs->pc;
413 regs->pc = pc + 4;
414 regs->code = code = fetch(regs, psxMemRLUT, pc);
905b7c25 415
bc7c5acb 416 addCycle(regs);
ef79bbde 417
b9698f9d 418 // check for branch in delay slot
419 if (unlikely(isBranch(code))) {
bc7c5acb 420 regs->pc = pc;
421 if (taken == R3000A_BRANCH_TAKEN)
422 psxDoDelayBranch(regs, tar, code);
b9698f9d 423 log_unhandled("branch in DS: %08x->%08x\n", pc, regs->pc);
bc7c5acb 424 regs->branching = 0;
b9698f9d 425 psxBranchTest();
426 return;
427 }
428
f9ae4f29 429 dloadStep(regs);
b9698f9d 430 psxBSC[code >> 26](regs, code);
ef79bbde 431
bc7c5acb 432 if (likely(regs->branching != R3000A_BRANCH_NONE_OR_EXCEPTION))
433 regs->pc = pc_final;
434 else
435 regs->CP0.n.Target = pc_final;
436 regs->branching = 0;
ef79bbde
P		 437
438 psxBranchTest();
439}
440
b9698f9d 441static void doBranchReg(psxRegisters *regs, u32 tar) {
bc7c5acb 442 doBranch(regs, tar & ~3, R3000A_BRANCH_TAKEN);
443}
444
445static void doBranchRegE(psxRegisters *regs, u32 tar) {
446 if (unlikely(DBR_EN_EXEC(regs->CP0.n.DCIC, tar) &&
447 ((tar ^ regs->CP0.n.BPC) & regs->CP0.n.BPCM) == 0))
448 regs->CP0.n.DCIC |= 0x03;
905b7c25 449 if (unlikely(tar & 3)) {
f9ae4f29 450 SysPrintf("game crash @%08x, ra=%08x\n", tar, regs->GPR.n.ra);
bc7c5acb 451 regs->CP0.n.BadVAddr = tar;
f9ae4f29 452 intException(regs, tar, R3000E_AdEL << 2);
905b7c25 453 return;
454 }
bc7c5acb 455 doBranch(regs, tar, R3000A_BRANCH_TAKEN);
905b7c25 456}
457
905b7c25 458static void addExc(psxRegisters *regs, u32 rt, s32 a1, s32 a2) {
f9ae4f29 459 s32 val;
460 if (add_overflow(a1, a2, val)) {
461 //printf("ov %08x + %08x = %08x\n", a1, a2, val);
bc7c5acb 462 intExceptionInsn(regs, R3000E_Ov << 2);
905b7c25 463 return;
464 }
f9ae4f29 465 dloadRt(regs, rt, val);
905b7c25 466}
467
468static void subExc(psxRegisters *regs, u32 rt, s32 a1, s32 a2) {
f9ae4f29 469 s32 val;
470 if (sub_overflow(a1, a2, val)) {
bc7c5acb 471 intExceptionInsn(regs, R3000E_Ov << 2);
905b7c25 472 return;
473 }
f9ae4f29 474 dloadRt(regs, rt, val);
905b7c25 475}
476
ef79bbde
P		 477/*********************************************************
478* Arithmetic with immediate operand *
479* Format: OP rt, rs, immediate *
480*********************************************************/
f9ae4f29 481OP(psxADDI) { addExc (regs_, _Rt_, _i32(_rRs_), _Imm_); } // Rt = Rs + Im (Exception on Integer Overflow)
482OP(psxADDIU) { dloadRt(regs_, _Rt_, _u32(_rRs_) + _Imm_ ); } // Rt = Rs + Im
483OP(psxANDI) { dloadRt(regs_, _Rt_, _u32(_rRs_) & _ImmU_); } // Rt = Rs And Im
484OP(psxORI) { dloadRt(regs_, _Rt_, _u32(_rRs_) | _ImmU_); } // Rt = Rs Or Im
485OP(psxXORI) { dloadRt(regs_, _Rt_, _u32(_rRs_) ^ _ImmU_); } // Rt = Rs Xor Im
486OP(psxSLTI) { dloadRt(regs_, _Rt_, _i32(_rRs_) < _Imm_ ); } // Rt = Rs < Im (Signed)
487OP(psxSLTIU) { dloadRt(regs_, _Rt_, _u32(_rRs_) < ((u32)_Imm_)); } // Rt = Rs < Im (Unsigned)
ef79bbde
P		 488
489/*********************************************************
490* Register arithmetic *
491* Format: OP rd, rs, rt *
492*********************************************************/
f9ae4f29 493OP(psxADD) { addExc (regs_, _Rd_, _i32(_rRs_), _i32(_rRt_)); } // Rd = Rs + Rt (Exception on Integer Overflow)
494OP(psxSUB) { subExc (regs_, _Rd_, _i32(_rRs_), _i32(_rRt_)); } // Rd = Rs - Rt (Exception on Integer Overflow)
495OP(psxADDU) { dloadRt(regs_, _Rd_, _u32(_rRs_) + _u32(_rRt_)); } // Rd = Rs + Rt
496OP(psxSUBU) { dloadRt(regs_, _Rd_, _u32(_rRs_) - _u32(_rRt_)); } // Rd = Rs - Rt
497OP(psxAND) { dloadRt(regs_, _Rd_, _u32(_rRs_) & _u32(_rRt_)); } // Rd = Rs And Rt
498OP(psxOR) { dloadRt(regs_, _Rd_, _u32(_rRs_) | _u32(_rRt_)); } // Rd = Rs Or Rt
499OP(psxXOR) { dloadRt(regs_, _Rd_, _u32(_rRs_) ^ _u32(_rRt_)); } // Rd = Rs Xor Rt
500OP(psxNOR) { dloadRt(regs_, _Rd_, ~_u32(_rRs_ | _u32(_rRt_))); } // Rd = Rs Nor Rt
501OP(psxSLT) { dloadRt(regs_, _Rd_, _i32(_rRs_) < _i32(_rRt_)); } // Rd = Rs < Rt (Signed)
502OP(psxSLTU) { dloadRt(regs_, _Rd_, _u32(_rRs_) < _u32(_rRt_)); } // Rd = Rs < Rt (Unsigned)
ef79bbde
P		 503
504/*********************************************************
505* Register mult/div & Register trap logic *
506* Format: OP rs, rt *
507*********************************************************/
4cc373dd 508OP(psxDIV) {
509 if (!_rRt_) {
510 _rHi_ = _rRs_;
511 if (_rRs_ & 0x80000000) {
512 _rLo_ = 1;
513 } else {
514 _rLo_ = 0xFFFFFFFF;
515 }
516 }
a4ae3997 517#if !defined(__arm__) && !defined(__aarch64__)
4cc373dd 518 else if (_rRs_ == 0x80000000 && _rRt_ == 0xFFFFFFFF) {
519 _rLo_ = 0x80000000;
520 _rHi_ = 0;
521 }
a4ae3997 522#endif
4cc373dd 523 else {
524 _rLo_ = _i32(_rRs_) / _i32(_rRt_);
525 _rHi_ = _i32(_rRs_) % _i32(_rRt_);
526 }
ef79bbde
P		 527}
528
4cc373dd 529OP(psxDIV_stall) {
530 regs_->muldivBusyCycle = regs_->cycle + 37;
531 psxDIV(regs_, code);
32631e6a 532}
533
4cc373dd 534OP(psxDIVU) {
ef79bbde
P		 535 if (_rRt_ != 0) {
536 _rLo_ = _rRs_ / _rRt_;
537 _rHi_ = _rRs_ % _rRt_;
538 }
c7a56f4f 539 else {
4cc373dd 540 _rLo_ = 0xffffffff;
541 _rHi_ = _rRs_;
c7a56f4f 542 }
ef79bbde
P		 543}
544
4cc373dd 545OP(psxDIVU_stall) {
546 regs_->muldivBusyCycle = regs_->cycle + 37;
547 psxDIVU(regs_, code);
32631e6a 548}
549
4cc373dd 550OP(psxMULT) {
551 u64 res = (s64)_i32(_rRs_) * _i32(_rRt_);
ef79bbde 552
4cc373dd 553 regs_->GPR.n.lo = (u32)res;
554 regs_->GPR.n.hi = (u32)(res >> 32);
ef79bbde
P		 555}
556
4cc373dd 557OP(psxMULT_stall) {
32631e6a 558 // approximate, but maybe good enough
559 u32 rs = _rRs_;
560 u32 lz = __builtin_clz(((rs ^ ((s32)rs >> 21)) | 1));
561 u32 c = 7 + (2 - (lz / 11)) * 4;
4cc373dd 562 regs_->muldivBusyCycle = regs_->cycle + c;
563 psxMULT(regs_, code);
32631e6a 564}
565
4cc373dd 566OP(psxMULTU) {
567 u64 res = (u64)_u32(_rRs_) * _u32(_rRt_);
ef79bbde 568
4cc373dd 569 regs_->GPR.n.lo = (u32)(res & 0xffffffff);
570 regs_->GPR.n.hi = (u32)((res >> 32) & 0xffffffff);
ef79bbde
P		 571}
572
4cc373dd 573OP(psxMULTU_stall) {
32631e6a 574 // approximate, but maybe good enough
575 u32 lz = __builtin_clz(_rRs_ | 1);
576 u32 c = 7 + (2 - (lz / 11)) * 4;
4cc373dd 577 regs_->muldivBusyCycle = regs_->cycle + c;
578 psxMULTU(regs_, code);
32631e6a 579}
580
ef79bbde
P		 581/*********************************************************
582* Register branch logic *
583* Format: OP rs, offset *
584*********************************************************/
bc7c5acb 585#define BrCond(c) (c) ? R3000A_BRANCH_TAKEN : R3000A_BRANCH_NOT_TAKEN
19fae7fc 586#define RepZBranchi32(op) \
bc7c5acb 587 doBranch(regs_, _BranchTarget_, BrCond(_i32(_rRs_) op 0));
19fae7fc 588#define RepZBranchLinki32(op) { \
589 s32 temp = _i32(_rRs_); \
bc7c5acb 590 dloadFlush(regs_); \
19fae7fc 591 _SetLink(31); \
bc7c5acb 592 doBranch(regs_, _BranchTarget_, BrCond(temp op 0)); \
19fae7fc 593}
ef79bbde 594
4cc373dd 595OP(psxBGEZ) { RepZBranchi32(>=) } // Branch if Rs >= 0
596OP(psxBGEZAL) { RepZBranchLinki32(>=) } // Branch if Rs >= 0 and link
597OP(psxBGTZ) { RepZBranchi32(>) } // Branch if Rs > 0
598OP(psxBLEZ) { RepZBranchi32(<=) } // Branch if Rs <= 0
599OP(psxBLTZ) { RepZBranchi32(<) } // Branch if Rs < 0
600OP(psxBLTZAL) { RepZBranchLinki32(<) } // Branch if Rs < 0 and link
ef79bbde
P		 601
602/*********************************************************
603* Shift arithmetic with constant shift *
604* Format: OP rd, rt, sa *
605*********************************************************/
f9ae4f29 606OP(psxSLL) { dloadRt(regs_, _Rd_, _u32(_rRt_) << _Sa_); } // Rd = Rt << sa
607OP(psxSRA) { dloadRt(regs_, _Rd_, _i32(_rRt_) >> _Sa_); } // Rd = Rt >> sa (arithmetic)
608OP(psxSRL) { dloadRt(regs_, _Rd_, _u32(_rRt_) >> _Sa_); } // Rd = Rt >> sa (logical)
ef79bbde
P		 609
610/*********************************************************
611* Shift arithmetic with variant register shift *
612* Format: OP rd, rt, rs *
613*********************************************************/
f9ae4f29 614OP(psxSLLV) { dloadRt(regs_, _Rd_, _u32(_rRt_) << (_u32(_rRs_) & 0x1F)); } // Rd = Rt << rs
615OP(psxSRAV) { dloadRt(regs_, _Rd_, _i32(_rRt_) >> (_u32(_rRs_) & 0x1F)); } // Rd = Rt >> rs (arithmetic)
616OP(psxSRLV) { dloadRt(regs_, _Rd_, _u32(_rRt_) >> (_u32(_rRs_) & 0x1F)); } // Rd = Rt >> rs (logical)
ef79bbde
P		 617
618/*********************************************************
619* Load higher 16 bits of the first word in GPR with imm *
620* Format: OP rt, immediate *
621*********************************************************/
f9ae4f29 622OP(psxLUI) { dloadRt(regs_, _Rt_, code << 16); } // Upper halfword of Rt = Im
ef79bbde
P		 623
624/*********************************************************
625* Move from HI/LO to GPR *
626* Format: OP rd *
627*********************************************************/
f9ae4f29 628OP(psxMFHI) { dloadRt(regs_, _Rd_, _rHi_); } // Rd = Hi
629OP(psxMFLO) { dloadRt(regs_, _Rd_, _rLo_); } // Rd = Lo
ef79bbde 630
4cc373dd 631static void mflohiCheckStall(psxRegisters *regs_)
32631e6a 632{
4cc373dd 633 u32 left = regs_->muldivBusyCycle - regs_->cycle;
32631e6a 634 if (left <= 37) {
635 //printf("muldiv stall %u\n", left);
4cc373dd 636 regs_->cycle = regs_->muldivBusyCycle;
32631e6a 637 }
638}
639
4cc373dd 640OP(psxMFHI_stall) { mflohiCheckStall(regs_); psxMFHI(regs_, code); }
641OP(psxMFLO_stall) { mflohiCheckStall(regs_); psxMFLO(regs_, code); }
32631e6a 642
ef79bbde
P		 643/*********************************************************
644* Move to GPR to HI/LO & Register jump *
645* Format: OP rs *
646*********************************************************/
4cc373dd 647OP(psxMTHI) { _rHi_ = _rRs_; } // Hi = Rs
648OP(psxMTLO) { _rLo_ = _rRs_; } // Lo = Rs
ef79bbde
P		 649
650/*********************************************************
651* Special purpose instructions *
652* Format: OP *
653*********************************************************/
4cc373dd 654OP(psxBREAK) {
bc7c5acb 655 intExceptionInsn(regs_, R3000E_Bp << 2);
ef79bbde
P		 656}
657
4cc373dd 658OP(psxSYSCALL) {
bc7c5acb 659 intExceptionInsn(regs_, R3000E_Syscall << 2);
ef79bbde
P		 660}
661
905b7c25 662static inline void execI_(u8 **memRLUT, psxRegisters *regs_);
663
664static inline void psxTestSWInts(psxRegisters *regs_, int step) {
bc7c5acb 665 if ((regs_->CP0.n.Cause & regs_->CP0.n.SR & 0x0300) &&
666 (regs_->CP0.n.SR & 0x1)) {
905b7c25 667 if (step)
668 execI_(psxMemRLUT, regs_);
4cc373dd 669 regs_->CP0.n.Cause &= ~0x7c;
f9ae4f29 670 intException(regs_, regs_->pc, regs_->CP0.n.Cause);
4cc373dd 671 }
672}
673
674OP(psxRFE) {
bc7c5acb 675 regs_->CP0.n.SR = (regs_->CP0.n.SR & ~0x0f) | ((regs_->CP0.n.SR & 0x3c) >> 2);
905b7c25 676 psxTestSWInts(regs_, 0);
ef79bbde
P		 677}
678
679/*********************************************************
680* Register branch logic *
681* Format: OP rs, rt, offset *
682*********************************************************/
bc7c5acb 683#define RepBranchi32(op) \
684 doBranch(regs_, _BranchTarget_, BrCond(_i32(_rRs_) op _i32(_rRt_)));
ef79bbde 685
4cc373dd 686OP(psxBEQ) { RepBranchi32(==) } // Branch if Rs == Rt
687OP(psxBNE) { RepBranchi32(!=) } // Branch if Rs != Rt
ef79bbde
P		 688
689/*********************************************************
690* Jump to target *
691* Format: OP target *
692*********************************************************/
bc7c5acb 693OP(psxJ) { doBranch(regs_, _JumpTarget_, R3000A_BRANCH_TAKEN); }
694OP(psxJAL) {
695 dloadFlush(regs_);
696 _SetLink(31);
697 doBranch(regs_, _JumpTarget_, R3000A_BRANCH_TAKEN);
698}
ef79bbde
P		 699
700/*********************************************************
701* Register jump *
702* Format: OP rs, rd *
703*********************************************************/
4cc373dd 704OP(psxJR) {
b9698f9d 705 doBranchReg(regs_, _rRs_);
ef79bbde
P		 706 psxJumpTest();
707}
708
bc7c5acb 709OP(psxJRe) {
710 doBranchRegE(regs_, _rRs_);
711 psxJumpTest();
712}
713
4cc373dd 714OP(psxJALR) {
ef79bbde 715 u32 temp = _u32(_rRs_);
bc7c5acb 716 dloadFlush(regs_);
ef79bbde 717 if (_Rd_) { _SetLink(_Rd_); }
b9698f9d 718 doBranchReg(regs_, temp);
ef79bbde
P		 719}
720
bc7c5acb 721OP(psxJALRe) {
722 u32 temp = _u32(_rRs_);
723 dloadFlush(regs_);
724 if (_Rd_) { _SetLink(_Rd_); }
725 doBranchRegE(regs_, temp);
726}
727
ef79bbde 728/*********************************************************
ef79bbde
P		 729*********************************************************/
730
bc7c5acb 731// revisit: incomplete
732#define BUS_LOCKED_ADDR(a) \
733 ((0x1fc80000u <= (a) && (a) < 0x80000000u) || \
734 (0xc0000000u <= (a) && (a) < 0xfffe0000u))
735
736// exception checking order is important
737static inline int checkLD(psxRegisters *regs, u32 addr, u32 m) {
738 int bpException = 0;
739 if (unlikely(DBR_EN_LD(regs->CP0.n.DCIC, addr) &&
740 ((addr ^ regs->CP0.n.BDA) & regs->CP0.n.BDAM) == 0)) {
741 regs->CP0.n.DCIC |= 0x0d;
742 bpException = regs->CP0.n.DCIC >> 31;
743 }
f9ae4f29 744 if (unlikely(addr & m)) {
bc7c5acb 745 regs->CP0.n.BadVAddr = addr;
746 intExceptionInsn(regs, R3000E_AdEL << 2);
747 return 0;
748 }
749 if (unlikely(bpException)) {
750 intExceptionDebugBp(regs, regs->pc - 4);
751 return 0;
752 }
753 if (unlikely(BUS_LOCKED_ADDR(addr))) {
754 intException(regs, regs->pc - 4, R3000E_DBE << 2);
f9ae4f29 755 return 0;
f9ae4f29 756 }
757 return 1;
758}
759
bc7c5acb 760static inline int checkST(psxRegisters *regs, u32 addr, u32 m) {
761 int bpException = 0;
762 if (unlikely(DBR_EN_ST(regs->CP0.n.DCIC, addr) &&
763 ((addr ^ regs->CP0.n.BDA) & regs->CP0.n.BDAM) == 0)) {
764 regs->CP0.n.DCIC |= 0x15;
765 bpException = regs->CP0.n.DCIC >> 31;
766 }
f9ae4f29 767 if (unlikely(addr & m)) {
bc7c5acb 768 regs->CP0.n.BadVAddr = addr;
769 intExceptionInsn(regs, R3000E_AdES << 2);
770 return 0;
771 }
772 if (unlikely(bpException)) {
773 intExceptionDebugBp(regs, regs->pc - 4);
774 return 0;
775 }
776 if (unlikely(BUS_LOCKED_ADDR(addr))) {
777 intException(regs, regs->pc - 4, R3000E_DBE << 2);
f9ae4f29 778 return 0;
f9ae4f29 779 }
780 return 1;
781}
782
783/*********************************************************
784* Load and store for GPR *
785* Format: OP rt, offset(base) *
786*********************************************************/
787
bc7c5acb 788/*********************************************************
789* Load and store for GPR *
790* Format: OP rt, offset(base) *
791*********************************************************/
792
4cc373dd 793#define _oB_ (regs_->GPR.r[_Rs_] + _Imm_)
ef79bbde 794
bc7c5acb 795OP(psxLB) { doLoad(regs_, _Rt_, (s8)psxMemRead8(_oB_)); }
796OP(psxLBU) { doLoad(regs_, _Rt_, psxMemRead8(_oB_)); }
797OP(psxLH) { doLoad(regs_, _Rt_, (s16)psxMemRead16(_oB_ & ~1)); }
798OP(psxLHU) { doLoad(regs_, _Rt_, psxMemRead16(_oB_ & ~1)); }
799OP(psxLW) { doLoad(regs_, _Rt_, psxMemRead32(_oB_ & ~3)); }
ef79bbde 800
bc7c5acb 801OP(psxLBe) { if (checkLD(regs_, _oB_, 0)) doLoad(regs_, _Rt_, (s8)psxMemRead8(_oB_)); }
802OP(psxLBUe) { if (checkLD(regs_, _oB_, 0)) doLoad(regs_, _Rt_, psxMemRead8(_oB_)); }
803OP(psxLHe) { if (checkLD(regs_, _oB_, 1)) doLoad(regs_, _Rt_, (s16)psxMemRead16(_oB_)); }
804OP(psxLHUe) { if (checkLD(regs_, _oB_, 1)) doLoad(regs_, _Rt_, psxMemRead16(_oB_)); }
805OP(psxLWe) { if (checkLD(regs_, _oB_, 3)) doLoad(regs_, _Rt_, psxMemRead32(_oB_)); }
806
807static void doLWL(psxRegisters *regs, u32 rt, u32 addr) {
4cc373dd 808 static const u32 LWL_MASK[4] = { 0xffffff, 0xffff, 0xff, 0 };
809 static const u32 LWL_SHIFT[4] = { 24, 16, 8, 0 };
ef79bbde 810 u32 shift = addr & 3;
bc7c5acb 811 u32 val, mem;
812 u32 oldval = regs->GPR.r[rt];
ef79bbde 813
f9ae4f29 814#ifdef HANDLE_LOAD_DELAY
bc7c5acb 815 int sel = regs->dloadSel;
816 if (regs->dloadReg[sel] == rt)
817 oldval = regs->dloadVal[sel];
f9ae4f29 818#endif
bc7c5acb 819 mem = psxMemRead32(addr & ~3);
f9ae4f29 820 val = (oldval & LWL_MASK[shift]) | (mem << LWL_SHIFT[shift]);
bc7c5acb 821 doLoad(regs, rt, val);
ef79bbde
P		 822
823 /*
824 Mem = 1234. Reg = abcd
825
826 0 4bcd (mem << 24) | (reg & 0x00ffffff)
827 1 34cd (mem << 16) | (reg & 0x0000ffff)
828 2 234d (mem << 8) | (reg & 0x000000ff)
829 3 1234 (mem ) | (reg & 0x00000000)
830 */
831}
832
bc7c5acb 833static void doLWR(psxRegisters *regs, u32 rt, u32 addr) {
4cc373dd 834 static const u32 LWR_MASK[4] = { 0, 0xff000000, 0xffff0000, 0xffffff00 };
835 static const u32 LWR_SHIFT[4] = { 0, 8, 16, 24 };
ef79bbde 836 u32 shift = addr & 3;
bc7c5acb 837 u32 val, mem;
838 u32 oldval = regs->GPR.r[rt];
ef79bbde 839
f9ae4f29 840#ifdef HANDLE_LOAD_DELAY
bc7c5acb 841 int sel = regs->dloadSel;
842 if (regs->dloadReg[sel] == rt)
843 oldval = regs->dloadVal[sel];
f9ae4f29 844#endif
bc7c5acb 845 mem = psxMemRead32(addr & ~3);
f9ae4f29 846 val = (oldval & LWR_MASK[shift]) | (mem >> LWR_SHIFT[shift]);
bc7c5acb 847 doLoad(regs, rt, val);
ef79bbde
P		 848
849 /*
850 Mem = 1234. Reg = abcd
851
852 0 1234 (mem ) | (reg & 0x00000000)
853 1 a123 (mem >> 8) | (reg & 0xff000000)
854 2 ab12 (mem >> 16) | (reg & 0xffff0000)
855 3 abc1 (mem >> 24) | (reg & 0xffffff00)
856 */
857}
858
bc7c5acb 859OP(psxLWL) { doLWL(regs_, _Rt_, _oB_); }
860OP(psxLWR) { doLWR(regs_, _Rt_, _oB_); }
ef79bbde 861
bc7c5acb 862OP(psxLWLe) { if (checkLD(regs_, _oB_ & ~3, 0)) doLWL(regs_, _Rt_, _oB_); }
863OP(psxLWRe) { if (checkLD(regs_, _oB_ , 0)) doLWR(regs_, _Rt_, _oB_); }
ef79bbde 864
bc7c5acb 865OP(psxSB) { psxMemWrite8 (_oB_, _rRt_ & 0xff); }
866OP(psxSH) { psxMemWrite16(_oB_, _rRt_ & 0xffff); }
867OP(psxSW) { psxMemWrite32(_oB_, _rRt_); }
868
869OP(psxSBe) { if (checkST(regs_, _oB_, 0)) psxMemWrite8 (_oB_, _rRt_ & 0xff); }
870OP(psxSHe) { if (checkST(regs_, _oB_, 1)) psxMemWrite16(_oB_, _rRt_ & 0xffff); }
871OP(psxSWe) { if (checkST(regs_, _oB_, 3)) psxMemWrite32(_oB_, _rRt_); }
872
873static void doSWL(psxRegisters *regs, u32 rt, u32 addr) {
874 u32 val = regs->GPR.r[rt];
875 switch (addr & 3) {
876 case 0: psxMemWrite8( addr , val >> 24); break;
877 case 1: psxMemWrite16(addr & ~3, val >> 16); break;
878 case 2: // revisit: should be a single 24bit write
879 psxMemWrite16(addr & ~3, (val >> 8) & 0xffff);
880 psxMemWrite8( addr , val >> 24); break;
881 case 3: psxMemWrite32(addr & ~3, val); break;
882 }
ef79bbde
P		 883 /*
884 Mem = 1234. Reg = abcd
885
886 0 123a (reg >> 24) | (mem & 0xffffff00)
887 1 12ab (reg >> 16) | (mem & 0xffff0000)
888 2 1abc (reg >> 8) | (mem & 0xff000000)
889 3 abcd (reg ) | (mem & 0x00000000)
890 */
891}
892
bc7c5acb 893static void doSWR(psxRegisters *regs, u32 rt, u32 addr) {
894 u32 val = regs->GPR.r[rt];
895 switch (addr & 3) {
896 case 0: psxMemWrite32(addr , val); break;
897 case 1: // revisit: should be a single 24bit write
898 psxMemWrite8 (addr , val & 0xff);
899 psxMemWrite16(addr + 1, (val >> 8) & 0xffff); break;
900 case 2: psxMemWrite16(addr , val & 0xffff); break;
901 case 3: psxMemWrite8 (addr , val & 0xff); break;
902 }
ef79bbde
P		 903
904 /*
905 Mem = 1234. Reg = abcd
906
907 0 abcd (reg ) | (mem & 0x00000000)
908 1 bcd4 (reg << 8) | (mem & 0x000000ff)
909 2 cd34 (reg << 16) | (mem & 0x0000ffff)
910 3 d234 (reg << 24) | (mem & 0x00ffffff)
911 */
912}
913
bc7c5acb 914OP(psxSWL) { doSWL(regs_, _Rt_, _oB_); }
915OP(psxSWR) { doSWR(regs_, _Rt_, _oB_); }
916
917OP(psxSWLe) { if (checkST(regs_, _oB_ & ~3, 0)) doSWL(regs_, _Rt_, _oB_); }
918OP(psxSWRe) { if (checkST(regs_, _oB_ , 0)) doSWR(regs_, _Rt_, _oB_); }
919
ef79bbde
P		 920/*********************************************************
921* Moves between GPR and COPx *
922* Format: OP rt, fs *
923*********************************************************/
905b7c25 924OP(psxMFC0) {
925 u32 r = _Rd_;
926#ifdef DO_EXCEPTION_RESERVEDI
bc7c5acb 927 if (unlikely(0x00000417u & (1u << r)))
928 intExceptionInsn(regs_, R3000E_RI << 2);
905b7c25 929#endif
f9ae4f29 930 doLoad(regs_, _Rt_, regs_->CP0.r[r]);
905b7c25 931}
932
905b7c25 933static void setupCop(u32 sr);
934
4cc373dd 935void MTC0(psxRegisters *regs_, int reg, u32 val) {
ef79bbde
P		 936// SysPrintf("MTC0 %d: %x\n", reg, val);
937 switch (reg) {
bc7c5acb 938 case 12: // SR
939 if (unlikely((regs_->CP0.n.SR ^ val) & (1 << 16)))
679d5ee3 940 psxMemOnIsolate((val >> 16) & 1);
bc7c5acb 941 if (unlikely((regs_->CP0.n.SR ^ val) & (7 << 29)))
905b7c25 942 setupCop(val);
bc7c5acb 943 regs_->CP0.n.SR = val;
905b7c25 944 psxTestSWInts(regs_, 1);
ef79bbde
P		 945 break;
946
947 case 13: // Cause
4cc373dd 948 regs_->CP0.n.Cause &= ~0x0300;
949 regs_->CP0.n.Cause |= val & 0x0300;
905b7c25 950 psxTestSWInts(regs_, 0);
ef79bbde
P		 951 break;
952
bc7c5acb 953 case 7:
954 if ((regs_->CP0.n.DCIC ^ val) & 0xff800000)
955 log_unhandled("DCIC: %08x->%08x\n", regs_->CP0.n.DCIC, val);
956 // fallthrough
ef79bbde 957 default:
4cc373dd 958 regs_->CP0.r[reg] = val;
ef79bbde
P		 959 break;
960 }
961}
962
4cc373dd 963OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); }
ef79bbde 964
bc7c5acb 965// no exception
966static inline void psxNULLne(psxRegisters *regs) {
967 log_unhandled("unhandled op %08x @%08x\n", regs->code, regs->pc - 4);
968}
969
ef79bbde 970/*********************************************************
905b7c25 971* Unknown instruction (would generate an exception) *
ef79bbde
P		 972* Format: ? *
973*********************************************************/
905b7c25 974
975OP(psxNULL) {
bc7c5acb 976 psxNULLne(regs_);
905b7c25 977#ifdef DO_EXCEPTION_RESERVEDI
bc7c5acb 978 intExceptionInsn(regs_, R3000E_RI << 2);
ef79bbde
P		 979#endif
980}
981
905b7c25 982void gteNULL(struct psxCP2Regs *regs) {
bc7c5acb 983 psxRegisters *regs_ = (psxRegisters *)((u8 *)regs - offsetof(psxRegisters, CP2));
984 psxNULLne(regs_);
905b7c25 985}
ef79bbde 986
4cc373dd 987OP(psxSPECIAL) {
988 psxSPC[_Funct_](regs_, code);
ef79bbde
P		 989}
990
4cc373dd 991OP(psxCOP0) {
3d1c03e7 992 u32 rs = _Rs_;
993 if (rs & 0x10) {
994 u32 op2 = code & 0x1f;
995 switch (op2) {
996 case 0x01:
997 case 0x02:
998 case 0x06:
999 case 0x08: psxNULL(regs_, code); break;
1000 case 0x10: psxRFE(regs_, code); break;
1001 default: psxNULLne(regs_); break;
1002 }
1003 return;
1004 }
1005 switch (rs) {
4cc373dd 1006 case 0x00: psxMFC0(regs_, code); break;
4cc373dd 1007 case 0x04: psxMTC0(regs_, code); break;
3d1c03e7 1008 case 0x02: // CFC
1009 case 0x06: psxNULL(regs_, code); break; // CTC -> exception
1010 case 0x08:
1011 case 0x0c: log_unhandled("BC0 %08x @%08x\n", code, regs_->pc - 4);
bc7c5acb 1012 default: psxNULLne(regs_); break;
4cc373dd 1013 }
ef79bbde
P		 1014}
1015
905b7c25 1016OP(psxCOP1) {
1017 // ??? what actually happens here?
bc7c5acb 1018 log_unhandled("COP1 %08x @%08x\n", code, regs_->pc - 4);
905b7c25 1019}
1020
4cc373dd 1021OP(psxCOP2) {
3d1c03e7 1022 u32 rt = _Rt_, rd = _Rd_, rs = _Rs_;
1023 if (rs & 0x10) {
1024 psxCP2[_Funct_](&regs_->CP2);
1025 return;
1026 }
1027 switch (rs) {
1028 case 0x00: doLoad(regs_, rt, MFC2(&regs_->CP2, rd)); break; // MFC2
1029 case 0x02: doLoad(regs_, rt, regs_->CP2C.r[rd]); break; // CFC2
1030 case 0x04: MTC2(&regs_->CP2, regs_->GPR.r[rt], rd); break; // MTC2
1031 case 0x06: CTC2(&regs_->CP2, regs_->GPR.r[rt], rd); break; // CTC2
1032 case 0x08:
1033 case 0x0c: log_unhandled("BC2 %08x @%08x\n", code, regs_->pc - 4);
1034 default: psxNULLne(regs_); break;
1035 }
32631e6a 1036}
1037
4cc373dd 1038OP(psxCOP2_stall) {
81dbbf4c 1039 u32 f = _Funct_;
32631e6a 1040 gteCheckStall(f);
3d1c03e7 1041 psxCOP2(regs_, code);
4cc373dd 1042}
1043
1044OP(gteLWC2) {
1045 MTC2(&regs_->CP2, psxMemRead32(_oB_), _Rt_);
1046}
1047
4cc373dd 1048OP(gteLWC2_stall) {
1049 gteCheckStall(0);
1050 gteLWC2(regs_, code);
ef79bbde
P		 1051}
1052
bc7c5acb 1053OP(gteLWC2e_stall) {
1054 gteCheckStall(0);
1055 if (checkLD(regs_, _oB_, 3))
1056 MTC2(&regs_->CP2, psxMemRead32(_oB_), _Rt_);
1057}
1058
1059OP(gteSWC2) {
1060 psxMemWrite32(_oB_, MFC2(&regs_->CP2, _Rt_));
1061}
1062
4cc373dd 1063OP(gteSWC2_stall) {
1064 gteCheckStall(0);
1065 gteSWC2(regs_, code);
1066}
1067
bc7c5acb 1068OP(gteSWC2e_stall) {
1069 gteCheckStall(0);
1070 if (checkST(regs_, _oB_, 3))
1071 gteSWC2(regs_, code);
1072}
1073
905b7c25 1074OP(psxCOP3) {
1075 // ??? what actually happens here?
bc7c5acb 1076 log_unhandled("COP3 %08x @%08x\n", code, regs_->pc - 4);
905b7c25 1077}
1078
bc7c5acb 1079OP(psxCOPd) {
1080 log_unhandled("disabled cop%d @%08x\n", (code >> 26) & 3, regs_->pc - 4);
905b7c25 1081#ifdef DO_EXCEPTION_RESERVEDI
bc7c5acb 1082 intExceptionInsn(regs_, R3000E_CpU << 2);
905b7c25 1083#endif
1084}
1085
1086OP(psxLWCx) {
bc7c5acb 1087 log_unhandled("LWCx %08x @%08x\n", code, regs_->pc - 4);
1088 checkLD(regs_, _oB_, 3);
905b7c25 1089}
1090
1091OP(psxSWCx) {
1092 // does this write something to memory?
bc7c5acb 1093 log_unhandled("SWCx %08x @%08x\n", code, regs_->pc - 4);
1094 checkST(regs_, _oB_, 3);
905b7c25 1095}
1096
4cc373dd 1097OP(psxREGIMM) {
19fae7fc 1098 u32 rt = _Rt_;
1099 switch (rt) {
4cc373dd 1100 case 0x10: psxBLTZAL(regs_, code); break;
1101 case 0x11: psxBGEZAL(regs_, code); break;
19fae7fc 1102 default:
1103 if (rt & 1)
1104 psxBGEZ(regs_, code);
1105 else
1106 psxBLTZ(regs_, code);
4cc373dd 1107 }
ef79bbde
P		 1108}
1109
4cc373dd 1110OP(psxHLE) {
905b7c25 1111 u32 hleCode;
1112 if (unlikely(!Config.HLE)) {
1113 psxSWCx(regs_, code);
1114 return;
1115 }
1116 hleCode = code & 0x03ffffff;
1117 if (hleCode >= (sizeof(psxHLEt) / sizeof(psxHLEt[0]))) {
1118 psxSWCx(regs_, code);
1119 return;
1120 }
1121 psxHLEt[hleCode]();
dc4fa8bc 1122 branchSeen = 1;
ef79bbde
P		 1123}
1124
4cc373dd 1125static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code) = {
ef79bbde
P		 1126 psxSPECIAL, psxREGIMM, psxJ , psxJAL , psxBEQ , psxBNE , psxBLEZ, psxBGTZ,
1127 psxADDI , psxADDIU , psxSLTI, psxSLTIU, psxANDI, psxORI , psxXORI, psxLUI ,
bc7c5acb 1128 psxCOP0 , psxCOPd , psxCOP2, psxCOPd, psxNULL, psxNULL, psxNULL, psxNULL,
1129 psxNULL , psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL,
1130 psxLB , psxLH , psxLWL , psxLW , psxLBU , psxLHU , psxLWR , psxNULL,
1131 psxSB , psxSH , psxSWL , psxSW , psxNULL, psxNULL, psxSWR , psxNULL,
1132 psxLWCx , psxLWCx , gteLWC2, psxLWCx , psxNULL, psxNULL, psxNULL, psxNULL,
1133 psxSWCx , psxSWCx , gteSWC2, psxHLE , psxNULL, psxNULL, psxNULL, psxNULL,
ef79bbde
P		 1134};
1135
4cc373dd 1136static void (INT_ATTR *psxSPC[64])(psxRegisters *regs_, u32 code) = {
ef79bbde
P		 1137 psxSLL , psxNULL , psxSRL , psxSRA , psxSLLV , psxNULL , psxSRLV, psxSRAV,
1138 psxJR , psxJALR , psxNULL, psxNULL, psxSYSCALL, psxBREAK, psxNULL, psxNULL,
1139 psxMFHI, psxMTHI , psxMFLO, psxMTLO, psxNULL , psxNULL , psxNULL, psxNULL,
1140 psxMULT, psxMULTU, psxDIV , psxDIVU, psxNULL , psxNULL , psxNULL, psxNULL,
1141 psxADD , psxADDU , psxSUB , psxSUBU, psxAND , psxOR , psxXOR , psxNOR ,
1142 psxNULL, psxNULL , psxSLT , psxSLTU, psxNULL , psxNULL , psxNULL, psxNULL,
1143 psxNULL, psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, psxNULL,
1144 psxNULL, psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, psxNULL
1145};
1146
6c0eefaf 1147void (*psxCP2[64])(struct psxCP2Regs *regs) = {
3d1c03e7 1148 gteNULL , gteRTPS , gteNULL , gteNULL, gteNULL, gteNULL , gteNCLIP, gteNULL, // 00
4cc373dd 1149 gteNULL , gteNULL , gteNULL , gteNULL, gteOP , gteNULL , gteNULL , gteNULL, // 08
1150 gteDPCS , gteINTPL, gteMVMVA, gteNCDS, gteCDP , gteNULL , gteNCDT , gteNULL, // 10
1151 gteNULL , gteNULL , gteNULL , gteNCCS, gteCC , gteNULL , gteNCS , gteNULL, // 18
1152 gteNCT , gteNULL , gteNULL , gteNULL, gteNULL, gteNULL , gteNULL , gteNULL, // 20
1153 gteSQR , gteDCPL , gteDPCT , gteNULL, gteNULL, gteAVSZ3, gteAVSZ4, gteNULL, // 28
1154 gteRTPT , gteNULL , gteNULL , gteNULL, gteNULL, gteNULL , gteNULL , gteNULL, // 30
1155 gteNULL , gteNULL , gteNULL , gteNULL, gteNULL, gteGPF , gteGPL , gteNCCT // 38
ef79bbde
P		 1156};
1157
ef79bbde
P		 1158///////////////////////////////////////////
1159
1160static int intInit() {
1161 return 0;
1162}
1163
1164static void intReset() {
f9ae4f29 1165 dloadClear(&psxRegs);
3d1c03e7 1166 psxRegs.subCycle = 0;
ef79bbde
P		 1167}
1168
bc7c5acb 1169static inline void execI_(u8 **memRLUT, psxRegisters *regs) {
1170 u32 pc = regs->pc;
905b7c25 1171
bc7c5acb 1172 addCycle(regs);
1173 dloadStep(regs);
4cc373dd 1174
bc7c5acb 1175 regs->pc += 4;
1176 regs->code = fetch(regs, memRLUT, pc);
1177 psxBSC[regs->code >> 26](regs, regs->code);
1178}
1179
1180static inline void execIbp(u8 **memRLUT, psxRegisters *regs) {
1181 u32 pc = regs->pc;
1182
1183 addCycle(regs);
1184 dloadStep(regs);
1185
1186 if (execBreakCheck(regs, pc))
1187 return;
1188
1189 regs->pc += 4;
1190 regs->code = fetch(regs, memRLUT, pc);
1191 psxBSC[regs->code >> 26](regs, regs->code);
4cc373dd 1192}
1193
1194static void intExecute() {
1195 psxRegisters *regs_ = &psxRegs;
1196 u8 **memRLUT = psxMemRLUT;
796a91ef 1197 extern int stop;
4cc373dd 1198
1199 while (!stop)
1200 execI_(memRLUT, regs_);
ef79bbde
P		 1201}
1202
bc7c5acb 1203static void intExecuteBp() {
1204 psxRegisters *regs_ = &psxRegs;
1205 u8 **memRLUT = psxMemRLUT;
1206 extern int stop;
1207
1208 while (!stop)
1209 execIbp(memRLUT, regs_);
1210}
1211
da65071f 1212void intExecuteBlock(enum blockExecCaller caller) {
4cc373dd 1213 psxRegisters *regs_ = &psxRegs;
1214 u8 **memRLUT = psxMemRLUT;
1215
bc7c5acb 1216 branchSeen = 0;
1217 while (!branchSeen)
4cc373dd 1218 execI_(memRLUT, regs_);
ef79bbde
P		 1219}
1220
1221static void intClear(u32 Addr, u32 Size) {
1222}
1223
980f7a58 1224static void intNotify(enum R3000Anote note, void *data) {
1225 switch (note) {
f9ae4f29 1226 case R3000ACPU_NOTIFY_BEFORE_SAVE:
1227 dloadFlush(&psxRegs);
1228 break;
980f7a58 1229 case R3000ACPU_NOTIFY_AFTER_LOAD:
f9ae4f29 1230 dloadClear(&psxRegs);
3d1c03e7 1231 psxRegs.subCycle = 0;
bc7c5acb 1232 setupCop(psxRegs.CP0.n.SR);
905b7c25 1233 // fallthrough
1234 case R3000ACPU_NOTIFY_CACHE_ISOLATED: // Armored Core?
9f84fc93 1235 memset(&ICache, 0xff, sizeof(ICache));
980f7a58 1236 break;
1237 case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
980f7a58 1238 break;
943a507a 1239 }
943a507a 1240}
1241
905b7c25 1242static void setupCop(u32 sr)
1243{
1244 if (sr & (1u << 29))
1245 psxBSC[17] = psxCOP1;
1246 else
bc7c5acb 1247 psxBSC[17] = psxCOPd;
905b7c25 1248 if (sr & (1u << 30))
1249 psxBSC[18] = Config.DisableStalls ? psxCOP2 : psxCOP2_stall;
1250 else
bc7c5acb 1251 psxBSC[18] = psxCOPd;
905b7c25 1252 if (sr & (1u << 31))
1253 psxBSC[19] = psxCOP3;
1254 else
bc7c5acb 1255 psxBSC[19] = psxCOPd;
905b7c25 1256}
1257
61ad2a61 1258void intApplyConfig() {
d5aeda23 1259 int cycle_mult;
1260
32631e6a 1261 assert(psxSPC[16] == psxMFHI || psxSPC[16] == psxMFHI_stall);
1262 assert(psxSPC[18] == psxMFLO || psxSPC[18] == psxMFLO_stall);
1263 assert(psxSPC[24] == psxMULT || psxSPC[24] == psxMULT_stall);
1264 assert(psxSPC[25] == psxMULTU || psxSPC[25] == psxMULTU_stall);
1265 assert(psxSPC[26] == psxDIV || psxSPC[26] == psxDIV_stall);
1266 assert(psxSPC[27] == psxDIVU || psxSPC[27] == psxDIVU_stall);
1267
1268 if (Config.DisableStalls) {
1269 psxBSC[18] = psxCOP2;
1270 psxBSC[50] = gteLWC2;
1271 psxBSC[58] = gteSWC2;
1272 psxSPC[16] = psxMFHI;
1273 psxSPC[18] = psxMFLO;
1274 psxSPC[24] = psxMULT;
1275 psxSPC[25] = psxMULTU;
1276 psxSPC[26] = psxDIV;
1277 psxSPC[27] = psxDIVU;
1278 } else {
1279 psxBSC[18] = psxCOP2_stall;
1280 psxBSC[50] = gteLWC2_stall;
1281 psxBSC[58] = gteSWC2_stall;
1282 psxSPC[16] = psxMFHI_stall;
1283 psxSPC[18] = psxMFLO_stall;
1284 psxSPC[24] = psxMULT_stall;
1285 psxSPC[25] = psxMULTU_stall;
1286 psxSPC[26] = psxDIV_stall;
1287 psxSPC[27] = psxDIVU_stall;
1288 }
bc7c5acb 1289 setupCop(psxRegs.CP0.n.SR);
1290
1291 if (Config.PreciseExceptions) {
1292 psxBSC[0x20] = psxLBe;
1293 psxBSC[0x21] = psxLHe;
1294 psxBSC[0x22] = psxLWLe;
1295 psxBSC[0x23] = psxLWe;
1296 psxBSC[0x24] = psxLBUe;
1297 psxBSC[0x25] = psxLHUe;
1298 psxBSC[0x26] = psxLWRe;
1299 psxBSC[0x28] = psxSBe;
1300 psxBSC[0x29] = psxSHe;
1301 psxBSC[0x2a] = psxSWLe;
1302 psxBSC[0x2b] = psxSWe;
1303 psxBSC[0x2e] = psxSWRe;
1304 psxBSC[0x32] = gteLWC2e_stall;
1305 psxBSC[0x3a] = gteSWC2e_stall;
1306 psxSPC[0x08] = psxJRe;
1307 psxSPC[0x09] = psxJALRe;
1308 psxInt.Execute = intExecuteBp;
1309 } else {
1310 psxBSC[0x20] = psxLB;
1311 psxBSC[0x21] = psxLH;
1312 psxBSC[0x22] = psxLWL;
1313 psxBSC[0x23] = psxLW;
1314 psxBSC[0x24] = psxLBU;
1315 psxBSC[0x25] = psxLHU;
1316 psxBSC[0x26] = psxLWR;
1317 psxBSC[0x28] = psxSB;
1318 psxBSC[0x29] = psxSH;
1319 psxBSC[0x2a] = psxSWL;
1320 psxBSC[0x2b] = psxSW;
1321 psxBSC[0x2e] = psxSWR;
1322 // LWC2, SWC2 handled by Config.DisableStalls
1323 psxSPC[0x08] = psxJR;
1324 psxSPC[0x09] = psxJALR;
1325 psxInt.Execute = intExecute;
1326 }
61ad2a61 1327
bc7c5acb 1328 // the dynarec may occasionally call the interpreter, in such a case the
61ad2a61 1329 // cache won't work (cache only works right if all fetches go through it)
1330 if (!Config.icache_emulation || psxCpu != &psxInt)
1331 fetch = fetchNoCache;
1332 else
1333 fetch = fetchICache;
d5aeda23 1334
1335 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
1336 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
1337 psxRegs.subCycleStep = 0x10000 * cycle_mult / 100;
32631e6a 1338}
1339
ef79bbde 1340static void intShutdown() {
a5cd72d0 1341 dloadClear(&psxRegs);
ef79bbde
P		 1342}
1343
a5cd72d0 1344// single step (may do several ops in case of a branch or load delay)
de6dbc52 1345// called by asm/dynarec
bc7c5acb 1346void execI(psxRegisters *regs) {
a5cd72d0 1347 do {
1348 execIbp(psxMemRLUT, regs);
1349 } while (regs->dloadReg[0] || regs->dloadReg[1]);
ef79bbde
P		 1350}
1351
1352R3000Acpu psxInt = {
1353 intInit,
1354 intReset,
1355 intExecute,
1356 intExecuteBlock,
1357 intClear,
943a507a 1358 intNotify,
61ad2a61 1359 intApplyConfig,
ef79bbde
P		 1360 intShutdown
1361};
ARM optimized PCSX fork