[pcsx_rearmed.git] / libpcsxcore / r3000a.h

/***************************************************************************
 *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
 ***************************************************************************/

#ifndef __R3000A_H__
#define __R3000A_H__

#ifdef __cplusplus
extern "C" {
#endif

#include "psxcommon.h"
#include "psxmem.h"
#include "psxcounters.h"
#include "psxbios.h"

#ifdef ICACHE_EMULATION
enum {
	R3000ACPU_NOTIFY_CACHE_ISOLATED = 0,
	R3000ACPU_NOTIFY_CACHE_UNISOLATED = 1,
	R3000ACPU_NOTIFY_DMA3_EXE_LOAD = 2
};
extern uint32_t *Read_ICache(uint32_t pc);
#endif

typedef struct {
	int  (*Init)();
	void (*Reset)();
	void (*Execute)();		/* executes up to a break */
	void (*ExecuteBlock)();	/* executes up to a jump */
	void (*Clear)(u32 Addr, u32 Size);
#ifdef ICACHE_EMULATION
	void (*Notify)(int note, void *data);
#endif
	void (*ApplyConfig)();
	void (*Shutdown)();
} R3000Acpu;

extern R3000Acpu *psxCpu;
extern R3000Acpu psxInt;
extern R3000Acpu psxRec;

typedef union {
#if defined(__BIGENDIAN__)
	struct { u8 h3, h2, h, l; } b;
	struct { s8 h3, h2, h, l; } sb;
	struct { u16 h, l; } w;
	struct { s16 h, l; } sw;
#else
	struct { u8 l, h, h2, h3; } b;
	struct { u16 l, h; } w;
	struct { s8 l, h, h2, h3; } sb;
	struct { s16 l, h; } sw;
#endif
} PAIR;

typedef union {
	struct {
		u32   r0, at, v0, v1, a0, a1, a2, a3,
						t0, t1, t2, t3, t4, t5, t6, t7,
						s0, s1, s2, s3, s4, s5, s6, s7,
						t8, t9, k0, k1, gp, sp, s8, ra, lo, hi;
	} n;
	u32 r[34]; /* Lo, Hi in r[32] and r[33] */
	PAIR p[34];
} psxGPRRegs;

typedef union {
	struct {
		u32	Index,     Random,    EntryLo0,  EntryLo1,
						Context,   PageMask,  Wired,     Reserved0,
						BadVAddr,  Count,     EntryHi,   Compare,
						Status,    Cause,     EPC,       PRid,
						Config,    LLAddr,    WatchLO,   WatchHI,
						XContext,  Reserved1, Reserved2, Reserved3,
						Reserved4, Reserved5, ECC,       CacheErr,
						TagLo,     TagHi,     ErrorEPC,  Reserved6;
	} n;
	u32 r[32];
	PAIR p[32];
} psxCP0Regs;

typedef struct {
	short x, y;
} SVector2D;

typedef struct {
	short z, pad;
} SVector2Dz;

typedef struct {
	short x, y, z, pad;
} SVector3D;

typedef struct {
	short x, y, z, pad;
} LVector3D;

typedef struct {
	unsigned char r, g, b, c;
} CBGR;

typedef struct {
	short m11, m12, m13, m21, m22, m23, m31, m32, m33, pad;
} SMatrix3D;

typedef union {
	struct {
		SVector3D     v0, v1, v2;
		CBGR          rgb;
		s32          otz;
		s32          ir0, ir1, ir2, ir3;
		SVector2D     sxy0, sxy1, sxy2, sxyp;
		SVector2Dz    sz0, sz1, sz2, sz3;
		CBGR          rgb0, rgb1, rgb2;
		s32          reserved;
		s32          mac0, mac1, mac2, mac3;
		u32 irgb, orgb;
		s32          lzcs, lzcr;
	} n;
	u32 r[32];
	PAIR p[32];
} psxCP2Data;

typedef union {
	struct {
		SMatrix3D rMatrix;
		s32      trX, trY, trZ;
		SMatrix3D lMatrix;
		s32      rbk, gbk, bbk;
		SMatrix3D cMatrix;
		s32      rfc, gfc, bfc;
		s32      ofx, ofy;
		s32      h;
		s32      dqa, dqb;
		s32      zsf3, zsf4;
		s32      flag;
	} n;
	u32 r[32];
	PAIR p[32];
} psxCP2Ctrl;

enum {
	PSXINT_SIO = 0,
	PSXINT_CDR,
	PSXINT_CDREAD,
	PSXINT_GPUDMA,
	PSXINT_MDECOUTDMA,
	PSXINT_SPUDMA,
	PSXINT_GPUBUSY,
	PSXINT_MDECINDMA,
	PSXINT_GPUOTCDMA,
	PSXINT_CDRDMA,
	PSXINT_NEWDRC_CHECK,
	PSXINT_RCNT,
	PSXINT_CDRLID,
	PSXINT_CDRPLAY,
	PSXINT_SPU_UPDATE,
	PSXINT_COUNT
};

typedef struct psxCP2Regs {
	psxCP2Data CP2D; 	/* Cop2 data registers */
	psxCP2Ctrl CP2C; 	/* Cop2 control registers */
} psxCP2Regs;

typedef struct {
	psxGPRRegs GPR;		/* General Purpose Registers */
	psxCP0Regs CP0;		/* Coprocessor0 Registers */
	union {
		struct {
			psxCP2Data CP2D; 	/* Cop2 data registers */
			psxCP2Ctrl CP2C; 	/* Cop2 control registers */
		};
		psxCP2Regs CP2;
	};
    u32 pc;				/* Program counter */
    u32 code;			/* The instruction */
	u32 cycle;
	u32 interrupt;
	struct { u32 sCycle, cycle; } intCycle[32];
	u32 gteBusyCycle;
	u32 muldivBusyCycle;
	// warning: changing anything in psxRegisters requires update of all
	// asm in libpcsxcore/new_dynarec/, but this member can be replaced
	u32 reserved[2];
} psxRegisters;

extern psxRegisters psxRegs;

/* new_dynarec stuff */
extern u32 event_cycles[PSXINT_COUNT];
extern u32 next_interupt;

void new_dyna_before_save(void);
void new_dyna_after_save(void);
void new_dyna_freeze(void *f, int mode);

#define new_dyna_set_event(e, c) { \
	s32 c_ = c; \
	u32 abs_ = psxRegs.cycle + c_; \
	s32 odi_ = next_interupt - psxRegs.cycle; \
	event_cycles[e] = abs_; \
	if (c_ < odi_) { \
		/*printf("%u: next_interupt %d -> %d (%u)\n", psxRegs.cycle, odi_, c_, abs_);*/ \
		next_interupt = abs_; \
	} \
}

#if defined(__BIGENDIAN__)

#define _i32(x) *(s32 *)&x
#define _u32(x) x

#define _i16(x) (((short *)&x)[1])
#define _u16(x) (((unsigned short *)&x)[1])

#define _i8(x) (((char *)&x)[3])
#define _u8(x) (((unsigned char *)&x)[3])

#else

#define _i32(x) *(s32 *)&x
#define _u32(x) x

#define _i16(x) *(short *)&x
#define _u16(x) *(unsigned short *)&x

#define _i8(x) *(char *)&x
#define _u8(x) *(unsigned char *)&x

#endif

/**** R3000A Instruction Macros ****/
#define _PC_       psxRegs.pc       // The next PC to be executed

#define _fOp_(code)		((code >> 26)       )  // The opcode part of the instruction register 
#define _fFunct_(code)	((code      ) & 0x3F)  // The funct part of the instruction register 
#define _fRd_(code)		((code >> 11) & 0x1F)  // The rd part of the instruction register 
#define _fRt_(code)		((code >> 16) & 0x1F)  // The rt part of the instruction register 
#define _fRs_(code)		((code >> 21) & 0x1F)  // The rs part of the instruction register 
#define _fSa_(code)		((code >>  6) & 0x1F)  // The sa part of the instruction register
#define _fIm_(code)		((u16)code)            // The immediate part of the instruction register
#define _fTarget_(code)	(code & 0x03ffffff)    // The target part of the instruction register

#define _fImm_(code)	((s16)code)            // sign-extended immediate
#define _fImmU_(code)	(code&0xffff)          // zero-extended immediate

#define _Op_     _fOp_(psxRegs.code)
#define _Funct_  _fFunct_(psxRegs.code)
#define _Rd_     _fRd_(psxRegs.code)
#define _Rt_     _fRt_(psxRegs.code)
#define _Rs_     _fRs_(psxRegs.code)
#define _Sa_     _fSa_(psxRegs.code)
#define _Im_     _fIm_(psxRegs.code)
#define _Target_ _fTarget_(psxRegs.code)

#define _Imm_	 _fImm_(psxRegs.code)
#define _ImmU_	 _fImmU_(psxRegs.code)

#define _rRs_   psxRegs.GPR.r[_Rs_]   // Rs register
#define _rRt_   psxRegs.GPR.r[_Rt_]   // Rt register
#define _rRd_   psxRegs.GPR.r[_Rd_]   // Rd register
#define _rSa_   psxRegs.GPR.r[_Sa_]   // Sa register
#define _rFs_   psxRegs.CP0.r[_Rd_]   // Fs register

#define _c2dRs_ psxRegs.CP2D.r[_Rs_]  // Rs cop2 data register
#define _c2dRt_ psxRegs.CP2D.r[_Rt_]  // Rt cop2 data register
#define _c2dRd_ psxRegs.CP2D.r[_Rd_]  // Rd cop2 data register
#define _c2dSa_ psxRegs.CP2D.r[_Sa_]  // Sa cop2 data register

#define _rHi_   psxRegs.GPR.n.hi   // The HI register
#define _rLo_   psxRegs.GPR.n.lo   // The LO register

#define _JumpTarget_    ((_Target_ * 4) + (_PC_ & 0xf0000000))   // Calculates the target during a jump instruction
#define _BranchTarget_  ((s16)_Im_ * 4 + _PC_)                 // Calculates the target during a branch instruction

#define _SetLink(x)     psxRegs.GPR.r[x] = _PC_ + 4;       // Sets the return address in the link register

int  psxInit();
void psxReset();
void psxShutdown();
void psxException(u32 code, u32 bd);
void psxBranchTest();
void psxExecuteBios();
int  psxTestLoadDelay(int reg, u32 tmp);
void psxDelayTest(int reg, u32 bpc);
void psxTestSWInts();
void psxJumpTest();

#ifdef __cplusplus
}
#endif
#endif
Commit	Line	Data
ef79bbde P	1	/***************************************************************************
	2	* Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
	3	* *
	4	* This program is free software; you can redistribute it and/or modify *
	5	* it under the terms of the GNU General Public License as published by *
	6	* the Free Software Foundation; either version 2 of the License, or *
	7	* (at your option) any later version. *
	8	* *
	9	* This program is distributed in the hope that it will be useful, *
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	12	* GNU General Public License for more details. *
	13	* *
	14	* You should have received a copy of the GNU General Public License *
	15	* along with this program; if not, write to the *
	16	* Free Software Foundation, Inc., *
	17	* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
	18	***************************************************************************/
	19
	20	#ifndef __R3000A_H__
	21	#define __R3000A_H__
	22
	23	#ifdef __cplusplus
	24	extern "C" {
	25	#endif
	26
	27	#include "psxcommon.h"
	28	#include "psxmem.h"
	29	#include "psxcounters.h"
	30	#include "psxbios.h"
	31
943a507a	32	#ifdef ICACHE_EMULATION
	33	enum {
	34	R3000ACPU_NOTIFY_CACHE_ISOLATED = 0,
	35	R3000ACPU_NOTIFY_CACHE_UNISOLATED = 1,
	36	R3000ACPU_NOTIFY_DMA3_EXE_LOAD = 2
	37	};
	38	extern uint32_t *Read_ICache(uint32_t pc);
	39	#endif
	40
ef79bbde P	41	typedef struct {
	42	int (*Init)();
	43	void (*Reset)();
	44	void (Execute)(); / executes up to a break */
	45	void (ExecuteBlock)(); / executes up to a jump */
	46	void (*Clear)(u32 Addr, u32 Size);
943a507a	47	#ifdef ICACHE_EMULATION
	48	void (Notify)(int note, void data);
	49	#endif
32631e6a	50	void (*ApplyConfig)();
ef79bbde P	51	void (*Shutdown)();
	52	} R3000Acpu;
	53
	54	extern R3000Acpu *psxCpu;
	55	extern R3000Acpu psxInt;
ef79bbde	56	extern R3000Acpu psxRec;
ef79bbde P	57
	58	typedef union {
	59	#if defined(__BIGENDIAN__)
	60	struct { u8 h3, h2, h, l; } b;
	61	struct { s8 h3, h2, h, l; } sb;
	62	struct { u16 h, l; } w;
	63	struct { s16 h, l; } sw;
	64	#else
	65	struct { u8 l, h, h2, h3; } b;
	66	struct { u16 l, h; } w;
	67	struct { s8 l, h, h2, h3; } sb;
	68	struct { s16 l, h; } sw;
	69	#endif
	70	} PAIR;
	71
	72	typedef union {
	73	struct {
	74	u32 r0, at, v0, v1, a0, a1, a2, a3,
	75	t0, t1, t2, t3, t4, t5, t6, t7,
	76	s0, s1, s2, s3, s4, s5, s6, s7,
	77	t8, t9, k0, k1, gp, sp, s8, ra, lo, hi;
	78	} n;
	79	u32 r[34]; /* Lo, Hi in r[32] and r[33] */
	80	PAIR p[34];
	81	} psxGPRRegs;
	82
	83	typedef union {
	84	struct {
	85	u32 Index, Random, EntryLo0, EntryLo1,
	86	Context, PageMask, Wired, Reserved0,
	87	BadVAddr, Count, EntryHi, Compare,
	88	Status, Cause, EPC, PRid,
	89	Config, LLAddr, WatchLO, WatchHI,
	90	XContext, Reserved1, Reserved2, Reserved3,
	91	Reserved4, Reserved5, ECC, CacheErr,
	92	TagLo, TagHi, ErrorEPC, Reserved6;
	93	} n;
	94	u32 r[32];
	95	PAIR p[32];
	96	} psxCP0Regs;
	97
	98	typedef struct {
	99	short x, y;
	100	} SVector2D;
	101
	102	typedef struct {
	103	short z, pad;
	104	} SVector2Dz;
	105
	106	typedef struct {
	107	short x, y, z, pad;
	108	} SVector3D;
	109
	110	typedef struct {
	111	short x, y, z, pad;
	112	} LVector3D;
	113
	114	typedef struct {
	115	unsigned char r, g, b, c;
	116	} CBGR;
	117
	118	typedef struct {
	119	short m11, m12, m13, m21, m22, m23, m31, m32, m33, pad;
	120	} SMatrix3D;
121
122	typedef union {
123	struct {
124	SVector3D v0, v1, v2;
125	CBGR rgb;
126	s32 otz;
127	s32 ir0, ir1, ir2, ir3;
128	SVector2D sxy0, sxy1, sxy2, sxyp;
129	SVector2Dz sz0, sz1, sz2, sz3;
130	CBGR rgb0, rgb1, rgb2;
131	s32 reserved;
132	s32 mac0, mac1, mac2, mac3;
133	u32 irgb, orgb;
134	s32 lzcs, lzcr;
135	} n;
136	u32 r[32];
137	PAIR p[32];
138	} psxCP2Data;
139
140	typedef union {
141	struct {
142	SMatrix3D rMatrix;
143	s32 trX, trY, trZ;
144	SMatrix3D lMatrix;
145	s32 rbk, gbk, bbk;
146	SMatrix3D cMatrix;
147	s32 rfc, gfc, bfc;
148	s32 ofx, ofy;
149	s32 h;
150	s32 dqa, dqb;
151	s32 zsf3, zsf4;
152	s32 flag;
153	} n;
154	u32 r[32];
155	PAIR p[32];
156	} psxCP2Ctrl;
157
d28b54b1	158	enum {
	159	PSXINT_SIO = 0,
	160	PSXINT_CDR,
	161	PSXINT_CDREAD,
	162	PSXINT_GPUDMA,
	163	PSXINT_MDECOUTDMA,
	164	PSXINT_SPUDMA,
528ad661	165	PSXINT_GPUBUSY,
528ad661	166	PSXINT_MDECINDMA,
57a757ce	167	PSXINT_GPUOTCDMA,
9f8b032d	168	PSXINT_CDRDMA,
d28b54b1	169	PSXINT_NEWDRC_CHECK,
5b8c000f	170	PSXINT_RCNT,
9f8b032d	171	PSXINT_CDRLID,
7f457614	172	PSXINT_CDRPLAY,
2b30c129	173	PSXINT_SPU_UPDATE,
d28b54b1	174	PSXINT_COUNT
	175	};
	176
eac38522	177	typedef struct psxCP2Regs {
	178	psxCP2Data CP2D; /* Cop2 data registers */
	179	psxCP2Ctrl CP2C; /* Cop2 control registers */
	180	} psxCP2Regs;
	181
ef79bbde P	182	typedef struct {
	183	psxGPRRegs GPR; /* General Purpose Registers */
	184	psxCP0Regs CP0; /* Coprocessor0 Registers */
eac38522	185	union {
	186	struct {
	187	psxCP2Data CP2D; /* Cop2 data registers */
	188	psxCP2Ctrl CP2C; /* Cop2 control registers */
	189	};
	190	psxCP2Regs CP2;
	191	};
ef79bbde P	192	u32 pc; /* Program counter */
	193	u32 code; /* The instruction */
	194	u32 cycle;
	195	u32 interrupt;
d28b54b1	196	struct { u32 sCycle, cycle; } intCycle[32];
81dbbf4c	197	u32 gteBusyCycle;
32631e6a	198	u32 muldivBusyCycle;
81dbbf4c	199	// warning: changing anything in psxRegisters requires update of all
81dbbf4c	200	// asm in libpcsxcore/new_dynarec/, but this member can be replaced
32631e6a	201	u32 reserved[2];
ef79bbde P	202	} psxRegisters;
	203
	204	extern psxRegisters psxRegs;
	205
d28b54b1	206	/* new_dynarec stuff */
	207	extern u32 event_cycles[PSXINT_COUNT];
	208	extern u32 next_interupt;
	209
03f55e6b	210	void new_dyna_before_save(void);
5b8c000f	211	void new_dyna_after_save(void);
03f55e6b	212	void new_dyna_freeze(void *f, int mode);
52082bc1	213
d28b54b1	214	#define new_dyna_set_event(e, c) { \
	215	s32 c_ = c; \
	216	u32 abs_ = psxRegs.cycle + c_; \
	217	s32 odi_ = next_interupt - psxRegs.cycle; \
	218	event_cycles[e] = abs_; \
	219	if (c_ < odi_) { \
	220	/printf("%u: next_interupt %d -> %d (%u)\n", psxRegs.cycle, odi_, c_, abs_);/ \
	221	next_interupt = abs_; \
	222	} \
	223	}
	224
ef79bbde P	225	#if defined(__BIGENDIAN__)
	226
	227	#define _i32(x) (s32 )&x
	228	#define _u32(x) x
	229
	230	#define _i16(x) (((short *)&x)[1])
	231	#define _u16(x) (((unsigned short *)&x)[1])
	232
	233	#define _i8(x) (((char *)&x)[3])
	234	#define _u8(x) (((unsigned char *)&x)[3])
	235
	236	#else
	237
	238	#define _i32(x) (s32 )&x
	239	#define _u32(x) x
	240
	241	#define _i16(x) (short )&x
	242	#define _u16(x) (unsigned short )&x
	243
	244	#define _i8(x) (char )&x
	245	#define _u8(x) (unsigned char )&x
	246
	247	#endif
	248
	249	/** R3000A Instruction Macros **/
	250	#define _PC_ psxRegs.pc // The next PC to be executed
	251
	252	#define _fOp_(code) ((code >> 26) ) // The opcode part of the instruction register
	253	#define _fFunct_(code) ((code ) & 0x3F) // The funct part of the instruction register
	254	#define _fRd_(code) ((code >> 11) & 0x1F) // The rd part of the instruction register
	255	#define _fRt_(code) ((code >> 16) & 0x1F) // The rt part of the instruction register
	256	#define _fRs_(code) ((code >> 21) & 0x1F) // The rs part of the instruction register
	257	#define _fSa_(code) ((code >> 6) & 0x1F) // The sa part of the instruction register
	258	#define _fIm_(code) ((u16)code) // The immediate part of the instruction register
	259	#define _fTarget_(code) (code & 0x03ffffff) // The target part of the instruction register
	260
	261	#define _fImm_(code) ((s16)code) // sign-extended immediate
	262	#define _fImmU_(code) (code&0xffff) // zero-extended immediate
	263
	264	#define _Op_ _fOp_(psxRegs.code)
	265	#define _Funct_ _fFunct_(psxRegs.code)
	266	#define _Rd_ _fRd_(psxRegs.code)
	267	#define _Rt_ _fRt_(psxRegs.code)
	268	#define _Rs_ _fRs_(psxRegs.code)
	269	#define _Sa_ _fSa_(psxRegs.code)
	270	#define _Im_ _fIm_(psxRegs.code)
	271	#define _Target_ _fTarget_(psxRegs.code)
	272
	273	#define _Imm_ _fImm_(psxRegs.code)
	274	#define _ImmU_ _fImmU_(psxRegs.code)
	275
	276	#define _rRs_ psxRegs.GPR.r[_Rs_] // Rs register
	277	#define _rRt_ psxRegs.GPR.r[_Rt_] // Rt register
	278	#define _rRd_ psxRegs.GPR.r[_Rd_] // Rd register
	279	#define _rSa_ psxRegs.GPR.r[_Sa_] // Sa register
	280	#define _rFs_ psxRegs.CP0.r[_Rd_] // Fs register
	281
	282	#define _c2dRs_ psxRegs.CP2D.r[_Rs_] // Rs cop2 data register
	283	#define _c2dRt_ psxRegs.CP2D.r[_Rt_] // Rt cop2 data register
	284	#define _c2dRd_ psxRegs.CP2D.r[_Rd_] // Rd cop2 data register
	285	#define _c2dSa_ psxRegs.CP2D.r[_Sa_] // Sa cop2 data register
	286
	287	#define _rHi_ psxRegs.GPR.n.hi // The HI register
	288	#define _rLo_ psxRegs.GPR.n.lo // The LO register
289
290	#define _JumpTarget_ ((_Target_ * 4) + (_PC_ & 0xf0000000)) // Calculates the target during a jump instruction
291	#define _BranchTarget_ ((s16)_Im_ * 4 + _PC_) // Calculates the target during a branch instruction
292
293	#define _SetLink(x) psxRegs.GPR.r[x] = _PC_ + 4; // Sets the return address in the link register
294
295	int psxInit();
296	void psxReset();
297	void psxShutdown();
298	void psxException(u32 code, u32 bd);
299	void psxBranchTest();
300	void psxExecuteBios();
301	int psxTestLoadDelay(int reg, u32 tmp);
302	void psxDelayTest(int reg, u32 bpc);
303	void psxTestSWInts();
304	void psxJumpTest();
305
306	#ifdef __cplusplus
307	}
308	#endif
309	#endif