Merge pull request #292 from pcercuei/dfsound-big-endian
[pcsx_rearmed.git] / libpcsxcore / r3000a.h
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1/***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
19
20#ifndef __R3000A_H__
21#define __R3000A_H__
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27#include "psxcommon.h"
28#include "psxmem.h"
29#include "psxcounters.h"
30#include "psxbios.h"
31
943a507a 32enum {
33 R3000ACPU_NOTIFY_CACHE_ISOLATED = 0,
34 R3000ACPU_NOTIFY_CACHE_UNISOLATED = 1,
943a507a 35};
943a507a 36
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37typedef struct {
38 int (*Init)();
39 void (*Reset)();
40 void (*Execute)(); /* executes up to a break */
41 void (*ExecuteBlock)(); /* executes up to a jump */
42 void (*Clear)(u32 Addr, u32 Size);
943a507a 43 void (*Notify)(int note, void *data);
32631e6a 44 void (*ApplyConfig)();
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45 void (*Shutdown)();
46} R3000Acpu;
47
48extern R3000Acpu *psxCpu;
49extern R3000Acpu psxInt;
ef79bbde 50extern R3000Acpu psxRec;
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51
52typedef union {
04bd10b1 53#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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54 struct { u8 h3, h2, h, l; } b;
55 struct { s8 h3, h2, h, l; } sb;
56 struct { u16 h, l; } w;
57 struct { s16 h, l; } sw;
58#else
59 struct { u8 l, h, h2, h3; } b;
60 struct { u16 l, h; } w;
61 struct { s8 l, h, h2, h3; } sb;
62 struct { s16 l, h; } sw;
63#endif
64} PAIR;
65
66typedef union {
67 struct {
68 u32 r0, at, v0, v1, a0, a1, a2, a3,
69 t0, t1, t2, t3, t4, t5, t6, t7,
70 s0, s1, s2, s3, s4, s5, s6, s7,
71 t8, t9, k0, k1, gp, sp, s8, ra, lo, hi;
72 } n;
73 u32 r[34]; /* Lo, Hi in r[32] and r[33] */
74 PAIR p[34];
75} psxGPRRegs;
76
77typedef union {
78 struct {
79 u32 Index, Random, EntryLo0, EntryLo1,
80 Context, PageMask, Wired, Reserved0,
81 BadVAddr, Count, EntryHi, Compare,
82 Status, Cause, EPC, PRid,
83 Config, LLAddr, WatchLO, WatchHI,
84 XContext, Reserved1, Reserved2, Reserved3,
85 Reserved4, Reserved5, ECC, CacheErr,
86 TagLo, TagHi, ErrorEPC, Reserved6;
87 } n;
88 u32 r[32];
89 PAIR p[32];
90} psxCP0Regs;
91
92typedef struct {
93 short x, y;
94} SVector2D;
95
96typedef struct {
97 short z, pad;
98} SVector2Dz;
99
100typedef struct {
101 short x, y, z, pad;
102} SVector3D;
103
104typedef struct {
105 short x, y, z, pad;
106} LVector3D;
107
108typedef struct {
109 unsigned char r, g, b, c;
110} CBGR;
111
112typedef struct {
113 short m11, m12, m13, m21, m22, m23, m31, m32, m33, pad;
114} SMatrix3D;
115
116typedef union {
117 struct {
118 SVector3D v0, v1, v2;
119 CBGR rgb;
120 s32 otz;
121 s32 ir0, ir1, ir2, ir3;
122 SVector2D sxy0, sxy1, sxy2, sxyp;
123 SVector2Dz sz0, sz1, sz2, sz3;
124 CBGR rgb0, rgb1, rgb2;
125 s32 reserved;
126 s32 mac0, mac1, mac2, mac3;
127 u32 irgb, orgb;
128 s32 lzcs, lzcr;
129 } n;
130 u32 r[32];
131 PAIR p[32];
132} psxCP2Data;
133
134typedef union {
135 struct {
136 SMatrix3D rMatrix;
137 s32 trX, trY, trZ;
138 SMatrix3D lMatrix;
139 s32 rbk, gbk, bbk;
140 SMatrix3D cMatrix;
141 s32 rfc, gfc, bfc;
142 s32 ofx, ofy;
143 s32 h;
144 s32 dqa, dqb;
145 s32 zsf3, zsf4;
146 s32 flag;
147 } n;
148 u32 r[32];
149 PAIR p[32];
150} psxCP2Ctrl;
151
d28b54b1 152enum {
153 PSXINT_SIO = 0,
154 PSXINT_CDR,
155 PSXINT_CDREAD,
156 PSXINT_GPUDMA,
157 PSXINT_MDECOUTDMA,
158 PSXINT_SPUDMA,
528ad661 159 PSXINT_GPUBUSY,
160 PSXINT_MDECINDMA,
57a757ce 161 PSXINT_GPUOTCDMA,
9f8b032d 162 PSXINT_CDRDMA,
d28b54b1 163 PSXINT_NEWDRC_CHECK,
5b8c000f 164 PSXINT_RCNT,
9f8b032d 165 PSXINT_CDRLID,
d9a02493 166 PSXINT_CDRPLAY_OLD, /* unused */
2b30c129 167 PSXINT_SPU_UPDATE,
d28b54b1 168 PSXINT_COUNT
169};
170
eac38522 171typedef struct psxCP2Regs {
172 psxCP2Data CP2D; /* Cop2 data registers */
173 psxCP2Ctrl CP2C; /* Cop2 control registers */
174} psxCP2Regs;
175
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176typedef struct {
177 psxGPRRegs GPR; /* General Purpose Registers */
178 psxCP0Regs CP0; /* Coprocessor0 Registers */
eac38522 179 union {
180 struct {
181 psxCP2Data CP2D; /* Cop2 data registers */
182 psxCP2Ctrl CP2C; /* Cop2 control registers */
183 };
184 psxCP2Regs CP2;
185 };
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186 u32 pc; /* Program counter */
187 u32 code; /* The instruction */
188 u32 cycle;
189 u32 interrupt;
d28b54b1 190 struct { u32 sCycle, cycle; } intCycle[32];
81dbbf4c 191 u32 gteBusyCycle;
32631e6a 192 u32 muldivBusyCycle;
d5aeda23 193 u32 subCycle; /* interpreter cycle counting */
194 u32 subCycleStep;
679d5ee3 195 u32 biuReg;
196 u32 reserved[3];
81dbbf4c 197 // warning: changing anything in psxRegisters requires update of all
d5aeda23 198 // asm in libpcsxcore/new_dynarec/
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199} psxRegisters;
200
201extern psxRegisters psxRegs;
202
d28b54b1 203/* new_dynarec stuff */
204extern u32 event_cycles[PSXINT_COUNT];
205extern u32 next_interupt;
206
03f55e6b 207void new_dyna_before_save(void);
5b8c000f 208void new_dyna_after_save(void);
03f55e6b 209void new_dyna_freeze(void *f, int mode);
52082bc1 210
df717ca9 211#define new_dyna_set_event_abs(e, abs) { \
212 u32 abs_ = abs; \
213 s32 di_ = next_interupt - abs_; \
d28b54b1 214 event_cycles[e] = abs_; \
df717ca9 215 if (di_ > 0) { \
216 /*printf("%u: next_interupt %u -> %u\n", psxRegs.cycle, next_interupt, abs_);*/ \
d28b54b1 217 next_interupt = abs_; \
218 } \
219}
220
df717ca9 221#define new_dyna_set_event(e, c) \
222 new_dyna_set_event_abs(e, psxRegs.cycle + (c))
223
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224int psxInit();
225void psxReset();
226void psxShutdown();
227void psxException(u32 code, u32 bd);
228void psxBranchTest();
229void psxExecuteBios();
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230void psxJumpTest();
231
232#ifdef __cplusplus
233}
234#endif
235#endif