use pc-relative offsets for PIC too
[pcsx_rearmed.git] / plugins / gpu_neon / psx_gpu / psx_gpu_arm_neon.S
CommitLineData
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1/*
2 * Copyright (C) 2011 Gilead Kutnick "Exophase" <exophase@gmail.com>
59d15d23 3 * Copyright (C) 2012 GraÅžvydas Ignotas "notaz" <notasas@gmail.com>
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4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 */
15
16#define MAX_SPANS 512
17#define MAX_BLOCKS 64
18#define MAX_BLOCKS_PER_ROW 128
19
f0931e56 20#define RENDER_STATE_MASK_EVALUATE 0x20
21#define RENDER_FLAGS_MODULATE_TEXELS 0x1
22#define RENDER_FLAGS_BLEND 0x2
d5c08ed3 23#define RENDER_INTERLACE_ENABLED 0x1
f0931e56 24
cb88320b 25#include "psx_gpu_offsets.h"
75e28f62 26
cb88320b 27#define psx_gpu_b_dx_offset (psx_gpu_b_block_span_offset + 4)
75e28f62 28
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29#define edge_data_left_x_offset 0
30#define edge_data_num_blocks_offset 2
31#define edge_data_right_mask_offset 4
32#define edge_data_y_offset 6
33
ed0fd81d 34.syntax unified
35.text
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36
37#define psx_gpu r0
38#define v_a r1
39#define v_b r2
40#define v_c r3
41
42#define x0 r4
43#define x1 r5
44#define x2 r6
45#define x0_x1 r5
46#define x1_x2 r6
47#define y0 r7
48#define y1 r8
49#define y2 r9
50#define y0_y1 r7
51#define y1_y2 r8
52#define b0 r9
53#define b1 r10
54#define b2 r11
55#define b0_b1 r10
56#define b1_b2 r11
57
58
59#define area_r_s r5
60
61#define g_bx0 r2
62#define g_bx r3
63#define g_bx2 r4
64#define g_bx3 r5
65#define b_base r6
66#define g_by r8
67
68#define gs_bx r7
69#define gs_by r10
70
71#define ga_bx g_bx
72#define ga_by g_by
73
74#define gw_bx_h g_bx
75#define gw_by_h g_by
76
77#define gw_bx_l r11
78#define gw_by_l gw_bx_l
79
80#define store_a r0
81#define store_b r1
82#define store_inc r5
83
84
85#define v0 q0
86#define uvrgb0 d0
87#define x0_y0 d1
88
89#define v1 q1
90#define uvrgb1 d2
91#define x1_y1 d3
92
93#define v2 q2
94#define uvrgb2 d4
95#define x2_y2 d5
96
97#define x0_ab q3
98#define uvrg_xxxx0 q3
99#define uvrg0 d6
100#define xxxx0 d7
101
102#define x1_ab q4
103#define uvrg_xxxx1 q4
104#define uvrg1 d8
105#define xxxx1 d9
106
107#define x2_ab q5
108#define uvrg_xxxx2 q5
109#define uvrg2 d10
110#define xxxx2 d11
111
112#define y0_ab q6
113#define yyyy_uvrg0 q6
114#define yyyy0 d12
115#define uvrg0b d13
116
117#define y1_ab q7
118#define yyyy_uvrg1 q7
119#define yyyy1 d14
120#define uvrg1b d15
121
122#define y2_ab q8
123#define yyyy_uvrg2 q8
124#define yyyy2 d16
125#define uvrg2b d17
126
127#define d0_ab q9
128#define d0_a d18
129#define d0_b d19
130
131#define d1_ab q10
132#define d1_a d20
133#define d1_b d21
134
135#define d2_ab q11
136#define d2_a d22
137#define d2_b d23
138
139#define d3_ab q12
140#define d3_a d24
141#define d3_b d25
142
143#define ga_uvrg_x q1
144#define ga_uvrg_y q4
145
146#define dx x0_x1
147#define dy y0_y1
148#define db b0_b1
149
150#define uvrg_base q11
151
152#define gs_uvrg_x q5
153#define gs_uvrg_y q6
154
155#define g_uvrg_x q1
156#define ga_uv_x d2
157#define g_uv_x d2
158#define ga_rg_x d3
159#define g_rg_x d3
160
161#define g_uvrg_y q4
162#define ga_uv_y d8
163#define g_uv_y d8
164#define ga_rg_y d9
165#define g_rg_y d9
166
167#define gw_uv_x q1
168#define gw_rg_x q2
169#define gw_uv_y q4
170#define gw_rg_y q3
171
172#define w_mask q9
173#define w_mask_l d18
174
175#define r_shift q10
176
177#define uvrg_dx0 q0
178#define uvrg_dx0l d0
179#define uvrg_dx0h d1
180
181#define uvrg_dx1 q1
182#define uvrg_dx1l d2
183#define uvrg_dx1h d3
184
185#define uvrg_dx2 q2
186#define uvrg_dx2l d4
187#define uvrg_dx2h d5
188
189#define uvrg_dx3 q3
190#define uvrg_dx3l d6
191#define uvrg_dx3h d7
192
c6063f89 193#define uvrgb_phase q13
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194
195.align 4
196
0e4ad319 197#include "arm_features.h"
8184d7c5 198
0e4ad319 199#define function(name) FUNCTION(name):
200
201#ifndef TEXRELS_FORBIDDEN
75e28f62 202
8184d7c5 203#define JT_OP_REL(table_label, index_reg, temp)
204#define JT_OP(x...) x
205#define JTE(start, target) target
206
207#else
208
8184d7c5 209#define JT_OP_REL(table_label, index_reg, temp) \
210 adr temp, table_label; \
e1f6de8f 211 ldr temp, [temp, index_reg, lsl #2]; \
8184d7c5 212 add pc, pc, temp \
213
214#define JT_OP(x...)
215#define JTE(start, target) (target - start)
216
0e4ad319 217#endif
4d646738 218
0e4ad319 219#ifdef __MACH__
8184d7c5 220#define flush_render_block_buffer _flush_render_block_buffer
221#define setup_sprite_untextured_simple _setup_sprite_untextured_simple
222#define update_texture_8bpp_cache _update_texture_8bpp_cache
8184d7c5 223#endif
224
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225@ r0: psx_gpu
226@ r1: v_a
227@ r2: v_b
228@ r3: v_c
229
230function(compute_all_gradients)
231 // First compute the triangle area reciprocal and shift. The division will
232 // happen concurrently with much of the work which follows.
233 @ r12 = psx_gpu->triangle_area
e1f6de8f 234 ldr r12, [psx_gpu, #psx_gpu_triangle_area_offset]
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235 stmdb sp!, { r4 - r11, lr }
236
237 @ load exponent of 62 into upper half of double
238 movw r4, #0
239 clz r14, r12 @ r14 = shift
240
241 movt r4, #((62 + 1023) << 4)
242 mov r12, r12, lsl r14 @ r12 = triangle_area_normalized
243
244 @ load area normalized into lower half of double
245 mov r5, r12, lsr #10
246 vmov.f64 d30, r5, r4 @ d30 = (1 << 62) + ta_n
247
248 movt r4, #((1022 + 31) << 4)
249 mov r5, r12, lsl #20
250
251 add r4, r4, r12, lsr #11
252 vmov.f64 d31, r5, r4
253
254 vdiv.f64 d30, d30, d31 @ d30 = ((1 << 62) + ta_n) / ta_n
255
256 // ((x1 - x0) * (y2 - y1)) - ((x2 - x1) * (y1 - y0)) =
257 // ( d0 * d1 ) - ( d2 * d3 ) =
258 // ( m0 ) - ( m1 ) = gradient
259
260 // This is split to do 12 elements at a time over three sets: a, b, and c.
261 // Technically we only need to do 10 elements (uvrgb_x and uvrgb_y), so
262 // two of the slots are unused.
263
264 // Inputs are all 16-bit signed. The m0/m1 results are 32-bit signed, as
265 // is g.
266
267 // First type is: uvrg bxxx xxxx
268 // Second type is: yyyy ybyy uvrg
269 // Since x_a and y_c are the same the same variable is used for both.
270
e1f6de8f 271 vld1.u32 { v0 }, [v_a, :128] @ v0 = { uvrg0, b0, x0, y0 }
272 ldrsh x0, [v_a, #8] @ load x0
75e28f62 273
e1f6de8f 274 vld1.u32 { v1 }, [v_b, :128] @ v1 = { uvrg1, b1, x1, y1}
275 ldrh x1, [v_b, #8] @ load x1
75e28f62 276
e1f6de8f 277 vld1.u32 { v2 }, [v_c, :128] @ v2 = { uvrg2, b2, x2, y2 }
278 ldrh x2, [v_c, #8] @ load x2
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279
280 vmovl.u8 uvrg_xxxx0, uvrgb0 @ uvrg_xxxx0 = { uv0, rg0, b0-, -- }
e1f6de8f 281 ldrh y0, [v_a, #10] @ load y0
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282
283 vmovl.u8 uvrg_xxxx1, uvrgb1 @ uvrg_xxxx1 = { uv1, rg1, b1-, -- }
e1f6de8f 284 ldrh y1, [v_b, #10] @ load y1
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285
286 vmovl.u8 uvrg_xxxx2, uvrgb2 @ uvrg_xxxx2 = { uv2, rg2, b2-, -- }
e1f6de8f 287 ldrh y2, [v_c, #10] @ load y2
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288
289 vmov.u8 uvrg0b, uvrg0 @ uvrg0b = { uv0, rg0 }
290 vdup.u16 xxxx0, x0_y0[0] @ xxxx0 = { xx0, xx0 }
291
292 orr x1_x2, x1, x2, lsl #16 @ x1_x2 = { x1, x2 }
293 pkhbt x0_x1, x0, x1, lsl #16 @ x0_x1 = { x0, x1 }
294
295 vmov.u8 uvrg1b, uvrg1 @ uvrg1b = { uv1, rg1 }
296 vdup.u16 xxxx1, x1_y1[0] @ xxxx1 = { xx1, xx1 }
297
298 vmov.u8 uvrg2b, uvrg2 @ uvrg2b = { uv2, rg2 }
299 vdup.u16 xxxx2, x2_y2[0] @ xxxx2 = { xx2, xx2 }
300
e1f6de8f 301 ldrb b2, [v_c, #4] @ load b2
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302 orr y0_y1, y0, y1, lsl #16 @ y0_y1 = { y0, y1 }
303
e1f6de8f 304 ldrb b1, [v_b, #4] @ load b1
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305 orr y1_y2, y1, y2, lsl #16 @ y1_y2 = { y1, y2 }
306
307 vdup.u16 yyyy0, x0_y0[1] @ yyyy0 = { yy0, yy0 }
308 vsub.s16 d0_ab, x1_ab, x0_ab
309
e1f6de8f 310 ldrb b0, [v_a, #4] @ load b0
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311 orr b1_b2, b1, b2, lsl #16 @ b1_b2 = { b1, b2 }
312
313 vdup.u16 yyyy1, x1_y1[1] @ yyyy1 = { yy1, yy1 }
314 vsub.s16 d2_ab, x2_ab, x1_ab
315
316 vdup.u16 yyyy2, x2_y2[1] @ yyyy2 = { yy2, yy2 }
317 vsub.s16 d1_ab, y2_ab, y1_ab
318
319 orr b0_b1, b0, b1, lsl #16 @ b1_b2 = { b1, b2 }
320 ssub16 dx, x1_x2, x0_x1 @ dx = { x1 - x0, x2 - x1 }
321
322 ssub16 dy, y1_y2, y0_y1 @ dy = { y1 - y0, y2 - y1 }
323 ssub16 db, b1_b2, b0_b1 @ db = { b1 - b0, b2 - b1 }
324
325 vsub.s16 d3_ab, y1_ab, y0_ab
326 smusdx ga_by, dx, db @ ga_by = ((x1 - x0) * (b2 - b1)) -
327 @ ((x2 - X1) * (b1 - b0))
328 vmull.s16 ga_uvrg_x, d0_a, d1_a
329 smusdx ga_bx, db, dy @ ga_bx = ((b1 - b0) * (y2 - y1)) -
330 @ ((b2 - b1) * (y1 - y0))
331 vmlsl.s16 ga_uvrg_x, d2_a, d3_a
332 movs gs_bx, ga_bx, asr #31
333
334 vmull.s16 ga_uvrg_y, d0_b, d1_b
335 rsbmi ga_bx, ga_bx, #0
336
c6063f89 337 @ r12 = psx_gpu->uvrgb_phase
e1f6de8f 338 ldr r12, [psx_gpu, #psx_gpu_uvrgb_phase_offset]
c6063f89 339
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340 vmlsl.s16 ga_uvrg_y, d2_b, d3_b
341 movs gs_by, ga_by, asr #31
342
343 vshr.u64 d0, d30, #22
c6063f89 344 add b_base, r12, b0, lsl #16
345
346 vdup.u32 uvrgb_phase, r12
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347
348 rsbmi ga_by, ga_by, #0
349 vclt.s32 gs_uvrg_x, ga_uvrg_x, #0 @ gs_uvrg_x = ga_uvrg_x < 0
350
351 @ r12 = psx_gpu->triangle_winding_offset
e1f6de8f 352 ldrb r12, [psx_gpu, #psx_gpu_triangle_winding_offset]
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353 vclt.s32 gs_uvrg_y, ga_uvrg_y, #0 @ gs_uvrg_y = ga_uvrg_y < 0
354
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355 rsb r12, r12, #0 @ r12 = -(triangle->winding)
356
357 vdup.u32 w_mask, r12 @ w_mask = { -w, -w, -w, -w }
358 sub r14, r14, #(62 - 12) @ r14 = shift - (62 - FIXED_BITS)
359
360 vshll.u16 uvrg_base, uvrg0, #16 @ uvrg_base = uvrg0 << 16
361 vdup.u32 r_shift, r14 @ r_shift = { shift, shift, shift, shift }
362
c6063f89 363 vadd.u32 uvrg_base, uvrgb_phase
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364 vabs.s32 ga_uvrg_x, ga_uvrg_x @ ga_uvrg_x = abs(ga_uvrg_x)
365
366 vmov area_r_s, s0 @ area_r_s = triangle_reciprocal
367 vabs.s32 ga_uvrg_y, ga_uvrg_y @ ga_uvrg_y = abs(ga_uvrg_y)
368
369 vmull.u32 gw_rg_x, ga_rg_x, d0[0]
370 vmull.u32 gw_uv_x, ga_uv_x, d0[0]
371 vmull.u32 gw_rg_y, ga_rg_y, d0[0]
372 vmull.u32 gw_uv_y, ga_uv_y, d0[0]
373
374 vshl.u64 gw_rg_x, gw_rg_x, r_shift
375 vshl.u64 gw_uv_x, gw_uv_x, r_shift
376 vshl.u64 gw_rg_y, gw_rg_y, r_shift
377 vshl.u64 gw_uv_y, gw_uv_y, r_shift
378
379 veor.u32 gs_uvrg_x, gs_uvrg_x, w_mask
380 vmovn.u64 g_uv_x, gw_uv_x
381
382 veor.u32 gs_uvrg_y, gs_uvrg_y, w_mask
383 vmovn.u64 g_rg_x, gw_rg_x
384
385 veor.u32 g_uvrg_x, g_uvrg_x, gs_uvrg_x
386 vmovn.u64 g_uv_y, gw_uv_y
387
388 vsub.u32 g_uvrg_x, g_uvrg_x, gs_uvrg_x
389 vmovn.u64 g_rg_y, gw_rg_y
390
391 veor.u32 g_uvrg_y, g_uvrg_y, gs_uvrg_y
392 mov ga_bx, ga_bx, lsl #13
393
394 vsub.u32 g_uvrg_y, g_uvrg_y, gs_uvrg_y
395 mov ga_by, ga_by, lsl #13
396
397 vdup.u32 x0_y0, x0
398 umull gw_bx_l, gw_bx_h, ga_bx, area_r_s
399
400 vshl.u32 g_uvrg_x, g_uvrg_x, #4
401 vshl.u32 g_uvrg_y, g_uvrg_y, #4
402
403 umull gw_by_l, gw_by_h, ga_by, area_r_s
404 vmls.s32 uvrg_base, ga_uvrg_x, x0_y0[0]
405
406 eor gs_bx, gs_bx, r12
407 vadd.u32 uvrg_dx2, uvrg_dx1, uvrg_dx1
408
409 veor.u32 uvrg_dx0, uvrg_dx0, uvrg_dx0
410 eor gs_by, gs_by, r12
411
412 rsb r11, r14, #0 @ r11 = negative shift for scalar lsr
413 add store_a, psx_gpu, #psx_gpu_uvrg_offset
414
415 sub r11, r11, #(32 - 13)
416
417 add store_b, store_a, #16
418 mov store_inc, #32
419
420 vadd.u32 uvrg_dx3, uvrg_dx2, uvrg_dx1
e1f6de8f 421 vst1.u32 { uvrg_base }, [store_a, :128], store_inc
75e28f62 422
e1f6de8f 423 vst1.u32 { uvrg_dx1 }, [store_b, :128], store_inc
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424 mov g_bx, gw_bx_h, lsr r11
425
e1f6de8f 426 vst1.u32 { g_uvrg_y }, [store_a, :128], store_inc
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427 mov g_by, gw_by_h, lsr r11
428
429 vst4.u32 { uvrg_dx0l, uvrg_dx1l, uvrg_dx2l, uvrg_dx3l }, \
e1f6de8f 430 [store_b, :128], store_inc
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431 eor g_bx, g_bx, gs_bx
432
433 vst4.u32 { uvrg_dx0h, uvrg_dx1h, uvrg_dx2h, uvrg_dx3h }, \
e1f6de8f 434 [store_b, :128], store_inc
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435 sub g_bx, g_bx, gs_bx
436
437 lsl g_bx, g_bx, #4
438 eor g_by, g_by, gs_by
439
440 mls b_base, g_bx, x0, b_base
441 sub g_by, g_by, gs_by
442
443 lsl g_by, g_by, #4
444 mov g_bx0, #0
445
446 add g_bx2, g_bx, g_bx
447 add g_bx3, g_bx, g_bx2
448
449 stmia store_b, { g_bx0, g_bx, g_bx2, g_bx3, b_base, g_by }
450
451 ldmia sp!, { r4 - r11, pc }
452
453
454#define psx_gpu r0
455#define v_a r1
456#define v_b r2
457#define v_c r3
458
459#define temp r14
460
461#define x_a r4
462#define x_b r5
463#define x_c r6
464#define y_a r1
465#define y_b r2
466#define y_c r3
467
468#define height_minor_a r7
469#define height_minor_b r8
470#define height_major r9
471#define height r9
472
473#define reciprocal_table_ptr r10
474
475#define edge_alt_low r4
476#define edge_alt_high r5
477#define edge_dx_dy_alt r6
478#define edge_shift_alt r10
479
480#define edge_dx_dy_alt_low r4
481#define edge_dx_dy_alt_high r5
482
483#define span_edge_data r4
484#define span_uvrg_offset r5
485#define span_b_offset r6
486
487#define clip r14
488
489#define b r11
490#define b_dy r12
491
492
493#define alternate_x q0
494#define alternate_dx_dy q1
495#define alternate_x_32 q2
496
497#define alternate_x_low d0
498#define alternate_x_high d1
499#define alternate_dx_dy_low d2
500#define alternate_dx_dy_high d3
501#define alternate_x_32_low d4
502#define alternate_x_32_high d5
503
504#define left_x q3
505#define right_x q4
506#define left_dx_dy q5
507#define right_dx_dy q6
508#define left_edge q7
509#define right_edge q8
510
511#define left_x_low d6
512#define left_x_high d7
513#define right_x_low d8
514#define right_x_high d9
515#define left_dx_dy_low d10
516#define left_dx_dy_high d11
517#define right_dx_dy_low d12
518#define right_dx_dy_high d13
519#define left_edge_low d14
520#define left_edge_high d15
521#define right_edge_low d16
522#define right_edge_high d17
523
524#define y_mid_point d18
525#define c_0x0004 d19
526
527#define left_right_x_16 q11
528#define span_shifts_y q12
529#define c_0x0001 q13
530
531#define span_shifts d24
532#define y_x4 d25
533#define c_0xFFFE d26
534#define c_0x0007 d27
535
536#define left_right_x_16_low d22
537#define left_right_x_16_high d23
538
539#define uvrg q14
540#define uvrg_dy q15
541
542#define alternate_x_16 d4
543
544#define v_clip q3
545#define v_clip_low d6
546
547#define right_x_32 q10
548#define left_x_32 q11
549#define alternate_select d24
550
551#define right_x_32_low d20
552#define right_x_32_high d21
553#define left_x_32_low d22
554#define left_x_32_high d23
555
556#define edges_xy q0
557#define edges_dx_dy d2
558#define edge_shifts d3
559#define edge_shifts_64 q2
560
561#define edges_xy_left d0
562#define edges_xy_right d1
563
564#define height_reciprocals d6
565#define heights d7
566
567#define widths d8
568#define c_0x01 d9
569#define x_starts d10
570#define x_ends d11
571
572#define heights_b d12
573#define edges_dx_dy_64 q10
574
575#define edges_dx_dy_64_left d20
576#define edges_dx_dy_64_right d21
577
578
579#define setup_spans_prologue() \
580 stmdb sp!, { r4 - r11, lr }; \
581 \
e1f6de8f 582 ldrsh x_a, [v_a, #8]; \
583 ldrsh x_b, [v_b, #8]; \
584 ldrsh x_c, [v_c, #8]; \
585 ldrsh y_a, [v_a, #10]; \
586 ldrsh y_b, [v_b, #10]; \
587 ldrsh y_c, [v_c, #10]; \
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588 \
589 add temp, psx_gpu, #psx_gpu_uvrg_offset; \
e1f6de8f 590 vld1.32 { uvrg }, [temp]; \
75e28f62 591 add temp, psx_gpu, #psx_gpu_uvrg_dy_offset; \
e1f6de8f 592 vld1.32 { uvrg_dy }, [temp]; \
593 ldr reciprocal_table_ptr, [psx_gpu, #psx_gpu_reciprocal_table_ptr_offset]; \
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594 \
595 vmov.u32 c_0x01, #0x01 \
596
597#define setup_spans_load_b() \
e1f6de8f 598 ldr b, [psx_gpu, #psx_gpu_b_offset]; \
599 ldr b_dy, [psx_gpu, #psx_gpu_b_dy_offset] \
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600
601#define setup_spans_prologue_b() \
602 add span_uvrg_offset, psx_gpu, #psx_gpu_span_uvrg_offset_offset; \
603 add temp, psx_gpu, #psx_gpu_viewport_start_x_offset; \
604 \
605 add span_edge_data, psx_gpu, #psx_gpu_span_edge_data_offset; \
606 vmov.u16 c_0x0004, #0x0004; \
607 \
608 add span_b_offset, psx_gpu, #psx_gpu_span_b_offset_offset; \
609 vmov.u16 c_0x0001, #0x0001; \
610 \
e1f6de8f 611 vld1.u16 { left_edge_low[], left_edge_high[] }, [temp]; \
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612 add temp, psx_gpu, #psx_gpu_viewport_end_x_offset; \
613 \
e1f6de8f 614 vld1.u16 { right_edge_low[], right_edge_high[] }, [temp]; \
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615 vadd.u16 right_edge, right_edge, c_0x0001; \
616 \
617 vmov.u16 c_0x0007, #0x0007; \
618 vmvn.u16 c_0xFFFE, #0x0001 \
619
620
621#define compute_edge_delta_x2() \
e1f6de8f 622 ldr temp, [reciprocal_table_ptr, height, lsl #2]; \
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E
623 \
624 vdup.u32 heights, height; \
625 vsub.u32 widths, x_ends, x_starts; \
626 \
627 vdup.u32 edge_shifts, temp; \
628 vsub.u32 heights_b, heights, c_0x01; \
7d5140f5 629 vshr.u32 height_reciprocals, edge_shifts, #10; \
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E
630 \
631 vmla.s32 heights_b, x_starts, heights; \
632 vbic.u16 edge_shifts, #0xE0; \
633 vmul.s32 edges_dx_dy, widths, height_reciprocals; \
634 vmull.s32 edges_xy, heights_b, height_reciprocals \
635
636#define width_alt r6
637#define height_reciprocal_alt r11
638#define height_b_alt r12
639
640#define compute_edge_delta_x3(start_c, height_a, height_b) \
ed0fd81d 641 vmov heights, height_a, height_b; \
e1f6de8f 642 ldr temp, [reciprocal_table_ptr, height_a, lsl #2]; \
75e28f62 643 vmov.u32 edge_shifts[0], temp; \
e1f6de8f 644 ldr temp, [reciprocal_table_ptr, height_b, lsl #2]; \
75e28f62 645 vmov.u32 edge_shifts[1], temp; \
e1f6de8f 646 ldr edge_shift_alt, [reciprocal_table_ptr, height_minor_b, lsl #2]; \
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647 \
648 vsub.u32 widths, x_ends, x_starts; \
649 sub width_alt, x_c, start_c; \
650 \
651 vsub.u32 heights_b, heights, c_0x01; \
652 sub height_b_alt, height_minor_b, #1; \
653 \
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E
654 vshr.u32 height_reciprocals, edge_shifts, #10; \
655 lsr height_reciprocal_alt, edge_shift_alt, #10; \
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E
656 \
657 vmla.s32 heights_b, x_starts, heights; \
658 mla height_b_alt, height_minor_b, start_c, height_b_alt; \
659 \
660 vbic.u16 edge_shifts, #0xE0; \
661 and edge_shift_alt, edge_shift_alt, #0x1F; \
662 \
663 vmul.s32 edges_dx_dy, widths, height_reciprocals; \
664 mul edge_dx_dy_alt, width_alt, height_reciprocal_alt; \
665 \
666 vmull.s32 edges_xy, heights_b, height_reciprocals; \
667 smull edge_alt_low, edge_alt_high, height_b_alt, height_reciprocal_alt \
668
669
670#define setup_spans_adjust_y_up() \
671 vsub.u32 y_x4, y_x4, c_0x0004 \
672
673#define setup_spans_adjust_y_down() \
674 vadd.u32 y_x4, y_x4, c_0x0004 \
675
676#define setup_spans_adjust_interpolants_up() \
677 vsub.u32 uvrg, uvrg, uvrg_dy; \
678 sub b, b, b_dy \
679
680#define setup_spans_adjust_interpolants_down() \
681 vadd.u32 uvrg, uvrg, uvrg_dy; \
682 add b, b, b_dy \
683
684
685#define setup_spans_clip_interpolants_increment() \
686 mla b, b_dy, clip, b; \
687 vmla.s32 uvrg, uvrg_dy, v_clip \
688
689#define setup_spans_clip_interpolants_decrement() \
690 mls b, b_dy, clip, b; \
691 vmls.s32 uvrg, uvrg_dy, v_clip \
692
693#define setup_spans_clip_alternate_yes() \
694 smlal edge_alt_low, edge_alt_high, edge_dx_dy_alt, clip \
695
696#define setup_spans_clip_alternate_no() \
697
698#define setup_spans_clip(direction, alternate_active) \
699 vdup.u32 v_clip, clip; \
700 setup_spans_clip_alternate_##alternate_active(); \
701 setup_spans_clip_interpolants_##direction(); \
702 vmlal.s32 edges_xy, edges_dx_dy, v_clip_low \
703
704
705#define setup_spans_adjust_edges_alternate_no(left_index, right_index) \
706 vmovl.s32 edge_shifts_64, edge_shifts; \
707 vmovl.s32 edges_dx_dy_64, edges_dx_dy; \
708 \
709 vshl.s64 edges_xy, edges_xy, edge_shifts_64; \
710 vshl.s64 edges_dx_dy_64, edges_dx_dy_64, edge_shifts_64; \
711 \
712 vmov left_x_low, edges_xy_##left_index; \
713 vmov right_x_low, edges_xy_##right_index; \
714 \
715 vmov left_dx_dy_low, edges_dx_dy_64_##left_index; \
716 vmov left_dx_dy_high, edges_dx_dy_64_##left_index; \
717 vmov right_dx_dy_low, edges_dx_dy_64_##right_index; \
718 vmov right_dx_dy_high, edges_dx_dy_64_##right_index; \
719 \
720 vadd.u64 left_x_high, left_x_low, left_dx_dy_low; \
721 vadd.u64 right_x_high, right_x_low, right_dx_dy_low; \
722 \
723 vadd.u64 left_dx_dy, left_dx_dy, left_dx_dy; \
724 vadd.u64 right_dx_dy, right_dx_dy, right_dx_dy \
725
726
727#define setup_spans_adjust_edges_alternate_yes(left_index, right_index) \
728 setup_spans_adjust_edges_alternate_no(left_index, right_index); \
729 \
730 vdup.u16 y_mid_point, y_b; \
731 rsb temp, edge_shift_alt, #32; \
732 \
733 lsl edge_alt_high, edge_alt_high, edge_shift_alt; \
734 orr edge_alt_high, edge_alt_high, edge_alt_low, lsr temp; \
735 lsl edge_alt_low, edge_alt_low, edge_shift_alt; \
736 vmov alternate_x_low, edge_alt_low, edge_alt_high; \
737 \
738 asr edge_dx_dy_alt_high, edge_dx_dy_alt, temp; \
739 lsl edge_dx_dy_alt_low, edge_dx_dy_alt, edge_shift_alt; \
740 vmov alternate_dx_dy_low, edge_dx_dy_alt_low, edge_dx_dy_alt_high; \
741 vmov alternate_dx_dy_high, alternate_dx_dy_low; \
742 \
743 vadd.u64 alternate_x_high, alternate_x_low, alternate_dx_dy_low; \
744 vadd.u64 alternate_dx_dy, alternate_dx_dy, alternate_dx_dy \
745
746
747#define setup_spans_y_select_up() \
748 vclt.s16 alternate_select, y_x4, y_mid_point \
749
750#define setup_spans_y_select_down() \
751 vcgt.s16 alternate_select, y_x4, y_mid_point \
752
753
754#define setup_spans_alternate_select_left() \
755 vbit.u16 left_right_x_16_low, alternate_x_16, alternate_select \
756
757#define setup_spans_alternate_select_right() \
758 vbit.u16 left_right_x_16_high, alternate_x_16, alternate_select \
759
760
761#define setup_spans_set_x4_alternate_yes(alternate, direction) \
762 vshrn.s64 alternate_x_32_low, alternate_x, #32; \
763 vshrn.s64 left_x_32_low, left_x, #32; \
764 vshrn.s64 right_x_32_low, right_x, #32; \
765 \
766 vadd.u64 alternate_x, alternate_x, alternate_dx_dy; \
767 vadd.u64 left_x, left_x, left_dx_dy; \
768 vadd.u64 right_x, right_x, right_dx_dy; \
769 \
770 vshrn.s64 alternate_x_32_high, alternate_x, #32; \
771 vshrn.s64 left_x_32_high, left_x, #32; \
772 vshrn.s64 right_x_32_high, right_x, #32; \
773 \
774 vadd.u64 alternate_x, alternate_x, alternate_dx_dy; \
775 vadd.u64 left_x, left_x, left_dx_dy; \
776 vadd.u64 right_x, right_x, right_dx_dy; \
777 \
778 vmovn.u32 alternate_x_16, alternate_x_32; \
779 setup_spans_y_select_##direction(); \
780 vmovn.u32 left_right_x_16_low, left_x_32; \
781 \
782 vmovn.u32 left_right_x_16_high, right_x_32; \
783 setup_spans_alternate_select_##alternate(); \
784 \
e1f6de8f 785 vst1.u32 { uvrg }, [span_uvrg_offset, :128]!; \
786 str b, [span_b_offset], #4; \
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787 setup_spans_adjust_interpolants_##direction(); \
788 \
789 vmax.s16 left_right_x_16, left_right_x_16, left_edge; \
790 \
e1f6de8f 791 vst1.u32 { uvrg }, [span_uvrg_offset, :128]!; \
792 str b, [span_b_offset], #4; \
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793 setup_spans_adjust_interpolants_##direction(); \
794 \
795 vmin.s16 left_right_x_16, left_right_x_16, right_edge; \
796 \
e1f6de8f 797 vst1.u32 { uvrg }, [span_uvrg_offset, :128]!; \
798 str b, [span_b_offset], #4; \
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799 setup_spans_adjust_interpolants_##direction(); \
800 \
801 vsub.u16 left_right_x_16_high, left_right_x_16_high, left_right_x_16_low; \
802 vadd.u16 left_right_x_16_high, left_right_x_16_high, c_0x0007; \
803 vand.u16 span_shifts, left_right_x_16_high, c_0x0007; \
804 \
e1f6de8f 805 vst1.u32 { uvrg }, [span_uvrg_offset, :128]!; \
806 str b, [span_b_offset], #4; \
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E
807 setup_spans_adjust_interpolants_##direction(); \
808 \
809 vshr.u16 left_right_x_16_high, left_right_x_16_high, #3; \
810 vshl.u16 span_shifts, c_0xFFFE, span_shifts; \
811 \
e1f6de8f 812 vst4.u16 { left_right_x_16, span_shifts_y }, [span_edge_data]!; \
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E
813 \
814 setup_spans_adjust_y_##direction() \
815
816
817#define setup_spans_set_x4_alternate_no(alternate, direction) \
818 vshrn.s64 left_x_32_low, left_x, #32; \
819 vshrn.s64 right_x_32_low, right_x, #32; \
820 \
821 vadd.u64 left_x, left_x, left_dx_dy; \
822 vadd.u64 right_x, right_x, right_dx_dy; \
823 \
824 vshrn.s64 left_x_32_high, left_x, #32; \
825 vshrn.s64 right_x_32_high, right_x, #32; \
826 \
827 vadd.u64 left_x, left_x, left_dx_dy; \
828 vadd.u64 right_x, right_x, right_dx_dy; \
829 \
830 vmovn.u32 left_right_x_16_low, left_x_32; \
831 vmovn.u32 left_right_x_16_high, right_x_32; \
832 \
e1f6de8f 833 vst1.u32 { uvrg }, [span_uvrg_offset, :128]!; \
834 str b, [span_b_offset], #4; \
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E
835 setup_spans_adjust_interpolants_##direction(); \
836 \
837 vmax.s16 left_right_x_16, left_right_x_16, left_edge; \
838 \
e1f6de8f 839 vst1.u32 { uvrg }, [span_uvrg_offset, :128]!; \
840 str b, [span_b_offset], #4; \
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E
841 setup_spans_adjust_interpolants_##direction(); \
842 \
843 vmin.s16 left_right_x_16, left_right_x_16, right_edge; \
844 \
e1f6de8f 845 vst1.u32 { uvrg }, [span_uvrg_offset, :128]!; \
846 str b, [span_b_offset], #4; \
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E
847 setup_spans_adjust_interpolants_##direction(); \
848 \
849 vsub.u16 left_right_x_16_high, left_right_x_16_high, left_right_x_16_low; \
850 vadd.u16 left_right_x_16_high, left_right_x_16_high, c_0x0007; \
851 vand.u16 span_shifts, left_right_x_16_high, c_0x0007; \
852 \
e1f6de8f 853 vst1.u32 { uvrg }, [span_uvrg_offset, :128]!; \
854 str b, [span_b_offset], #4; \
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E
855 setup_spans_adjust_interpolants_##direction(); \
856 \
857 vshl.u16 span_shifts, c_0xFFFE, span_shifts; \
858 vshr.u16 left_right_x_16_high, left_right_x_16_high, #3; \
859 \
e1f6de8f 860 vst4.u16 { left_right_x_16, span_shifts_y }, [span_edge_data]!; \
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E
861 \
862 setup_spans_adjust_y_##direction() \
863
864
865#define edge_adjust_low r11
866#define edge_adjust_high r12
867
868#define setup_spans_alternate_adjust_yes() \
869 smull edge_adjust_low, edge_adjust_high, edge_dx_dy_alt, height_minor_a; \
870 subs edge_alt_low, edge_alt_low, edge_adjust_low; \
871 sbc edge_alt_high, edge_alt_high, edge_adjust_high \
872
873#define setup_spans_alternate_adjust_no() \
874
875
876#define setup_spans_down(left_index, right_index, alternate, alternate_active) \
877 setup_spans_alternate_adjust_##alternate_active(); \
878 setup_spans_load_b(); \
879 \
e1f6de8f 880 ldrsh temp, [psx_gpu, #psx_gpu_viewport_end_y_offset]; \
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E
881 subs y_c, y_c, temp; \
882 subgt height, height, y_c; \
883 addgt height, height, #1; \
884 \
e1f6de8f 885 ldrsh temp, [psx_gpu, #psx_gpu_viewport_start_y_offset]; \
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E
886 subs clip, temp, y_a; \
887 ble 0f; \
888 \
889 sub height, height, clip; \
890 add y_a, y_a, clip; \
891 setup_spans_clip(increment, alternate_active); \
892 \
893 0: \
894 cmp height, #0; \
895 ble 1f; \
896 \
897 orr temp, y_a, y_a, lsl #16; \
898 add temp, temp, #(1 << 16); \
899 add y_a, temp, #2; \
900 add y_a, y_a, #(2 << 16); \
ed0fd81d 901 vmov y_x4, temp, y_a; \
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E
902 \
903 setup_spans_adjust_edges_alternate_##alternate_active(left_index, \
904 right_index); \
905 setup_spans_prologue_b(); \
906 \
e1f6de8f 907 strh height, [psx_gpu, #psx_gpu_num_spans_offset]; \
75e28f62
E
908 \
909 2: \
910 setup_spans_set_x4_alternate_##alternate_active(alternate, down); \
911 subs height, height, #4; \
912 bhi 2b; \
913 \
914 1: \
915
916
917#define setup_spans_alternate_pre_increment_yes() \
918 adds edge_alt_low, edge_alt_low, edge_dx_dy_alt; \
919 adc edge_alt_high, edge_alt_high, edge_dx_dy_alt, asr #31 \
920
921#define setup_spans_alternate_pre_increment_no() \
922
923
924#define setup_spans_up_decrement_yes() \
925 suble height, height, #1 \
926
927#define setup_spans_up_decrement_no() \
928
929
930#define setup_spans_up(left_index, right_index, alternate, alternate_active) \
931 setup_spans_alternate_adjust_##alternate_active(); \
932 setup_spans_load_b(); \
933 sub y_a, y_a, #1; \
934 \
e1f6de8f 935 ldrh temp, [psx_gpu, #psx_gpu_viewport_start_y_offset]; \
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936 subs temp, temp, y_c; \
937 subgt height, height, temp; \
938 setup_spans_up_decrement_##alternate_active(); \
939 \
e1f6de8f 940 ldrh temp, [psx_gpu, #psx_gpu_viewport_end_y_offset]; \
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E
941 subs clip, y_a, temp; \
942 ble 0f; \
943 \
944 sub height, height, clip; \
945 sub y_a, y_a, clip; \
946 setup_spans_clip(decrement, alternate_active); \
947 \
948 0: \
949 cmp height, #0; \
950 ble 1f; \
951 \
952 orr temp, y_a, y_a, lsl #16; \
953 sub temp, temp, #(1 << 16); \
954 sub y_a, temp, #2; \
955 sub y_a, y_a, #(2 << 16); \
ed0fd81d 956 vmov y_x4, temp, y_a; \
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E
957 \
958 vaddw.s32 edges_xy, edges_xy, edges_dx_dy; \
959 \
960 setup_spans_alternate_pre_increment_##alternate_active(); \
961 setup_spans_adjust_edges_alternate_##alternate_active(left_index, \
962 right_index); \
963 setup_spans_adjust_interpolants_up(); \
964 setup_spans_prologue_b(); \
965 \
e1f6de8f 966 strh height, [psx_gpu, #psx_gpu_num_spans_offset]; \
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E
967 \
968 2: \
969 setup_spans_set_x4_alternate_##alternate_active(alternate, up); \
970 subs height, height, #4; \
971 bhi 2b; \
972 \
973 1: \
974
975
976#define setup_spans_epilogue() \
977 ldmia sp!, { r4 - r11, pc } \
978
979
980#define setup_spans_up_up(minor, major) \
981 setup_spans_prologue(); \
982 sub height_minor_a, y_a, y_b; \
983 sub height_minor_b, y_b, y_c; \
984 sub height, y_a, y_c; \
985 \
986 vdup.u32 x_starts, x_a; \
ed0fd81d 987 vmov x_ends, x_c, x_b; \
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988 \
989 compute_edge_delta_x3(x_b, height_major, height_minor_a); \
990 setup_spans_up(major, minor, minor, yes); \
991 setup_spans_epilogue() \
992
993function(setup_spans_up_left)
994 setup_spans_up_up(left, right)
995
996function(setup_spans_up_right)
997 setup_spans_up_up(right, left)
998
75e28f62
E
999#define setup_spans_down_down(minor, major) \
1000 setup_spans_prologue(); \
1001 sub height_minor_a, y_b, y_a; \
1002 sub height_minor_b, y_c, y_b; \
1003 sub height, y_c, y_a; \
1004 \
1005 vdup.u32 x_starts, x_a; \
ed0fd81d 1006 vmov x_ends, x_c, x_b; \
75e28f62
E
1007 \
1008 compute_edge_delta_x3(x_b, height_major, height_minor_a); \
1009 setup_spans_down(major, minor, minor, yes); \
1010 setup_spans_epilogue() \
1011
1012function(setup_spans_down_left)
1013 setup_spans_down_down(left, right)
1014
1015function(setup_spans_down_right)
1016 setup_spans_down_down(right, left)
1017
1018
1019#define setup_spans_up_flat() \
1020 sub height, y_a, y_c; \
1021 \
1022 compute_edge_delta_x2(); \
1023 setup_spans_up(left, right, none, no); \
1024 setup_spans_epilogue() \
1025
1026function(setup_spans_up_a)
1027 setup_spans_prologue()
1028
ed0fd81d 1029 vmov x_starts, x_a, x_b
75e28f62
E
1030 vdup.u32 x_ends, x_c
1031
1032 setup_spans_up_flat()
1033
1034function(setup_spans_up_b)
1035 setup_spans_prologue()
1036
1037 vdup.u32 x_starts, x_a
ed0fd81d 1038 vmov x_ends, x_b, x_c
75e28f62
E
1039
1040 setup_spans_up_flat()
1041
1042#define setup_spans_down_flat() \
1043 sub height, y_c, y_a; \
1044 \
1045 compute_edge_delta_x2(); \
1046 setup_spans_down(left, right, none, no); \
1047 setup_spans_epilogue() \
1048
1049function(setup_spans_down_a)
1050 setup_spans_prologue()
1051
ed0fd81d 1052 vmov x_starts, x_a, x_b
75e28f62
E
1053 vdup.u32 x_ends, x_c
1054
1055 setup_spans_down_flat()
1056
1057function(setup_spans_down_b)
1058 setup_spans_prologue()
1059
1060 vdup.u32 x_starts, x_a
ed0fd81d 1061 vmov x_ends, x_b, x_c
75e28f62
E
1062
1063 setup_spans_down_flat()
1064
1065
1066#define middle_y r9
1067
1068#define edges_xy_b q11
1069#define edges_dx_dy_b d26
1070#define edge_shifts_b d27
1071#define edges_dx_dy_and_shifts_b q13
1072#define height_increment d20
1073
1074#define edges_dx_dy_and_shifts q1
1075
1076#define edges_xy_b_left d22
1077#define edges_xy_b_right d23
1078
1079#define setup_spans_up_down_load_edge_set_b() \
1080 vmov edges_xy, edges_xy_b; \
1081 vmov edges_dx_dy_and_shifts, edges_dx_dy_and_shifts_b \
1082
1083
1084function(setup_spans_up_down)
1085 setup_spans_prologue()
1086
1087 // s32 middle_y = y_a;
1088 sub height_minor_a, y_a, y_b
1089 sub height_minor_b, y_c, y_a
1090 sub height_major, y_c, y_b
1091
ed0fd81d 1092 vmov x_starts, x_a, x_c
75e28f62
E
1093 vdup.u32 x_ends, x_b
1094
1095 compute_edge_delta_x3(x_a, height_minor_a, height_major)
1096
1097 mov temp, #0
ed0fd81d 1098 vmov height_increment, temp, height_minor_b
75e28f62
E
1099 vmlal.s32 edges_xy, edges_dx_dy, height_increment
1100
1101 vmov edges_xy_b_left, edge_alt_low, edge_alt_high
1102 vmov edges_xy_b_right, edges_xy_right
1103
1104 vmov edge_shifts_b, edge_shifts
1105 vmov.u32 edge_shifts_b[0], edge_shift_alt
1106
1107 vneg.s32 edges_dx_dy_b, edges_dx_dy
1108 vmov.u32 edges_dx_dy_b[0], edge_dx_dy_alt
1109
1110 mov middle_y, y_a
1111
1112 setup_spans_load_b()
1113 sub y_a, y_a, #1
1114
e1f6de8f 1115 ldrh temp, [psx_gpu, #psx_gpu_viewport_start_y_offset]
75e28f62
E
1116 subs temp, temp, y_b
1117 subgt height_minor_a, height_minor_a, temp
1118
e1f6de8f 1119 ldrh temp, [psx_gpu, #psx_gpu_viewport_end_y_offset]
75e28f62
E
1120 subs clip, y_a, temp
1121 ble 0f
1122
1123 sub height_minor_a, height_minor_a, clip
1124 sub y_a, y_a, clip
1125 setup_spans_clip(decrement, no)
1126
1127 0:
1128 cmp height_minor_a, #0
1129 ble 3f
1130
1131 orr temp, y_a, y_a, lsl #16
1132 sub temp, temp, #(1 << 16)
1133 sub y_a, temp, #2
1134 sub y_a, y_a, #(2 << 16)
ed0fd81d 1135 vmov y_x4, temp, y_a
75e28f62
E
1136
1137 vaddw.s32 edges_xy, edges_xy, edges_dx_dy
1138
e1f6de8f 1139 strh height_minor_a, [psx_gpu, #psx_gpu_num_spans_offset]
75e28f62
E
1140
1141 setup_spans_adjust_edges_alternate_no(left, right);
1142 setup_spans_adjust_interpolants_up()
1143 setup_spans_up_down_load_edge_set_b()
1144
1145 setup_spans_prologue_b()
1146
1147
1148 2:
1149 setup_spans_set_x4_alternate_no(none, up)
1150 subs height_minor_a, height_minor_a, #4
1151 bhi 2b
1152
1153 add span_edge_data, span_edge_data, height_minor_a, lsl #3
1154 add span_uvrg_offset, span_uvrg_offset, height_minor_a, lsl #4
1155 add span_b_offset, span_b_offset, height_minor_a, lsl #2
1156
1157 4:
1158 add temp, psx_gpu, #psx_gpu_uvrg_offset
e1f6de8f 1159 vld1.32 { uvrg }, [temp]
75e28f62
E
1160 mov y_a, middle_y
1161
1162 setup_spans_load_b()
1163
e1f6de8f 1164 ldrh temp, [psx_gpu, #psx_gpu_viewport_end_y_offset]
75e28f62
E
1165 subs y_c, y_c, temp
1166 subgt height_minor_b, height_minor_b, y_c
1167 addgt height_minor_b, height_minor_b, #1
1168
e1f6de8f 1169 ldrh temp, [psx_gpu, #psx_gpu_viewport_start_y_offset]
75e28f62
E
1170 subs clip, temp, y_a
1171 ble 0f
1172
1173 sub height_minor_b, height_minor_b, clip
1174 add y_a, y_a, clip
1175 setup_spans_clip(increment, no)
1176
1177 0:
1178 cmp height_minor_b, #0
1179 ble 1f
1180
1181 orr temp, y_a, y_a, lsl #16
1182 add temp, temp, #(1 << 16)
1183 add y_a, temp, #2
1184 add y_a, y_a, #(2 << 16)
ed0fd81d 1185 vmov y_x4, temp, y_a
75e28f62
E
1186
1187 setup_spans_adjust_edges_alternate_no(left, right)
1188
e1f6de8f 1189 ldrh temp, [psx_gpu, #psx_gpu_num_spans_offset]
75e28f62 1190 add temp, temp, height_minor_b
b7569147 1191
1192 cmp temp, #MAX_SPANS
1193 beq 5f
1194
e1f6de8f 1195 strh temp, [psx_gpu, #psx_gpu_num_spans_offset]
75e28f62
E
1196
1197 2:
1198 setup_spans_set_x4_alternate_no(none, down)
1199 subs height_minor_b, height_minor_b, #4
1200 bhi 2b
1201
1202 1:
1203 setup_spans_epilogue()
1204
1205 3:
1206 setup_spans_up_down_load_edge_set_b()
1207 setup_spans_prologue_b()
1208 bal 4b
1209
b7569147 1210 5:
1211 // FIXME: overflow corner case
1212 sub temp, temp, height_minor_b
1213 bics height_minor_b, #3
1214 add temp, temp, height_minor_b
e1f6de8f 1215 strh temp, [psx_gpu, #psx_gpu_num_spans_offset]
b7569147 1216 bne 2b
1217 bal 1b
1218
75e28f62
E
1219#undef span_uvrg_offset
1220#undef span_edge_data
1221#undef span_b_offset
1222#undef left_x
1223#undef b
1224
1225#define psx_gpu r0
1226#define num_spans r1
1227#define span_uvrg_offset r2
1228#define span_edge_data r3
1229#define span_b_offset r4
1230#define b_dx r5
1231#define span_num_blocks r6
1232#define y r7
1233#define left_x r8
1234#define b r9
1235#define dither_offset_ptr r10
1236#define block_ptr_a r11
1237#define fb_ptr r12
1238#define num_blocks r14
1239
1240#define uvrg_dx_ptr r2
1241#define texture_mask_ptr r3
1242#define dither_shift r8
1243#define dither_row r10
1244
1245#define c_32 r7
1246#define b_dx4 r8
1247#define b_dx8 r9
1248#define block_ptr_b r10
1249
1250#define block_span_ptr r10
1251#define right_mask r8
1252
1253#define color r2
1254#define color_r r3
1255#define color_g r4
1256#define color_b r5
1257
1258#undef uvrg
1259
1260#define u_block q0
1261#define v_block q1
1262#define r_block q2
1263#define g_block q3
1264#define b_block q4
1265
1266#define uv_dx4 d10
1267#define rg_dx4 d11
1268#define uv_dx8 d12
1269#define rg_dx8 d13
1270#define b_whole_8 d14
1271#define fb_mask_ptrs d15
1272
1273#define uvrg_dx4 q5
1274#define uvrg_dx8 q6
1275#define uv_dx8 d12
1276#define rg_dx8 d13
1277
1278#define u_whole q8
1279#define v_whole q9
1280#define r_whole q10
1281#define g_whole q11
1282#define b_whole q12
1283
1284#define u_whole_low d16
1285#define u_whole_high d17
1286#define v_whole_low d18
1287#define v_whole_high d19
1288#define r_whole_low d20
1289#define r_whole_high d21
1290#define g_whole_low d22
1291#define g_whole_high d23
1292#define b_whole_low d24
1293#define b_whole_high d25
1294
1295#define dx4 q13
1296#define dx8 q13
1297
1298#define u_whole_8 d26
1299#define v_whole_8 d27
1300#define u_whole_8b d24
1301#define r_whole_8 d24
1302#define g_whole_8 d25
1303
1304#define uv_whole_8 q13
1305#define uv_whole_8b q14
1306
1307#define dither_offsets q14
1308#define texture_mask q15
1309#define texture_mask_u d30
1310#define texture_mask_v d31
1311
1312#define dither_offsets_short d28
1313
1314#define v_left_x q8
1315#define uvrg q9
1316#define block_span q10
1317
1318#define uv d18
1319#define rg d19
1320
1321#define draw_mask q1
1322#define draw_mask_edge q13
1323#define test_mask q0
1324
1325#define uvrg_dx q3
1326
1327#define colors q2
1328
1329#define setup_blocks_texture_swizzled() \
1330 vand.u8 u_whole_8b, u_whole_8, texture_mask_u; \
1331 vsli.u8 u_whole_8, v_whole_8, #4; \
1332 vsri.u8 v_whole_8, u_whole_8b, #4 \
1333
1334#define setup_blocks_texture_unswizzled() \
1335
1336
1337#define setup_blocks_shaded_textured_builder(swizzling) \
1338.align 3; \
1339 \
1340function(setup_blocks_shaded_textured_dithered_##swizzling##_indirect) \
e1f6de8f 1341 ldrh num_spans, [psx_gpu, #psx_gpu_num_spans_offset]; \
75e28f62
E
1342 add uvrg_dx_ptr, psx_gpu, #psx_gpu_uvrg_dx_offset; \
1343 \
e1f6de8f 1344 vld1.u32 { uvrg_dx }, [uvrg_dx_ptr, :128]; \
75e28f62
E
1345 add texture_mask_ptr, psx_gpu, #psx_gpu_texture_mask_width_offset; \
1346 \
1347 cmp num_spans, #0; \
1348 bxeq lr; \
1349 \
1350 stmdb sp!, { r4 - r11, r14 }; \
1351 vshl.u32 uvrg_dx4, uvrg_dx, #2; \
1352 \
e1f6de8f 1353 ldr b_dx, [psx_gpu, #psx_gpu_b_dx_offset]; \
75e28f62
E
1354 vshl.u32 uvrg_dx8, uvrg_dx, #3; \
1355 \
e1f6de8f 1356 vld2.u8 { texture_mask_u[], texture_mask_v[] }, [texture_mask_ptr, :16]; \
75e28f62
E
1357 add span_uvrg_offset, psx_gpu, #psx_gpu_span_uvrg_offset_offset; \
1358 \
e1f6de8f 1359 ldrh num_blocks, [psx_gpu, #psx_gpu_num_blocks_offset]; \
75e28f62
E
1360 add span_edge_data, psx_gpu, #psx_gpu_span_edge_data_offset; \
1361 \
1362 add span_b_offset, psx_gpu, #psx_gpu_span_b_offset_offset; \
1363 add block_ptr_a, psx_gpu, #psx_gpu_blocks_offset; \
1364 \
1365 add block_ptr_a, block_ptr_a, num_blocks, lsl #6; \
1366 \
1367 0: \
1368 vmov.u8 fb_mask_ptrs, #0; \
1369 \
e1f6de8f 1370 ldrh span_num_blocks, [span_edge_data, #edge_data_num_blocks_offset]; \
75e28f62
E
1371 add dither_offset_ptr, psx_gpu, #psx_gpu_dither_table_offset; \
1372 \
e1f6de8f 1373 ldrh y, [span_edge_data, #edge_data_y_offset]; \
1374 ldr fb_ptr, [psx_gpu, #psx_gpu_vram_out_ptr_offset]; \
75e28f62
E
1375 \
1376 cmp span_num_blocks, #0; \
1377 beq 1f; \
1378 \
e1f6de8f 1379 ldrh left_x, [span_edge_data, #edge_data_left_x_offset]; \
75e28f62
E
1380 add num_blocks, span_num_blocks, num_blocks; \
1381 \
1382 cmp num_blocks, #MAX_BLOCKS; \
1383 bgt 2f; \
1384 \
1385 3: \
e1f6de8f 1386 ldr b, [span_b_offset]; \
75e28f62
E
1387 add fb_ptr, fb_ptr, y, lsl #11; \
1388 \
1389 vdup.u32 v_left_x, left_x; \
1390 and y, y, #0x3; \
1391 \
e1f6de8f 1392 ldr dither_row, [dither_offset_ptr, y, lsl #2]; \
75e28f62
E
1393 add fb_ptr, fb_ptr, left_x, lsl #1; \
1394 \
1395 mla b, b_dx, left_x, b; \
1396 and dither_shift, left_x, #0x03; \
1397 \
e1f6de8f 1398 vld1.u32 { uvrg }, [span_uvrg_offset, :128]; \
75e28f62
E
1399 vshr.u32 uvrg_dx, uvrg_dx4, #2; \
1400 \
1401 mov dither_shift, dither_shift, lsl #3; \
1402 vmla.u32 uvrg, uvrg_dx, v_left_x; \
1403 \
1404 mov c_32, #32; \
1405 subs span_num_blocks, span_num_blocks, #1; \
1406 \
1407 mov dither_row, dither_row, ror dither_shift; \
1408 mov b_dx4, b_dx, lsl #2; \
1409 \
1410 vdup.u32 dither_offsets_short, dither_row; \
1411 add block_span_ptr, psx_gpu, #psx_gpu_u_block_span_offset; \
1412 \
1413 vdup.u32 b_block, b; \
1414 vshll.s8 dither_offsets, dither_offsets_short, #4; \
1415 \
1416 vdup.u32 u_block, uv[0]; \
1417 mov b_dx8, b_dx, lsl #3; \
1418 \
1419 vdup.u32 v_block, uv[1]; \
1420 vdup.u32 r_block, rg[0]; \
1421 vdup.u32 g_block, rg[1]; \
1422 \
e1f6de8f 1423 vld1.u32 { block_span }, [block_span_ptr, :128]!; \
75e28f62
E
1424 \
1425 vadd.u32 u_block, u_block, block_span; \
e1f6de8f 1426 vld1.u32 { block_span }, [block_span_ptr, :128]!; \
75e28f62
E
1427 \
1428 vadd.u32 v_block, v_block, block_span; \
e1f6de8f 1429 vld1.u32 { block_span }, [block_span_ptr, :128]!; \
75e28f62
E
1430 \
1431 vadd.u32 r_block, r_block, block_span; \
e1f6de8f 1432 vld1.u32 { block_span }, [block_span_ptr, :128]!; \
75e28f62
E
1433 \
1434 vadd.u32 g_block, g_block, block_span; \
e1f6de8f 1435 vld1.u32 { block_span }, [block_span_ptr, :128]; \
75e28f62
E
1436 \
1437 vadd.u32 b_block, b_block, block_span; \
1438 add block_ptr_b, block_ptr_a, #16; \
1439 \
1440 vshrn.u32 u_whole_low, u_block, #16; \
1441 vshrn.u32 v_whole_low, v_block, #16; \
1442 vshrn.u32 r_whole_low, r_block, #16; \
1443 vshrn.u32 g_whole_low, g_block, #16; \
1444 \
1445 vdup.u32 dx4, uv_dx4[0]; \
1446 vshrn.u32 b_whole_low, b_block, #16; \
1447 \
1448 vaddhn.u32 u_whole_high, u_block, dx4; \
1449 vdup.u32 dx4, uv_dx4[1]; \
1450 \
1451 vaddhn.u32 v_whole_high, v_block, dx4; \
1452 vdup.u32 dx4, rg_dx4[0]; \
1453 \
1454 vaddhn.u32 r_whole_high, r_block, dx4; \
1455 vdup.u32 dx4, rg_dx4[1]; \
1456 \
1457 vaddhn.u32 g_whole_high, g_block, dx4; \
1458 vdup.u32 dx4, b_dx4; \
1459 \
1460 vaddhn.u32 b_whole_high, b_block, dx4; \
1461 vdup.u32 dx8, uv_dx8[0]; \
1462 \
1463 vadd.u32 u_block, u_block, dx8; \
1464 vdup.u32 dx8, uv_dx8[1]; \
1465 \
1466 vadd.u32 v_block, v_block, dx8; \
1467 vdup.u32 dx8, rg_dx8[0]; \
1468 \
1469 vadd.u32 r_block, r_block, dx8; \
1470 vdup.u32 dx8, rg_dx8[1]; \
1471 \
1472 vadd.u32 g_block, g_block, dx8; \
1473 vdup.u32 dx8, b_dx8; \
1474 \
1475 vadd.u32 b_block, b_block, dx8; \
1476 vmovn.u16 u_whole_8, u_whole; \
1477 \
1478 vmovn.u16 v_whole_8, v_whole; \
1479 \
1480 vmovn.u16 b_whole_8, b_whole; \
e1f6de8f 1481 pld [fb_ptr]; \
75e28f62
E
1482 vmov.u32 fb_mask_ptrs[1], fb_ptr; \
1483 \
1484 vand.u8 uv_whole_8, uv_whole_8, texture_mask; \
1485 setup_blocks_texture_##swizzling(); \
1486 \
1487 vmovn.u16 r_whole_8, r_whole; \
1488 beq 5f; \
1489 \
1490 4: \
1491 vmovn.u16 g_whole_8, g_whole; \
1492 vshrn.u32 u_whole_low, u_block, #16; \
1493 \
e1f6de8f 1494 vst2.u8 { u_whole_8, v_whole_8 }, [block_ptr_a, :128], c_32; \
75e28f62
E
1495 vshrn.u32 v_whole_low, v_block, #16; \
1496 \
e1f6de8f 1497 vst1.u32 { r_whole_8, g_whole_8 }, [block_ptr_b, :128], c_32; \
75e28f62
E
1498 vshrn.u32 r_whole_low, r_block, #16; \
1499 \
e1f6de8f 1500 vst1.u32 { b_whole_8, fb_mask_ptrs }, [block_ptr_a, :128], c_32; \
75e28f62
E
1501 vshrn.u32 g_whole_low, g_block, #16; \
1502 \
1503 vdup.u32 dx4, uv_dx4[0]; \
1504 vshrn.u32 b_whole_low, b_block, #16; \
1505 \
1506 vaddhn.u32 u_whole_high, u_block, dx4; \
1507 vdup.u32 dx4, uv_dx4[1]; \
1508 \
1509 vaddhn.u32 v_whole_high, v_block, dx4; \
1510 vdup.u32 dx4, rg_dx4[0]; \
1511 \
1512 vaddhn.u32 r_whole_high, r_block, dx4; \
1513 vdup.u32 dx4, rg_dx4[1]; \
1514 \
1515 vaddhn.u32 g_whole_high, g_block, dx4; \
1516 vdup.u32 dx4, b_dx4; \
1517 \
1518 vaddhn.u32 b_whole_high, b_block, dx4; \
1519 vdup.u32 dx8, uv_dx8[0]; \
1520 \
1521 vadd.u32 u_block, u_block, dx8; \
1522 vdup.u32 dx8, uv_dx8[1]; \
1523 \
1524 vadd.u32 v_block, v_block, dx8; \
1525 vdup.u32 dx8, rg_dx8[0]; \
1526 \
1527 vadd.u32 r_block, r_block, dx8; \
1528 vdup.u32 dx8, rg_dx8[1]; \
1529 \
1530 vadd.u32 g_block, g_block, dx8; \
1531 vdup.u32 dx8, b_dx8; \
1532 \
1533 vadd.u32 b_block, b_block, dx8; \
1534 vmovn.u16 u_whole_8, u_whole; \
1535 \
1536 add fb_ptr, fb_ptr, #16; \
1537 vmovn.u16 v_whole_8, v_whole; \
1538 \
e1f6de8f 1539 vst1.u32 { dither_offsets }, [block_ptr_b, :128], c_32; \
75e28f62
E
1540 vmovn.u16 b_whole_8, b_whole; \
1541 \
e1f6de8f 1542 pld [fb_ptr]; \
75e28f62
E
1543 \
1544 vmov.u32 fb_mask_ptrs[1], fb_ptr; \
1545 subs span_num_blocks, span_num_blocks, #1; \
1546 \
1547 vand.u8 uv_whole_8, uv_whole_8, texture_mask; \
1548 setup_blocks_texture_##swizzling(); \
1549 \
1550 vmovn.u16 r_whole_8, r_whole; \
1551 bne 4b; \
1552 \
1553 5: \
1554 vmovn.u16 g_whole_8, g_whole; \
e1f6de8f 1555 ldrh right_mask, [span_edge_data, #edge_data_right_mask_offset]; \
75e28f62 1556 \
e1f6de8f 1557 vld1.u32 { test_mask }, [psx_gpu, :128]; \
75e28f62
E
1558 vdup.u8 draw_mask, right_mask; \
1559 \
1560 vmov.u32 fb_mask_ptrs[0], right_mask; \
1561 vtst.u16 draw_mask, draw_mask, test_mask; \
1562 vzip.u8 u_whole_8, v_whole_8; \
1563 \
1564 vbic.u16 uv_whole_8, uv_whole_8, draw_mask; \
e1f6de8f 1565 vst1.u32 { r_whole_8, g_whole_8 }, [block_ptr_b, :128], c_32; \
1566 vst1.u32 { uv_whole_8 }, [block_ptr_a, :128], c_32; \
1567 vst1.u32 { dither_offsets }, [block_ptr_b, :128], c_32; \
1568 vst1.u32 { b_whole_8, fb_mask_ptrs }, [block_ptr_a, :128], c_32; \
75e28f62
E
1569 \
1570 1: \
1571 add span_uvrg_offset, span_uvrg_offset, #16; \
1572 add span_b_offset, span_b_offset, #4; \
1573 \
1574 add span_edge_data, span_edge_data, #8; \
1575 subs num_spans, num_spans, #1; \
1576 \
e1f6de8f 1577 strh num_blocks, [psx_gpu, #psx_gpu_num_blocks_offset]; \
75e28f62
E
1578 bne 0b; \
1579 \
1580 ldmia sp!, { r4 - r11, pc }; \
1581 \
1582 2: \
1583 /* TODO: Load from psx_gpu instead of saving/restoring these */\
1584 vpush { texture_mask }; \
1585 vpush { uvrg_dx4 }; \
1586 \
4d646738 1587 stmdb sp!, { r0 - r3, EXTRA_UNSAVED_REGS r12, r14 }; \
75e28f62 1588 bl flush_render_block_buffer; \
4d646738 1589 ldmia sp!, { r0 - r3, EXTRA_UNSAVED_REGS r12, r14 }; \
75e28f62
E
1590 \
1591 vpop { uvrg_dx4 }; \
1592 vpop { texture_mask }; \
1593 \
1594 vadd.u32 uvrg_dx8, uvrg_dx4, uvrg_dx4; \
1595 vmov.u8 fb_mask_ptrs, #0; \
1596 \
1597 mov num_blocks, span_num_blocks; \
1598 add block_ptr_a, psx_gpu, #psx_gpu_blocks_offset; \
1599 bal 3b \
1600
1601
1602setup_blocks_shaded_textured_builder(swizzled)
1603setup_blocks_shaded_textured_builder(unswizzled)
1604
1605
1606#define setup_blocks_unshaded_textured_builder(swizzling) \
1607.align 3; \
1608 \
1609function(setup_blocks_unshaded_textured_dithered_##swizzling##_indirect) \
e1f6de8f 1610 ldrh num_spans, [psx_gpu, #psx_gpu_num_spans_offset]; \
75e28f62
E
1611 add uvrg_dx_ptr, psx_gpu, #psx_gpu_uvrg_dx_offset; \
1612 \
e1f6de8f 1613 vld1.u32 { uvrg_dx }, [uvrg_dx_ptr, :128]; \
75e28f62
E
1614 add texture_mask_ptr, psx_gpu, #psx_gpu_texture_mask_width_offset; \
1615 \
1616 cmp num_spans, #0; \
1617 bxeq lr; \
1618 \
1619 stmdb sp!, { r4 - r11, r14 }; \
1620 vshl.u32 uvrg_dx4, uvrg_dx, #2; \
1621 \
1622 vshl.u32 uvrg_dx8, uvrg_dx, #3; \
1623 \
e1f6de8f 1624 vld2.u8 { texture_mask_u[], texture_mask_v[] }, [texture_mask_ptr, :16]; \
75e28f62
E
1625 add span_uvrg_offset, psx_gpu, #psx_gpu_span_uvrg_offset_offset; \
1626 \
e1f6de8f 1627 ldrh num_blocks, [psx_gpu, #psx_gpu_num_blocks_offset]; \
75e28f62
E
1628 add span_edge_data, psx_gpu, #psx_gpu_span_edge_data_offset; \
1629 \
1630 add block_ptr_a, psx_gpu, #psx_gpu_blocks_offset; \
1631 \
1632 add block_ptr_a, block_ptr_a, num_blocks, lsl #6; \
1633 \
1634 0: \
1635 vmov.u8 fb_mask_ptrs, #0; \
1636 \
e1f6de8f 1637 ldrh span_num_blocks, [span_edge_data, #edge_data_num_blocks_offset]; \
75e28f62
E
1638 add dither_offset_ptr, psx_gpu, #psx_gpu_dither_table_offset; \
1639 \
e1f6de8f 1640 ldrh y, [span_edge_data, #edge_data_y_offset]; \
1641 ldr fb_ptr, [psx_gpu, #psx_gpu_vram_out_ptr_offset]; \
75e28f62
E
1642 \
1643 cmp span_num_blocks, #0; \
1644 beq 1f; \
1645 \
e1f6de8f 1646 ldrh left_x, [span_edge_data, #edge_data_left_x_offset]; \
75e28f62
E
1647 add num_blocks, span_num_blocks, num_blocks; \
1648 \
1649 cmp num_blocks, #MAX_BLOCKS; \
1650 bgt 2f; \
1651 \
1652 3: \
1653 add fb_ptr, fb_ptr, y, lsl #11; \
1654 \
1655 vdup.u32 v_left_x, left_x; \
1656 and y, y, #0x3; \
1657 \
e1f6de8f 1658 ldr dither_row, [dither_offset_ptr, y, lsl #2]; \
75e28f62
E
1659 add fb_ptr, fb_ptr, left_x, lsl #1; \
1660 \
1661 and dither_shift, left_x, #0x03; \
1662 \
e1f6de8f 1663 vld1.u32 { uvrg }, [span_uvrg_offset, :128]; \
75e28f62
E
1664 vshr.u32 uvrg_dx, uvrg_dx4, #2; \
1665 \
1666 mov dither_shift, dither_shift, lsl #3; \
1667 vmla.u32 uvrg, uvrg_dx, v_left_x; \
1668 \
1669 mov c_32, #32; \
1670 subs span_num_blocks, span_num_blocks, #1; \
1671 \
1672 mov dither_row, dither_row, ror dither_shift; \
1673 \
1674 vdup.u32 dither_offsets_short, dither_row; \
1675 add block_span_ptr, psx_gpu, #psx_gpu_u_block_span_offset; \
1676 \
1677 vshll.s8 dither_offsets, dither_offsets_short, #4; \
1678 \
1679 vdup.u32 u_block, uv[0]; \
1680 \
1681 vdup.u32 v_block, uv[1]; \
e1f6de8f 1682 vld1.u32 { block_span }, [block_span_ptr, :128]!; \
75e28f62
E
1683 \
1684 vadd.u32 u_block, u_block, block_span; \
e1f6de8f 1685 vld1.u32 { block_span }, [block_span_ptr, :128]!; \
75e28f62
E
1686 \
1687 vadd.u32 v_block, v_block, block_span; \
1688 add block_ptr_b, block_ptr_a, #16; \
1689 \
1690 vshrn.u32 u_whole_low, u_block, #16; \
1691 vshrn.u32 v_whole_low, v_block, #16; \
1692 \
1693 vdup.u32 dx4, uv_dx4[0]; \
1694 \
1695 vaddhn.u32 u_whole_high, u_block, dx4; \
1696 vdup.u32 dx4, uv_dx4[1]; \
1697 \
1698 vaddhn.u32 v_whole_high, v_block, dx4; \
1699 vdup.u32 dx8, uv_dx8[0]; \
1700 \
1701 vadd.u32 u_block, u_block, dx8; \
1702 vdup.u32 dx8, uv_dx8[1]; \
1703 \
1704 vadd.u32 v_block, v_block, dx8; \
1705 vmovn.u16 u_whole_8, u_whole; \
1706 \
1707 vmovn.u16 v_whole_8, v_whole; \
1708 \
e1f6de8f 1709 pld [fb_ptr]; \
75e28f62
E
1710 vmov.u32 fb_mask_ptrs[1], fb_ptr; \
1711 \
1712 vand.u8 uv_whole_8, uv_whole_8, texture_mask; \
1713 setup_blocks_texture_##swizzling(); \
1714 \
1715 beq 5f; \
1716 \
1717 4: \
1718 vshrn.u32 u_whole_low, u_block, #16; \
1719 \
e1f6de8f 1720 vst2.u8 { u_whole_8, v_whole_8 }, [block_ptr_a, :128], c_32; \
75e28f62
E
1721 vshrn.u32 v_whole_low, v_block, #16; \
1722 \
1723 add block_ptr_b, block_ptr_b, #32; \
e1f6de8f 1724 vst1.u32 { b_whole_8, fb_mask_ptrs }, [block_ptr_a, :128], c_32; \
75e28f62
E
1725 \
1726 vdup.u32 dx4, uv_dx4[0]; \
1727 vaddhn.u32 u_whole_high, u_block, dx4; \
1728 vdup.u32 dx4, uv_dx4[1]; \
1729 \
1730 vaddhn.u32 v_whole_high, v_block, dx4; \
1731 vdup.u32 dx8, uv_dx8[0]; \
1732 \
1733 vadd.u32 u_block, u_block, dx8; \
1734 vdup.u32 dx8, uv_dx8[1]; \
1735 \
1736 vadd.u32 v_block, v_block, dx8; \
1737 vmovn.u16 u_whole_8, u_whole; \
1738 \
1739 add fb_ptr, fb_ptr, #16; \
1740 vmovn.u16 v_whole_8, v_whole; \
1741 \
e1f6de8f 1742 vst1.u32 { dither_offsets }, [block_ptr_b, :128], c_32; \
1743 pld [fb_ptr]; \
75e28f62
E
1744 \
1745 vmov.u32 fb_mask_ptrs[1], fb_ptr; \
1746 subs span_num_blocks, span_num_blocks, #1; \
1747 \
1748 vand.u8 uv_whole_8, uv_whole_8, texture_mask; \
1749 setup_blocks_texture_##swizzling(); \
1750 \
1751 bne 4b; \
1752 \
1753 5: \
e1f6de8f 1754 ldrh right_mask, [span_edge_data, #edge_data_right_mask_offset]; \
75e28f62 1755 \
e1f6de8f 1756 vld1.u32 { test_mask }, [psx_gpu, :128]; \
75e28f62
E
1757 vdup.u8 draw_mask, right_mask; \
1758 \
1759 vmov.u32 fb_mask_ptrs[0], right_mask; \
1760 vtst.u16 draw_mask, draw_mask, test_mask; \
1761 vzip.u8 u_whole_8, v_whole_8; \
1762 \
1763 vbic.u16 uv_whole_8, uv_whole_8, draw_mask; \
1764 add block_ptr_b, block_ptr_b, #32; \
e1f6de8f 1765 vst1.u32 { uv_whole_8 }, [block_ptr_a, :128], c_32; \
1766 vst1.u32 { dither_offsets }, [block_ptr_b, :128], c_32; \
1767 vst1.u32 { b_whole_8, fb_mask_ptrs }, [block_ptr_a, :128], c_32; \
75e28f62
E
1768 \
1769 1: \
1770 add span_uvrg_offset, span_uvrg_offset, #16; \
1771 add span_edge_data, span_edge_data, #8; \
1772 subs num_spans, num_spans, #1; \
1773 \
e1f6de8f 1774 strh num_blocks, [psx_gpu, #psx_gpu_num_blocks_offset]; \
75e28f62
E
1775 bne 0b; \
1776 \
1777 ldmia sp!, { r4 - r11, pc }; \
1778 \
1779 2: \
1780 /* TODO: Load from psx_gpu instead of saving/restoring these */\
1781 vpush { texture_mask }; \
1782 vpush { uvrg_dx4 }; \
1783 \
4d646738 1784 stmdb sp!, { r0 - r3, EXTRA_UNSAVED_REGS r12, r14 }; \
75e28f62 1785 bl flush_render_block_buffer; \
4d646738 1786 ldmia sp!, { r0 - r3, EXTRA_UNSAVED_REGS r12, r14 }; \
75e28f62
E
1787 \
1788 vpop { uvrg_dx4 }; \
1789 vpop { texture_mask }; \
1790 \
1791 vadd.u32 uvrg_dx8, uvrg_dx4, uvrg_dx4; \
1792 vmov.u8 fb_mask_ptrs, #0; \
1793 \
1794 mov num_blocks, span_num_blocks; \
1795 add block_ptr_a, psx_gpu, #psx_gpu_blocks_offset; \
1796 bal 3b \
1797
1798
1799setup_blocks_unshaded_textured_builder(swizzled)
1800setup_blocks_unshaded_textured_builder(unswizzled)
1801
1802
1803.align 3
1804
1805function(setup_blocks_unshaded_untextured_undithered_unswizzled_indirect)
e1f6de8f 1806 ldrh num_spans, [psx_gpu, #psx_gpu_num_spans_offset]
75e28f62
E
1807 veor.u32 draw_mask, draw_mask, draw_mask
1808
1809 cmp num_spans, #0
1810 bxeq lr
1811
1812 stmdb sp!, { r4 - r11, r14 }
e1f6de8f 1813 vld1.u32 { test_mask }, [psx_gpu, :128]
75e28f62 1814
e1f6de8f 1815 ldr color, [psx_gpu, #psx_gpu_triangle_color_offset]
75e28f62
E
1816
1817 ubfx color_r, color, #3, #5
1818 ubfx color_g, color, #11, #5
1819 ubfx color_b, color, #19, #5
1820
1821 orr color, color_r, color_b, lsl #10
1822 orr color, color, color_g, lsl #5
1823
1824 vdup.u16 colors, color
1825
e1f6de8f 1826 ldrh num_blocks, [psx_gpu, #psx_gpu_num_blocks_offset]
75e28f62
E
1827 add span_edge_data, psx_gpu, #psx_gpu_span_edge_data_offset
1828
1829 add block_ptr_a, psx_gpu, #psx_gpu_blocks_offset
1830 add block_ptr_a, block_ptr_a, num_blocks, lsl #6
1831
1832 0:
e1f6de8f 1833 ldrh span_num_blocks, [span_edge_data, #edge_data_num_blocks_offset]
1834 ldrh y, [span_edge_data, #edge_data_y_offset]
75e28f62 1835
e1f6de8f 1836 ldr fb_ptr, [psx_gpu, #psx_gpu_vram_out_ptr_offset]
75e28f62
E
1837
1838 cmp span_num_blocks, #0
1839 beq 1f
1840
e1f6de8f 1841 ldrh left_x, [span_edge_data, #edge_data_left_x_offset]
75e28f62
E
1842 add num_blocks, span_num_blocks, num_blocks
1843
1844 cmp num_blocks, #MAX_BLOCKS
1845 bgt 2f
1846
1847 3:
1848 add fb_ptr, fb_ptr, y, lsl #11
1849 and y, y, #0x3
1850
1851 add fb_ptr, fb_ptr, left_x, lsl #1
1852 mov c_32, #32
1853
1854 subs span_num_blocks, span_num_blocks, #1
1855
1856 add block_ptr_b, block_ptr_a, #16
e1f6de8f 1857 pld [fb_ptr]
75e28f62
E
1858
1859 vmov.u32 fb_mask_ptrs[1], fb_ptr
1860 beq 5f
1861
1862 4:
e1f6de8f 1863 vst1.u32 { draw_mask }, [block_ptr_a, :128], c_32
1864 vst1.u32 { colors }, [block_ptr_b, :128], c_32
1865 vst1.u32 { b_whole_8, fb_mask_ptrs }, [block_ptr_a, :128], c_32
75e28f62
E
1866
1867 add fb_ptr, fb_ptr, #16
1868 add block_ptr_b, block_ptr_b, #32
1869
e1f6de8f 1870 pld [fb_ptr]
75e28f62
E
1871
1872 vmov.u32 fb_mask_ptrs[1], fb_ptr
1873 subs span_num_blocks, span_num_blocks, #1
1874
1875 bne 4b
1876
1877 5:
e1f6de8f 1878 ldrh right_mask, [span_edge_data, #edge_data_right_mask_offset]
75e28f62
E
1879
1880 vdup.u8 draw_mask_edge, right_mask
1881 vtst.u16 draw_mask_edge, draw_mask_edge, test_mask
1882
e1f6de8f 1883 vst1.u32 { colors }, [block_ptr_b, :128], c_32
1884 vst1.u32 { draw_mask_edge }, [block_ptr_a, :128], c_32
75e28f62 1885 add block_ptr_b, block_ptr_b, #32
e1f6de8f 1886 vst1.u32 { b_whole_8, fb_mask_ptrs }, [block_ptr_a, :128], c_32
75e28f62
E
1887
1888 1:
1889 add span_edge_data, span_edge_data, #8
1890 subs num_spans, num_spans, #1
1891
e1f6de8f 1892 strh num_blocks, [psx_gpu, #psx_gpu_num_blocks_offset]
75e28f62
E
1893 bne 0b
1894
1895 ldmia sp!, { r4 - r11, pc }
1896
1897 2:
1898 vpush { colors }
1899
4d646738 1900 stmdb sp!, { r0 - r3, EXTRA_UNSAVED_REGS r12, r14 }
75e28f62 1901 bl flush_render_block_buffer
4d646738 1902 ldmia sp!, { r0 - r3, EXTRA_UNSAVED_REGS r12, r14 }
75e28f62
E
1903
1904 vpop { colors }
1905
e1f6de8f 1906 vld1.u32 { test_mask }, [psx_gpu, :128]
75e28f62
E
1907 veor.u32 draw_mask, draw_mask, draw_mask
1908
1909 mov num_blocks, span_num_blocks
1910 add block_ptr_a, psx_gpu, #psx_gpu_blocks_offset
1911 bal 3b
1912
1913
1914#define mask_msb_scalar r14
1915
1916#define msb_mask q15
1917
1918#define pixels_low d16
1919
1920#define msb_mask_low d30
1921#define msb_mask_high d31
1922
1923
1924.align 3
1925
1926function(setup_blocks_unshaded_untextured_undithered_unswizzled_direct)
e1f6de8f 1927 ldrh num_spans, [psx_gpu, #psx_gpu_num_spans_offset]
75e28f62
E
1928
1929 cmp num_spans, #0
1930 bxeq lr
1931
1932 stmdb sp!, { r4 - r11, r14 }
1933
e1f6de8f 1934 ldr color, [psx_gpu, #psx_gpu_triangle_color_offset]
75e28f62
E
1935
1936 ubfx color_r, color, #3, #5
1937 ubfx color_g, color, #11, #5
1938
e1f6de8f 1939 ldrh mask_msb_scalar, [psx_gpu, #psx_gpu_mask_msb_offset]
75e28f62
E
1940 ubfx color_b, color, #19, #5
1941
1942 orr color, color_r, color_b, lsl #10
1943 orr color, color, color_g, lsl #5
1944 orr color, color, mask_msb_scalar
1945
1946 vdup.u16 colors, color
1947
1948 add span_edge_data, psx_gpu, #psx_gpu_span_edge_data_offset
ed0fd81d 1949 orr color, color, color, lsl #16
3867c6ef 1950
75e28f62
E
1951
1952 0:
e1f6de8f 1953 ldrh span_num_blocks, [span_edge_data, #edge_data_num_blocks_offset]
1954 ldrh y, [span_edge_data, #edge_data_y_offset]
75e28f62 1955
e1f6de8f 1956 ldr fb_ptr, [psx_gpu, #psx_gpu_vram_out_ptr_offset]
75e28f62
E
1957
1958 cmp span_num_blocks, #0
1959 beq 1f
1960
e1f6de8f 1961 ldrh left_x, [span_edge_data, #edge_data_left_x_offset]
75e28f62
E
1962
1963 add fb_ptr, fb_ptr, y, lsl #11
1964 subs span_num_blocks, span_num_blocks, #1
1965
1966 add fb_ptr, fb_ptr, left_x, lsl #1
1967 beq 3f
1968
1969 2:
e1f6de8f 1970 vst1.u32 { colors }, [fb_ptr]!
75e28f62
E
1971 subs span_num_blocks, span_num_blocks, #1
1972
1973 bne 2b
1974
1975 3:
e1f6de8f 1976 ldrb right_mask, [span_edge_data, #edge_data_right_mask_offset]
75e28f62 1977
3867c6ef
E
1978 cmp right_mask, #0x0
1979 beq 5f
1980
1981 tst right_mask, #0xF
e1f6de8f 1982 streq color, [fb_ptr], #4
3867c6ef 1983 moveq right_mask, right_mask, lsr #4
e1f6de8f 1984 streq color, [fb_ptr], #4
3867c6ef
E
1985
1986 tst right_mask, #0x3
e1f6de8f 1987 streq color, [fb_ptr], #4
3867c6ef
E
1988 moveq right_mask, right_mask, lsr #2
1989
1990 tst right_mask, #0x1
e1f6de8f 1991 strheq color, [fb_ptr]
75e28f62
E
1992
1993 1:
1994 add span_edge_data, span_edge_data, #8
1995 subs num_spans, num_spans, #1
75e28f62
E
1996 bne 0b
1997
1998 ldmia sp!, { r4 - r11, pc }
1999
3867c6ef 2000 5:
e1f6de8f 2001 vst1.u32 { colors }, [fb_ptr]
3867c6ef 2002 bal 1b
75e28f62
E
2003
2004
2005#undef c_64
2006
2007#define c_64 r7
2008#define rg_dx_ptr r2
2009
2010
2011#undef r_block
2012#undef g_block
2013#undef b_block
2014#undef r_whole
2015#undef g_whole
2016#undef b_whole
2017#undef r_whole_low
2018#undef r_whole_high
2019#undef g_whole_low
2020#undef g_whole_high
2021#undef b_whole_low
2022#undef b_whole_high
2023#undef r_whole_8
2024#undef g_whole_8
2025#undef b_whole_8
2026#undef dither_offsets
2027#undef rg_dx4
2028#undef rg_dx8
2029#undef dx4
2030#undef dx8
2031#undef v_left_x
2032#undef uvrg
2033#undef block_span
2034#undef rg
2035#undef draw_mask
2036#undef test_mask
2037
2038#define r_block q0
2039#define g_block q1
2040#define b_block q2
2041
2042#define r_whole q3
2043#define g_whole q4
2044#define b_whole q5
2045
2046#define r_whole_low d6
2047#define r_whole_high d7
2048#define g_whole_low d8
2049#define g_whole_high d9
2050#define b_whole_low d10
2051#define b_whole_high d11
2052
2053#define gb_whole_8 q6
2054
2055#define g_whole_8 d12
2056#define b_whole_8 d13
2057
2058#define r_whole_8 d14
2059
2060#define pixels q8
2061
2062#define rg_dx4 d18
2063#define rg_dx8 d19
2064
2065#define dx4 q10
2066#define dx8 q10
2067
2068#define v_left_x d6
2069#define uvrg q4
2070#define block_span q5
2071
2072#define rg d9
2073
2074#define d64_1 d22
2075#define d64_128 d23
2076
2077#define d128_4 q12
2078#define d128_0x7 q13
2079
2080#define d64_4 d24
2081
2082#define dither_offsets q14
2083#define draw_mask q15
2084
2085#define dither_offsets_low d28
2086
2087#define rg_dx d0
2088#define test_mask q10
2089
2090
2091#define setup_blocks_shaded_untextured_dither_a_dithered() \
2092 vqadd.u8 r_whole_8, r_whole_8, dither_offsets_low; \
2093 vqadd.u8 gb_whole_8, gb_whole_8, dither_offsets; \
2094
2095#define setup_blocks_shaded_untextured_dither_b_dithered() \
2096 vqsub.u8 r_whole_8, r_whole_8, d64_4; \
2097 vqsub.u8 gb_whole_8, gb_whole_8, d128_4 \
2098
2099#define setup_blocks_shaded_untextured_dither_a_undithered() \
2100
2101#define setup_blocks_shaded_untextured_dither_b_undithered() \
2102
2103
2104#define setup_blocks_shaded_untextured_indirect_builder(dithering) \
2105.align 3; \
2106 \
2107function(setup_blocks_shaded_untextured_##dithering##_unswizzled_indirect) \
e1f6de8f 2108 ldrh num_spans, [psx_gpu, #psx_gpu_num_spans_offset]; \
75e28f62
E
2109 add rg_dx_ptr, psx_gpu, #(psx_gpu_uvrg_dx_offset + 8); \
2110 \
e1f6de8f 2111 vld1.u32 { rg_dx }, [rg_dx_ptr, :64]; \
75e28f62
E
2112 \
2113 cmp num_spans, #0; \
2114 bxeq lr; \
2115 \
2116 stmdb sp!, { r4 - r11, r14 }; \
2117 vshl.u32 rg_dx4, rg_dx, #2; \
2118 \
e1f6de8f 2119 ldr b_dx, [psx_gpu, #psx_gpu_b_dx_offset]; \
75e28f62
E
2120 vshl.u32 rg_dx8, rg_dx, #3; \
2121 \
2122 add span_uvrg_offset, psx_gpu, #psx_gpu_span_uvrg_offset_offset; \
2123 \
e1f6de8f 2124 ldrh num_blocks, [psx_gpu, #psx_gpu_num_blocks_offset]; \
75e28f62
E
2125 add span_edge_data, psx_gpu, #psx_gpu_span_edge_data_offset; \
2126 \
2127 add span_b_offset, psx_gpu, #psx_gpu_span_b_offset_offset; \
2128 add block_ptr_a, psx_gpu, #psx_gpu_blocks_offset; \
2129 \
2130 add block_ptr_a, block_ptr_a, num_blocks, lsl #6; \
2131 vmov.u8 d64_1, #1; \
2132 \
2133 vmov.u8 d128_4, #4; \
2134 vmov.u8 d64_128, #128; \
2135 \
2136 vmov.u8 d128_0x7, #0x7; \
2137 \
2138 0: \
e1f6de8f 2139 ldrh span_num_blocks, [span_edge_data, #edge_data_num_blocks_offset]; \
75e28f62
E
2140 add dither_offset_ptr, psx_gpu, #psx_gpu_dither_table_offset; \
2141 \
e1f6de8f 2142 ldrh y, [span_edge_data, #edge_data_y_offset]; \
2143 ldr fb_ptr, [psx_gpu, #psx_gpu_vram_out_ptr_offset]; \
75e28f62
E
2144 \
2145 cmp span_num_blocks, #0; \
2146 beq 1f; \
2147 \
e1f6de8f 2148 ldrh left_x, [span_edge_data, #edge_data_left_x_offset]; \
75e28f62
E
2149 add num_blocks, span_num_blocks, num_blocks; \
2150 \
2151 cmp num_blocks, #MAX_BLOCKS; \
2152 bgt 2f; \
2153 \
2154 3: \
e1f6de8f 2155 ldr b, [span_b_offset]; \
75e28f62
E
2156 add fb_ptr, fb_ptr, y, lsl #11; \
2157 \
2158 vdup.u32 v_left_x, left_x; \
2159 and y, y, #0x3; \
2160 \
e1f6de8f 2161 ldr dither_row, [dither_offset_ptr, y, lsl #2]; \
75e28f62
E
2162 add fb_ptr, fb_ptr, left_x, lsl #1; \
2163 \
2164 mla b, b_dx, left_x, b; \
2165 and dither_shift, left_x, #0x03; \
2166 \
e1f6de8f 2167 vld1.u32 { uvrg }, [span_uvrg_offset, :128]; \
75e28f62
E
2168 vshr.u32 rg_dx, rg_dx4, #2; \
2169 \
2170 mov dither_shift, dither_shift, lsl #3; \
2171 vmla.u32 rg, rg_dx, v_left_x; \
2172 \
2173 mov c_64, #64; \
2174 subs span_num_blocks, span_num_blocks, #1; \
2175 \
2176 mov dither_row, dither_row, ror dither_shift; \
2177 mov b_dx4, b_dx, lsl #2; \
2178 \
2179 vdup.u32 dither_offsets, dither_row; \
2180 add block_span_ptr, psx_gpu, #psx_gpu_r_block_span_offset; \
2181 \
2182 vdup.u32 b_block, b; \
2183 vadd.u8 dither_offsets, dither_offsets, d128_4; \
2184 \
2185 mov b_dx8, b_dx, lsl #3; \
2186 vdup.u32 r_block, rg[0]; \
2187 vdup.u32 g_block, rg[1]; \
2188 \
e1f6de8f 2189 vld1.u32 { block_span }, [block_span_ptr, :128]!; \
75e28f62
E
2190 \
2191 vadd.u32 r_block, r_block, block_span; \
e1f6de8f 2192 vld1.u32 { block_span }, [block_span_ptr, :128]!; \
75e28f62
E
2193 \
2194 vadd.u32 g_block, g_block, block_span; \
e1f6de8f 2195 vld1.u32 { block_span }, [block_span_ptr, :128]; \
75e28f62
E
2196 \
2197 vadd.u32 b_block, b_block, block_span; \
2198 add block_ptr_b, block_ptr_a, #16; \
2199 \
2200 vshrn.u32 r_whole_low, r_block, #16; \
2201 vshrn.u32 g_whole_low, g_block, #16; \
2202 vshrn.u32 b_whole_low, b_block, #16; \
2203 vdup.u32 dx4, rg_dx4[0]; \
2204 \
2205 vaddhn.u32 r_whole_high, r_block, dx4; \
2206 vdup.u32 dx4, rg_dx4[1]; \
2207 \
2208 vaddhn.u32 g_whole_high, g_block, dx4; \
2209 vdup.u32 dx4, b_dx4; \
2210 \
2211 vaddhn.u32 b_whole_high, b_block, dx4; \
2212 vdup.u32 dx8, rg_dx8[0]; \
2213 \
2214 vadd.u32 r_block, r_block, dx8; \
2215 vdup.u32 dx8, rg_dx8[1]; \
2216 \
2217 vadd.u32 g_block, g_block, dx8; \
2218 vdup.u32 dx8, b_dx8; \
2219 \
2220 vadd.u32 b_block, b_block, dx8; \
2221 \
2222 vmovn.u16 r_whole_8, r_whole; \
2223 vmovn.u16 g_whole_8, g_whole; \
2224 vmovn.u16 b_whole_8, b_whole; \
2225 \
2226 beq 5f; \
2227 veor.u32 draw_mask, draw_mask, draw_mask; \
2228 \
2229 4: \
2230 setup_blocks_shaded_untextured_dither_a_##dithering(); \
2231 vshrn.u32 r_whole_low, r_block, #16; \
2232 \
2233 setup_blocks_shaded_untextured_dither_b_##dithering(); \
2234 vshrn.u32 g_whole_low, g_block, #16; \
2235 \
2236 vshrn.u32 b_whole_low, b_block, #16; \
e1f6de8f 2237 str fb_ptr, [block_ptr_a, #44]; \
75e28f62
E
2238 \
2239 vdup.u32 dx4, rg_dx4[0]; \
2240 vshr.u8 r_whole_8, r_whole_8, #3; \
2241 vbic.u8 gb_whole_8, gb_whole_8, d128_0x7; \
2242 \
2243 vaddhn.u32 r_whole_high, r_block, dx4; \
2244 vdup.u32 dx4, rg_dx4[1]; \
2245 \
2246 vaddhn.u32 g_whole_high, g_block, dx4; \
2247 vdup.u32 dx4, b_dx4; \
2248 \
2249 vaddhn.u32 b_whole_high, b_block, dx4; \
2250 vdup.u32 dx8, rg_dx8[0]; \
2251 \
2252 vmull.u8 pixels, r_whole_8, d64_1; \
2253 vmlal.u8 pixels, g_whole_8, d64_4; \
2254 vmlal.u8 pixels, b_whole_8, d64_128; \
2255 \
2256 vadd.u32 r_block, r_block, dx8; \
2257 vdup.u32 dx8, rg_dx8[1]; \
2258 \
2259 vadd.u32 g_block, g_block, dx8; \
2260 vdup.u32 dx8, b_dx8; \
2261 \
2262 vadd.u32 b_block, b_block, dx8; \
2263 add fb_ptr, fb_ptr, #16; \
2264 \
2265 vmovn.u16 r_whole_8, r_whole; \
2266 vmovn.u16 g_whole_8, g_whole; \
2267 vmovn.u16 b_whole_8, b_whole; \
2268 \
e1f6de8f 2269 vst1.u32 { draw_mask }, [block_ptr_a, :128], c_64; \
2270 vst1.u32 { pixels }, [block_ptr_b, :128], c_64; \
75e28f62 2271 \
e1f6de8f 2272 pld [fb_ptr]; \
75e28f62
E
2273 \
2274 subs span_num_blocks, span_num_blocks, #1; \
2275 bne 4b; \
2276 \
2277 5: \
e1f6de8f 2278 str fb_ptr, [block_ptr_a, #44]; \
75e28f62
E
2279 setup_blocks_shaded_untextured_dither_a_##dithering(); \
2280 \
e1f6de8f 2281 ldrh right_mask, [span_edge_data, #edge_data_right_mask_offset]; \
75e28f62
E
2282 setup_blocks_shaded_untextured_dither_b_##dithering(); \
2283 \
2284 vshr.u8 r_whole_8, r_whole_8, #3; \
2285 vdup.u8 draw_mask, right_mask; \
2286 \
2287 vbic.u8 gb_whole_8, gb_whole_8, d128_0x7; \
e1f6de8f 2288 vld1.u32 { test_mask }, [psx_gpu, :128]; \
75e28f62
E
2289 \
2290 vtst.u16 draw_mask, draw_mask, test_mask; \
2291 \
2292 vmull.u8 pixels, r_whole_8, d64_1; \
2293 vmlal.u8 pixels, g_whole_8, d64_4; \
2294 vmlal.u8 pixels, b_whole_8, d64_128; \
2295 \
e1f6de8f 2296 vst1.u32 { draw_mask }, [block_ptr_a, :128], c_64; \
2297 vst1.u32 { pixels }, [block_ptr_b, :128], c_64; \
75e28f62
E
2298 \
2299 1: \
2300 add span_uvrg_offset, span_uvrg_offset, #16; \
2301 add span_b_offset, span_b_offset, #4; \
2302 \
2303 add span_edge_data, span_edge_data, #8; \
2304 subs num_spans, num_spans, #1; \
2305 \
e1f6de8f 2306 strh num_blocks, [psx_gpu, #psx_gpu_num_blocks_offset]; \
75e28f62
E
2307 bne 0b; \
2308 \
2309 ldmia sp!, { r4 - r11, pc }; \
2310 \
2311 2: \
2312 /* TODO: Load from psx_gpu instead of saving/restoring these */\
2313 vpush { rg_dx4 }; \
2314 \
4d646738 2315 stmdb sp!, { r0 - r3, EXTRA_UNSAVED_REGS r12, r14 }; \
75e28f62 2316 bl flush_render_block_buffer; \
4d646738 2317 ldmia sp!, { r0 - r3, EXTRA_UNSAVED_REGS r12, r14 }; \
75e28f62
E
2318 \
2319 vpop { rg_dx4 }; \
2320 \
2321 vmov.u8 d64_1, #1; \
2322 vmov.u8 d128_4, #4; \
2323 vmov.u8 d64_128, #128; \
2324 vmov.u8 d128_0x7, #0x7; \
2325 \
2326 vadd.u32 rg_dx8, rg_dx4, rg_dx4; \
2327 \
2328 mov num_blocks, span_num_blocks; \
2329 add block_ptr_a, psx_gpu, #psx_gpu_blocks_offset; \
2330 bal 3b \
2331
2332
2333setup_blocks_shaded_untextured_indirect_builder(undithered)
2334setup_blocks_shaded_untextured_indirect_builder(dithered)
2335
2336
2337#undef draw_mask
2338
2339#define mask_msb_ptr r14
2340
2341#define draw_mask q0
2342#define pixels_low d16
3867c6ef 2343#define pixels_high d17
75e28f62
E
2344
2345
2346
2347#define setup_blocks_shaded_untextured_direct_builder(dithering) \
2348.align 3; \
2349 \
2350function(setup_blocks_shaded_untextured_##dithering##_unswizzled_direct) \
e1f6de8f 2351 ldrh num_spans, [psx_gpu, #psx_gpu_num_spans_offset]; \
75e28f62
E
2352 add rg_dx_ptr, psx_gpu, #(psx_gpu_uvrg_dx_offset + 8); \
2353 \
e1f6de8f 2354 vld1.u32 { rg_dx }, [rg_dx_ptr, :64]; \
75e28f62
E
2355 \
2356 cmp num_spans, #0; \
2357 bxeq lr; \
2358 \
2359 stmdb sp!, { r4 - r11, r14 }; \
2360 vshl.u32 rg_dx4, rg_dx, #2; \
2361 \
e1f6de8f 2362 ldr b_dx, [psx_gpu, #psx_gpu_b_dx_offset]; \
75e28f62
E
2363 vshl.u32 rg_dx8, rg_dx, #3; \
2364 \
2365 add span_uvrg_offset, psx_gpu, #psx_gpu_span_uvrg_offset_offset; \
2366 add span_edge_data, psx_gpu, #psx_gpu_span_edge_data_offset; \
2367 \
2368 add span_b_offset, psx_gpu, #psx_gpu_span_b_offset_offset; \
2369 vmov.u8 d64_1, #1; \
2370 \
2371 vmov.u8 d128_4, #4; \
2372 vmov.u8 d64_128, #128; \
2373 \
2374 vmov.u8 d128_0x7, #0x7; \
2375 add mask_msb_ptr, psx_gpu, #psx_gpu_mask_msb_offset; \
e1f6de8f 2376 vld1.u16 { msb_mask_low[], msb_mask_high[] }, [mask_msb_ptr, :16]; \
75e28f62
E
2377 \
2378 0: \
e1f6de8f 2379 ldrh span_num_blocks, [span_edge_data, #edge_data_num_blocks_offset]; \
75e28f62
E
2380 add dither_offset_ptr, psx_gpu, #psx_gpu_dither_table_offset; \
2381 \
e1f6de8f 2382 ldrh y, [span_edge_data, #edge_data_y_offset]; \
2383 ldr fb_ptr, [psx_gpu, #psx_gpu_vram_out_ptr_offset]; \
75e28f62
E
2384 \
2385 cmp span_num_blocks, #0; \
2386 beq 1f; \
2387 \
e1f6de8f 2388 ldrh left_x, [span_edge_data, #edge_data_left_x_offset]; \
75e28f62
E
2389 add fb_ptr, fb_ptr, y, lsl #11; \
2390 \
e1f6de8f 2391 ldr b, [span_b_offset]; \
75e28f62
E
2392 vdup.u32 v_left_x, left_x; \
2393 and y, y, #0x3; \
2394 \
e1f6de8f 2395 ldr dither_row, [dither_offset_ptr, y, lsl #2]; \
75e28f62
E
2396 add fb_ptr, fb_ptr, left_x, lsl #1; \
2397 \
2398 mla b, b_dx, left_x, b; \
2399 and dither_shift, left_x, #0x03; \
2400 \
e1f6de8f 2401 vld1.u32 { uvrg }, [span_uvrg_offset, :128]; \
75e28f62
E
2402 vshr.u32 rg_dx, rg_dx4, #2; \
2403 \
2404 mov dither_shift, dither_shift, lsl #3; \
2405 vmla.u32 rg, rg_dx, v_left_x; \
2406 \
2407 subs span_num_blocks, span_num_blocks, #1; \
2408 \
2409 mov dither_row, dither_row, ror dither_shift; \
2410 mov b_dx4, b_dx, lsl #2; \
2411 \
2412 vdup.u32 dither_offsets, dither_row; \
2413 add block_span_ptr, psx_gpu, #psx_gpu_r_block_span_offset; \
2414 \
2415 vdup.u32 b_block, b; \
2416 vadd.u8 dither_offsets, dither_offsets, d128_4; \
2417 \
2418 mov b_dx8, b_dx, lsl #3; \
2419 vdup.u32 r_block, rg[0]; \
2420 vdup.u32 g_block, rg[1]; \
2421 \
e1f6de8f 2422 vld1.u32 { block_span }, [block_span_ptr, :128]!; \
75e28f62
E
2423 \
2424 vadd.u32 r_block, r_block, block_span; \
e1f6de8f 2425 vld1.u32 { block_span }, [block_span_ptr, :128]!; \
75e28f62
E
2426 \
2427 vadd.u32 g_block, g_block, block_span; \
e1f6de8f 2428 vld1.u32 { block_span }, [block_span_ptr, :128]; \
75e28f62
E
2429 \
2430 vadd.u32 b_block, b_block, block_span; \
2431 add block_ptr_b, block_ptr_a, #16; \
2432 \
2433 vshrn.u32 r_whole_low, r_block, #16; \
2434 vshrn.u32 g_whole_low, g_block, #16; \
2435 vshrn.u32 b_whole_low, b_block, #16; \
2436 vdup.u32 dx4, rg_dx4[0]; \
2437 \
2438 vaddhn.u32 r_whole_high, r_block, dx4; \
2439 vdup.u32 dx4, rg_dx4[1]; \
2440 \
2441 vaddhn.u32 g_whole_high, g_block, dx4; \
2442 vdup.u32 dx4, b_dx4; \
2443 \
2444 vaddhn.u32 b_whole_high, b_block, dx4; \
2445 vdup.u32 dx8, rg_dx8[0]; \
2446 \
2447 vadd.u32 r_block, r_block, dx8; \
2448 vdup.u32 dx8, rg_dx8[1]; \
2449 \
2450 vadd.u32 g_block, g_block, dx8; \
2451 vdup.u32 dx8, b_dx8; \
2452 \
2453 vadd.u32 b_block, b_block, dx8; \
2454 \
2455 vmovn.u16 r_whole_8, r_whole; \
2456 vmovn.u16 g_whole_8, g_whole; \
2457 vmovn.u16 b_whole_8, b_whole; \
2458 \
2459 beq 3f; \
2460 \
2461 2: \
2462 setup_blocks_shaded_untextured_dither_a_##dithering(); \
2463 vshrn.u32 r_whole_low, r_block, #16; \
2464 \
2465 setup_blocks_shaded_untextured_dither_b_##dithering(); \
2466 vshrn.u32 g_whole_low, g_block, #16; \
2467 \
2468 vshrn.u32 b_whole_low, b_block, #16; \
2469 \
2470 vdup.u32 dx4, rg_dx4[0]; \
2471 vshr.u8 r_whole_8, r_whole_8, #3; \
2472 vbic.u8 gb_whole_8, gb_whole_8, d128_0x7; \
2473 \
2474 vaddhn.u32 r_whole_high, r_block, dx4; \
2475 vdup.u32 dx4, rg_dx4[1]; \
2476 \
2477 vmov pixels, msb_mask; \
2478 vaddhn.u32 g_whole_high, g_block, dx4; \
2479 vdup.u32 dx4, b_dx4; \
2480 \
2481 vaddhn.u32 b_whole_high, b_block, dx4; \
2482 vdup.u32 dx8, rg_dx8[0]; \
2483 \
2484 vmlal.u8 pixels, r_whole_8, d64_1; \
2485 vmlal.u8 pixels, g_whole_8, d64_4; \
2486 vmlal.u8 pixels, b_whole_8, d64_128; \
2487 \
2488 vadd.u32 r_block, r_block, dx8; \
2489 vdup.u32 dx8, rg_dx8[1]; \
2490 \
2491 vadd.u32 g_block, g_block, dx8; \
2492 vdup.u32 dx8, b_dx8; \
2493 \
2494 vadd.u32 b_block, b_block, dx8; \
2495 \
2496 vmovn.u16 r_whole_8, r_whole; \
2497 vmovn.u16 g_whole_8, g_whole; \
2498 vmovn.u16 b_whole_8, b_whole; \
2499 \
e1f6de8f 2500 vst1.u32 { pixels }, [fb_ptr]!; \
75e28f62
E
2501 subs span_num_blocks, span_num_blocks, #1; \
2502 bne 2b; \
2503 \
2504 3: \
2505 setup_blocks_shaded_untextured_dither_a_##dithering(); \
2506 \
e1f6de8f 2507 ldrh right_mask, [span_edge_data, #edge_data_right_mask_offset]; \
75e28f62
E
2508 setup_blocks_shaded_untextured_dither_b_##dithering(); \
2509 \
2510 vshr.u8 r_whole_8, r_whole_8, #3; \
3867c6ef 2511 rbit right_mask, right_mask; \
75e28f62
E
2512 vmov pixels, msb_mask; \
2513 vbic.u8 gb_whole_8, gb_whole_8, d128_0x7; \
3867c6ef 2514 clz right_mask, right_mask; \
75e28f62
E
2515 \
2516 vmlal.u8 pixels, r_whole_8, d64_1; \
2517 vmlal.u8 pixels, g_whole_8, d64_4; \
2518 vmlal.u8 pixels, b_whole_8, d64_128; \
2519 \
8184d7c5 2520 JT_OP_REL(100f, right_mask, temp); \
e1f6de8f 2521 JT_OP(ldr pc, [pc, right_mask, lsl #2]); \
3867c6ef 2522 nop; \
8184d7c5 2523 100: \
3867c6ef 2524 nop; \
8184d7c5 2525 .word JTE(100b, 4f); \
2526 .word JTE(100b, 5f); \
2527 .word JTE(100b, 6f); \
2528 .word JTE(100b, 7f); \
2529 .word JTE(100b, 8f); \
2530 .word JTE(100b, 9f); \
2531 .word JTE(100b, 10f); \
2532 .word JTE(100b, 11f); \
3867c6ef 2533 \
75e28f62 2534 4: \
e1f6de8f 2535 vst1.u16 { pixels_low[0] }, [fb_ptr]; \
3867c6ef
E
2536 bal 1f; \
2537 \
2538 5: \
e1f6de8f 2539 vst1.u32 { pixels_low[0] }, [fb_ptr]; \
3867c6ef
E
2540 bal 1f; \
2541 \
2542 6: \
e1f6de8f 2543 vst1.u32 { pixels_low[0] }, [fb_ptr]!; \
2544 vst1.u16 { pixels_low[2] }, [fb_ptr]; \
3867c6ef
E
2545 bal 1f; \
2546 \
2547 7: \
e1f6de8f 2548 vst1.u32 { pixels_low }, [fb_ptr]; \
3867c6ef
E
2549 bal 1f; \
2550 \
2551 8: \
e1f6de8f 2552 vst1.u32 { pixels_low }, [fb_ptr]!; \
2553 vst1.u16 { pixels_high[0] }, [fb_ptr]; \
3867c6ef
E
2554 bal 1f; \
2555 \
2556 9: \
e1f6de8f 2557 vst1.u32 { pixels_low }, [fb_ptr]!; \
2558 vst1.u32 { pixels_high[0] }, [fb_ptr]!; \
3867c6ef
E
2559 bal 1f; \
2560 \
2561 10: \
e1f6de8f 2562 vst1.u32 { pixels_low }, [fb_ptr]!; \
2563 vst1.u32 { pixels_high[0] }, [fb_ptr]!; \
2564 vst1.u16 { pixels_high[2] }, [fb_ptr]; \
3867c6ef
E
2565 bal 1f; \
2566 \
2567 11: \
e1f6de8f 2568 vst1.u32 { pixels }, [fb_ptr]; \
3867c6ef 2569 bal 1f; \
75e28f62
E
2570 \
2571 1: \
2572 add span_uvrg_offset, span_uvrg_offset, #16; \
2573 add span_b_offset, span_b_offset, #4; \
2574 \
2575 add span_edge_data, span_edge_data, #8; \
2576 subs num_spans, num_spans, #1; \
2577 \
2578 bne 0b; \
2579 \
2580 ldmia sp!, { r4 - r11, pc } \
2581
2582setup_blocks_shaded_untextured_direct_builder(undithered)
2583setup_blocks_shaded_untextured_direct_builder(dithered)
2584
2585
2586#undef psx_gpu
2587#undef num_blocks
2588#undef triangle
2589#undef c_64
2590
2591#define psx_gpu r0
2592#define block_ptr r1
2593#define num_blocks r2
2594#define uv_01 r3
2595#define uv_23 r4
2596#define uv_45 r5
2597#define uv_67 r6
2598#define uv_0 r7
2599#define uv_1 r3
2600#define uv_2 r8
2601#define uv_3 r4
2602#define uv_4 r9
2603#define uv_5 r5
2604#define uv_6 r10
2605#define uv_7 r6
2606#define texture_ptr r11
2607
2608#define pixel_0 r7
2609#define pixel_1 r3
2610#define pixel_2 r8
2611#define pixel_3 r4
2612#define pixel_4 r9
2613#define pixel_5 r5
2614#define pixel_6 r10
2615#define pixel_7 r6
2616
2617#define pixels_a r7
2618#define pixels_b r9
2619#define pixels_c r8
2620#define pixels_d r10
2621
2622#define c_64 r0
2623
2624#define clut_ptr r12
2625#define current_texture_mask r5
2626#define dirty_textures_mask r6
2627
2628#define texels d0
2629
2630#define clut_low_a d2
2631#define clut_low_b d3
2632#define clut_high_a d4
2633#define clut_high_b d5
2634
2635#define clut_a q1
2636#define clut_b q2
2637
2638#define texels_low d6
2639#define texels_high d7
2640
2641.align 3
2642
2643function(texture_blocks_untextured)
2644 bx lr
2645
2646
2647.align 3
2648
2649function(texture_blocks_4bpp)
2650 stmdb sp!, { r3 - r11, r14 }
2651 add block_ptr, psx_gpu, #psx_gpu_blocks_offset
2652
e1f6de8f 2653 ldr texture_ptr, [psx_gpu, #psx_gpu_texture_page_ptr_offset]
2654 ldrh num_blocks, [psx_gpu, #psx_gpu_num_blocks_offset]
75e28f62 2655
e1f6de8f 2656 ldr clut_ptr, [psx_gpu, #psx_gpu_clut_ptr_offset]
2657 vld1.u32 { clut_a, clut_b }, [clut_ptr, :128]
75e28f62 2658
e1f6de8f 2659 ldr current_texture_mask, [psx_gpu, #psx_gpu_current_texture_mask_offset]
75e28f62
E
2660 vuzp.u8 clut_a, clut_b
2661
e1f6de8f 2662 ldr dirty_textures_mask, [psx_gpu, #psx_gpu_dirty_textures_4bpp_mask_offset]
75e28f62
E
2663 tst dirty_textures_mask, current_texture_mask
2664
2665 bne 1f
2666 mov c_64, #64
2667
26680:
2669 ldm block_ptr, { uv_01, uv_23, uv_45, uv_67 }
2670
2671 uxtah uv_0, texture_ptr, uv_01
2672 uxtah uv_1, texture_ptr, uv_01, ror #16
2673
2674 uxtah uv_2, texture_ptr, uv_23
2675 uxtah uv_3, texture_ptr, uv_23, ror #16
2676
2677 uxtah uv_4, texture_ptr, uv_45
e1f6de8f 2678 ldrb pixel_0, [uv_0]
75e28f62
E
2679
2680 uxtah uv_5, texture_ptr, uv_45, ror #16
e1f6de8f 2681 ldrb pixel_1, [uv_1]
75e28f62
E
2682
2683 uxtah uv_6, texture_ptr, uv_67
e1f6de8f 2684 ldrb pixel_2, [uv_2]
75e28f62
E
2685
2686 uxtah uv_7, texture_ptr, uv_67, ror #16
e1f6de8f 2687 ldrb pixel_3, [uv_3]
75e28f62 2688
e1f6de8f 2689 ldrb pixel_4, [uv_4]
75e28f62
E
2690 subs num_blocks, num_blocks, #1
2691
e1f6de8f 2692 ldrb pixel_5, [uv_5]
75e28f62
E
2693 orr pixels_a, pixel_0, pixel_1, lsl #8
2694
e1f6de8f 2695 ldrb pixel_6, [uv_6]
75e28f62
E
2696 orr pixels_b, pixel_4, pixel_5, lsl #8
2697
e1f6de8f 2698 ldrb pixel_7, [uv_7]
75e28f62
E
2699 orr pixels_a, pixels_a, pixel_2, lsl #16
2700
2701 orr pixels_b, pixels_b, pixel_6, lsl #16
2702 orr pixels_a, pixels_a, pixel_3, lsl #24
2703
2704 orr pixels_b, pixels_b, pixel_7, lsl #24
ed0fd81d 2705 vmov texels, pixels_a, pixels_b
75e28f62
E
2706
2707 vtbl.8 texels_low, { clut_low_a, clut_low_b }, texels
2708 vtbl.8 texels_high, { clut_high_a, clut_high_b }, texels
2709
e1f6de8f 2710 vst2.u8 { texels_low, texels_high }, [block_ptr, :128], c_64
75e28f62
E
2711 bne 0b
2712
2713 ldmia sp!, { r3 - r11, pc }
2714
27151:
2716 stmdb sp!, { r1 - r2 }
2717 bl update_texture_4bpp_cache
2718
2719 mov c_64, #64
2720 ldmia sp!, { r1 - r2 }
2721 bal 0b
2722
2723
2724.align 3
2725
2726function(texture_blocks_8bpp)
2727 stmdb sp!, { r3 - r11, r14 }
2728 add block_ptr, psx_gpu, #psx_gpu_blocks_offset
2729
e1f6de8f 2730 ldr texture_ptr, [psx_gpu, #psx_gpu_texture_page_ptr_offset]
2731 ldrh num_blocks, [psx_gpu, #psx_gpu_num_blocks_offset]
75e28f62 2732
e1f6de8f 2733 ldr clut_ptr, [psx_gpu, #psx_gpu_clut_ptr_offset]
2734 ldr current_texture_mask, [psx_gpu, #psx_gpu_current_texture_mask_offset]
75e28f62 2735
e1f6de8f 2736 ldr dirty_textures_mask, [psx_gpu, #psx_gpu_dirty_textures_8bpp_mask_offset]
75e28f62
E
2737 tst dirty_textures_mask, current_texture_mask
2738
2739 bne 1f
2740 nop
2741
27420:
2743 ldm block_ptr, { uv_01, uv_23, uv_45, uv_67 }
2744
2745 uxtah uv_0, texture_ptr, uv_01
2746 uxtah uv_1, texture_ptr, uv_01, ror #16
2747
2748 uxtah uv_2, texture_ptr, uv_23
2749 uxtah uv_3, texture_ptr, uv_23, ror #16
2750
2751 uxtah uv_4, texture_ptr, uv_45
e1f6de8f 2752 ldrb pixel_0, [uv_0]
75e28f62
E
2753
2754 uxtah uv_5, texture_ptr, uv_45, ror #16
e1f6de8f 2755 ldrb pixel_1, [uv_1]
75e28f62
E
2756
2757 uxtah uv_6, texture_ptr, uv_67
e1f6de8f 2758 ldrb pixel_2, [uv_2]
75e28f62
E
2759
2760 uxtah uv_7, texture_ptr, uv_67, ror #16
e1f6de8f 2761 ldrb pixel_3, [uv_3]
75e28f62 2762
e1f6de8f 2763 ldrb pixel_4, [uv_4]
75e28f62
E
2764 add pixel_0, pixel_0, pixel_0
2765
e1f6de8f 2766 ldrb pixel_5, [uv_5]
75e28f62
E
2767 add pixel_1, pixel_1, pixel_1
2768
e1f6de8f 2769 ldrb pixel_6, [uv_6]
75e28f62
E
2770 add pixel_2, pixel_2, pixel_2
2771
e1f6de8f 2772 ldrb pixel_7, [uv_7]
75e28f62
E
2773 add pixel_3, pixel_3, pixel_3
2774
e1f6de8f 2775 ldrh pixel_0, [clut_ptr, pixel_0]
75e28f62
E
2776 add pixel_4, pixel_4, pixel_4
2777
e1f6de8f 2778 ldrh pixel_1, [clut_ptr, pixel_1]
75e28f62
E
2779 add pixel_5, pixel_5, pixel_5
2780
e1f6de8f 2781 ldrh pixel_2, [clut_ptr, pixel_2]
75e28f62
E
2782 add pixel_6, pixel_6, pixel_6
2783
e1f6de8f 2784 ldrh pixel_3, [clut_ptr, pixel_3]
75e28f62
E
2785 add pixel_7, pixel_7, pixel_7
2786
e1f6de8f 2787 ldrh pixel_4, [clut_ptr, pixel_4]
75e28f62
E
2788 orr pixels_a, pixel_0, pixel_1, lsl #16
2789
e1f6de8f 2790 ldrh pixel_5, [clut_ptr, pixel_5]
75e28f62
E
2791 orr pixels_c, pixel_2, pixel_3, lsl #16
2792
e1f6de8f 2793 ldrh pixel_6, [clut_ptr, pixel_6]
75e28f62
E
2794 subs num_blocks, num_blocks, #1
2795
e1f6de8f 2796 ldrh pixel_7, [clut_ptr, pixel_7]
75e28f62
E
2797 orr pixels_b, pixel_4, pixel_5, lsl #16
2798
2799 orr pixels_d, pixel_6, pixel_7, lsl #16
2800 stm block_ptr, { pixels_a, pixels_c, pixels_b, pixels_d }
2801
2802 add block_ptr, block_ptr, #64
2803 bne 0b
2804
2805 ldmia sp!, { r3 - r11, pc }
2806
28071:
4d646738 2808 stmdb sp!, { r1 - r2, EXTRA_UNSAVED_REGS r12 }
75e28f62
E
2809
2810 bl update_texture_8bpp_cache
2811
4d646738 2812 ldmia sp!, { r1 - r2, EXTRA_UNSAVED_REGS r12 }
75e28f62
E
2813 bal 0b
2814
2815
2816#undef uv_0
2817#undef uv_1
2818#undef uv_2
2819#undef uv_3
2820#undef uv_4
2821#undef uv_5
2822#undef uv_6
2823#undef uv_7
2824
2825#undef pixel_0
2826#undef pixel_1
2827#undef pixel_2
2828#undef pixel_3
2829#undef pixel_4
2830#undef pixel_5
2831#undef pixel_6
2832#undef pixel_7
2833
2834#undef texture_ptr
2835
2836#undef pixels_a
2837#undef pixels_b
2838#undef pixels_c
2839#undef pixels_d
2840
2841#define psx_gpu r0
2842#define block_ptr r1
2843#define num_blocks r2
2844
2845#define uv_0 r3
2846#define uv_1 r4
2847#define u_0 r3
2848#define u_1 r4
2849#define v_0 r5
2850#define v_1 r6
2851
2852#define uv_2 r5
2853#define uv_3 r6
2854#define u_2 r5
2855#define u_3 r6
2856#define v_2 r7
2857#define v_3 r8
2858
2859#define uv_4 r7
2860#define uv_5 r8
2861#define u_4 r7
2862#define u_5 r8
2863#define v_4 r9
2864#define v_5 r10
2865
2866#define uv_6 r9
2867#define uv_7 r10
2868#define u_6 r9
2869#define u_7 r10
2870#define v_6 r11
2871#define v_7 r0
2872
2873#define pixel_0 r3
2874#define pixel_1 r4
2875#define pixel_2 r5
2876#define pixel_3 r6
2877#define pixel_4 r7
2878#define pixel_5 r8
2879#define pixel_6 r9
2880#define pixel_7 r10
2881
2882#define pixels_a r3
2883#define pixels_b r5
2884#define pixels_c r7
2885#define pixels_d r9
2886
2887#define texture_ptr r12
2888
2889
2890.align 3
2891