1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus/PCSX - assem_arm.c *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2011 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 extern int cycle_count;
23 extern int last_count;
25 extern int pending_exception;
26 extern int branch_target;
27 extern uint64_t readmem_dword;
29 extern precomp_instr fake_pc;
31 extern void *dynarec_local;
32 extern u_int memory_map[1048576];
33 extern u_int mini_ht[32][2];
34 extern u_int rounding_modes[4];
36 void indirect_jump_indexed();
49 void jump_vaddr_r10();
50 void jump_vaddr_r12();
52 const u_int jump_vaddr_reg[16] = {
70 void invalidate_addr_r0();
71 void invalidate_addr_r1();
72 void invalidate_addr_r2();
73 void invalidate_addr_r3();
74 void invalidate_addr_r4();
75 void invalidate_addr_r5();
76 void invalidate_addr_r6();
77 void invalidate_addr_r7();
78 void invalidate_addr_r8();
79 void invalidate_addr_r9();
80 void invalidate_addr_r10();
81 void invalidate_addr_r12();
83 const u_int invalidate_addr_reg[16] = {
84 (int)invalidate_addr_r0,
85 (int)invalidate_addr_r1,
86 (int)invalidate_addr_r2,
87 (int)invalidate_addr_r3,
88 (int)invalidate_addr_r4,
89 (int)invalidate_addr_r5,
90 (int)invalidate_addr_r6,
91 (int)invalidate_addr_r7,
92 (int)invalidate_addr_r8,
93 (int)invalidate_addr_r9,
94 (int)invalidate_addr_r10,
96 (int)invalidate_addr_r12,
103 unsigned int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
107 void set_jump_target(int addr,u_int target)
109 u_char *ptr=(u_char *)addr;
110 u_int *ptr2=(u_int *)ptr;
112 assert((target-(u_int)ptr2-8)<1024);
114 assert((target&3)==0);
115 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
116 //printf("target=%x addr=%x insn=%x\n",target,addr,*ptr2);
118 else if(ptr[3]==0x72) {
119 // generated by emit_jno_unlikely
120 if((target-(u_int)ptr2-8)<1024) {
122 assert((target&3)==0);
123 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
125 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
127 assert((target&3)==0);
128 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
130 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
133 assert((ptr[3]&0x0e)==0xa);
134 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
138 // This optionally copies the instruction from the target of the branch into
139 // the space before the branch. Works, but the difference in speed is
140 // usually insignificant.
141 void set_jump_target_fillslot(int addr,u_int target,int copy)
143 u_char *ptr=(u_char *)addr;
144 u_int *ptr2=(u_int *)ptr;
145 assert(!copy||ptr2[-1]==0xe28dd000);
148 assert((target-(u_int)ptr2-8)<4096);
149 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
152 assert((ptr[3]&0x0e)==0xa);
153 u_int target_insn=*(u_int *)target;
154 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
157 if((target_insn&0x0c100000)==0x04100000) { // Load
160 if(target_insn&0x08000000) {
164 ptr2[-1]=target_insn;
167 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
172 add_literal(int addr,int val)
174 assert(literalcount<sizeof(literals)/sizeof(literals[0]));
175 literals[literalcount][0]=addr;
176 literals[literalcount][1]=val;
180 void *kill_pointer(void *stub)
182 int *ptr=(int *)(stub+4);
183 assert((*ptr&0x0ff00000)==0x05900000);
184 u_int offset=*ptr&0xfff;
185 int **l_ptr=(void *)ptr+offset+8;
187 set_jump_target((int)i_ptr,(int)stub);
191 // find where external branch is liked to using addr of it's stub:
192 // get address that insn one after stub loads (dyna_linker arg1),
193 // treat it as a pointer to branch insn,
194 // return addr where that branch jumps to
195 int get_pointer(void *stub)
197 //printf("get_pointer(%x)\n",(int)stub);
198 int *ptr=(int *)(stub+4);
199 assert((*ptr&0x0fff0000)==0x059f0000);
200 u_int offset=*ptr&0xfff;
201 int **l_ptr=(void *)ptr+offset+8;
203 assert((*i_ptr&0x0f000000)==0x0a000000);
204 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
207 // Find the "clean" entry point from a "dirty" entry point
208 // by skipping past the call to verify_code
209 u_int get_clean_addr(int addr)
211 int *ptr=(int *)addr;
217 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
218 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
220 if((*ptr&0xFF000000)==0xea000000) {
221 return (int)ptr+((*ptr<<8)>>6)+8; // follow jump
226 int verify_dirty(int addr)
228 u_int *ptr=(u_int *)addr;
230 // get from literal pool
231 assert((*ptr&0xFFFF0000)==0xe59f0000);
232 u_int offset=*ptr&0xfff;
233 u_int *l_ptr=(void *)ptr+offset+8;
234 u_int source=l_ptr[0];
240 assert((*ptr&0xFFF00000)==0xe3000000);
241 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
242 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
243 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
246 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
247 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
248 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
249 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
250 unsigned int page=source>>12;
251 unsigned int map_value=memory_map[page];
252 if(map_value>=0x80000000) return 0;
253 while(page<((source+len-1)>>12)) {
254 if((memory_map[++page]<<2)!=(map_value<<2)) return 0;
256 source = source+(map_value<<2);
258 //printf("verify_dirty: %x %x %x\n",source,copy,len);
259 return !memcmp((void *)source,(void *)copy,len);
262 // This doesn't necessarily find all clean entry points, just
263 // guarantees that it's not dirty
264 int isclean(int addr)
267 int *ptr=((u_int *)addr)+4;
269 int *ptr=((u_int *)addr)+6;
271 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
272 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
273 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
274 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
275 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
279 void get_bounds(int addr,u_int *start,u_int *end)
281 u_int *ptr=(u_int *)addr;
283 // get from literal pool
284 assert((*ptr&0xFFFF0000)==0xe59f0000);
285 u_int offset=*ptr&0xfff;
286 u_int *l_ptr=(void *)ptr+offset+8;
287 u_int source=l_ptr[0];
288 //u_int copy=l_ptr[1];
293 assert((*ptr&0xFFF00000)==0xe3000000);
294 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
295 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
296 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
299 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
300 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
301 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
302 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
303 if(memory_map[source>>12]>=0x80000000) source = 0;
304 else source = source+(memory_map[source>>12]<<2);
310 /* Register allocation */
312 // Note: registers are allocated clean (unmodified state)
313 // if you intend to modify the register, you must call dirty_reg().
314 void alloc_reg(struct regstat *cur,int i,signed char reg)
317 int preferred_reg = (reg&7);
318 if(reg==CCREG) preferred_reg=HOST_CCREG;
319 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
321 // Don't allocate unused registers
322 if((cur->u>>reg)&1) return;
324 // see if it's already allocated
325 for(hr=0;hr<HOST_REGS;hr++)
327 if(cur->regmap[hr]==reg) return;
330 // Keep the same mapping if the register was already allocated in a loop
331 preferred_reg = loop_reg(i,reg,preferred_reg);
333 // Try to allocate the preferred register
334 if(cur->regmap[preferred_reg]==-1) {
335 cur->regmap[preferred_reg]=reg;
336 cur->dirty&=~(1<<preferred_reg);
337 cur->isconst&=~(1<<preferred_reg);
340 r=cur->regmap[preferred_reg];
341 if(r<64&&((cur->u>>r)&1)) {
342 cur->regmap[preferred_reg]=reg;
343 cur->dirty&=~(1<<preferred_reg);
344 cur->isconst&=~(1<<preferred_reg);
347 if(r>=64&&((cur->uu>>(r&63))&1)) {
348 cur->regmap[preferred_reg]=reg;
349 cur->dirty&=~(1<<preferred_reg);
350 cur->isconst&=~(1<<preferred_reg);
354 // Clear any unneeded registers
355 // We try to keep the mapping consistent, if possible, because it
356 // makes branches easier (especially loops). So we try to allocate
357 // first (see above) before removing old mappings. If this is not
358 // possible then go ahead and clear out the registers that are no
360 for(hr=0;hr<HOST_REGS;hr++)
365 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
369 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
373 // Try to allocate any available register, but prefer
374 // registers that have not been used recently.
376 for(hr=0;hr<HOST_REGS;hr++) {
377 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
378 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
380 cur->dirty&=~(1<<hr);
381 cur->isconst&=~(1<<hr);
387 // Try to allocate any available register
388 for(hr=0;hr<HOST_REGS;hr++) {
389 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
391 cur->dirty&=~(1<<hr);
392 cur->isconst&=~(1<<hr);
397 // Ok, now we have to evict someone
398 // Pick a register we hopefully won't need soon
399 u_char hsn[MAXREG+1];
400 memset(hsn,10,sizeof(hsn));
402 lsn(hsn,i,&preferred_reg);
403 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
404 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
406 // Don't evict the cycle count at entry points, otherwise the entry
407 // stub will have to write it.
408 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
409 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
412 // Alloc preferred register if available
413 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
414 for(hr=0;hr<HOST_REGS;hr++) {
415 // Evict both parts of a 64-bit register
416 if((cur->regmap[hr]&63)==r) {
418 cur->dirty&=~(1<<hr);
419 cur->isconst&=~(1<<hr);
422 cur->regmap[preferred_reg]=reg;
425 for(r=1;r<=MAXREG;r++)
427 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
428 for(hr=0;hr<HOST_REGS;hr++) {
429 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
430 if(cur->regmap[hr]==r+64) {
432 cur->dirty&=~(1<<hr);
433 cur->isconst&=~(1<<hr);
438 for(hr=0;hr<HOST_REGS;hr++) {
439 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
440 if(cur->regmap[hr]==r) {
442 cur->dirty&=~(1<<hr);
443 cur->isconst&=~(1<<hr);
454 for(r=1;r<=MAXREG;r++)
457 for(hr=0;hr<HOST_REGS;hr++) {
458 if(cur->regmap[hr]==r+64) {
460 cur->dirty&=~(1<<hr);
461 cur->isconst&=~(1<<hr);
465 for(hr=0;hr<HOST_REGS;hr++) {
466 if(cur->regmap[hr]==r) {
468 cur->dirty&=~(1<<hr);
469 cur->isconst&=~(1<<hr);
476 printf("This shouldn't happen (alloc_reg)");exit(1);
479 void alloc_reg64(struct regstat *cur,int i,signed char reg)
481 int preferred_reg = 8+(reg&1);
484 // allocate the lower 32 bits
485 alloc_reg(cur,i,reg);
487 // Don't allocate unused registers
488 if((cur->uu>>reg)&1) return;
490 // see if the upper half is already allocated
491 for(hr=0;hr<HOST_REGS;hr++)
493 if(cur->regmap[hr]==reg+64) return;
496 // Keep the same mapping if the register was already allocated in a loop
497 preferred_reg = loop_reg(i,reg,preferred_reg);
499 // Try to allocate the preferred register
500 if(cur->regmap[preferred_reg]==-1) {
501 cur->regmap[preferred_reg]=reg|64;
502 cur->dirty&=~(1<<preferred_reg);
503 cur->isconst&=~(1<<preferred_reg);
506 r=cur->regmap[preferred_reg];
507 if(r<64&&((cur->u>>r)&1)) {
508 cur->regmap[preferred_reg]=reg|64;
509 cur->dirty&=~(1<<preferred_reg);
510 cur->isconst&=~(1<<preferred_reg);
513 if(r>=64&&((cur->uu>>(r&63))&1)) {
514 cur->regmap[preferred_reg]=reg|64;
515 cur->dirty&=~(1<<preferred_reg);
516 cur->isconst&=~(1<<preferred_reg);
520 // Clear any unneeded registers
521 // We try to keep the mapping consistent, if possible, because it
522 // makes branches easier (especially loops). So we try to allocate
523 // first (see above) before removing old mappings. If this is not
524 // possible then go ahead and clear out the registers that are no
526 for(hr=HOST_REGS-1;hr>=0;hr--)
531 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
535 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
539 // Try to allocate any available register, but prefer
540 // registers that have not been used recently.
542 for(hr=0;hr<HOST_REGS;hr++) {
543 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
544 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
545 cur->regmap[hr]=reg|64;
546 cur->dirty&=~(1<<hr);
547 cur->isconst&=~(1<<hr);
553 // Try to allocate any available register
554 for(hr=0;hr<HOST_REGS;hr++) {
555 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
556 cur->regmap[hr]=reg|64;
557 cur->dirty&=~(1<<hr);
558 cur->isconst&=~(1<<hr);
563 // Ok, now we have to evict someone
564 // Pick a register we hopefully won't need soon
565 u_char hsn[MAXREG+1];
566 memset(hsn,10,sizeof(hsn));
568 lsn(hsn,i,&preferred_reg);
569 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
570 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
572 // Don't evict the cycle count at entry points, otherwise the entry
573 // stub will have to write it.
574 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
575 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
578 // Alloc preferred register if available
579 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
580 for(hr=0;hr<HOST_REGS;hr++) {
581 // Evict both parts of a 64-bit register
582 if((cur->regmap[hr]&63)==r) {
584 cur->dirty&=~(1<<hr);
585 cur->isconst&=~(1<<hr);
588 cur->regmap[preferred_reg]=reg|64;
591 for(r=1;r<=MAXREG;r++)
593 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
594 for(hr=0;hr<HOST_REGS;hr++) {
595 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
596 if(cur->regmap[hr]==r+64) {
597 cur->regmap[hr]=reg|64;
598 cur->dirty&=~(1<<hr);
599 cur->isconst&=~(1<<hr);
604 for(hr=0;hr<HOST_REGS;hr++) {
605 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
606 if(cur->regmap[hr]==r) {
607 cur->regmap[hr]=reg|64;
608 cur->dirty&=~(1<<hr);
609 cur->isconst&=~(1<<hr);
620 for(r=1;r<=MAXREG;r++)
623 for(hr=0;hr<HOST_REGS;hr++) {
624 if(cur->regmap[hr]==r+64) {
625 cur->regmap[hr]=reg|64;
626 cur->dirty&=~(1<<hr);
627 cur->isconst&=~(1<<hr);
631 for(hr=0;hr<HOST_REGS;hr++) {
632 if(cur->regmap[hr]==r) {
633 cur->regmap[hr]=reg|64;
634 cur->dirty&=~(1<<hr);
635 cur->isconst&=~(1<<hr);
642 printf("This shouldn't happen");exit(1);
645 // Allocate a temporary register. This is done without regard to
646 // dirty status or whether the register we request is on the unneeded list
647 // Note: This will only allocate one register, even if called multiple times
648 void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
651 int preferred_reg = -1;
653 // see if it's already allocated
654 for(hr=0;hr<HOST_REGS;hr++)
656 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
659 // Try to allocate any available register
660 for(hr=HOST_REGS-1;hr>=0;hr--) {
661 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
663 cur->dirty&=~(1<<hr);
664 cur->isconst&=~(1<<hr);
669 // Find an unneeded register
670 for(hr=HOST_REGS-1;hr>=0;hr--)
676 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
678 cur->dirty&=~(1<<hr);
679 cur->isconst&=~(1<<hr);
686 if((cur->uu>>(r&63))&1) {
687 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
689 cur->dirty&=~(1<<hr);
690 cur->isconst&=~(1<<hr);
698 // Ok, now we have to evict someone
699 // Pick a register we hopefully won't need soon
700 // TODO: we might want to follow unconditional jumps here
701 // TODO: get rid of dupe code and make this into a function
702 u_char hsn[MAXREG+1];
703 memset(hsn,10,sizeof(hsn));
705 lsn(hsn,i,&preferred_reg);
706 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
708 // Don't evict the cycle count at entry points, otherwise the entry
709 // stub will have to write it.
710 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
711 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
714 for(r=1;r<=MAXREG;r++)
716 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
717 for(hr=0;hr<HOST_REGS;hr++) {
718 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
719 if(cur->regmap[hr]==r+64) {
721 cur->dirty&=~(1<<hr);
722 cur->isconst&=~(1<<hr);
727 for(hr=0;hr<HOST_REGS;hr++) {
728 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
729 if(cur->regmap[hr]==r) {
731 cur->dirty&=~(1<<hr);
732 cur->isconst&=~(1<<hr);
743 for(r=1;r<=MAXREG;r++)
746 for(hr=0;hr<HOST_REGS;hr++) {
747 if(cur->regmap[hr]==r+64) {
749 cur->dirty&=~(1<<hr);
750 cur->isconst&=~(1<<hr);
754 for(hr=0;hr<HOST_REGS;hr++) {
755 if(cur->regmap[hr]==r) {
757 cur->dirty&=~(1<<hr);
758 cur->isconst&=~(1<<hr);
765 printf("This shouldn't happen");exit(1);
767 // Allocate a specific ARM register.
768 void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
773 // see if it's already allocated (and dealloc it)
774 for(n=0;n<HOST_REGS;n++)
776 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {
777 dirty=(cur->dirty>>n)&1;
783 cur->dirty&=~(1<<hr);
784 cur->dirty|=dirty<<hr;
785 cur->isconst&=~(1<<hr);
788 // Alloc cycle count into dedicated register
789 alloc_cc(struct regstat *cur,int i)
791 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
799 char regname[16][4] = {
817 void output_byte(u_char byte)
821 void output_modrm(u_char mod,u_char rm,u_char ext)
826 u_char byte=(mod<<6)|(ext<<3)|rm;
829 void output_sib(u_char scale,u_char index,u_char base)
834 u_char byte=(scale<<6)|(index<<3)|base;
837 void output_w32(u_int word)
839 *((u_int *)out)=word;
842 u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
847 return((rn<<16)|(rd<<12)|rm);
849 u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
854 assert((shift&1)==0);
855 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
857 u_int genimm(u_int imm,u_int *encoded)
865 *encoded=((i&30)<<7)|imm;
868 imm=(imm>>2)|(imm<<30);i-=2;
872 void genimm_checked(u_int imm,u_int *encoded)
874 u_int ret=genimm(imm,encoded);
877 u_int genjmp(u_int addr)
879 int offset=addr-(int)out-8;
880 if(offset<-33554432||offset>=33554432) {
882 printf("genjmp: out of range: %08x\n", offset);
887 return ((u_int)offset>>2)&0xffffff;
890 void emit_mov(int rs,int rt)
892 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
893 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
896 void emit_movs(int rs,int rt)
898 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
899 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
902 void emit_add(int rs1,int rs2,int rt)
904 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
905 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
908 void emit_adds(int rs1,int rs2,int rt)
910 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
911 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
914 void emit_adcs(int rs1,int rs2,int rt)
916 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
917 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
920 void emit_sbc(int rs1,int rs2,int rt)
922 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
923 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
926 void emit_sbcs(int rs1,int rs2,int rt)
928 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
929 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
932 void emit_neg(int rs, int rt)
934 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
935 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
938 void emit_negs(int rs, int rt)
940 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
941 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
944 void emit_sub(int rs1,int rs2,int rt)
946 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
947 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
950 void emit_subs(int rs1,int rs2,int rt)
952 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
953 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
956 void emit_zeroreg(int rt)
958 assem_debug("mov %s,#0\n",regname[rt]);
959 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
962 void emit_loadlp(u_int imm,u_int rt)
964 add_literal((int)out,imm);
965 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
966 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
968 void emit_movw(u_int imm,u_int rt)
971 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
972 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
974 void emit_movt(u_int imm,u_int rt)
976 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
977 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
979 void emit_movimm(u_int imm,u_int rt)
982 if(genimm(imm,&armval)) {
983 assem_debug("mov %s,#%d\n",regname[rt],imm);
984 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
985 }else if(genimm(~imm,&armval)) {
986 assem_debug("mvn %s,#%d\n",regname[rt],imm);
987 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
988 }else if(imm<65536) {
990 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
991 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
992 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
993 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1001 emit_movw(imm&0x0000FFFF,rt);
1002 emit_movt(imm&0xFFFF0000,rt);
1006 void emit_pcreladdr(u_int rt)
1008 assem_debug("add %s,pc,#?\n",regname[rt]);
1009 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
1012 void emit_loadreg(int r, int hr)
1016 printf("64bit load in 32bit mode!\n");
1024 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1025 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1026 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1027 if(r==CCREG) addr=(int)&cycle_count;
1028 if(r==CSREG) addr=(int)&Status;
1029 if(r==FSREG) addr=(int)&FCR31;
1030 if(r==INVCP) addr=(int)&invc_ptr;
1031 u_int offset = addr-(u_int)&dynarec_local;
1032 assert(offset<4096);
1033 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
1034 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
1037 void emit_storereg(int r, int hr)
1041 printf("64bit store in 32bit mode!\n");
1046 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1047 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1048 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1049 if(r==CCREG) addr=(int)&cycle_count;
1050 if(r==FSREG) addr=(int)&FCR31;
1051 u_int offset = addr-(u_int)&dynarec_local;
1052 assert(offset<4096);
1053 assem_debug("str %s,fp+%d\n",regname[hr],offset);
1054 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
1057 void emit_test(int rs, int rt)
1059 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
1060 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
1063 void emit_testimm(int rs,int imm)
1066 assem_debug("tst %s,#%d\n",regname[rs],imm);
1067 genimm_checked(imm,&armval);
1068 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
1071 void emit_testeqimm(int rs,int imm)
1074 assem_debug("tsteq %s,$%d\n",regname[rs],imm);
1075 genimm_checked(imm,&armval);
1076 output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
1079 void emit_not(int rs,int rt)
1081 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
1082 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
1085 void emit_mvnmi(int rs,int rt)
1087 assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
1088 output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
1091 void emit_and(u_int rs1,u_int rs2,u_int rt)
1093 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1094 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
1097 void emit_or(u_int rs1,u_int rs2,u_int rt)
1099 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1100 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
1102 void emit_or_and_set_flags(int rs1,int rs2,int rt)
1104 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1105 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
1108 void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
1113 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs],imm);
1114 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|(imm<<7));
1117 void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
1122 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm);
1123 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
1126 void emit_xor(u_int rs1,u_int rs2,u_int rt)
1128 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1129 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
1132 void emit_addimm(u_int rs,int imm,u_int rt)
1137 assert(imm>-65536&&imm<65536);
1139 if(genimm(imm,&armval)) {
1140 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1141 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1142 }else if(genimm(-imm,&armval)) {
1143 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],imm);
1144 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1146 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1147 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1148 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1149 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1151 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1152 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1153 output_w32(0xe2800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1154 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1157 else if(rs!=rt) emit_mov(rs,rt);
1160 void emit_addimm_and_set_flags(int imm,int rt)
1162 assert(imm>-65536&&imm<65536);
1164 if(genimm(imm,&armval)) {
1165 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1166 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1167 }else if(genimm(-imm,&armval)) {
1168 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1169 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1171 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1172 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1173 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1174 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1176 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1177 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1178 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1179 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1182 void emit_addimm_no_flags(u_int imm,u_int rt)
1184 emit_addimm(rt,imm,rt);
1187 void emit_addnop(u_int r)
1190 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1191 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1194 void emit_adcimm(u_int rs,int imm,u_int rt)
1197 genimm_checked(imm,&armval);
1198 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1199 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1201 /*void emit_sbcimm(int imm,u_int rt)
1204 genimm_checked(imm,&armval);
1205 assem_debug("sbc %s,%s,#%d\n",regname[rt],regname[rt],imm);
1206 output_w32(0xe2c00000|rd_rn_rm(rt,rt,0)|armval);
1208 void emit_sbbimm(int imm,u_int rt)
1210 assem_debug("sbb $%d,%%%s\n",imm,regname[rt]);
1212 if(imm<128&&imm>=-128) {
1214 output_modrm(3,rt,3);
1220 output_modrm(3,rt,3);
1224 void emit_rscimm(int rs,int imm,u_int rt)
1228 genimm_checked(imm,&armval);
1229 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1230 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1233 void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1235 // TODO: if(genimm(imm,&armval)) ...
1237 emit_movimm(imm,HOST_TEMPREG);
1238 emit_adds(HOST_TEMPREG,rsl,rtl);
1239 emit_adcimm(rsh,0,rth);
1242 void emit_sbb(int rs1,int rs2)
1244 assem_debug("sbb %%%s,%%%s\n",regname[rs2],regname[rs1]);
1246 output_modrm(3,rs1,rs2);
1249 void emit_andimm(int rs,int imm,int rt)
1254 }else if(genimm(imm,&armval)) {
1255 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1256 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1257 }else if(genimm(~imm,&armval)) {
1258 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1259 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1260 }else if(imm==65535) {
1262 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1263 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1264 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1265 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1267 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1268 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1271 assert(imm>0&&imm<65535);
1273 assem_debug("mov r14,#%d\n",imm&0xFF00);
1274 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1275 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1276 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1278 emit_movw(imm,HOST_TEMPREG);
1280 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1281 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1285 void emit_orimm(int rs,int imm,int rt)
1289 if(rs!=rt) emit_mov(rs,rt);
1290 }else if(genimm(imm,&armval)) {
1291 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1292 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1294 assert(imm>0&&imm<65536);
1295 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1296 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1297 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1298 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1302 void emit_xorimm(int rs,int imm,int rt)
1306 if(rs!=rt) emit_mov(rs,rt);
1307 }else if(genimm(imm,&armval)) {
1308 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1309 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1311 assert(imm>0&&imm<65536);
1312 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1313 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1314 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1315 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1319 void emit_shlimm(int rs,u_int imm,int rt)
1324 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1325 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1328 void emit_lsls_imm(int rs,int imm,int rt)
1332 assem_debug("lsls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1333 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1336 void emit_shrimm(int rs,u_int imm,int rt)
1340 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1341 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1344 void emit_sarimm(int rs,u_int imm,int rt)
1348 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1349 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1352 void emit_rorimm(int rs,u_int imm,int rt)
1356 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1357 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1360 void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1362 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1366 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1367 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1368 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1369 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1372 void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1374 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1378 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1379 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1380 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1381 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1384 void emit_signextend16(int rs,int rt)
1387 emit_shlimm(rs,16,rt);
1388 emit_sarimm(rt,16,rt);
1390 assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
1391 output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
1395 void emit_signextend8(int rs,int rt)
1398 emit_shlimm(rs,24,rt);
1399 emit_sarimm(rt,24,rt);
1401 assem_debug("sxtb %s,%s\n",regname[rt],regname[rs]);
1402 output_w32(0xe6af0070|rd_rn_rm(rt,0,rs));
1406 void emit_shl(u_int rs,u_int shift,u_int rt)
1412 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1413 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1415 void emit_shr(u_int rs,u_int shift,u_int rt)
1420 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1421 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1423 void emit_sar(u_int rs,u_int shift,u_int rt)
1428 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1429 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1431 void emit_shlcl(int r)
1433 assem_debug("shl %%%s,%%cl\n",regname[r]);
1436 void emit_shrcl(int r)
1438 assem_debug("shr %%%s,%%cl\n",regname[r]);
1441 void emit_sarcl(int r)
1443 assem_debug("sar %%%s,%%cl\n",regname[r]);
1447 void emit_shldcl(int r1,int r2)
1449 assem_debug("shld %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1452 void emit_shrdcl(int r1,int r2)
1454 assem_debug("shrd %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1457 void emit_orrshl(u_int rs,u_int shift,u_int rt)
1462 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1463 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1465 void emit_orrshr(u_int rs,u_int shift,u_int rt)
1470 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1471 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1474 void emit_cmpimm(int rs,int imm)
1477 if(genimm(imm,&armval)) {
1478 assem_debug("cmp %s,#%d\n",regname[rs],imm);
1479 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1480 }else if(genimm(-imm,&armval)) {
1481 assem_debug("cmn %s,#%d\n",regname[rs],imm);
1482 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1486 emit_movimm(imm,HOST_TEMPREG);
1488 emit_movw(imm,HOST_TEMPREG);
1490 assem_debug("cmp %s,r14\n",regname[rs]);
1491 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1495 emit_movimm(-imm,HOST_TEMPREG);
1497 emit_movw(-imm,HOST_TEMPREG);
1499 assem_debug("cmn %s,r14\n",regname[rs]);
1500 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1504 void emit_cmovne(u_int *addr,int rt)
1506 assem_debug("cmovne %x,%%%s",(int)addr,regname[rt]);
1509 void emit_cmovl(u_int *addr,int rt)
1511 assem_debug("cmovl %x,%%%s",(int)addr,regname[rt]);
1514 void emit_cmovs(u_int *addr,int rt)
1516 assem_debug("cmovs %x,%%%s",(int)addr,regname[rt]);
1519 void emit_cmovne_imm(int imm,int rt)
1521 assem_debug("movne %s,#%d\n",regname[rt],imm);
1523 genimm_checked(imm,&armval);
1524 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1526 void emit_cmovl_imm(int imm,int rt)
1528 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1530 genimm_checked(imm,&armval);
1531 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1533 void emit_cmovb_imm(int imm,int rt)
1535 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1537 genimm_checked(imm,&armval);
1538 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1540 void emit_cmovs_imm(int imm,int rt)
1542 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1544 genimm_checked(imm,&armval);
1545 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1547 void emit_cmove_reg(int rs,int rt)
1549 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1550 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1552 void emit_cmovne_reg(int rs,int rt)
1554 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1555 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1557 void emit_cmovl_reg(int rs,int rt)
1559 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1560 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1562 void emit_cmovs_reg(int rs,int rt)
1564 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1565 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1568 void emit_slti32(int rs,int imm,int rt)
1570 if(rs!=rt) emit_zeroreg(rt);
1571 emit_cmpimm(rs,imm);
1572 if(rs==rt) emit_movimm(0,rt);
1573 emit_cmovl_imm(1,rt);
1575 void emit_sltiu32(int rs,int imm,int rt)
1577 if(rs!=rt) emit_zeroreg(rt);
1578 emit_cmpimm(rs,imm);
1579 if(rs==rt) emit_movimm(0,rt);
1580 emit_cmovb_imm(1,rt);
1582 void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1585 emit_slti32(rsl,imm,rt);
1589 emit_cmovne_imm(0,rt);
1590 emit_cmovs_imm(1,rt);
1594 emit_cmpimm(rsh,-1);
1595 emit_cmovne_imm(0,rt);
1596 emit_cmovl_imm(1,rt);
1599 void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1602 emit_sltiu32(rsl,imm,rt);
1606 emit_cmovne_imm(0,rt);
1610 emit_cmpimm(rsh,-1);
1611 emit_cmovne_imm(1,rt);
1615 void emit_cmp(int rs,int rt)
1617 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1618 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1620 void emit_set_gz32(int rs, int rt)
1622 //assem_debug("set_gz32\n");
1625 emit_cmovl_imm(0,rt);
1627 void emit_set_nz32(int rs, int rt)
1629 //assem_debug("set_nz32\n");
1630 if(rs!=rt) emit_movs(rs,rt);
1631 else emit_test(rs,rs);
1632 emit_cmovne_imm(1,rt);
1634 void emit_set_gz64_32(int rsh, int rsl, int rt)
1636 //assem_debug("set_gz64\n");
1637 emit_set_gz32(rsl,rt);
1639 emit_cmovne_imm(1,rt);
1640 emit_cmovs_imm(0,rt);
1642 void emit_set_nz64_32(int rsh, int rsl, int rt)
1644 //assem_debug("set_nz64\n");
1645 emit_or_and_set_flags(rsh,rsl,rt);
1646 emit_cmovne_imm(1,rt);
1648 void emit_set_if_less32(int rs1, int rs2, int rt)
1650 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1651 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1653 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1654 emit_cmovl_imm(1,rt);
1656 void emit_set_if_carry32(int rs1, int rs2, int rt)
1658 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1659 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1661 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1662 emit_cmovb_imm(1,rt);
1664 void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1666 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1671 emit_sbcs(u1,u2,HOST_TEMPREG);
1672 emit_cmovl_imm(1,rt);
1674 void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1676 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1681 emit_sbcs(u1,u2,HOST_TEMPREG);
1682 emit_cmovb_imm(1,rt);
1685 void emit_call(int a)
1687 assem_debug("bl %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1688 u_int offset=genjmp(a);
1689 output_w32(0xeb000000|offset);
1691 void emit_jmp(int a)
1693 assem_debug("b %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1694 u_int offset=genjmp(a);
1695 output_w32(0xea000000|offset);
1697 void emit_jne(int a)
1699 assem_debug("bne %x\n",a);
1700 u_int offset=genjmp(a);
1701 output_w32(0x1a000000|offset);
1703 void emit_jeq(int a)
1705 assem_debug("beq %x\n",a);
1706 u_int offset=genjmp(a);
1707 output_w32(0x0a000000|offset);
1711 assem_debug("bmi %x\n",a);
1712 u_int offset=genjmp(a);
1713 output_w32(0x4a000000|offset);
1715 void emit_jns(int a)
1717 assem_debug("bpl %x\n",a);
1718 u_int offset=genjmp(a);
1719 output_w32(0x5a000000|offset);
1723 assem_debug("blt %x\n",a);
1724 u_int offset=genjmp(a);
1725 output_w32(0xba000000|offset);
1727 void emit_jge(int a)
1729 assem_debug("bge %x\n",a);
1730 u_int offset=genjmp(a);
1731 output_w32(0xaa000000|offset);
1733 void emit_jno(int a)
1735 assem_debug("bvc %x\n",a);
1736 u_int offset=genjmp(a);
1737 output_w32(0x7a000000|offset);
1741 assem_debug("bcs %x\n",a);
1742 u_int offset=genjmp(a);
1743 output_w32(0x2a000000|offset);
1745 void emit_jcc(int a)
1747 assem_debug("bcc %x\n",a);
1748 u_int offset=genjmp(a);
1749 output_w32(0x3a000000|offset);
1752 void emit_pushimm(int imm)
1754 assem_debug("push $%x\n",imm);
1759 assem_debug("pusha\n");
1764 assem_debug("popa\n");
1767 void emit_pushreg(u_int r)
1769 assem_debug("push %%%s\n",regname[r]);
1772 void emit_popreg(u_int r)
1774 assem_debug("pop %%%s\n",regname[r]);
1777 void emit_callreg(u_int r)
1780 assem_debug("blx %s\n",regname[r]);
1781 output_w32(0xe12fff30|r);
1783 void emit_jmpreg(u_int r)
1785 assem_debug("mov pc,%s\n",regname[r]);
1786 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1789 void emit_readword_indexed(int offset, int rs, int rt)
1791 assert(offset>-4096&&offset<4096);
1792 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1794 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1796 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1799 void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1801 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1802 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1804 void emit_ldrcc_dualindexed(int rs1, int rs2, int rt)
1806 assem_debug("ldrcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1807 output_w32(0x37900000|rd_rn_rm(rt,rs1,rs2));
1809 void emit_ldrccb_dualindexed(int rs1, int rs2, int rt)
1811 assem_debug("ldrccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1812 output_w32(0x37d00000|rd_rn_rm(rt,rs1,rs2));
1814 void emit_ldrccsb_dualindexed(int rs1, int rs2, int rt)
1816 assem_debug("ldrccsb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1817 output_w32(0x319000d0|rd_rn_rm(rt,rs1,rs2));
1819 void emit_ldrcch_dualindexed(int rs1, int rs2, int rt)
1821 assem_debug("ldrcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1822 output_w32(0x319000b0|rd_rn_rm(rt,rs1,rs2));
1824 void emit_ldrccsh_dualindexed(int rs1, int rs2, int rt)
1826 assem_debug("ldrccsh %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1827 output_w32(0x319000f0|rd_rn_rm(rt,rs1,rs2));
1829 void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1831 if(map<0) emit_readword_indexed(addr, rs, rt);
1834 emit_readword_dualindexedx4(rs, map, rt);
1837 void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1840 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1841 emit_readword_indexed(addr+4, rs, rl);
1844 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1845 emit_addimm(map,1,map);
1846 emit_readword_indexed_tlb(addr, rs, map, rl);
1849 void emit_movsbl_indexed(int offset, int rs, int rt)
1851 assert(offset>-256&&offset<256);
1852 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1854 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1856 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1859 void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1861 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1864 emit_shlimm(map,2,map);
1865 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1866 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1868 assert(addr>-256&&addr<256);
1869 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1870 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1871 emit_movsbl_indexed(addr, rt, rt);
1875 void emit_movswl_indexed(int offset, int rs, int rt)
1877 assert(offset>-256&&offset<256);
1878 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1880 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1882 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1885 void emit_movzbl_indexed(int offset, int rs, int rt)
1887 assert(offset>-4096&&offset<4096);
1888 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1890 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1892 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1895 void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1897 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1898 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1900 void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1902 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1905 emit_movzbl_dualindexedx4(rs, map, rt);
1907 emit_addimm(rs,addr,rt);
1908 emit_movzbl_dualindexedx4(rt, map, rt);
1912 void emit_movzwl_indexed(int offset, int rs, int rt)
1914 assert(offset>-256&&offset<256);
1915 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1917 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1919 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1922 void emit_readword(int addr, int rt)
1924 u_int offset = addr-(u_int)&dynarec_local;
1925 assert(offset<4096);
1926 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1927 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1929 void emit_movsbl(int addr, int rt)
1931 u_int offset = addr-(u_int)&dynarec_local;
1933 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1934 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1936 void emit_movswl(int addr, int rt)
1938 u_int offset = addr-(u_int)&dynarec_local;
1940 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1941 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1943 void emit_movzbl(int addr, int rt)
1945 u_int offset = addr-(u_int)&dynarec_local;
1946 assert(offset<4096);
1947 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1948 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1950 void emit_movzwl(int addr, int rt)
1952 u_int offset = addr-(u_int)&dynarec_local;
1954 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1955 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1957 void emit_movzwl_reg(int rs, int rt)
1959 assem_debug("movzwl %%%s,%%%s\n",regname[rs]+1,regname[rt]);
1963 void emit_xchg(int rs, int rt)
1965 assem_debug("xchg %%%s,%%%s\n",regname[rs],regname[rt]);
1968 void emit_writeword_indexed(int rt, int offset, int rs)
1970 assert(offset>-4096&&offset<4096);
1971 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
1973 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
1975 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
1978 void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
1980 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1981 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
1983 void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1985 if(map<0) emit_writeword_indexed(rt, addr, rs);
1988 emit_writeword_dualindexedx4(rt, rs, map);
1991 void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
1994 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
1995 emit_writeword_indexed(rl, addr+4, rs);
1998 if(temp!=rs) emit_addimm(map,1,temp);
1999 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
2000 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
2002 emit_addimm(rs,4,rs);
2003 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
2007 void emit_writehword_indexed(int rt, int offset, int rs)
2009 assert(offset>-256&&offset<256);
2010 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
2012 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
2014 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
2017 void emit_writebyte_indexed(int rt, int offset, int rs)
2019 assert(offset>-4096&&offset<4096);
2020 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
2022 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
2024 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
2027 void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
2029 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
2030 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
2032 void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
2034 if(map<0) emit_writebyte_indexed(rt, addr, rs);
2037 emit_writebyte_dualindexedx4(rt, rs, map);
2039 emit_addimm(rs,addr,temp);
2040 emit_writebyte_dualindexedx4(rt, temp, map);
2044 void emit_strcc_dualindexed(int rs1, int rs2, int rt)
2046 assem_debug("strcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2047 output_w32(0x37800000|rd_rn_rm(rt,rs1,rs2));
2049 void emit_strccb_dualindexed(int rs1, int rs2, int rt)
2051 assem_debug("strccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2052 output_w32(0x37c00000|rd_rn_rm(rt,rs1,rs2));
2054 void emit_strcch_dualindexed(int rs1, int rs2, int rt)
2056 assem_debug("strcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2057 output_w32(0x318000b0|rd_rn_rm(rt,rs1,rs2));
2059 void emit_writeword(int rt, int addr)
2061 u_int offset = addr-(u_int)&dynarec_local;
2062 assert(offset<4096);
2063 assem_debug("str %s,fp+%d\n",regname[rt],offset);
2064 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
2066 void emit_writehword(int rt, int addr)
2068 u_int offset = addr-(u_int)&dynarec_local;
2070 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
2071 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
2073 void emit_writebyte(int rt, int addr)
2075 u_int offset = addr-(u_int)&dynarec_local;
2076 assert(offset<4096);
2077 assem_debug("strb %s,fp+%d\n",regname[rt],offset);
2078 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
2080 void emit_writeword_imm(int imm, int addr)
2082 assem_debug("movl $%x,%x\n",imm,addr);
2085 void emit_writebyte_imm(int imm, int addr)
2087 assem_debug("movb $%x,%x\n",imm,addr);
2091 void emit_mul(int rs)
2093 assem_debug("mul %%%s\n",regname[rs]);
2096 void emit_imul(int rs)
2098 assem_debug("imul %%%s\n",regname[rs]);
2101 void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2103 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2108 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2110 void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2112 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2117 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2120 void emit_div(int rs)
2122 assem_debug("div %%%s\n",regname[rs]);
2125 void emit_idiv(int rs)
2127 assem_debug("idiv %%%s\n",regname[rs]);
2132 assem_debug("cdq\n");
2136 void emit_clz(int rs,int rt)
2138 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
2139 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
2142 void emit_subcs(int rs1,int rs2,int rt)
2144 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2145 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
2148 void emit_shrcc_imm(int rs,u_int imm,int rt)
2152 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2153 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2156 void emit_negmi(int rs, int rt)
2158 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
2159 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2162 void emit_negsmi(int rs, int rt)
2164 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2165 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2168 void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2170 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2171 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2174 void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2176 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2177 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2180 void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2182 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2183 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2186 void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2188 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2189 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2192 void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2194 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2195 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2198 void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2200 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2201 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2204 void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2206 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2207 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2210 void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2212 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2213 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2216 void emit_teq(int rs, int rt)
2218 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2219 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2222 void emit_rsbimm(int rs, int imm, int rt)
2225 genimm_checked(imm,&armval);
2226 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2227 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2230 // Load 2 immediates optimizing for small code size
2231 void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2233 emit_movimm(imm1,rt1);
2235 if(genimm(imm2-imm1,&armval)) {
2236 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2237 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2238 }else if(genimm(imm1-imm2,&armval)) {
2239 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2240 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2242 else emit_movimm(imm2,rt2);
2245 // Conditionally select one of two immediates, optimizing for small code size
2246 // This will only be called if HAVE_CMOV_IMM is defined
2247 void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2250 if(genimm(imm2-imm1,&armval)) {
2251 emit_movimm(imm1,rt);
2252 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2253 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2254 }else if(genimm(imm1-imm2,&armval)) {
2255 emit_movimm(imm1,rt);
2256 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2257 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2261 emit_movimm(imm1,rt);
2262 add_literal((int)out,imm2);
2263 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2264 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2266 emit_movw(imm1&0x0000FFFF,rt);
2267 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2268 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2269 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2271 emit_movt(imm1&0xFFFF0000,rt);
2272 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2273 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2274 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2280 // special case for checking invalid_code
2281 void emit_cmpmem_indexedsr12_imm(int addr,int r,int imm)
2286 // special case for checking invalid_code
2287 void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2289 assert(imm<128&&imm>=0);
2291 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2292 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2293 emit_cmpimm(HOST_TEMPREG,imm);
2296 // special case for tlb mapping
2297 void emit_addsr12(int rs1,int rs2,int rt)
2299 assem_debug("add %s,%s,%s lsr #12\n",regname[rt],regname[rs1],regname[rs2]);
2300 output_w32(0xe0800620|rd_rn_rm(rt,rs1,rs2));
2303 void emit_callne(int a)
2305 assem_debug("blne %x\n",a);
2306 u_int offset=genjmp(a);
2307 output_w32(0x1b000000|offset);
2310 // Used to preload hash table entries
2311 void emit_prefetch(void *addr)
2313 assem_debug("prefetch %x\n",(int)addr);
2316 output_modrm(0,5,1);
2317 output_w32((int)addr);
2319 void emit_prefetchreg(int r)
2321 assem_debug("pld %s\n",regname[r]);
2322 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2325 // Special case for mini_ht
2326 void emit_ldreq_indexed(int rs, u_int offset, int rt)
2328 assert(offset<4096);
2329 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2330 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2333 void emit_flds(int r,int sr)
2335 assem_debug("flds s%d,[%s]\n",sr,regname[r]);
2336 output_w32(0xed900a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2339 void emit_vldr(int r,int vr)
2341 assem_debug("vldr d%d,[%s]\n",vr,regname[r]);
2342 output_w32(0xed900b00|(vr<<12)|(r<<16));
2345 void emit_fsts(int sr,int r)
2347 assem_debug("fsts s%d,[%s]\n",sr,regname[r]);
2348 output_w32(0xed800a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2351 void emit_vstr(int vr,int r)
2353 assem_debug("vstr d%d,[%s]\n",vr,regname[r]);
2354 output_w32(0xed800b00|(vr<<12)|(r<<16));
2357 void emit_ftosizs(int s,int d)
2359 assem_debug("ftosizs s%d,s%d\n",d,s);
2360 output_w32(0xeebd0ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2363 void emit_ftosizd(int s,int d)
2365 assem_debug("ftosizd s%d,d%d\n",d,s);
2366 output_w32(0xeebd0bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2369 void emit_fsitos(int s,int d)
2371 assem_debug("fsitos s%d,s%d\n",d,s);
2372 output_w32(0xeeb80ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2375 void emit_fsitod(int s,int d)
2377 assem_debug("fsitod d%d,s%d\n",d,s);
2378 output_w32(0xeeb80bc0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2381 void emit_fcvtds(int s,int d)
2383 assem_debug("fcvtds d%d,s%d\n",d,s);
2384 output_w32(0xeeb70ac0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2387 void emit_fcvtsd(int s,int d)
2389 assem_debug("fcvtsd s%d,d%d\n",d,s);
2390 output_w32(0xeeb70bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2393 void emit_fsqrts(int s,int d)
2395 assem_debug("fsqrts d%d,s%d\n",d,s);
2396 output_w32(0xeeb10ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2399 void emit_fsqrtd(int s,int d)
2401 assem_debug("fsqrtd s%d,d%d\n",d,s);
2402 output_w32(0xeeb10bc0|((d&7)<<12)|(s&7));
2405 void emit_fabss(int s,int d)
2407 assem_debug("fabss d%d,s%d\n",d,s);
2408 output_w32(0xeeb00ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2411 void emit_fabsd(int s,int d)
2413 assem_debug("fabsd s%d,d%d\n",d,s);
2414 output_w32(0xeeb00bc0|((d&7)<<12)|(s&7));
2417 void emit_fnegs(int s,int d)
2419 assem_debug("fnegs d%d,s%d\n",d,s);
2420 output_w32(0xeeb10a40|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2423 void emit_fnegd(int s,int d)
2425 assem_debug("fnegd s%d,d%d\n",d,s);
2426 output_w32(0xeeb10b40|((d&7)<<12)|(s&7));
2429 void emit_fadds(int s1,int s2,int d)
2431 assem_debug("fadds s%d,s%d,s%d\n",d,s1,s2);
2432 output_w32(0xee300a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2435 void emit_faddd(int s1,int s2,int d)
2437 assem_debug("faddd d%d,d%d,d%d\n",d,s1,s2);
2438 output_w32(0xee300b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2441 void emit_fsubs(int s1,int s2,int d)
2443 assem_debug("fsubs s%d,s%d,s%d\n",d,s1,s2);
2444 output_w32(0xee300a40|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2447 void emit_fsubd(int s1,int s2,int d)
2449 assem_debug("fsubd d%d,d%d,d%d\n",d,s1,s2);
2450 output_w32(0xee300b40|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2453 void emit_fmuls(int s1,int s2,int d)
2455 assem_debug("fmuls s%d,s%d,s%d\n",d,s1,s2);
2456 output_w32(0xee200a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2459 void emit_fmuld(int s1,int s2,int d)
2461 assem_debug("fmuld d%d,d%d,d%d\n",d,s1,s2);
2462 output_w32(0xee200b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2465 void emit_fdivs(int s1,int s2,int d)
2467 assem_debug("fdivs s%d,s%d,s%d\n",d,s1,s2);
2468 output_w32(0xee800a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2471 void emit_fdivd(int s1,int s2,int d)
2473 assem_debug("fdivd d%d,d%d,d%d\n",d,s1,s2);
2474 output_w32(0xee800b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2477 void emit_fcmps(int x,int y)
2479 assem_debug("fcmps s14, s15\n");
2480 output_w32(0xeeb47a67);
2483 void emit_fcmpd(int x,int y)
2485 assem_debug("fcmpd d6, d7\n");
2486 output_w32(0xeeb46b47);
2491 assem_debug("fmstat\n");
2492 output_w32(0xeef1fa10);
2495 void emit_bicne_imm(int rs,int imm,int rt)
2498 genimm_checked(imm,&armval);
2499 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2500 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2503 void emit_biccs_imm(int rs,int imm,int rt)
2506 genimm_checked(imm,&armval);
2507 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2508 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2511 void emit_bicvc_imm(int rs,int imm,int rt)
2514 genimm_checked(imm,&armval);
2515 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2516 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2519 void emit_bichi_imm(int rs,int imm,int rt)
2522 genimm_checked(imm,&armval);
2523 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2524 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2527 void emit_orrvs_imm(int rs,int imm,int rt)
2530 genimm_checked(imm,&armval);
2531 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2532 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2535 void emit_orrne_imm(int rs,int imm,int rt)
2538 genimm_checked(imm,&armval);
2539 assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2540 output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
2543 void emit_andne_imm(int rs,int imm,int rt)
2546 genimm_checked(imm,&armval);
2547 assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2548 output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
2551 void emit_jno_unlikely(int a)
2554 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2555 output_w32(0x72800000|rd_rn_rm(15,15,0));
2558 // Save registers before function call
2559 void save_regs(u_int reglist)
2561 reglist&=0x100f; // only save the caller-save registers, r0-r3, r12
2562 if(!reglist) return;
2563 assem_debug("stmia fp,{");
2564 if(reglist&1) assem_debug("r0, ");
2565 if(reglist&2) assem_debug("r1, ");
2566 if(reglist&4) assem_debug("r2, ");
2567 if(reglist&8) assem_debug("r3, ");
2568 if(reglist&0x1000) assem_debug("r12");
2570 output_w32(0xe88b0000|reglist);
2572 // Restore registers after function call
2573 void restore_regs(u_int reglist)
2575 reglist&=0x100f; // only restore the caller-save registers, r0-r3, r12
2576 if(!reglist) return;
2577 assem_debug("ldmia fp,{");
2578 if(reglist&1) assem_debug("r0, ");
2579 if(reglist&2) assem_debug("r1, ");
2580 if(reglist&4) assem_debug("r2, ");
2581 if(reglist&8) assem_debug("r3, ");
2582 if(reglist&0x1000) assem_debug("r12");
2584 output_w32(0xe89b0000|reglist);
2587 // Write back consts using r14 so we don't disturb the other registers
2588 void wb_consts(signed char i_regmap[],uint64_t i_is32,u_int i_dirty,int i)
2591 for(hr=0;hr<HOST_REGS;hr++) {
2592 if(hr!=EXCLUDE_REG&&i_regmap[hr]>=0&&((i_dirty>>hr)&1)) {
2593 if(((regs[i].isconst>>hr)&1)&&i_regmap[hr]>0) {
2594 if(i_regmap[hr]<64 || !((i_is32>>(i_regmap[hr]&63))&1) ) {
2595 int value=constmap[i][hr];
2597 emit_zeroreg(HOST_TEMPREG);
2600 emit_movimm(value,HOST_TEMPREG);
2602 emit_storereg(i_regmap[hr],HOST_TEMPREG);
2604 if((i_is32>>i_regmap[hr])&1) {
2605 if(value!=-1&&value!=0) emit_sarimm(HOST_TEMPREG,31,HOST_TEMPREG);
2606 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
2615 /* Stubs/epilogue */
2617 void literal_pool(int n)
2619 if(!literalcount) return;
2621 if((int)out-literals[0][0]<4096-n) return;
2625 for(i=0;i<literalcount;i++)
2627 ptr=(u_int *)literals[i][0];
2628 u_int offset=(u_int)out-(u_int)ptr-8;
2629 assert(offset<4096);
2630 assert(!(offset&3));
2632 output_w32(literals[i][1]);
2637 void literal_pool_jumpover(int n)
2639 if(!literalcount) return;
2641 if((int)out-literals[0][0]<4096-n) return;
2646 set_jump_target(jaddr,(int)out);
2649 emit_extjump2(int addr, int target, int linker)
2651 u_char *ptr=(u_char *)addr;
2652 assert((ptr[3]&0x0e)==0xa);
2653 emit_loadlp(target,0);
2654 emit_loadlp(addr,1);
2655 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
2656 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2658 #ifdef DEBUG_CYCLE_COUNT
2659 emit_readword((int)&last_count,ECX);
2660 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2661 emit_readword((int)&next_interupt,ECX);
2662 emit_writeword(HOST_CCREG,(int)&Count);
2663 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2664 emit_writeword(ECX,(int)&last_count);
2670 emit_extjump(int addr, int target)
2672 emit_extjump2(addr, target, (int)dyna_linker);
2674 emit_extjump_ds(int addr, int target)
2676 emit_extjump2(addr, target, (int)dyna_linker_ds);
2680 #include "pcsxmem_inline.c"
2684 static void pass_args(int a0, int a1)
2688 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2690 else if(a0!=0&&a1==0) {
2692 if (a0>=0) emit_mov(a0,0);
2695 if(a0>=0&&a0!=0) emit_mov(a0,0);
2696 if(a1>=0&&a1!=1) emit_mov(a1,1);
2702 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2704 set_jump_target(stubs[n][1],(int)out);
2705 int type=stubs[n][0];
2708 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2709 u_int reglist=stubs[n][7];
2710 signed char *i_regmap=i_regs->regmap;
2711 int addr=get_reg(i_regmap,AGEN1+(i&1));
2714 if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
2715 rth=get_reg(i_regmap,FTEMP|64);
2716 rt=get_reg(i_regmap,FTEMP);
2718 rth=get_reg(i_regmap,rt1[i]|64);
2719 rt=get_reg(i_regmap,rt1[i]);
2723 int r,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0;
2725 for(r=0;r<=12;r++) {
2726 if(((1<<r)&0x13ff)&&((1<<r)®list)==0) {
2737 if((regs_saved||(reglist&2)==0)&&temp!=1&&rs!=1)
2739 emit_readword((int)&mem_rtab,temp);
2740 emit_shrimm(rs,12,temp2);
2741 emit_readword_dualindexedx4(temp,temp2,temp2);
2742 emit_lsls_imm(temp2,1,temp2);
2743 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2745 case LOADB_STUB: emit_ldrccsb_dualindexed(temp2,rs,rt); break;
2746 case LOADBU_STUB: emit_ldrccb_dualindexed(temp2,rs,rt); break;
2747 case LOADH_STUB: emit_ldrccsh_dualindexed(temp2,rs,rt); break;
2748 case LOADHU_STUB: emit_ldrcch_dualindexed(temp2,rs,rt); break;
2749 case LOADW_STUB: emit_ldrcc_dualindexed(temp2,rs,rt); break;
2753 restore_jump=(int)out;
2754 emit_jcc(0); // jump to reg restore
2757 emit_jcc(stubs[n][2]); // return address
2762 if(type==LOADB_STUB||type==LOADBU_STUB)
2763 handler=(int)jump_handler_read8;
2764 if(type==LOADH_STUB||type==LOADHU_STUB)
2765 handler=(int)jump_handler_read16;
2766 if(type==LOADW_STUB)
2767 handler=(int)jump_handler_read32;
2769 pass_args(rs,temp2);
2770 int cc=get_reg(i_regmap,CCREG);
2772 emit_loadreg(CCREG,2);
2773 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*stubs[n][6]+2,2);
2775 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2777 case LOADB_STUB: emit_signextend8(0,rt); break;
2778 case LOADBU_STUB: emit_andimm(0,0xff,rt); break;
2779 case LOADH_STUB: emit_signextend16(0,rt); break;
2780 case LOADHU_STUB: emit_andimm(0,0xffff,rt); break;
2781 case LOADW_STUB: if(rt!=0) emit_mov(0,rt); break;
2785 set_jump_target(restore_jump,(int)out);
2786 restore_regs(reglist);
2787 emit_jmp(stubs[n][2]); // return address
2790 if(addr<0&&itype[i]!=C1LS&&itype[i]!=C2LS&&itype[i]!=LOADLR) addr=get_reg(i_regmap,-1);
2793 if(type==LOADB_STUB||type==LOADBU_STUB)
2794 ftable=(int)readmemb;
2795 if(type==LOADH_STUB||type==LOADHU_STUB)
2796 ftable=(int)readmemh;
2797 if(type==LOADW_STUB)
2798 ftable=(int)readmem;
2800 if(type==LOADD_STUB)
2801 ftable=(int)readmemd;
2804 emit_writeword(rs,(int)&address);
2808 ds=i_regs!=®s[i];
2809 int real_rs=(itype[i]==LOADLR)?-1:get_reg(i_regmap,rs1[i]);
2810 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2811 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2812 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2813 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2815 emit_shrimm(rs,16,1);
2816 int cc=get_reg(i_regmap,CCREG);
2818 emit_loadreg(CCREG,2);
2820 emit_movimm(ftable,0);
2821 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2823 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2825 //emit_readword((int)&last_count,temp);
2826 //emit_add(cc,temp,cc);
2827 //emit_writeword(cc,(int)&Count);
2829 emit_call((int)&indirect_jump_indexed);
2831 //emit_readword_dualindexedx4(rs,HOST_TEMPREG,15);
2833 // We really shouldn't need to update the count here,
2834 // but not doing so causes random crashes...
2835 emit_readword((int)&Count,HOST_TEMPREG);
2836 emit_readword((int)&next_interupt,2);
2837 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2838 emit_writeword(2,(int)&last_count);
2839 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2841 emit_storereg(CCREG,HOST_TEMPREG);
2845 restore_regs(reglist);
2846 //if((cc=get_reg(regmap,CCREG))>=0) {
2847 // emit_loadreg(CCREG,cc);
2849 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2851 if(type==LOADB_STUB)
2852 emit_movsbl((int)&readmem_dword,rt);
2853 if(type==LOADBU_STUB)
2854 emit_movzbl((int)&readmem_dword,rt);
2855 if(type==LOADH_STUB)
2856 emit_movswl((int)&readmem_dword,rt);
2857 if(type==LOADHU_STUB)
2858 emit_movzwl((int)&readmem_dword,rt);
2859 if(type==LOADW_STUB)
2860 emit_readword((int)&readmem_dword,rt);
2861 if(type==LOADD_STUB) {
2862 emit_readword((int)&readmem_dword,rt);
2863 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2866 emit_jmp(stubs[n][2]); // return address
2871 // return memhandler, or get directly accessable address and return 0
2872 u_int get_direct_memhandler(void *table,u_int addr,int type,u_int *addr_host)
2875 l1=((u_int *)table)[addr>>12];
2876 if((l1&(1<<31))==0) {
2883 if(type==LOADB_STUB||type==LOADBU_STUB||type==STOREB_STUB)
2884 l2=((u_int *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2885 else if(type==LOADH_STUB||type==LOADHU_STUB||type==STOREH_STUB)
2886 l2=((u_int *)l1)[0x1000/4 + (addr&0xfff)/2];
2888 l2=((u_int *)l1)[(addr&0xfff)/4];
2889 if((l2&(1<<31))==0) {
2891 *addr_host=v+(addr&0xfff);
2899 inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2901 int rs=get_reg(regmap,target);
2902 int rth=get_reg(regmap,target|64);
2903 int rt=get_reg(regmap,target);
2904 if(rs<0) rs=get_reg(regmap,-1);
2907 u_int handler,host_addr=0;
2908 if(pcsx_direct_read(type,addr,target?rs:-1,rt))
2910 handler=get_direct_memhandler(mem_rtab,addr,type,&host_addr);
2914 if(target==0||addr!=host_addr)
2915 emit_movimm(host_addr,rs);
2917 case LOADB_STUB: emit_movsbl_indexed(0,rs,rt); break;
2918 case LOADBU_STUB: emit_movzbl_indexed(0,rs,rt); break;
2919 case LOADH_STUB: emit_movswl_indexed(0,rs,rt); break;
2920 case LOADHU_STUB: emit_movzwl_indexed(0,rs,rt); break;
2921 case LOADW_STUB: emit_readword_indexed(0,rs,rt); break;
2927 // call a memhandler
2932 emit_movimm(addr,0);
2935 int cc=get_reg(regmap,CCREG);
2937 emit_loadreg(CCREG,2);
2938 emit_readword((int)&last_count,3);
2939 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
2941 emit_writeword(3,(int)&Count);
2943 int offset=(int)handler-(int)out-8;
2944 if(offset<-33554432||offset>=33554432) {
2945 // unreachable memhandler, a plugin func perhaps
2946 emit_movimm(handler,1);
2953 case LOADB_STUB: emit_signextend8(0,rt); break;
2954 case LOADBU_STUB: emit_andimm(0,0xff,rt); break;
2955 case LOADH_STUB: emit_signextend16(0,rt); break;
2956 case LOADHU_STUB: emit_andimm(0,0xffff,rt); break;
2957 case LOADW_STUB: if(rt!=0) emit_mov(0,rt); break;
2961 restore_regs(reglist);
2964 if(type==LOADB_STUB||type==LOADBU_STUB)
2965 ftable=(int)readmemb;
2966 if(type==LOADH_STUB||type==LOADHU_STUB)
2967 ftable=(int)readmemh;
2968 if(type==LOADW_STUB)
2969 ftable=(int)readmem;
2971 if(type==LOADD_STUB)
2972 ftable=(int)readmemd;
2976 emit_movimm(addr,rs);
2977 emit_writeword(rs,(int)&address);
2981 if((signed int)addr>=(signed int)0xC0000000) {
2982 // Theoretically we can have a pagefault here, if the TLB has never
2983 // been enabled and the address is outside the range 80000000..BFFFFFFF
2984 // Write out the registers so the pagefault can be handled. This is
2985 // a very rare case and likely represents a bug.
2986 int ds=regmap!=regs[i].regmap;
2987 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
2988 if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
2989 else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty);
2992 //emit_shrimm(rs,16,1);
2993 int cc=get_reg(regmap,CCREG);
2995 emit_loadreg(CCREG,2);
2997 //emit_movimm(ftable,0);
2998 emit_movimm(((u_int *)ftable)[addr>>16],0);
2999 //emit_readword((int)&last_count,12);
3000 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
3002 if((signed int)addr>=(signed int)0xC0000000) {
3003 // Pagefault address
3004 int ds=regmap!=regs[i].regmap;
3005 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3009 //emit_writeword(2,(int)&Count);
3010 //emit_call(((u_int *)ftable)[addr>>16]);
3011 emit_call((int)&indirect_jump);
3013 // We really shouldn't need to update the count here,
3014 // but not doing so causes random crashes...
3015 emit_readword((int)&Count,HOST_TEMPREG);
3016 emit_readword((int)&next_interupt,2);
3017 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
3018 emit_writeword(2,(int)&last_count);
3019 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3021 emit_storereg(CCREG,HOST_TEMPREG);
3025 restore_regs(reglist);
3027 if(type==LOADB_STUB)
3028 emit_movsbl((int)&readmem_dword,rt);
3029 if(type==LOADBU_STUB)
3030 emit_movzbl((int)&readmem_dword,rt);
3031 if(type==LOADH_STUB)
3032 emit_movswl((int)&readmem_dword,rt);
3033 if(type==LOADHU_STUB)
3034 emit_movzwl((int)&readmem_dword,rt);
3035 if(type==LOADW_STUB)
3036 emit_readword((int)&readmem_dword,rt);
3037 if(type==LOADD_STUB) {
3038 emit_readword((int)&readmem_dword,rt);
3039 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
3047 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
3049 set_jump_target(stubs[n][1],(int)out);
3050 int type=stubs[n][0];
3053 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3054 u_int reglist=stubs[n][7];
3055 signed char *i_regmap=i_regs->regmap;
3056 int addr=get_reg(i_regmap,AGEN1+(i&1));
3059 if(itype[i]==C1LS||itype[i]==C2LS) {
3060 rth=get_reg(i_regmap,FTEMP|64);
3061 rt=get_reg(i_regmap,r=FTEMP);
3063 rth=get_reg(i_regmap,rs2[i]|64);
3064 rt=get_reg(i_regmap,r=rs2[i]);
3069 int rtmp,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0,ra;
3070 int reglist2=reglist|(1<<rs)|(1<<rt);
3071 for(rtmp=0;rtmp<=12;rtmp++) {
3072 if(((1<<rtmp)&0x13ff)&&((1<<rtmp)®list2)==0) {
3079 for(rtmp=0;rtmp<=3;rtmp++)
3080 if(rtmp!=rs&&rtmp!=rt)
3083 if((regs_saved||(reglist2&8)==0)&&temp!=3&&rs!=3&&rt!=3)
3085 emit_readword((int)&mem_wtab,temp);
3086 emit_shrimm(rs,12,temp2);
3087 emit_readword_dualindexedx4(temp,temp2,temp2);
3088 emit_lsls_imm(temp2,1,temp2);
3090 case STOREB_STUB: emit_strccb_dualindexed(temp2,rs,rt); break;
3091 case STOREH_STUB: emit_strcch_dualindexed(temp2,rs,rt); break;
3092 case STOREW_STUB: emit_strcc_dualindexed(temp2,rs,rt); break;
3096 restore_jump=(int)out;
3097 emit_jcc(0); // jump to reg restore
3100 emit_jcc(stubs[n][2]); // return address (invcode check)
3106 case STOREB_STUB: handler=(int)jump_handler_write8; break;
3107 case STOREH_STUB: handler=(int)jump_handler_write16; break;
3108 case STOREW_STUB: handler=(int)jump_handler_write32; break;
3114 int cc=get_reg(i_regmap,CCREG);
3116 emit_loadreg(CCREG,2);
3117 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*stubs[n][6]+2,2);
3118 // returns new cycle_count
3120 emit_addimm(0,-CLOCK_DIVIDER*stubs[n][6]-2,cc<0?2:cc);
3122 emit_storereg(CCREG,2);
3124 set_jump_target(restore_jump,(int)out);
3125 restore_regs(reglist);
3127 if(!restore_jump) ra+=4*3; // skip invcode check
3130 if(addr<0) addr=get_reg(i_regmap,-1);
3133 if(type==STOREB_STUB)
3134 ftable=(int)writememb;
3135 if(type==STOREH_STUB)
3136 ftable=(int)writememh;
3137 if(type==STOREW_STUB)
3138 ftable=(int)writemem;
3140 if(type==STORED_STUB)
3141 ftable=(int)writememd;
3144 emit_writeword(rs,(int)&address);
3145 //emit_shrimm(rs,16,rs);
3146 //emit_movmem_indexedx4(ftable,rs,rs);
3147 if(type==STOREB_STUB)
3148 emit_writebyte(rt,(int)&byte);
3149 if(type==STOREH_STUB)
3150 emit_writehword(rt,(int)&hword);
3151 if(type==STOREW_STUB)
3152 emit_writeword(rt,(int)&word);
3153 if(type==STORED_STUB) {
3155 emit_writeword(rt,(int)&dword);
3156 emit_writeword(r?rth:rt,(int)&dword+4);
3158 printf("STORED_STUB\n");
3164 ds=i_regs!=®s[i];
3165 int real_rs=get_reg(i_regmap,rs1[i]);
3166 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
3167 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
3168 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
3169 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
3171 emit_shrimm(rs,16,1);
3172 int cc=get_reg(i_regmap,CCREG);
3174 emit_loadreg(CCREG,2);
3176 emit_movimm(ftable,0);
3177 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
3179 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3181 //emit_readword((int)&last_count,temp);
3182 //emit_addimm(cc,2*stubs[n][5]+2,cc);
3183 //emit_add(cc,temp,cc);
3184 //emit_writeword(cc,(int)&Count);
3185 emit_call((int)&indirect_jump_indexed);
3187 emit_readword((int)&Count,HOST_TEMPREG);
3188 emit_readword((int)&next_interupt,2);
3189 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
3190 emit_writeword(2,(int)&last_count);
3191 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3193 emit_storereg(CCREG,HOST_TEMPREG);
3196 restore_regs(reglist);
3197 //if((cc=get_reg(regmap,CCREG))>=0) {
3198 // emit_loadreg(CCREG,cc);
3200 emit_jmp(stubs[n][2]); // return address
3204 inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
3206 int rs=get_reg(regmap,-1);
3207 int rth=get_reg(regmap,target|64);
3208 int rt=get_reg(regmap,target);
3212 u_int handler,host_addr=0;
3213 if(pcsx_direct_write(type,addr,rs,rt,regmap))
3215 handler=get_direct_memhandler(mem_wtab,addr,type,&host_addr);
3217 if(target==0||addr!=host_addr)
3218 emit_movimm(host_addr,rs);
3220 case STOREB_STUB: emit_writebyte_indexed(rt,0,rs); break;
3221 case STOREH_STUB: emit_writehword_indexed(rt,0,rs); break;
3222 case STOREW_STUB: emit_writeword_indexed(rt,0,rs); break;
3228 // call a memhandler
3230 pass_args(target!=0?rs:-1,rt);
3232 emit_movimm(addr,0);
3233 int cc=get_reg(regmap,CCREG);
3235 emit_loadreg(CCREG,2);
3236 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
3237 emit_movimm(handler,3);
3238 // returns new cycle_count
3239 emit_call((int)jump_handler_write_h);
3240 emit_addimm(0,-CLOCK_DIVIDER*(adj+1),cc<0?2:cc);
3242 emit_storereg(CCREG,2);
3243 restore_regs(reglist);
3246 if(type==STOREB_STUB)
3247 ftable=(int)writememb;
3248 if(type==STOREH_STUB)
3249 ftable=(int)writememh;
3250 if(type==STOREW_STUB)
3251 ftable=(int)writemem;
3253 if(type==STORED_STUB)
3254 ftable=(int)writememd;
3257 emit_writeword(rs,(int)&address);
3258 //emit_shrimm(rs,16,rs);
3259 //emit_movmem_indexedx4(ftable,rs,rs);
3260 if(type==STOREB_STUB)
3261 emit_writebyte(rt,(int)&byte);
3262 if(type==STOREH_STUB)
3263 emit_writehword(rt,(int)&hword);
3264 if(type==STOREW_STUB)
3265 emit_writeword(rt,(int)&word);
3266 if(type==STORED_STUB) {
3268 emit_writeword(rt,(int)&dword);
3269 emit_writeword(target?rth:rt,(int)&dword+4);
3271 printf("STORED_STUB\n");
3277 // rearmed note: load_all_consts prevents BIOS boot, some bug?
3278 if((signed int)addr>=(signed int)0xC0000000) {
3279 // Theoretically we can have a pagefault here, if the TLB has never
3280 // been enabled and the address is outside the range 80000000..BFFFFFFF
3281 // Write out the registers so the pagefault can be handled. This is
3282 // a very rare case and likely represents a bug.
3283 int ds=regmap!=regs[i].regmap;
3284 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3285 if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3286 else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty);
3289 //emit_shrimm(rs,16,1);
3290 int cc=get_reg(regmap,CCREG);
3292 emit_loadreg(CCREG,2);
3294 //emit_movimm(ftable,0);
3295 emit_movimm(((u_int *)ftable)[addr>>16],0);
3296 //emit_readword((int)&last_count,12);
3297 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
3299 if((signed int)addr>=(signed int)0xC0000000) {
3300 // Pagefault address
3301 int ds=regmap!=regs[i].regmap;
3302 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3306 //emit_writeword(2,(int)&Count);
3307 //emit_call(((u_int *)ftable)[addr>>16]);
3308 emit_call((int)&indirect_jump);
3309 emit_readword((int)&Count,HOST_TEMPREG);
3310 emit_readword((int)&next_interupt,2);
3311 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
3312 emit_writeword(2,(int)&last_count);
3313 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3315 emit_storereg(CCREG,HOST_TEMPREG);
3318 restore_regs(reglist);
3322 do_unalignedwritestub(int n)
3324 assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
3326 set_jump_target(stubs[n][1],(int)out);
3329 struct regstat *i_regs=(struct regstat *)stubs[n][4];
3330 int addr=stubs[n][5];
3331 u_int reglist=stubs[n][7];
3332 signed char *i_regmap=i_regs->regmap;
3333 int temp2=get_reg(i_regmap,FTEMP);
3336 rt=get_reg(i_regmap,rs2[i]);
3339 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
3341 reglist&=~(1<<temp2);
3344 // don't bother with it and call write handler
3347 int cc=get_reg(i_regmap,CCREG);
3349 emit_loadreg(CCREG,2);
3350 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*stubs[n][6]+2,2);
3351 emit_call((int)(opcode[i]==0x2a?jump_handle_swl:jump_handle_swr));
3352 emit_addimm(0,-CLOCK_DIVIDER*stubs[n][6]-2,cc<0?2:cc);
3354 emit_storereg(CCREG,2);
3355 restore_regs(reglist);
3356 emit_jmp(stubs[n][2]); // return address
3358 emit_andimm(addr,0xfffffffc,temp2);
3359 emit_writeword(temp2,(int)&address);
3363 ds=i_regs!=®s[i];
3364 real_rs=get_reg(i_regmap,rs1[i]);
3365 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
3366 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
3367 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
3368 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
3370 emit_shrimm(addr,16,1);
3371 int cc=get_reg(i_regmap,CCREG);
3373 emit_loadreg(CCREG,2);
3375 emit_movimm((u_int)readmem,0);
3376 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
3378 // pagefault address
3379 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3381 emit_call((int)&indirect_jump_indexed);
3382 restore_regs(reglist);
3384 emit_readword((int)&readmem_dword,temp2);
3385 int temp=addr; //hmh
3386 emit_shlimm(addr,3,temp);
3387 emit_andimm(temp,24,temp);
3388 #ifdef BIG_ENDIAN_MIPS
3389 if (opcode[i]==0x2e) // SWR
3391 if (opcode[i]==0x2a) // SWL
3393 emit_xorimm(temp,24,temp);
3394 emit_movimm(-1,HOST_TEMPREG);
3395 if (opcode[i]==0x2a) { // SWL
3396 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
3397 emit_orrshr(rt,temp,temp2);
3399 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
3400 emit_orrshl(rt,temp,temp2);
3402 emit_readword((int)&address,addr);
3403 emit_writeword(temp2,(int)&word);
3404 //save_regs(reglist); // don't need to, no state changes
3405 emit_shrimm(addr,16,1);
3406 emit_movimm((u_int)writemem,0);
3407 //emit_call((int)&indirect_jump_indexed);
3409 emit_readword_dualindexedx4(0,1,15);
3410 emit_readword((int)&Count,HOST_TEMPREG);
3411 emit_readword((int)&next_interupt,2);
3412 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
3413 emit_writeword(2,(int)&last_count);
3414 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3416 emit_storereg(CCREG,HOST_TEMPREG);
3418 restore_regs(reglist);
3419 emit_jmp(stubs[n][2]); // return address
3423 void printregs(int edi,int esi,int ebp,int esp,int b,int d,int c,int a)
3425 printf("regs: %x %x %x %x %x %x %x (%x)\n",a,b,c,d,ebp,esi,edi,(&edi)[-1]);
3431 u_int reglist=stubs[n][3];
3432 set_jump_target(stubs[n][1],(int)out);
3434 if(stubs[n][4]!=0) emit_mov(stubs[n][4],0);
3435 emit_call((int)&invalidate_addr);
3436 restore_regs(reglist);
3437 emit_jmp(stubs[n][2]); // return address
3440 int do_dirty_stub(int i)
3442 assem_debug("do_dirty_stub %x\n",start+i*4);
3443 u_int addr=(int)start<(int)0xC0000000?(u_int)source:(u_int)start;
3447 // Careful about the code output here, verify_dirty needs to parse it.
3449 emit_loadlp(addr,1);
3450 emit_loadlp((int)copy,2);
3451 emit_loadlp(slen*4,3);
3453 emit_movw(addr&0x0000FFFF,1);
3454 emit_movw(((u_int)copy)&0x0000FFFF,2);
3455 emit_movt(addr&0xFFFF0000,1);
3456 emit_movt(((u_int)copy)&0xFFFF0000,2);
3457 emit_movw(slen*4,3);
3459 emit_movimm(start+i*4,0);
3460 emit_call((int)start<(int)0xC0000000?(int)&verify_code:(int)&verify_code_vm);
3463 if(entry==(int)out) entry=instr_addr[i];
3464 emit_jmp(instr_addr[i]);
3468 void do_dirty_stub_ds()
3470 // Careful about the code output here, verify_dirty needs to parse it.
3472 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
3473 emit_loadlp((int)copy,2);
3474 emit_loadlp(slen*4,3);
3476 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
3477 emit_movw(((u_int)copy)&0x0000FFFF,2);
3478 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
3479 emit_movt(((u_int)copy)&0xFFFF0000,2);
3480 emit_movw(slen*4,3);
3482 emit_movimm(start+1,0);
3483 emit_call((int)&verify_code_ds);
3489 assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
3490 set_jump_target(stubs[n][1],(int)out);
3492 // int rs=stubs[n][4];
3493 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3496 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3497 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3499 //else {printf("fp exception in delay slot\n");}
3500 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty);
3501 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3502 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3503 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3504 emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
3509 int do_tlb_r(int s,int ar,int map,int x,int a,int shift,int c,u_int addr)
3512 if((signed int)addr>=(signed int)0xC0000000) {
3513 // address_generation already loaded the const
3514 emit_readword_dualindexedx4(FP,map,map);
3517 return -1; // No mapping
3521 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3522 emit_addsr12(map,s,map);
3523 // Schedule this while we wait on the load
3524 //if(x) emit_xorimm(s,x,ar);
3525 if(shift>=0) emit_shlimm(s,3,shift);
3526 if(~a) emit_andimm(s,a,ar);
3527 emit_readword_dualindexedx4(FP,map,map);
3531 int do_tlb_r_branch(int map, int c, u_int addr, int *jaddr)
3533 if(!c||(signed int)addr>=(signed int)0xC0000000) {
3541 int gen_tlb_addr_r(int ar, int map) {
3543 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3544 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3548 int do_tlb_w(int s,int ar,int map,int x,int c,u_int addr)
3551 if(addr<0x80800000||addr>=0xC0000000) {
3552 // address_generation already loaded the const
3553 emit_readword_dualindexedx4(FP,map,map);
3556 return -1; // No mapping
3560 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3561 emit_addsr12(map,s,map);
3562 // Schedule this while we wait on the load
3563 //if(x) emit_xorimm(s,x,ar);
3564 emit_readword_dualindexedx4(FP,map,map);