1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus/PCSX - assem_arm.c *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2011 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
26 #include "../gte_arm.h"
27 #include "../gte_neon.h"
29 #include "arm_features.h"
32 char translation_cache[1 << TARGET_SIZE_2] __attribute__((aligned(4096)));
36 #define CALLER_SAVE_REGS 0x100f
38 #define CALLER_SAVE_REGS 0x120f
41 extern int cycle_count;
42 extern int last_count;
44 extern int pending_exception;
45 extern int branch_target;
46 extern uint64_t readmem_dword;
47 extern void *dynarec_local;
48 extern u_int memory_map[1048576];
49 extern u_int mini_ht[32][2];
50 extern u_int rounding_modes[4];
52 void indirect_jump_indexed();
65 void jump_vaddr_r10();
66 void jump_vaddr_r12();
68 const u_int jump_vaddr_reg[16] = {
86 void invalidate_addr_r0();
87 void invalidate_addr_r1();
88 void invalidate_addr_r2();
89 void invalidate_addr_r3();
90 void invalidate_addr_r4();
91 void invalidate_addr_r5();
92 void invalidate_addr_r6();
93 void invalidate_addr_r7();
94 void invalidate_addr_r8();
95 void invalidate_addr_r9();
96 void invalidate_addr_r10();
97 void invalidate_addr_r12();
99 const u_int invalidate_addr_reg[16] = {
100 (int)invalidate_addr_r0,
101 (int)invalidate_addr_r1,
102 (int)invalidate_addr_r2,
103 (int)invalidate_addr_r3,
104 (int)invalidate_addr_r4,
105 (int)invalidate_addr_r5,
106 (int)invalidate_addr_r6,
107 (int)invalidate_addr_r7,
108 (int)invalidate_addr_r8,
109 (int)invalidate_addr_r9,
110 (int)invalidate_addr_r10,
112 (int)invalidate_addr_r12,
117 unsigned int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
121 void set_jump_target(int addr,u_int target)
123 u_char *ptr=(u_char *)addr;
124 u_int *ptr2=(u_int *)ptr;
126 assert((target-(u_int)ptr2-8)<1024);
128 assert((target&3)==0);
129 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
130 //printf("target=%x addr=%x insn=%x\n",target,addr,*ptr2);
132 else if(ptr[3]==0x72) {
133 // generated by emit_jno_unlikely
134 if((target-(u_int)ptr2-8)<1024) {
136 assert((target&3)==0);
137 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
139 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
141 assert((target&3)==0);
142 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
144 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
147 assert((ptr[3]&0x0e)==0xa);
148 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
152 // This optionally copies the instruction from the target of the branch into
153 // the space before the branch. Works, but the difference in speed is
154 // usually insignificant.
155 void set_jump_target_fillslot(int addr,u_int target,int copy)
157 u_char *ptr=(u_char *)addr;
158 u_int *ptr2=(u_int *)ptr;
159 assert(!copy||ptr2[-1]==0xe28dd000);
162 assert((target-(u_int)ptr2-8)<4096);
163 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
166 assert((ptr[3]&0x0e)==0xa);
167 u_int target_insn=*(u_int *)target;
168 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
171 if((target_insn&0x0c100000)==0x04100000) { // Load
174 if(target_insn&0x08000000) {
178 ptr2[-1]=target_insn;
181 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
186 add_literal(int addr,int val)
188 assert(literalcount<sizeof(literals)/sizeof(literals[0]));
189 literals[literalcount][0]=addr;
190 literals[literalcount][1]=val;
194 void *kill_pointer(void *stub)
196 int *ptr=(int *)(stub+4);
197 assert((*ptr&0x0ff00000)==0x05900000);
198 u_int offset=*ptr&0xfff;
199 int **l_ptr=(void *)ptr+offset+8;
201 set_jump_target((int)i_ptr,(int)stub);
205 // find where external branch is liked to using addr of it's stub:
206 // get address that insn one after stub loads (dyna_linker arg1),
207 // treat it as a pointer to branch insn,
208 // return addr where that branch jumps to
209 int get_pointer(void *stub)
211 //printf("get_pointer(%x)\n",(int)stub);
212 int *ptr=(int *)(stub+4);
213 assert((*ptr&0x0fff0000)==0x059f0000);
214 u_int offset=*ptr&0xfff;
215 int **l_ptr=(void *)ptr+offset+8;
217 assert((*i_ptr&0x0f000000)==0x0a000000);
218 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
221 // Find the "clean" entry point from a "dirty" entry point
222 // by skipping past the call to verify_code
223 u_int get_clean_addr(int addr)
225 int *ptr=(int *)addr;
231 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
232 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
234 if((*ptr&0xFF000000)==0xea000000) {
235 return (int)ptr+((*ptr<<8)>>6)+8; // follow jump
240 int verify_dirty(int addr)
242 u_int *ptr=(u_int *)addr;
244 // get from literal pool
245 assert((*ptr&0xFFFF0000)==0xe59f0000);
246 u_int offset=*ptr&0xfff;
247 u_int *l_ptr=(void *)ptr+offset+8;
248 u_int source=l_ptr[0];
254 assert((*ptr&0xFFF00000)==0xe3000000);
255 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
256 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
257 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
260 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
261 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
262 //printf("verify_dirty: %x %x %x\n",source,copy,len);
263 return !memcmp((void *)source,(void *)copy,len);
266 // This doesn't necessarily find all clean entry points, just
267 // guarantees that it's not dirty
268 int isclean(int addr)
271 int *ptr=((u_int *)addr)+4;
273 int *ptr=((u_int *)addr)+6;
275 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
276 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
277 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
278 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
279 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
283 // get source that block at addr was compiled from (host pointers)
284 void get_bounds(int addr,u_int *start,u_int *end)
286 u_int *ptr=(u_int *)addr;
288 // get from literal pool
289 assert((*ptr&0xFFFF0000)==0xe59f0000);
290 u_int offset=*ptr&0xfff;
291 u_int *l_ptr=(void *)ptr+offset+8;
292 u_int source=l_ptr[0];
293 //u_int copy=l_ptr[1];
298 assert((*ptr&0xFFF00000)==0xe3000000);
299 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
300 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
301 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
304 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
305 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
310 /* Register allocation */
312 // Note: registers are allocated clean (unmodified state)
313 // if you intend to modify the register, you must call dirty_reg().
314 void alloc_reg(struct regstat *cur,int i,signed char reg)
317 int preferred_reg = (reg&7);
318 if(reg==CCREG) preferred_reg=HOST_CCREG;
319 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
321 // Don't allocate unused registers
322 if((cur->u>>reg)&1) return;
324 // see if it's already allocated
325 for(hr=0;hr<HOST_REGS;hr++)
327 if(cur->regmap[hr]==reg) return;
330 // Keep the same mapping if the register was already allocated in a loop
331 preferred_reg = loop_reg(i,reg,preferred_reg);
333 // Try to allocate the preferred register
334 if(cur->regmap[preferred_reg]==-1) {
335 cur->regmap[preferred_reg]=reg;
336 cur->dirty&=~(1<<preferred_reg);
337 cur->isconst&=~(1<<preferred_reg);
340 r=cur->regmap[preferred_reg];
341 if(r<64&&((cur->u>>r)&1)) {
342 cur->regmap[preferred_reg]=reg;
343 cur->dirty&=~(1<<preferred_reg);
344 cur->isconst&=~(1<<preferred_reg);
347 if(r>=64&&((cur->uu>>(r&63))&1)) {
348 cur->regmap[preferred_reg]=reg;
349 cur->dirty&=~(1<<preferred_reg);
350 cur->isconst&=~(1<<preferred_reg);
354 // Clear any unneeded registers
355 // We try to keep the mapping consistent, if possible, because it
356 // makes branches easier (especially loops). So we try to allocate
357 // first (see above) before removing old mappings. If this is not
358 // possible then go ahead and clear out the registers that are no
360 for(hr=0;hr<HOST_REGS;hr++)
365 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
369 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
373 // Try to allocate any available register, but prefer
374 // registers that have not been used recently.
376 for(hr=0;hr<HOST_REGS;hr++) {
377 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
378 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
380 cur->dirty&=~(1<<hr);
381 cur->isconst&=~(1<<hr);
387 // Try to allocate any available register
388 for(hr=0;hr<HOST_REGS;hr++) {
389 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
391 cur->dirty&=~(1<<hr);
392 cur->isconst&=~(1<<hr);
397 // Ok, now we have to evict someone
398 // Pick a register we hopefully won't need soon
399 u_char hsn[MAXREG+1];
400 memset(hsn,10,sizeof(hsn));
402 lsn(hsn,i,&preferred_reg);
403 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
404 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
406 // Don't evict the cycle count at entry points, otherwise the entry
407 // stub will have to write it.
408 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
409 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
412 // Alloc preferred register if available
413 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
414 for(hr=0;hr<HOST_REGS;hr++) {
415 // Evict both parts of a 64-bit register
416 if((cur->regmap[hr]&63)==r) {
418 cur->dirty&=~(1<<hr);
419 cur->isconst&=~(1<<hr);
422 cur->regmap[preferred_reg]=reg;
425 for(r=1;r<=MAXREG;r++)
427 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
428 for(hr=0;hr<HOST_REGS;hr++) {
429 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
430 if(cur->regmap[hr]==r+64) {
432 cur->dirty&=~(1<<hr);
433 cur->isconst&=~(1<<hr);
438 for(hr=0;hr<HOST_REGS;hr++) {
439 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
440 if(cur->regmap[hr]==r) {
442 cur->dirty&=~(1<<hr);
443 cur->isconst&=~(1<<hr);
454 for(r=1;r<=MAXREG;r++)
457 for(hr=0;hr<HOST_REGS;hr++) {
458 if(cur->regmap[hr]==r+64) {
460 cur->dirty&=~(1<<hr);
461 cur->isconst&=~(1<<hr);
465 for(hr=0;hr<HOST_REGS;hr++) {
466 if(cur->regmap[hr]==r) {
468 cur->dirty&=~(1<<hr);
469 cur->isconst&=~(1<<hr);
476 SysPrintf("This shouldn't happen (alloc_reg)");exit(1);
479 void alloc_reg64(struct regstat *cur,int i,signed char reg)
481 int preferred_reg = 8+(reg&1);
484 // allocate the lower 32 bits
485 alloc_reg(cur,i,reg);
487 // Don't allocate unused registers
488 if((cur->uu>>reg)&1) return;
490 // see if the upper half is already allocated
491 for(hr=0;hr<HOST_REGS;hr++)
493 if(cur->regmap[hr]==reg+64) return;
496 // Keep the same mapping if the register was already allocated in a loop
497 preferred_reg = loop_reg(i,reg,preferred_reg);
499 // Try to allocate the preferred register
500 if(cur->regmap[preferred_reg]==-1) {
501 cur->regmap[preferred_reg]=reg|64;
502 cur->dirty&=~(1<<preferred_reg);
503 cur->isconst&=~(1<<preferred_reg);
506 r=cur->regmap[preferred_reg];
507 if(r<64&&((cur->u>>r)&1)) {
508 cur->regmap[preferred_reg]=reg|64;
509 cur->dirty&=~(1<<preferred_reg);
510 cur->isconst&=~(1<<preferred_reg);
513 if(r>=64&&((cur->uu>>(r&63))&1)) {
514 cur->regmap[preferred_reg]=reg|64;
515 cur->dirty&=~(1<<preferred_reg);
516 cur->isconst&=~(1<<preferred_reg);
520 // Clear any unneeded registers
521 // We try to keep the mapping consistent, if possible, because it
522 // makes branches easier (especially loops). So we try to allocate
523 // first (see above) before removing old mappings. If this is not
524 // possible then go ahead and clear out the registers that are no
526 for(hr=HOST_REGS-1;hr>=0;hr--)
531 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
535 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
539 // Try to allocate any available register, but prefer
540 // registers that have not been used recently.
542 for(hr=0;hr<HOST_REGS;hr++) {
543 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
544 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
545 cur->regmap[hr]=reg|64;
546 cur->dirty&=~(1<<hr);
547 cur->isconst&=~(1<<hr);
553 // Try to allocate any available register
554 for(hr=0;hr<HOST_REGS;hr++) {
555 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
556 cur->regmap[hr]=reg|64;
557 cur->dirty&=~(1<<hr);
558 cur->isconst&=~(1<<hr);
563 // Ok, now we have to evict someone
564 // Pick a register we hopefully won't need soon
565 u_char hsn[MAXREG+1];
566 memset(hsn,10,sizeof(hsn));
568 lsn(hsn,i,&preferred_reg);
569 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
570 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
572 // Don't evict the cycle count at entry points, otherwise the entry
573 // stub will have to write it.
574 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
575 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
578 // Alloc preferred register if available
579 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
580 for(hr=0;hr<HOST_REGS;hr++) {
581 // Evict both parts of a 64-bit register
582 if((cur->regmap[hr]&63)==r) {
584 cur->dirty&=~(1<<hr);
585 cur->isconst&=~(1<<hr);
588 cur->regmap[preferred_reg]=reg|64;
591 for(r=1;r<=MAXREG;r++)
593 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
594 for(hr=0;hr<HOST_REGS;hr++) {
595 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
596 if(cur->regmap[hr]==r+64) {
597 cur->regmap[hr]=reg|64;
598 cur->dirty&=~(1<<hr);
599 cur->isconst&=~(1<<hr);
604 for(hr=0;hr<HOST_REGS;hr++) {
605 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
606 if(cur->regmap[hr]==r) {
607 cur->regmap[hr]=reg|64;
608 cur->dirty&=~(1<<hr);
609 cur->isconst&=~(1<<hr);
620 for(r=1;r<=MAXREG;r++)
623 for(hr=0;hr<HOST_REGS;hr++) {
624 if(cur->regmap[hr]==r+64) {
625 cur->regmap[hr]=reg|64;
626 cur->dirty&=~(1<<hr);
627 cur->isconst&=~(1<<hr);
631 for(hr=0;hr<HOST_REGS;hr++) {
632 if(cur->regmap[hr]==r) {
633 cur->regmap[hr]=reg|64;
634 cur->dirty&=~(1<<hr);
635 cur->isconst&=~(1<<hr);
642 SysPrintf("This shouldn't happen");exit(1);
645 // Allocate a temporary register. This is done without regard to
646 // dirty status or whether the register we request is on the unneeded list
647 // Note: This will only allocate one register, even if called multiple times
648 void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
651 int preferred_reg = -1;
653 // see if it's already allocated
654 for(hr=0;hr<HOST_REGS;hr++)
656 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
659 // Try to allocate any available register
660 for(hr=HOST_REGS-1;hr>=0;hr--) {
661 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
663 cur->dirty&=~(1<<hr);
664 cur->isconst&=~(1<<hr);
669 // Find an unneeded register
670 for(hr=HOST_REGS-1;hr>=0;hr--)
676 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
678 cur->dirty&=~(1<<hr);
679 cur->isconst&=~(1<<hr);
686 if((cur->uu>>(r&63))&1) {
687 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
689 cur->dirty&=~(1<<hr);
690 cur->isconst&=~(1<<hr);
698 // Ok, now we have to evict someone
699 // Pick a register we hopefully won't need soon
700 // TODO: we might want to follow unconditional jumps here
701 // TODO: get rid of dupe code and make this into a function
702 u_char hsn[MAXREG+1];
703 memset(hsn,10,sizeof(hsn));
705 lsn(hsn,i,&preferred_reg);
706 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
708 // Don't evict the cycle count at entry points, otherwise the entry
709 // stub will have to write it.
710 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
711 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
714 for(r=1;r<=MAXREG;r++)
716 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
717 for(hr=0;hr<HOST_REGS;hr++) {
718 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
719 if(cur->regmap[hr]==r+64) {
721 cur->dirty&=~(1<<hr);
722 cur->isconst&=~(1<<hr);
727 for(hr=0;hr<HOST_REGS;hr++) {
728 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
729 if(cur->regmap[hr]==r) {
731 cur->dirty&=~(1<<hr);
732 cur->isconst&=~(1<<hr);
743 for(r=1;r<=MAXREG;r++)
746 for(hr=0;hr<HOST_REGS;hr++) {
747 if(cur->regmap[hr]==r+64) {
749 cur->dirty&=~(1<<hr);
750 cur->isconst&=~(1<<hr);
754 for(hr=0;hr<HOST_REGS;hr++) {
755 if(cur->regmap[hr]==r) {
757 cur->dirty&=~(1<<hr);
758 cur->isconst&=~(1<<hr);
765 SysPrintf("This shouldn't happen");exit(1);
767 // Allocate a specific ARM register.
768 void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
773 // see if it's already allocated (and dealloc it)
774 for(n=0;n<HOST_REGS;n++)
776 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {
777 dirty=(cur->dirty>>n)&1;
783 cur->dirty&=~(1<<hr);
784 cur->dirty|=dirty<<hr;
785 cur->isconst&=~(1<<hr);
788 // Alloc cycle count into dedicated register
789 alloc_cc(struct regstat *cur,int i)
791 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
799 char regname[16][4] = {
817 void output_byte(u_char byte)
821 void output_modrm(u_char mod,u_char rm,u_char ext)
826 u_char byte=(mod<<6)|(ext<<3)|rm;
829 void output_sib(u_char scale,u_char index,u_char base)
834 u_char byte=(scale<<6)|(index<<3)|base;
837 void output_w32(u_int word)
839 *((u_int *)out)=word;
842 u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
847 return((rn<<16)|(rd<<12)|rm);
849 u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
854 assert((shift&1)==0);
855 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
857 u_int genimm(u_int imm,u_int *encoded)
865 *encoded=((i&30)<<7)|imm;
868 imm=(imm>>2)|(imm<<30);i-=2;
872 void genimm_checked(u_int imm,u_int *encoded)
874 u_int ret=genimm(imm,encoded);
877 u_int genjmp(u_int addr)
879 int offset=addr-(int)out-8;
880 if(offset<-33554432||offset>=33554432) {
882 SysPrintf("genjmp: out of range: %08x\n", offset);
887 return ((u_int)offset>>2)&0xffffff;
890 void emit_mov(int rs,int rt)
892 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
893 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
896 void emit_movs(int rs,int rt)
898 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
899 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
902 void emit_add(int rs1,int rs2,int rt)
904 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
905 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
908 void emit_adds(int rs1,int rs2,int rt)
910 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
911 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
914 void emit_adcs(int rs1,int rs2,int rt)
916 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
917 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
920 void emit_sbc(int rs1,int rs2,int rt)
922 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
923 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
926 void emit_sbcs(int rs1,int rs2,int rt)
928 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
929 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
932 void emit_neg(int rs, int rt)
934 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
935 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
938 void emit_negs(int rs, int rt)
940 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
941 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
944 void emit_sub(int rs1,int rs2,int rt)
946 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
947 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
950 void emit_subs(int rs1,int rs2,int rt)
952 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
953 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
956 void emit_zeroreg(int rt)
958 assem_debug("mov %s,#0\n",regname[rt]);
959 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
962 void emit_loadlp(u_int imm,u_int rt)
964 add_literal((int)out,imm);
965 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
966 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
968 void emit_movw(u_int imm,u_int rt)
971 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
972 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
974 void emit_movt(u_int imm,u_int rt)
976 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
977 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
979 void emit_movimm(u_int imm,u_int rt)
982 if(genimm(imm,&armval)) {
983 assem_debug("mov %s,#%d\n",regname[rt],imm);
984 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
985 }else if(genimm(~imm,&armval)) {
986 assem_debug("mvn %s,#%d\n",regname[rt],imm);
987 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
988 }else if(imm<65536) {
990 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
991 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
992 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
993 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1001 emit_movw(imm&0x0000FFFF,rt);
1002 emit_movt(imm&0xFFFF0000,rt);
1006 void emit_pcreladdr(u_int rt)
1008 assem_debug("add %s,pc,#?\n",regname[rt]);
1009 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
1012 void emit_loadreg(int r, int hr)
1015 SysPrintf("64bit load in 32bit mode!\n");
1022 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1023 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1024 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1025 if(r==CCREG) addr=(int)&cycle_count;
1026 if(r==CSREG) addr=(int)&Status;
1027 if(r==FSREG) addr=(int)&FCR31;
1028 if(r==INVCP) addr=(int)&invc_ptr;
1029 u_int offset = addr-(u_int)&dynarec_local;
1030 assert(offset<4096);
1031 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
1032 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
1035 void emit_storereg(int r, int hr)
1038 SysPrintf("64bit store in 32bit mode!\n");
1042 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1043 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1044 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1045 if(r==CCREG) addr=(int)&cycle_count;
1046 if(r==FSREG) addr=(int)&FCR31;
1047 u_int offset = addr-(u_int)&dynarec_local;
1048 assert(offset<4096);
1049 assem_debug("str %s,fp+%d\n",regname[hr],offset);
1050 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
1053 void emit_test(int rs, int rt)
1055 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
1056 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
1059 void emit_testimm(int rs,int imm)
1062 assem_debug("tst %s,#%d\n",regname[rs],imm);
1063 genimm_checked(imm,&armval);
1064 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
1067 void emit_testeqimm(int rs,int imm)
1070 assem_debug("tsteq %s,$%d\n",regname[rs],imm);
1071 genimm_checked(imm,&armval);
1072 output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
1075 void emit_not(int rs,int rt)
1077 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
1078 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
1081 void emit_mvnmi(int rs,int rt)
1083 assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
1084 output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
1087 void emit_and(u_int rs1,u_int rs2,u_int rt)
1089 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1090 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
1093 void emit_or(u_int rs1,u_int rs2,u_int rt)
1095 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1096 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
1098 void emit_or_and_set_flags(int rs1,int rs2,int rt)
1100 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1101 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
1104 void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
1109 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs],imm);
1110 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|(imm<<7));
1113 void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
1118 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm);
1119 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
1122 void emit_xor(u_int rs1,u_int rs2,u_int rt)
1124 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1125 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
1128 void emit_addimm(u_int rs,int imm,u_int rt)
1134 if(genimm(imm,&armval)) {
1135 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1136 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1137 }else if(genimm(-imm,&armval)) {
1138 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],-imm);
1139 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1141 }else if(rt!=rs&&(u_int)imm<65536) {
1142 emit_movw(imm&0x0000ffff,rt);
1144 }else if(rt!=rs&&(u_int)-imm<65536) {
1145 emit_movw(-imm&0x0000ffff,rt);
1148 }else if((u_int)-imm<65536) {
1149 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1150 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1151 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1152 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1155 int shift = (ffs(imm) - 1) & ~1;
1156 int imm8 = imm & (0xff << shift);
1157 genimm_checked(imm8,&armval);
1158 assem_debug("add %s,%s,#0x%x\n",regname[rt],regname[rs],imm8);
1159 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1166 else if(rs!=rt) emit_mov(rs,rt);
1169 void emit_addimm_and_set_flags(int imm,int rt)
1171 assert(imm>-65536&&imm<65536);
1173 if(genimm(imm,&armval)) {
1174 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1175 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1176 }else if(genimm(-imm,&armval)) {
1177 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1178 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1180 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1181 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1182 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1183 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1185 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1186 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1187 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1188 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1191 void emit_addimm_no_flags(u_int imm,u_int rt)
1193 emit_addimm(rt,imm,rt);
1196 void emit_addnop(u_int r)
1199 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1200 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1203 void emit_adcimm(u_int rs,int imm,u_int rt)
1206 genimm_checked(imm,&armval);
1207 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1208 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1210 /*void emit_sbcimm(int imm,u_int rt)
1213 genimm_checked(imm,&armval);
1214 assem_debug("sbc %s,%s,#%d\n",regname[rt],regname[rt],imm);
1215 output_w32(0xe2c00000|rd_rn_rm(rt,rt,0)|armval);
1217 void emit_sbbimm(int imm,u_int rt)
1219 assem_debug("sbb $%d,%%%s\n",imm,regname[rt]);
1221 if(imm<128&&imm>=-128) {
1223 output_modrm(3,rt,3);
1229 output_modrm(3,rt,3);
1233 void emit_rscimm(int rs,int imm,u_int rt)
1237 genimm_checked(imm,&armval);
1238 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1239 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1242 void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1244 // TODO: if(genimm(imm,&armval)) ...
1246 emit_movimm(imm,HOST_TEMPREG);
1247 emit_adds(HOST_TEMPREG,rsl,rtl);
1248 emit_adcimm(rsh,0,rth);
1251 void emit_sbb(int rs1,int rs2)
1253 assem_debug("sbb %%%s,%%%s\n",regname[rs2],regname[rs1]);
1255 output_modrm(3,rs1,rs2);
1258 void emit_andimm(int rs,int imm,int rt)
1263 }else if(genimm(imm,&armval)) {
1264 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1265 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1266 }else if(genimm(~imm,&armval)) {
1267 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1268 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1269 }else if(imm==65535) {
1271 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1272 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1273 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1274 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1276 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1277 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1280 assert(imm>0&&imm<65535);
1282 assem_debug("mov r14,#%d\n",imm&0xFF00);
1283 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1284 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1285 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1287 emit_movw(imm,HOST_TEMPREG);
1289 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1290 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1294 void emit_orimm(int rs,int imm,int rt)
1298 if(rs!=rt) emit_mov(rs,rt);
1299 }else if(genimm(imm,&armval)) {
1300 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1301 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1303 assert(imm>0&&imm<65536);
1304 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1305 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1306 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1307 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1311 void emit_xorimm(int rs,int imm,int rt)
1315 if(rs!=rt) emit_mov(rs,rt);
1316 }else if(genimm(imm,&armval)) {
1317 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1318 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1320 assert(imm>0&&imm<65536);
1321 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1322 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1323 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1324 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1328 void emit_shlimm(int rs,u_int imm,int rt)
1333 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1334 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1337 void emit_lsls_imm(int rs,int imm,int rt)
1341 assem_debug("lsls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1342 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1345 void emit_lslpls_imm(int rs,int imm,int rt)
1349 assem_debug("lslpls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1350 output_w32(0x51b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1353 void emit_shrimm(int rs,u_int imm,int rt)
1357 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1358 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1361 void emit_sarimm(int rs,u_int imm,int rt)
1365 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1366 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1369 void emit_rorimm(int rs,u_int imm,int rt)
1373 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1374 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1377 void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1379 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1383 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1384 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1385 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1386 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1389 void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1391 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1395 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1396 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1397 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1398 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1401 void emit_signextend16(int rs,int rt)
1404 emit_shlimm(rs,16,rt);
1405 emit_sarimm(rt,16,rt);
1407 assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
1408 output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
1412 void emit_signextend8(int rs,int rt)
1415 emit_shlimm(rs,24,rt);
1416 emit_sarimm(rt,24,rt);
1418 assem_debug("sxtb %s,%s\n",regname[rt],regname[rs]);
1419 output_w32(0xe6af0070|rd_rn_rm(rt,0,rs));
1423 void emit_shl(u_int rs,u_int shift,u_int rt)
1429 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1430 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1432 void emit_shr(u_int rs,u_int shift,u_int rt)
1437 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1438 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1440 void emit_sar(u_int rs,u_int shift,u_int rt)
1445 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1446 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1448 void emit_shlcl(int r)
1450 assem_debug("shl %%%s,%%cl\n",regname[r]);
1453 void emit_shrcl(int r)
1455 assem_debug("shr %%%s,%%cl\n",regname[r]);
1458 void emit_sarcl(int r)
1460 assem_debug("sar %%%s,%%cl\n",regname[r]);
1464 void emit_shldcl(int r1,int r2)
1466 assem_debug("shld %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1469 void emit_shrdcl(int r1,int r2)
1471 assem_debug("shrd %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1474 void emit_orrshl(u_int rs,u_int shift,u_int rt)
1479 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1480 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1482 void emit_orrshr(u_int rs,u_int shift,u_int rt)
1487 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1488 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1491 void emit_cmpimm(int rs,int imm)
1494 if(genimm(imm,&armval)) {
1495 assem_debug("cmp %s,#%d\n",regname[rs],imm);
1496 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1497 }else if(genimm(-imm,&armval)) {
1498 assem_debug("cmn %s,#%d\n",regname[rs],imm);
1499 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1502 emit_movimm(imm,HOST_TEMPREG);
1503 assem_debug("cmp %s,r14\n",regname[rs]);
1504 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1507 emit_movimm(-imm,HOST_TEMPREG);
1508 assem_debug("cmn %s,r14\n",regname[rs]);
1509 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1513 void emit_cmovne(u_int *addr,int rt)
1515 assem_debug("cmovne %x,%%%s",(int)addr,regname[rt]);
1518 void emit_cmovl(u_int *addr,int rt)
1520 assem_debug("cmovl %x,%%%s",(int)addr,regname[rt]);
1523 void emit_cmovs(u_int *addr,int rt)
1525 assem_debug("cmovs %x,%%%s",(int)addr,regname[rt]);
1528 void emit_cmovne_imm(int imm,int rt)
1530 assem_debug("movne %s,#%d\n",regname[rt],imm);
1532 genimm_checked(imm,&armval);
1533 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1535 void emit_cmovl_imm(int imm,int rt)
1537 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1539 genimm_checked(imm,&armval);
1540 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1542 void emit_cmovb_imm(int imm,int rt)
1544 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1546 genimm_checked(imm,&armval);
1547 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1549 void emit_cmovs_imm(int imm,int rt)
1551 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1553 genimm_checked(imm,&armval);
1554 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1556 void emit_cmove_reg(int rs,int rt)
1558 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1559 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1561 void emit_cmovne_reg(int rs,int rt)
1563 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1564 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1566 void emit_cmovl_reg(int rs,int rt)
1568 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1569 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1571 void emit_cmovs_reg(int rs,int rt)
1573 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1574 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1577 void emit_slti32(int rs,int imm,int rt)
1579 if(rs!=rt) emit_zeroreg(rt);
1580 emit_cmpimm(rs,imm);
1581 if(rs==rt) emit_movimm(0,rt);
1582 emit_cmovl_imm(1,rt);
1584 void emit_sltiu32(int rs,int imm,int rt)
1586 if(rs!=rt) emit_zeroreg(rt);
1587 emit_cmpimm(rs,imm);
1588 if(rs==rt) emit_movimm(0,rt);
1589 emit_cmovb_imm(1,rt);
1591 void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1594 emit_slti32(rsl,imm,rt);
1598 emit_cmovne_imm(0,rt);
1599 emit_cmovs_imm(1,rt);
1603 emit_cmpimm(rsh,-1);
1604 emit_cmovne_imm(0,rt);
1605 emit_cmovl_imm(1,rt);
1608 void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1611 emit_sltiu32(rsl,imm,rt);
1615 emit_cmovne_imm(0,rt);
1619 emit_cmpimm(rsh,-1);
1620 emit_cmovne_imm(1,rt);
1624 void emit_cmp(int rs,int rt)
1626 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1627 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1629 void emit_set_gz32(int rs, int rt)
1631 //assem_debug("set_gz32\n");
1634 emit_cmovl_imm(0,rt);
1636 void emit_set_nz32(int rs, int rt)
1638 //assem_debug("set_nz32\n");
1639 if(rs!=rt) emit_movs(rs,rt);
1640 else emit_test(rs,rs);
1641 emit_cmovne_imm(1,rt);
1643 void emit_set_gz64_32(int rsh, int rsl, int rt)
1645 //assem_debug("set_gz64\n");
1646 emit_set_gz32(rsl,rt);
1648 emit_cmovne_imm(1,rt);
1649 emit_cmovs_imm(0,rt);
1651 void emit_set_nz64_32(int rsh, int rsl, int rt)
1653 //assem_debug("set_nz64\n");
1654 emit_or_and_set_flags(rsh,rsl,rt);
1655 emit_cmovne_imm(1,rt);
1657 void emit_set_if_less32(int rs1, int rs2, int rt)
1659 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1660 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1662 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1663 emit_cmovl_imm(1,rt);
1665 void emit_set_if_carry32(int rs1, int rs2, int rt)
1667 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1668 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1670 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1671 emit_cmovb_imm(1,rt);
1673 void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1675 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1680 emit_sbcs(u1,u2,HOST_TEMPREG);
1681 emit_cmovl_imm(1,rt);
1683 void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1685 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1690 emit_sbcs(u1,u2,HOST_TEMPREG);
1691 emit_cmovb_imm(1,rt);
1694 void emit_call(int a)
1696 assem_debug("bl %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1697 u_int offset=genjmp(a);
1698 output_w32(0xeb000000|offset);
1700 void emit_jmp(int a)
1702 assem_debug("b %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1703 u_int offset=genjmp(a);
1704 output_w32(0xea000000|offset);
1706 void emit_jne(int a)
1708 assem_debug("bne %x\n",a);
1709 u_int offset=genjmp(a);
1710 output_w32(0x1a000000|offset);
1712 void emit_jeq(int a)
1714 assem_debug("beq %x\n",a);
1715 u_int offset=genjmp(a);
1716 output_w32(0x0a000000|offset);
1720 assem_debug("bmi %x\n",a);
1721 u_int offset=genjmp(a);
1722 output_w32(0x4a000000|offset);
1724 void emit_jns(int a)
1726 assem_debug("bpl %x\n",a);
1727 u_int offset=genjmp(a);
1728 output_w32(0x5a000000|offset);
1732 assem_debug("blt %x\n",a);
1733 u_int offset=genjmp(a);
1734 output_w32(0xba000000|offset);
1736 void emit_jge(int a)
1738 assem_debug("bge %x\n",a);
1739 u_int offset=genjmp(a);
1740 output_w32(0xaa000000|offset);
1742 void emit_jno(int a)
1744 assem_debug("bvc %x\n",a);
1745 u_int offset=genjmp(a);
1746 output_w32(0x7a000000|offset);
1750 assem_debug("bcs %x\n",a);
1751 u_int offset=genjmp(a);
1752 output_w32(0x2a000000|offset);
1754 void emit_jcc(int a)
1756 assem_debug("bcc %x\n",a);
1757 u_int offset=genjmp(a);
1758 output_w32(0x3a000000|offset);
1761 void emit_pushimm(int imm)
1763 assem_debug("push $%x\n",imm);
1768 assem_debug("pusha\n");
1773 assem_debug("popa\n");
1776 void emit_pushreg(u_int r)
1778 assem_debug("push %%%s\n",regname[r]);
1781 void emit_popreg(u_int r)
1783 assem_debug("pop %%%s\n",regname[r]);
1786 void emit_callreg(u_int r)
1789 assem_debug("blx %s\n",regname[r]);
1790 output_w32(0xe12fff30|r);
1792 void emit_jmpreg(u_int r)
1794 assem_debug("mov pc,%s\n",regname[r]);
1795 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1798 void emit_readword_indexed(int offset, int rs, int rt)
1800 assert(offset>-4096&&offset<4096);
1801 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1803 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1805 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1808 void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1810 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1811 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1813 void emit_ldrcc_dualindexed(int rs1, int rs2, int rt)
1815 assem_debug("ldrcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1816 output_w32(0x37900000|rd_rn_rm(rt,rs1,rs2));
1818 void emit_ldrccb_dualindexed(int rs1, int rs2, int rt)
1820 assem_debug("ldrccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1821 output_w32(0x37d00000|rd_rn_rm(rt,rs1,rs2));
1823 void emit_ldrccsb_dualindexed(int rs1, int rs2, int rt)
1825 assem_debug("ldrccsb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1826 output_w32(0x319000d0|rd_rn_rm(rt,rs1,rs2));
1828 void emit_ldrcch_dualindexed(int rs1, int rs2, int rt)
1830 assem_debug("ldrcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1831 output_w32(0x319000b0|rd_rn_rm(rt,rs1,rs2));
1833 void emit_ldrccsh_dualindexed(int rs1, int rs2, int rt)
1835 assem_debug("ldrccsh %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1836 output_w32(0x319000f0|rd_rn_rm(rt,rs1,rs2));
1838 void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1840 if(map<0) emit_readword_indexed(addr, rs, rt);
1843 emit_readword_dualindexedx4(rs, map, rt);
1846 void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1849 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1850 emit_readword_indexed(addr+4, rs, rl);
1853 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1854 emit_addimm(map,1,map);
1855 emit_readword_indexed_tlb(addr, rs, map, rl);
1858 void emit_movsbl_indexed(int offset, int rs, int rt)
1860 assert(offset>-256&&offset<256);
1861 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1863 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1865 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1868 void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1870 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1873 emit_shlimm(map,2,map);
1874 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1875 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1877 assert(addr>-256&&addr<256);
1878 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1879 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1880 emit_movsbl_indexed(addr, rt, rt);
1884 void emit_movswl_indexed(int offset, int rs, int rt)
1886 assert(offset>-256&&offset<256);
1887 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1889 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1891 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1894 void emit_movzbl_indexed(int offset, int rs, int rt)
1896 assert(offset>-4096&&offset<4096);
1897 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1899 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1901 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1904 void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1906 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1907 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1909 void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1911 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1914 emit_movzbl_dualindexedx4(rs, map, rt);
1916 emit_addimm(rs,addr,rt);
1917 emit_movzbl_dualindexedx4(rt, map, rt);
1921 void emit_movzwl_indexed(int offset, int rs, int rt)
1923 assert(offset>-256&&offset<256);
1924 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1926 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1928 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1931 static void emit_ldrd(int offset, int rs, int rt)
1933 assert(offset>-256&&offset<256);
1934 assem_debug("ldrd %s,%s+%d\n",regname[rt],regname[rs],offset);
1936 output_w32(0xe1c000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1938 output_w32(0xe14000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1941 void emit_readword(int addr, int rt)
1943 u_int offset = addr-(u_int)&dynarec_local;
1944 assert(offset<4096);
1945 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1946 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1948 void emit_movsbl(int addr, int rt)
1950 u_int offset = addr-(u_int)&dynarec_local;
1952 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1953 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1955 void emit_movswl(int addr, int rt)
1957 u_int offset = addr-(u_int)&dynarec_local;
1959 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1960 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1962 void emit_movzbl(int addr, int rt)
1964 u_int offset = addr-(u_int)&dynarec_local;
1965 assert(offset<4096);
1966 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1967 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1969 void emit_movzwl(int addr, int rt)
1971 u_int offset = addr-(u_int)&dynarec_local;
1973 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1974 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1976 void emit_movzwl_reg(int rs, int rt)
1978 assem_debug("movzwl %%%s,%%%s\n",regname[rs]+1,regname[rt]);
1982 void emit_xchg(int rs, int rt)
1984 assem_debug("xchg %%%s,%%%s\n",regname[rs],regname[rt]);
1987 void emit_writeword_indexed(int rt, int offset, int rs)
1989 assert(offset>-4096&&offset<4096);
1990 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
1992 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
1994 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
1997 void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
1999 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
2000 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
2002 void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
2004 if(map<0) emit_writeword_indexed(rt, addr, rs);
2007 emit_writeword_dualindexedx4(rt, rs, map);
2010 void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
2013 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
2014 emit_writeword_indexed(rl, addr+4, rs);
2017 if(temp!=rs) emit_addimm(map,1,temp);
2018 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
2019 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
2021 emit_addimm(rs,4,rs);
2022 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
2026 void emit_writehword_indexed(int rt, int offset, int rs)
2028 assert(offset>-256&&offset<256);
2029 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
2031 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
2033 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
2036 void emit_writebyte_indexed(int rt, int offset, int rs)
2038 assert(offset>-4096&&offset<4096);
2039 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
2041 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
2043 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
2046 void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
2048 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
2049 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
2051 void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
2053 if(map<0) emit_writebyte_indexed(rt, addr, rs);
2056 emit_writebyte_dualindexedx4(rt, rs, map);
2058 emit_addimm(rs,addr,temp);
2059 emit_writebyte_dualindexedx4(rt, temp, map);
2063 void emit_strcc_dualindexed(int rs1, int rs2, int rt)
2065 assem_debug("strcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2066 output_w32(0x37800000|rd_rn_rm(rt,rs1,rs2));
2068 void emit_strccb_dualindexed(int rs1, int rs2, int rt)
2070 assem_debug("strccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2071 output_w32(0x37c00000|rd_rn_rm(rt,rs1,rs2));
2073 void emit_strcch_dualindexed(int rs1, int rs2, int rt)
2075 assem_debug("strcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2076 output_w32(0x318000b0|rd_rn_rm(rt,rs1,rs2));
2078 void emit_writeword(int rt, int addr)
2080 u_int offset = addr-(u_int)&dynarec_local;
2081 assert(offset<4096);
2082 assem_debug("str %s,fp+%d\n",regname[rt],offset);
2083 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
2085 void emit_writehword(int rt, int addr)
2087 u_int offset = addr-(u_int)&dynarec_local;
2089 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
2090 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
2092 void emit_writebyte(int rt, int addr)
2094 u_int offset = addr-(u_int)&dynarec_local;
2095 assert(offset<4096);
2096 assem_debug("strb %s,fp+%d\n",regname[rt],offset);
2097 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
2099 void emit_writeword_imm(int imm, int addr)
2101 assem_debug("movl $%x,%x\n",imm,addr);
2104 void emit_writebyte_imm(int imm, int addr)
2106 assem_debug("movb $%x,%x\n",imm,addr);
2110 void emit_mul(int rs)
2112 assem_debug("mul %%%s\n",regname[rs]);
2115 void emit_imul(int rs)
2117 assem_debug("imul %%%s\n",regname[rs]);
2120 void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2122 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2127 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2129 void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2131 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2136 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2139 void emit_div(int rs)
2141 assem_debug("div %%%s\n",regname[rs]);
2144 void emit_idiv(int rs)
2146 assem_debug("idiv %%%s\n",regname[rs]);
2151 assem_debug("cdq\n");
2155 void emit_clz(int rs,int rt)
2157 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
2158 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
2161 void emit_subcs(int rs1,int rs2,int rt)
2163 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2164 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
2167 void emit_shrcc_imm(int rs,u_int imm,int rt)
2171 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2172 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2175 void emit_shrne_imm(int rs,u_int imm,int rt)
2179 assem_debug("lsrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2180 output_w32(0x11a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2183 void emit_negmi(int rs, int rt)
2185 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
2186 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2189 void emit_negsmi(int rs, int rt)
2191 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2192 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2195 void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2197 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2198 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2201 void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2203 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2204 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2207 void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2209 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2210 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2213 void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2215 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2216 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2219 void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2221 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2222 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2225 void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2227 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2228 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2231 void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2233 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2234 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2237 void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2239 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2240 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2243 void emit_teq(int rs, int rt)
2245 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2246 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2249 void emit_rsbimm(int rs, int imm, int rt)
2252 genimm_checked(imm,&armval);
2253 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2254 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2257 // Load 2 immediates optimizing for small code size
2258 void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2260 emit_movimm(imm1,rt1);
2262 if(genimm(imm2-imm1,&armval)) {
2263 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2264 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2265 }else if(genimm(imm1-imm2,&armval)) {
2266 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2267 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2269 else emit_movimm(imm2,rt2);
2272 // Conditionally select one of two immediates, optimizing for small code size
2273 // This will only be called if HAVE_CMOV_IMM is defined
2274 void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2277 if(genimm(imm2-imm1,&armval)) {
2278 emit_movimm(imm1,rt);
2279 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2280 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2281 }else if(genimm(imm1-imm2,&armval)) {
2282 emit_movimm(imm1,rt);
2283 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2284 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2288 emit_movimm(imm1,rt);
2289 add_literal((int)out,imm2);
2290 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2291 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2293 emit_movw(imm1&0x0000FFFF,rt);
2294 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2295 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2296 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2298 emit_movt(imm1&0xFFFF0000,rt);
2299 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2300 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2301 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2307 // special case for checking invalid_code
2308 void emit_cmpmem_indexedsr12_imm(int addr,int r,int imm)
2313 // special case for checking invalid_code
2314 void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2316 assert(imm<128&&imm>=0);
2318 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2319 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2320 emit_cmpimm(HOST_TEMPREG,imm);
2323 // special case for tlb mapping
2324 void emit_addsr12(int rs1,int rs2,int rt)
2326 assem_debug("add %s,%s,%s lsr #12\n",regname[rt],regname[rs1],regname[rs2]);
2327 output_w32(0xe0800620|rd_rn_rm(rt,rs1,rs2));
2330 void emit_callne(int a)
2332 assem_debug("blne %x\n",a);
2333 u_int offset=genjmp(a);
2334 output_w32(0x1b000000|offset);
2337 // Used to preload hash table entries
2338 void emit_prefetch(void *addr)
2340 assem_debug("prefetch %x\n",(int)addr);
2343 output_modrm(0,5,1);
2344 output_w32((int)addr);
2346 void emit_prefetchreg(int r)
2348 assem_debug("pld %s\n",regname[r]);
2349 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2352 // Special case for mini_ht
2353 void emit_ldreq_indexed(int rs, u_int offset, int rt)
2355 assert(offset<4096);
2356 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2357 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2360 void emit_flds(int r,int sr)
2362 assem_debug("flds s%d,[%s]\n",sr,regname[r]);
2363 output_w32(0xed900a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2366 void emit_vldr(int r,int vr)
2368 assem_debug("vldr d%d,[%s]\n",vr,regname[r]);
2369 output_w32(0xed900b00|(vr<<12)|(r<<16));
2372 void emit_fsts(int sr,int r)
2374 assem_debug("fsts s%d,[%s]\n",sr,regname[r]);
2375 output_w32(0xed800a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2378 void emit_vstr(int vr,int r)
2380 assem_debug("vstr d%d,[%s]\n",vr,regname[r]);
2381 output_w32(0xed800b00|(vr<<12)|(r<<16));
2384 void emit_ftosizs(int s,int d)
2386 assem_debug("ftosizs s%d,s%d\n",d,s);
2387 output_w32(0xeebd0ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2390 void emit_ftosizd(int s,int d)
2392 assem_debug("ftosizd s%d,d%d\n",d,s);
2393 output_w32(0xeebd0bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2396 void emit_fsitos(int s,int d)
2398 assem_debug("fsitos s%d,s%d\n",d,s);
2399 output_w32(0xeeb80ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2402 void emit_fsitod(int s,int d)
2404 assem_debug("fsitod d%d,s%d\n",d,s);
2405 output_w32(0xeeb80bc0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2408 void emit_fcvtds(int s,int d)
2410 assem_debug("fcvtds d%d,s%d\n",d,s);
2411 output_w32(0xeeb70ac0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2414 void emit_fcvtsd(int s,int d)
2416 assem_debug("fcvtsd s%d,d%d\n",d,s);
2417 output_w32(0xeeb70bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2420 void emit_fsqrts(int s,int d)
2422 assem_debug("fsqrts d%d,s%d\n",d,s);
2423 output_w32(0xeeb10ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2426 void emit_fsqrtd(int s,int d)
2428 assem_debug("fsqrtd s%d,d%d\n",d,s);
2429 output_w32(0xeeb10bc0|((d&7)<<12)|(s&7));
2432 void emit_fabss(int s,int d)
2434 assem_debug("fabss d%d,s%d\n",d,s);
2435 output_w32(0xeeb00ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2438 void emit_fabsd(int s,int d)
2440 assem_debug("fabsd s%d,d%d\n",d,s);
2441 output_w32(0xeeb00bc0|((d&7)<<12)|(s&7));
2444 void emit_fnegs(int s,int d)
2446 assem_debug("fnegs d%d,s%d\n",d,s);
2447 output_w32(0xeeb10a40|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2450 void emit_fnegd(int s,int d)
2452 assem_debug("fnegd s%d,d%d\n",d,s);
2453 output_w32(0xeeb10b40|((d&7)<<12)|(s&7));
2456 void emit_fadds(int s1,int s2,int d)
2458 assem_debug("fadds s%d,s%d,s%d\n",d,s1,s2);
2459 output_w32(0xee300a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2462 void emit_faddd(int s1,int s2,int d)
2464 assem_debug("faddd d%d,d%d,d%d\n",d,s1,s2);
2465 output_w32(0xee300b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2468 void emit_fsubs(int s1,int s2,int d)
2470 assem_debug("fsubs s%d,s%d,s%d\n",d,s1,s2);
2471 output_w32(0xee300a40|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2474 void emit_fsubd(int s1,int s2,int d)
2476 assem_debug("fsubd d%d,d%d,d%d\n",d,s1,s2);
2477 output_w32(0xee300b40|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2480 void emit_fmuls(int s1,int s2,int d)
2482 assem_debug("fmuls s%d,s%d,s%d\n",d,s1,s2);
2483 output_w32(0xee200a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2486 void emit_fmuld(int s1,int s2,int d)
2488 assem_debug("fmuld d%d,d%d,d%d\n",d,s1,s2);
2489 output_w32(0xee200b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2492 void emit_fdivs(int s1,int s2,int d)
2494 assem_debug("fdivs s%d,s%d,s%d\n",d,s1,s2);
2495 output_w32(0xee800a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2498 void emit_fdivd(int s1,int s2,int d)
2500 assem_debug("fdivd d%d,d%d,d%d\n",d,s1,s2);
2501 output_w32(0xee800b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2504 void emit_fcmps(int x,int y)
2506 assem_debug("fcmps s14, s15\n");
2507 output_w32(0xeeb47a67);
2510 void emit_fcmpd(int x,int y)
2512 assem_debug("fcmpd d6, d7\n");
2513 output_w32(0xeeb46b47);
2518 assem_debug("fmstat\n");
2519 output_w32(0xeef1fa10);
2522 void emit_bicne_imm(int rs,int imm,int rt)
2525 genimm_checked(imm,&armval);
2526 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2527 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2530 void emit_biccs_imm(int rs,int imm,int rt)
2533 genimm_checked(imm,&armval);
2534 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2535 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2538 void emit_bicvc_imm(int rs,int imm,int rt)
2541 genimm_checked(imm,&armval);
2542 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2543 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2546 void emit_bichi_imm(int rs,int imm,int rt)
2549 genimm_checked(imm,&armval);
2550 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2551 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2554 void emit_orrvs_imm(int rs,int imm,int rt)
2557 genimm_checked(imm,&armval);
2558 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2559 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2562 void emit_orrne_imm(int rs,int imm,int rt)
2565 genimm_checked(imm,&armval);
2566 assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2567 output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
2570 void emit_andne_imm(int rs,int imm,int rt)
2573 genimm_checked(imm,&armval);
2574 assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2575 output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
2578 void emit_addpl_imm(int rs,int imm,int rt)
2581 genimm_checked(imm,&armval);
2582 assem_debug("addpl %s,%s,#%d\n",regname[rt],regname[rs],imm);
2583 output_w32(0x52800000|rd_rn_rm(rt,rs,0)|armval);
2586 void emit_jno_unlikely(int a)
2589 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2590 output_w32(0x72800000|rd_rn_rm(15,15,0));
2593 static void save_regs_all(u_int reglist)
2596 if(!reglist) return;
2597 assem_debug("stmia fp,{");
2600 assem_debug("r%d,",i);
2602 output_w32(0xe88b0000|reglist);
2604 static void restore_regs_all(u_int reglist)
2607 if(!reglist) return;
2608 assem_debug("ldmia fp,{");
2611 assem_debug("r%d,",i);
2613 output_w32(0xe89b0000|reglist);
2615 // Save registers before function call
2616 static void save_regs(u_int reglist)
2618 reglist&=CALLER_SAVE_REGS; // only save the caller-save registers, r0-r3, r12
2619 save_regs_all(reglist);
2621 // Restore registers after function call
2622 static void restore_regs(u_int reglist)
2624 reglist&=CALLER_SAVE_REGS;
2625 restore_regs_all(reglist);
2628 // Write back consts using r14 so we don't disturb the other registers
2629 void wb_consts(signed char i_regmap[],uint64_t i_is32,u_int i_dirty,int i)
2632 for(hr=0;hr<HOST_REGS;hr++) {
2633 if(hr!=EXCLUDE_REG&&i_regmap[hr]>=0&&((i_dirty>>hr)&1)) {
2634 if(((regs[i].isconst>>hr)&1)&&i_regmap[hr]>0) {
2635 if(i_regmap[hr]<64 || !((i_is32>>(i_regmap[hr]&63))&1) ) {
2636 int value=constmap[i][hr];
2638 emit_zeroreg(HOST_TEMPREG);
2641 emit_movimm(value,HOST_TEMPREG);
2643 emit_storereg(i_regmap[hr],HOST_TEMPREG);
2650 /* Stubs/epilogue */
2652 void literal_pool(int n)
2654 if(!literalcount) return;
2656 if((int)out-literals[0][0]<4096-n) return;
2660 for(i=0;i<literalcount;i++)
2662 u_int l_addr=(u_int)out;
2665 if(literals[j][1]==literals[i][1]) {
2666 //printf("dup %08x\n",literals[i][1]);
2667 l_addr=literals[j][0];
2671 ptr=(u_int *)literals[i][0];
2672 u_int offset=l_addr-(u_int)ptr-8;
2673 assert(offset<4096);
2674 assert(!(offset&3));
2676 if(l_addr==(u_int)out) {
2677 literals[i][0]=l_addr; // remember for dupes
2678 output_w32(literals[i][1]);
2684 void literal_pool_jumpover(int n)
2686 if(!literalcount) return;
2688 if((int)out-literals[0][0]<4096-n) return;
2693 set_jump_target(jaddr,(int)out);
2696 emit_extjump2(u_int addr, int target, int linker)
2698 u_char *ptr=(u_char *)addr;
2699 assert((ptr[3]&0x0e)==0xa);
2700 emit_loadlp(target,0);
2701 emit_loadlp(addr,1);
2702 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
2703 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2705 #ifdef DEBUG_CYCLE_COUNT
2706 emit_readword((int)&last_count,ECX);
2707 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2708 emit_readword((int)&next_interupt,ECX);
2709 emit_writeword(HOST_CCREG,(int)&Count);
2710 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2711 emit_writeword(ECX,(int)&last_count);
2717 emit_extjump(int addr, int target)
2719 emit_extjump2(addr, target, (int)dyna_linker);
2721 emit_extjump_ds(int addr, int target)
2723 emit_extjump2(addr, target, (int)dyna_linker_ds);
2726 // put rt_val into rt, potentially making use of rs with value rs_val
2727 static void emit_movimm_from(u_int rs_val,int rs,u_int rt_val,int rt)
2731 if(genimm(rt_val,&armval)) {
2732 assem_debug("mov %s,#%d\n",regname[rt],rt_val);
2733 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
2736 if(genimm(~rt_val,&armval)) {
2737 assem_debug("mvn %s,#%d\n",regname[rt],rt_val);
2738 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
2742 if(genimm(diff,&armval)) {
2743 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],diff);
2744 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
2746 }else if(genimm(-diff,&armval)) {
2747 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],-diff);
2748 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
2751 emit_movimm(rt_val,rt);
2754 // return 1 if above function can do it's job cheaply
2755 static int is_similar_value(u_int v1,u_int v2)
2759 if(v1==v2) return 1;
2761 for(xs=diff;xs!=0&&(xs&3)==0;xs>>=2)
2763 if(xs<0x100) return 1;
2764 for(xs=-diff;xs!=0&&(xs&3)==0;xs>>=2)
2766 if(xs<0x100) return 1;
2771 static void pass_args(int a0, int a1)
2775 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2777 else if(a0!=0&&a1==0) {
2779 if (a0>=0) emit_mov(a0,0);
2782 if(a0>=0&&a0!=0) emit_mov(a0,0);
2783 if(a1>=0&&a1!=1) emit_mov(a1,1);
2787 static void mov_loadtype_adj(int type,int rs,int rt)
2790 case LOADB_STUB: emit_signextend8(rs,rt); break;
2791 case LOADBU_STUB: emit_andimm(rs,0xff,rt); break;
2792 case LOADH_STUB: emit_signextend16(rs,rt); break;
2793 case LOADHU_STUB: emit_andimm(rs,0xffff,rt); break;
2794 case LOADW_STUB: if(rs!=rt) emit_mov(rs,rt); break;
2799 #include "pcsxmem.h"
2800 #include "pcsxmem_inline.c"
2804 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2806 set_jump_target(stubs[n][1],(int)out);
2807 int type=stubs[n][0];
2810 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2811 u_int reglist=stubs[n][7];
2812 signed char *i_regmap=i_regs->regmap;
2813 int addr=get_reg(i_regmap,AGEN1+(i&1));
2816 if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
2817 rth=get_reg(i_regmap,FTEMP|64);
2818 rt=get_reg(i_regmap,FTEMP);
2820 rth=get_reg(i_regmap,rt1[i]|64);
2821 rt=get_reg(i_regmap,rt1[i]);
2824 int r,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0;
2826 for(r=0;r<=12;r++) {
2827 if(((1<<r)&0x13ff)&&((1<<r)®list)==0) {
2831 if(rt>=0&&rt1[i]!=0)
2838 if((regs_saved||(reglist&2)==0)&&temp!=1&&rs!=1)
2840 emit_readword((int)&mem_rtab,temp);
2841 emit_shrimm(rs,12,temp2);
2842 emit_readword_dualindexedx4(temp,temp2,temp2);
2843 emit_lsls_imm(temp2,1,temp2);
2844 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2846 case LOADB_STUB: emit_ldrccsb_dualindexed(temp2,rs,rt); break;
2847 case LOADBU_STUB: emit_ldrccb_dualindexed(temp2,rs,rt); break;
2848 case LOADH_STUB: emit_ldrccsh_dualindexed(temp2,rs,rt); break;
2849 case LOADHU_STUB: emit_ldrcch_dualindexed(temp2,rs,rt); break;
2850 case LOADW_STUB: emit_ldrcc_dualindexed(temp2,rs,rt); break;
2854 restore_jump=(int)out;
2855 emit_jcc(0); // jump to reg restore
2858 emit_jcc(stubs[n][2]); // return address
2863 if(type==LOADB_STUB||type==LOADBU_STUB)
2864 handler=(int)jump_handler_read8;
2865 if(type==LOADH_STUB||type==LOADHU_STUB)
2866 handler=(int)jump_handler_read16;
2867 if(type==LOADW_STUB)
2868 handler=(int)jump_handler_read32;
2870 pass_args(rs,temp2);
2871 int cc=get_reg(i_regmap,CCREG);
2873 emit_loadreg(CCREG,2);
2874 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2876 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2877 mov_loadtype_adj(type,0,rt);
2880 set_jump_target(restore_jump,(int)out);
2881 restore_regs(reglist);
2882 emit_jmp(stubs[n][2]); // return address
2885 // return memhandler, or get directly accessable address and return 0
2886 u_int get_direct_memhandler(void *table,u_int addr,int type,u_int *addr_host)
2889 l1=((u_int *)table)[addr>>12];
2890 if((l1&(1<<31))==0) {
2897 if(type==LOADB_STUB||type==LOADBU_STUB||type==STOREB_STUB)
2898 l2=((u_int *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2899 else if(type==LOADH_STUB||type==LOADHU_STUB||type==STOREH_STUB)
2900 l2=((u_int *)l1)[0x1000/4 + (addr&0xfff)/2];
2902 l2=((u_int *)l1)[(addr&0xfff)/4];
2903 if((l2&(1<<31))==0) {
2905 *addr_host=v+(addr&0xfff);
2912 inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2914 int rs=get_reg(regmap,target);
2915 int rth=get_reg(regmap,target|64);
2916 int rt=get_reg(regmap,target);
2917 if(rs<0) rs=get_reg(regmap,-1);
2919 u_int handler,host_addr=0,is_dynamic,far_call=0;
2920 int cc=get_reg(regmap,CCREG);
2921 if(pcsx_direct_read(type,addr,CLOCK_ADJUST(adj+1),cc,target?rs:-1,rt))
2923 handler=get_direct_memhandler(mem_rtab,addr,type,&host_addr);
2928 emit_movimm_from(addr,rs,host_addr,rs);
2930 case LOADB_STUB: emit_movsbl_indexed(0,rs,rt); break;
2931 case LOADBU_STUB: emit_movzbl_indexed(0,rs,rt); break;
2932 case LOADH_STUB: emit_movswl_indexed(0,rs,rt); break;
2933 case LOADHU_STUB: emit_movzwl_indexed(0,rs,rt); break;
2934 case LOADW_STUB: emit_readword_indexed(0,rs,rt); break;
2939 is_dynamic=pcsxmem_is_handler_dynamic(addr);
2941 if(type==LOADB_STUB||type==LOADBU_STUB)
2942 handler=(int)jump_handler_read8;
2943 if(type==LOADH_STUB||type==LOADHU_STUB)
2944 handler=(int)jump_handler_read16;
2945 if(type==LOADW_STUB)
2946 handler=(int)jump_handler_read32;
2949 // call a memhandler
2950 if(rt>=0&&rt1[i]!=0)
2954 emit_movimm(addr,0);
2957 int offset=(int)handler-(int)out-8;
2958 if(offset<-33554432||offset>=33554432) {
2959 // unreachable memhandler, a plugin func perhaps
2960 emit_movimm(handler,12);
2964 emit_loadreg(CCREG,2);
2966 emit_movimm(((u_int *)mem_rtab)[addr>>12]<<1,1);
2967 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
2970 emit_readword((int)&last_count,3);
2971 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
2973 emit_writeword(2,(int)&Count);
2981 if(rt>=0&&rt1[i]!=0) {
2983 case LOADB_STUB: emit_signextend8(0,rt); break;
2984 case LOADBU_STUB: emit_andimm(0,0xff,rt); break;
2985 case LOADH_STUB: emit_signextend16(0,rt); break;
2986 case LOADHU_STUB: emit_andimm(0,0xffff,rt); break;
2987 case LOADW_STUB: if(rt!=0) emit_mov(0,rt); break;
2991 restore_regs(reglist);
2996 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
2998 set_jump_target(stubs[n][1],(int)out);
2999 int type=stubs[n][0];
3002 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3003 u_int reglist=stubs[n][7];
3004 signed char *i_regmap=i_regs->regmap;
3005 int addr=get_reg(i_regmap,AGEN1+(i&1));
3008 if(itype[i]==C1LS||itype[i]==C2LS) {
3009 rth=get_reg(i_regmap,FTEMP|64);
3010 rt=get_reg(i_regmap,r=FTEMP);
3012 rth=get_reg(i_regmap,rs2[i]|64);
3013 rt=get_reg(i_regmap,r=rs2[i]);
3017 int rtmp,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0,ra;
3018 int reglist2=reglist|(1<<rs)|(1<<rt);
3019 for(rtmp=0;rtmp<=12;rtmp++) {
3020 if(((1<<rtmp)&0x13ff)&&((1<<rtmp)®list2)==0) {
3027 for(rtmp=0;rtmp<=3;rtmp++)
3028 if(rtmp!=rs&&rtmp!=rt)
3031 if((regs_saved||(reglist2&8)==0)&&temp!=3&&rs!=3&&rt!=3)
3033 emit_readword((int)&mem_wtab,temp);
3034 emit_shrimm(rs,12,temp2);
3035 emit_readword_dualindexedx4(temp,temp2,temp2);
3036 emit_lsls_imm(temp2,1,temp2);
3038 case STOREB_STUB: emit_strccb_dualindexed(temp2,rs,rt); break;
3039 case STOREH_STUB: emit_strcch_dualindexed(temp2,rs,rt); break;
3040 case STOREW_STUB: emit_strcc_dualindexed(temp2,rs,rt); break;
3044 restore_jump=(int)out;
3045 emit_jcc(0); // jump to reg restore
3048 emit_jcc(stubs[n][2]); // return address (invcode check)
3054 case STOREB_STUB: handler=(int)jump_handler_write8; break;
3055 case STOREH_STUB: handler=(int)jump_handler_write16; break;
3056 case STOREW_STUB: handler=(int)jump_handler_write32; break;
3062 int cc=get_reg(i_regmap,CCREG);
3064 emit_loadreg(CCREG,2);
3065 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
3066 // returns new cycle_count
3068 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
3070 emit_storereg(CCREG,2);
3072 set_jump_target(restore_jump,(int)out);
3073 restore_regs(reglist);
3078 inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
3080 int rs=get_reg(regmap,-1);
3081 int rth=get_reg(regmap,target|64);
3082 int rt=get_reg(regmap,target);
3085 u_int handler,host_addr=0;
3086 handler=get_direct_memhandler(mem_wtab,addr,type,&host_addr);
3089 emit_movimm_from(addr,rs,host_addr,rs);
3091 case STOREB_STUB: emit_writebyte_indexed(rt,0,rs); break;
3092 case STOREH_STUB: emit_writehword_indexed(rt,0,rs); break;
3093 case STOREW_STUB: emit_writeword_indexed(rt,0,rs); break;
3099 // call a memhandler
3102 int cc=get_reg(regmap,CCREG);
3104 emit_loadreg(CCREG,2);
3105 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
3106 emit_movimm(handler,3);
3107 // returns new cycle_count
3108 emit_call((int)jump_handler_write_h);
3109 emit_addimm(0,-CLOCK_ADJUST(adj+1),cc<0?2:cc);
3111 emit_storereg(CCREG,2);
3112 restore_regs(reglist);
3115 do_unalignedwritestub(int n)
3117 assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
3119 set_jump_target(stubs[n][1],(int)out);
3122 struct regstat *i_regs=(struct regstat *)stubs[n][4];
3123 int addr=stubs[n][5];
3124 u_int reglist=stubs[n][7];
3125 signed char *i_regmap=i_regs->regmap;
3126 int temp2=get_reg(i_regmap,FTEMP);
3129 rt=get_reg(i_regmap,rs2[i]);
3132 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
3134 reglist&=~(1<<temp2);
3137 // don't bother with it and call write handler
3140 int cc=get_reg(i_regmap,CCREG);
3142 emit_loadreg(CCREG,2);
3143 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
3144 emit_call((int)(opcode[i]==0x2a?jump_handle_swl:jump_handle_swr));
3145 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
3147 emit_storereg(CCREG,2);
3148 restore_regs(reglist);
3149 emit_jmp(stubs[n][2]); // return address
3151 emit_andimm(addr,0xfffffffc,temp2);
3152 emit_writeword(temp2,(int)&address);
3155 emit_shrimm(addr,16,1);
3156 int cc=get_reg(i_regmap,CCREG);
3158 emit_loadreg(CCREG,2);
3160 emit_movimm((u_int)readmem,0);
3161 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
3162 emit_call((int)&indirect_jump_indexed);
3163 restore_regs(reglist);
3165 emit_readword((int)&readmem_dword,temp2);
3166 int temp=addr; //hmh
3167 emit_shlimm(addr,3,temp);
3168 emit_andimm(temp,24,temp);
3169 #ifdef BIG_ENDIAN_MIPS
3170 if (opcode[i]==0x2e) // SWR
3172 if (opcode[i]==0x2a) // SWL
3174 emit_xorimm(temp,24,temp);
3175 emit_movimm(-1,HOST_TEMPREG);
3176 if (opcode[i]==0x2a) { // SWL
3177 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
3178 emit_orrshr(rt,temp,temp2);
3180 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
3181 emit_orrshl(rt,temp,temp2);
3183 emit_readword((int)&address,addr);
3184 emit_writeword(temp2,(int)&word);
3185 //save_regs(reglist); // don't need to, no state changes
3186 emit_shrimm(addr,16,1);
3187 emit_movimm((u_int)writemem,0);
3188 //emit_call((int)&indirect_jump_indexed);
3190 emit_readword_dualindexedx4(0,1,15);
3191 emit_readword((int)&Count,HOST_TEMPREG);
3192 emit_readword((int)&next_interupt,2);
3193 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
3194 emit_writeword(2,(int)&last_count);
3195 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3197 emit_storereg(CCREG,HOST_TEMPREG);
3199 restore_regs(reglist);
3200 emit_jmp(stubs[n][2]); // return address
3204 void printregs(int edi,int esi,int ebp,int esp,int b,int d,int c,int a)
3206 printf("regs: %x %x %x %x %x %x %x (%x)\n",a,b,c,d,ebp,esi,edi,(&edi)[-1]);
3212 u_int reglist=stubs[n][3];
3213 set_jump_target(stubs[n][1],(int)out);
3215 if(stubs[n][4]!=0) emit_mov(stubs[n][4],0);
3216 emit_call((int)&invalidate_addr);
3217 restore_regs(reglist);
3218 emit_jmp(stubs[n][2]); // return address
3221 int do_dirty_stub(int i)
3223 assem_debug("do_dirty_stub %x\n",start+i*4);
3224 u_int addr=(u_int)source;
3225 // Careful about the code output here, verify_dirty needs to parse it.
3227 emit_loadlp(addr,1);
3228 emit_loadlp((int)copy,2);
3229 emit_loadlp(slen*4,3);
3231 emit_movw(addr&0x0000FFFF,1);
3232 emit_movw(((u_int)copy)&0x0000FFFF,2);
3233 emit_movt(addr&0xFFFF0000,1);
3234 emit_movt(((u_int)copy)&0xFFFF0000,2);
3235 emit_movw(slen*4,3);
3237 emit_movimm(start+i*4,0);
3238 emit_call((int)start<(int)0xC0000000?(int)&verify_code:(int)&verify_code_vm);
3241 if(entry==(int)out) entry=instr_addr[i];
3242 emit_jmp(instr_addr[i]);
3246 void do_dirty_stub_ds()
3248 // Careful about the code output here, verify_dirty needs to parse it.
3250 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
3251 emit_loadlp((int)copy,2);
3252 emit_loadlp(slen*4,3);
3254 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
3255 emit_movw(((u_int)copy)&0x0000FFFF,2);
3256 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
3257 emit_movt(((u_int)copy)&0xFFFF0000,2);
3258 emit_movw(slen*4,3);
3260 emit_movimm(start+1,0);
3261 emit_call((int)&verify_code_ds);
3267 assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
3268 set_jump_target(stubs[n][1],(int)out);
3270 // int rs=stubs[n][4];
3271 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3274 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3275 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3277 //else {printf("fp exception in delay slot\n");}
3278 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty);
3279 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3280 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3281 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3282 emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
3285 static int do_tlb_r(int a, ...) { return 0; }
3286 static int do_tlb_r_branch(int a, ...) { return 0; }
3287 static int gen_tlb_addr_r(int a, ...) { return 0; }
3288 static int do_tlb_w(int a, ...) { return 0; }
3289 static int do_tlb_w_branch(int a, ...) { return 0; }
3290 static int gen_tlb_addr_w(int a, ...) { return 0; }
3294 void shift_assemble_arm(int i,struct regstat *i_regs)
3297 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
3299 signed char s,t,shift;
3300 t=get_reg(i_regs->regmap,rt1[i]);
3301 s=get_reg(i_regs->regmap,rs1[i]);
3302 shift=get_reg(i_regs->regmap,rs2[i]);
3311 if(s!=t) emit_mov(s,t);
3315 emit_andimm(shift,31,HOST_TEMPREG);
3316 if(opcode2[i]==4) // SLLV
3318 emit_shl(s,HOST_TEMPREG,t);
3320 if(opcode2[i]==6) // SRLV
3322 emit_shr(s,HOST_TEMPREG,t);
3324 if(opcode2[i]==7) // SRAV
3326 emit_sar(s,HOST_TEMPREG,t);
3330 } else { // DSLLV/DSRLV/DSRAV
3331 signed char sh,sl,th,tl,shift;
3332 th=get_reg(i_regs->regmap,rt1[i]|64);
3333 tl=get_reg(i_regs->regmap,rt1[i]);
3334 sh=get_reg(i_regs->regmap,rs1[i]|64);
3335 sl=get_reg(i_regs->regmap,rs1[i]);
3336 shift=get_reg(i_regs->regmap,rs2[i]);
3341 if(th>=0) emit_zeroreg(th);
3346 if(sl!=tl) emit_mov(sl,tl);
3347 if(th>=0&&sh!=th) emit_mov(sh,th);
3351 // FIXME: What if shift==tl ?
3353 int temp=get_reg(i_regs->regmap,-1);
3355 if(th<0&&opcode2[i]!=0x14) {th=temp;} // DSLLV doesn't need a temporary register
3358 emit_andimm(shift,31,HOST_TEMPREG);
3359 if(opcode2[i]==0x14) // DSLLV
3361 if(th>=0) emit_shl(sh,HOST_TEMPREG,th);
3362 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3363 emit_orrshr(sl,HOST_TEMPREG,th);
3364 emit_andimm(shift,31,HOST_TEMPREG);
3365 emit_testimm(shift,32);
3366 emit_shl(sl,HOST_TEMPREG,tl);
3367 if(th>=0) emit_cmovne_reg(tl,th);
3368 emit_cmovne_imm(0,tl);
3370 if(opcode2[i]==0x16) // DSRLV
3373 emit_shr(sl,HOST_TEMPREG,tl);
3374 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3375 emit_orrshl(sh,HOST_TEMPREG,tl);
3376 emit_andimm(shift,31,HOST_TEMPREG);
3377 emit_testimm(shift,32);
3378 emit_shr(sh,HOST_TEMPREG,th);
3379 emit_cmovne_reg(th,tl);
3380 if(real_th>=0) emit_cmovne_imm(0,th);
3382 if(opcode2[i]==0x17) // DSRAV
3385 emit_shr(sl,HOST_TEMPREG,tl);
3386 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3389 emit_sarimm(th,31,temp);
3391 emit_orrshl(sh,HOST_TEMPREG,tl);
3392 emit_andimm(shift,31,HOST_TEMPREG);
3393 emit_testimm(shift,32);
3394 emit_sar(sh,HOST_TEMPREG,th);
3395 emit_cmovne_reg(th,tl);
3396 if(real_th>=0) emit_cmovne_reg(temp,th);
3404 static void speculate_mov(int rs,int rt)
3407 smrv_strong_next|=1<<rt;
3412 static void speculate_mov_weak(int rs,int rt)
3415 smrv_weak_next|=1<<rt;
3420 static void speculate_register_values(int i)
3423 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3424 // gp,sp are likely to stay the same throughout the block
3425 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3426 smrv_weak_next=~smrv_strong_next;
3427 //printf(" llr %08x\n", smrv[4]);
3429 smrv_strong=smrv_strong_next;
3430 smrv_weak=smrv_weak_next;
3433 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3434 else if((smrv_strong>>rs2[i])&1) speculate_mov(rs2[i],rt1[i]);
3435 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3436 else if((smrv_weak>>rs2[i])&1) speculate_mov_weak(rs2[i],rt1[i]);
3438 smrv_strong_next&=~(1<<rt1[i]);
3439 smrv_weak_next&=~(1<<rt1[i]);
3443 smrv_strong_next&=~(1<<rt1[i]);
3444 smrv_weak_next&=~(1<<rt1[i]);
3447 if(rt1[i]&&is_const(®s[i],rt1[i])) {
3448 int value,hr=get_reg(regs[i].regmap,rt1[i]);
3450 if(get_final_value(hr,i,&value))
3452 else smrv[rt1[i]]=constmap[i][hr];
3453 smrv_strong_next|=1<<rt1[i];
3457 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3458 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3462 if(start<0x2000&&(rt1[i]==26||(smrv[rt1[i]]>>24)==0xa0)) {
3463 // special case for BIOS
3464 smrv[rt1[i]]=0xa0000000;
3465 smrv_strong_next|=1<<rt1[i];
3472 smrv_strong_next&=~(1<<rt1[i]);
3473 smrv_weak_next&=~(1<<rt1[i]);
3477 if(opcode2[i]==0||opcode2[i]==2) { // MFC/CFC
3478 smrv_strong_next&=~(1<<rt1[i]);
3479 smrv_weak_next&=~(1<<rt1[i]);
3483 if (opcode[i]==0x32) { // LWC2
3484 smrv_strong_next&=~(1<<rt1[i]);
3485 smrv_weak_next&=~(1<<rt1[i]);
3491 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
3492 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
3504 static int get_ptr_mem_type(u_int a)
3506 if(a < 0x00200000) {
3507 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
3508 // return wrong, must use memhandler for BIOS self-test to pass
3509 // 007 does similar stuff from a00 mirror, weird stuff
3513 if(0x1f800000 <= a && a < 0x1f801000)
3515 if(0x80200000 <= a && a < 0x80800000)
3517 if(0xa0000000 <= a && a < 0xa0200000)
3522 static int emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override)
3526 if(((smrv_strong|smrv_weak)>>mr)&1) {
3527 type=get_ptr_mem_type(smrv[mr]);
3528 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
3531 // use the mirror we are running on
3532 type=get_ptr_mem_type(start);
3533 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
3536 if(type==MTYPE_8020) { // RAM 80200000+ mirror
3537 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3538 addr=*addr_reg_override=HOST_TEMPREG;
3541 else if(type==MTYPE_0000) { // RAM 0 mirror
3542 emit_orimm(addr,0x80000000,HOST_TEMPREG);
3543 addr=*addr_reg_override=HOST_TEMPREG;
3546 else if(type==MTYPE_A000) { // RAM A mirror
3547 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
3548 addr=*addr_reg_override=HOST_TEMPREG;
3551 else if(type==MTYPE_1F80) { // scratchpad
3552 if (psxH == (void *)0x1f800000) {
3553 emit_addimm(addr,-0x1f800000,HOST_TEMPREG);
3554 emit_cmpimm(HOST_TEMPREG,0x1000);
3559 // do usual RAM check, jump will go to the right handler
3566 emit_cmpimm(addr,RAM_SIZE);
3568 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3569 // Hint to branch predictor that the branch is unlikely to be taken
3571 emit_jno_unlikely(0);
3576 emit_addimm(addr,ram_offset,HOST_TEMPREG);
3577 addr=*addr_reg_override=HOST_TEMPREG;
3584 #define shift_assemble shift_assemble_arm
3586 void loadlr_assemble_arm(int i,struct regstat *i_regs)
3588 int s,th,tl,temp,temp2,addr,map=-1;
3591 int memtarget=0,c=0;
3592 int fastload_reg_override=0;
3594 th=get_reg(i_regs->regmap,rt1[i]|64);
3595 tl=get_reg(i_regs->regmap,rt1[i]);
3596 s=get_reg(i_regs->regmap,rs1[i]);
3597 temp=get_reg(i_regs->regmap,-1);
3598 temp2=get_reg(i_regs->regmap,FTEMP);
3599 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3602 for(hr=0;hr<HOST_REGS;hr++) {
3603 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3606 if(offset||s<0||c) addr=temp2;
3609 c=(i_regs->wasconst>>s)&1;
3611 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3612 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3618 map=get_reg(i_regs->regmap,ROREG);
3619 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3621 emit_shlimm(addr,3,temp);
3622 if (opcode[i]==0x22||opcode[i]==0x26) {
3623 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3625 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3627 jaddr=emit_fastpath_cmp_jump(i,temp2,&fastload_reg_override);
3630 if(ram_offset&&memtarget) {
3631 emit_addimm(temp2,ram_offset,HOST_TEMPREG);
3632 fastload_reg_override=HOST_TEMPREG;
3634 if (opcode[i]==0x22||opcode[i]==0x26) {
3635 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3637 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3644 }else if (opcode[i]==0x22||opcode[i]==0x26) {
3645 a=0xFFFFFFFC; // LWL/LWR
3647 a=0xFFFFFFF8; // LDL/LDR
3649 map=get_reg(i_regs->regmap,TLREG);
3653 if (opcode[i]==0x22||opcode[i]==0x26) {
3654 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3656 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3660 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
3663 if(fastload_reg_override) a=fastload_reg_override;
3664 //emit_readword_indexed((int)rdram-0x80000000,temp2,temp2);
3665 emit_readword_indexed_tlb(0,a,map,temp2);
3666 if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3669 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
3672 emit_andimm(temp,24,temp);
3673 #ifdef BIG_ENDIAN_MIPS
3674 if (opcode[i]==0x26) // LWR
3676 if (opcode[i]==0x22) // LWL
3678 emit_xorimm(temp,24,temp);
3679 emit_movimm(-1,HOST_TEMPREG);
3680 if (opcode[i]==0x26) {
3681 emit_shr(temp2,temp,temp2);
3682 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3684 emit_shl(temp2,temp,temp2);
3685 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3687 emit_or(temp2,tl,tl);
3689 //emit_storereg(rt1[i],tl); // DEBUG
3691 if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
3692 // FIXME: little endian, fastload_reg_override
3693 int temp2h=get_reg(i_regs->regmap,FTEMP|64);
3695 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
3696 //emit_readword_indexed((int)rdram-0x7FFFFFFC,temp2,temp2);
3697 emit_readdword_indexed_tlb(0,temp2,map,temp2h,temp2);
3698 if(jaddr) add_stub(LOADD_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3701 inline_readstub(LOADD_STUB,i,(constmap[i][s]+offset)&0xFFFFFFF8,i_regs->regmap,FTEMP,ccadj[i],reglist);
3705 emit_testimm(temp,32);
3706 emit_andimm(temp,24,temp);
3707 if (opcode[i]==0x1A) { // LDL
3708 emit_rsbimm(temp,32,HOST_TEMPREG);
3709 emit_shl(temp2h,temp,temp2h);
3710 emit_orrshr(temp2,HOST_TEMPREG,temp2h);
3711 emit_movimm(-1,HOST_TEMPREG);
3712 emit_shl(temp2,temp,temp2);
3713 emit_cmove_reg(temp2h,th);
3714 emit_biceq_lsl(tl,HOST_TEMPREG,temp,tl);
3715 emit_bicne_lsl(th,HOST_TEMPREG,temp,th);
3716 emit_orreq(temp2,tl,tl);
3717 emit_orrne(temp2,th,th);
3719 if (opcode[i]==0x1B) { // LDR
3720 emit_xorimm(temp,24,temp);
3721 emit_rsbimm(temp,32,HOST_TEMPREG);
3722 emit_shr(temp2,temp,temp2);
3723 emit_orrshl(temp2h,HOST_TEMPREG,temp2);
3724 emit_movimm(-1,HOST_TEMPREG);
3725 emit_shr(temp2h,temp,temp2h);
3726 emit_cmovne_reg(temp2,tl);
3727 emit_bicne_lsr(th,HOST_TEMPREG,temp,th);
3728 emit_biceq_lsr(tl,HOST_TEMPREG,temp,tl);
3729 emit_orrne(temp2h,th,th);
3730 emit_orreq(temp2h,tl,tl);
3735 #define loadlr_assemble loadlr_assemble_arm
3737 void cop0_assemble(int i,struct regstat *i_regs)
3739 if(opcode2[i]==0) // MFC0
3741 signed char t=get_reg(i_regs->regmap,rt1[i]);
3742 char copr=(source[i]>>11)&0x1f;
3743 //assert(t>=0); // Why does this happen? OOT is weird
3744 if(t>=0&&rt1[i]!=0) {
3745 emit_readword((int)®_cop0+copr*4,t);
3748 else if(opcode2[i]==4) // MTC0
3750 signed char s=get_reg(i_regs->regmap,rs1[i]);
3751 char copr=(source[i]>>11)&0x1f;
3753 wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
3754 if(copr==9||copr==11||copr==12||copr==13) {
3755 emit_readword((int)&last_count,HOST_TEMPREG);
3756 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3757 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3758 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3759 emit_writeword(HOST_CCREG,(int)&Count);
3761 // What a mess. The status register (12) can enable interrupts,
3762 // so needs a special case to handle a pending interrupt.
3763 // The interrupt must be taken immediately, because a subsequent
3764 // instruction might disable interrupts again.
3765 if(copr==12||copr==13) {
3767 // burn cycles to cause cc_interrupt, which will
3768 // reschedule next_interupt. Relies on CCREG from above.
3769 assem_debug("MTC0 DS %d\n", copr);
3770 emit_writeword(HOST_CCREG,(int)&last_count);
3771 emit_movimm(0,HOST_CCREG);
3772 emit_storereg(CCREG,HOST_CCREG);
3773 emit_loadreg(rs1[i],1);
3774 emit_movimm(copr,0);
3775 emit_call((int)pcsx_mtc0_ds);
3776 emit_loadreg(rs1[i],s);
3779 emit_movimm(start+i*4+4,HOST_TEMPREG);
3780 emit_writeword(HOST_TEMPREG,(int)&pcaddr);
3781 emit_movimm(0,HOST_TEMPREG);
3782 emit_writeword(HOST_TEMPREG,(int)&pending_exception);
3784 //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
3787 emit_loadreg(rs1[i],1);
3790 emit_movimm(copr,0);
3791 emit_call((int)pcsx_mtc0);
3792 if(copr==9||copr==11||copr==12||copr==13) {
3793 emit_readword((int)&Count,HOST_CCREG);
3794 emit_readword((int)&next_interupt,HOST_TEMPREG);
3795 emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3796 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3797 emit_writeword(HOST_TEMPREG,(int)&last_count);
3798 emit_storereg(CCREG,HOST_CCREG);
3800 if(copr==12||copr==13) {
3801 assert(!is_delayslot);
3802 emit_readword((int)&pending_exception,14);
3804 emit_jne((int)&do_interrupt);
3806 emit_loadreg(rs1[i],s);
3807 if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
3808 emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
3813 assert(opcode2[i]==0x10);
3814 if((source[i]&0x3f)==0x10) // RFE
3816 emit_readword((int)&Status,0);
3817 emit_andimm(0,0x3c,1);
3818 emit_andimm(0,~0xf,0);
3819 emit_orrshr_imm(1,2,0);
3820 emit_writeword(0,(int)&Status);
3825 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3835 emit_readword((int)®_cop2d[copr],tl);
3836 emit_signextend16(tl,tl);
3837 emit_writeword(tl,(int)®_cop2d[copr]); // hmh
3844 emit_readword((int)®_cop2d[copr],tl);
3845 emit_andimm(tl,0xffff,tl);
3846 emit_writeword(tl,(int)®_cop2d[copr]);
3849 emit_readword((int)®_cop2d[14],tl); // SXY2
3850 emit_writeword(tl,(int)®_cop2d[copr]);
3854 emit_readword((int)®_cop2d[9],temp);
3855 emit_testimm(temp,0x8000); // do we need this?
3856 emit_andimm(temp,0xf80,temp);
3857 emit_andne_imm(temp,0,temp);
3858 emit_shrimm(temp,7,tl);
3859 emit_readword((int)®_cop2d[10],temp);
3860 emit_testimm(temp,0x8000);
3861 emit_andimm(temp,0xf80,temp);
3862 emit_andne_imm(temp,0,temp);
3863 emit_orrshr_imm(temp,2,tl);
3864 emit_readword((int)®_cop2d[11],temp);
3865 emit_testimm(temp,0x8000);
3866 emit_andimm(temp,0xf80,temp);
3867 emit_andne_imm(temp,0,temp);
3868 emit_orrshl_imm(temp,3,tl);
3869 emit_writeword(tl,(int)®_cop2d[copr]);
3872 emit_readword((int)®_cop2d[copr],tl);
3877 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3881 emit_readword((int)®_cop2d[13],temp); // SXY1
3882 emit_writeword(sl,(int)®_cop2d[copr]);
3883 emit_writeword(temp,(int)®_cop2d[12]); // SXY0
3884 emit_readword((int)®_cop2d[14],temp); // SXY2
3885 emit_writeword(sl,(int)®_cop2d[14]);
3886 emit_writeword(temp,(int)®_cop2d[13]); // SXY1
3889 emit_andimm(sl,0x001f,temp);
3890 emit_shlimm(temp,7,temp);
3891 emit_writeword(temp,(int)®_cop2d[9]);
3892 emit_andimm(sl,0x03e0,temp);
3893 emit_shlimm(temp,2,temp);
3894 emit_writeword(temp,(int)®_cop2d[10]);
3895 emit_andimm(sl,0x7c00,temp);
3896 emit_shrimm(temp,3,temp);
3897 emit_writeword(temp,(int)®_cop2d[11]);
3898 emit_writeword(sl,(int)®_cop2d[28]);
3902 emit_mvnmi(temp,temp);
3904 emit_clz(temp,temp);
3906 emit_movs(temp,HOST_TEMPREG);
3907 emit_movimm(0,temp);
3908 emit_jeq((int)out+4*4);
3909 emit_addpl_imm(temp,1,temp);
3910 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3911 emit_jns((int)out-2*4);
3913 emit_writeword(sl,(int)®_cop2d[30]);
3914 emit_writeword(temp,(int)®_cop2d[31]);
3919 emit_writeword(sl,(int)®_cop2d[copr]);
3924 void cop2_assemble(int i,struct regstat *i_regs)
3926 u_int copr=(source[i]>>11)&0x1f;
3927 signed char temp=get_reg(i_regs->regmap,-1);
3928 if (opcode2[i]==0) { // MFC2
3929 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3930 if(tl>=0&&rt1[i]!=0)
3931 cop2_get_dreg(copr,tl,temp);
3933 else if (opcode2[i]==4) { // MTC2
3934 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3935 cop2_put_dreg(copr,sl,temp);
3937 else if (opcode2[i]==2) // CFC2
3939 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3940 if(tl>=0&&rt1[i]!=0)
3941 emit_readword((int)®_cop2c[copr],tl);
3943 else if (opcode2[i]==6) // CTC2
3945 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3954 emit_signextend16(sl,temp);
3957 //value = value & 0x7ffff000;
3958 //if (value & 0x7f87e000) value |= 0x80000000;
3959 emit_shrimm(sl,12,temp);
3960 emit_shlimm(temp,12,temp);
3961 emit_testimm(temp,0x7f000000);
3962 emit_testeqimm(temp,0x00870000);
3963 emit_testeqimm(temp,0x0000e000);
3964 emit_orrne_imm(temp,0x80000000,temp);
3970 emit_writeword(temp,(int)®_cop2c[copr]);
3975 static void c2op_prologue(u_int op,u_int reglist)
3977 save_regs_all(reglist);
3980 emit_call((int)pcnt_gte_start);
3982 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0); // cop2 regs
3985 static void c2op_epilogue(u_int op,u_int reglist)
3989 emit_call((int)pcnt_gte_end);
3991 restore_regs_all(reglist);
3994 static void c2op_call_MACtoIR(int lm,int need_flags)
3997 emit_call((int)(lm?gteMACtoIR_lm1:gteMACtoIR_lm0));
3999 emit_call((int)(lm?gteMACtoIR_lm1_nf:gteMACtoIR_lm0_nf));
4002 static void c2op_call_rgb_func(void *func,int lm,int need_ir,int need_flags)
4004 emit_call((int)func);
4005 // func is C code and trashes r0
4006 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
4007 if(need_flags||need_ir)
4008 c2op_call_MACtoIR(lm,need_flags);
4009 emit_call((int)(need_flags?gteMACtoRGB:gteMACtoRGB_nf));
4012 static void c2op_assemble(int i,struct regstat *i_regs)
4014 signed char temp=get_reg(i_regs->regmap,-1);
4015 u_int c2op=source[i]&0x3f;
4016 u_int hr,reglist_full=0,reglist;
4017 int need_flags,need_ir;
4018 for(hr=0;hr<HOST_REGS;hr++) {
4019 if(i_regs->regmap[hr]>=0) reglist_full|=1<<hr;
4021 reglist=reglist_full&CALLER_SAVE_REGS;
4023 if (gte_handlers[c2op]!=NULL) {
4024 need_flags=!(gte_unneeded[i+1]>>63); // +1 because of how liveness detection works
4025 need_ir=(gte_unneeded[i+1]&0xe00)!=0xe00;
4026 assem_debug("gte op %08x, unneeded %016llx, need_flags %d, need_ir %d\n",
4027 source[i],gte_unneeded[i+1],need_flags,need_ir);
4028 if(new_dynarec_hacks&NDHACK_GTE_NO_FLAGS)
4030 int shift = (source[i] >> 19) & 1;
4031 int lm = (source[i] >> 10) & 1;
4036 int v = (source[i] >> 15) & 3;
4037 int cv = (source[i] >> 13) & 3;
4038 int mx = (source[i] >> 17) & 3;
4039 reglist=reglist_full&(CALLER_SAVE_REGS|0xf0); // +{r4-r7}
4040 c2op_prologue(c2op,reglist);
4041 /* r4,r5 = VXYZ(v) packed; r6 = &MX11(mx); r7 = &CV1(cv) */
4045 emit_movzwl_indexed(9*4,0,4); // gteIR
4046 emit_movzwl_indexed(10*4,0,6);
4047 emit_movzwl_indexed(11*4,0,5);
4048 emit_orrshl_imm(6,16,4);
4051 emit_addimm(0,32*4+mx*8*4,6);
4053 emit_readword((int)&zeromem_ptr,6);
4055 emit_addimm(0,32*4+(cv*8+5)*4,7);
4057 emit_readword((int)&zeromem_ptr,7);
4059 emit_movimm(source[i],1); // opcode
4060 emit_call((int)gteMVMVA_part_neon);
4063 emit_call((int)gteMACtoIR_flags_neon);
4067 emit_call((int)gteMVMVA_part_cv3sh12_arm);
4069 emit_movimm(shift,1);
4070 emit_call((int)(need_flags?gteMVMVA_part_arm:gteMVMVA_part_nf_arm));
4072 if(need_flags||need_ir)
4073 c2op_call_MACtoIR(lm,need_flags);
4075 #else /* if not HAVE_ARMV5 */
4076 c2op_prologue(c2op,reglist);
4077 emit_movimm(source[i],1); // opcode
4078 emit_writeword(1,(int)&psxRegs.code);
4079 emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op]));
4084 c2op_prologue(c2op,reglist);
4085 emit_call((int)(shift?gteOP_part_shift:gteOP_part_noshift));
4086 if(need_flags||need_ir) {
4087 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
4088 c2op_call_MACtoIR(lm,need_flags);
4092 c2op_prologue(c2op,reglist);
4093 c2op_call_rgb_func(shift?gteDPCS_part_shift:gteDPCS_part_noshift,lm,need_ir,need_flags);
4096 c2op_prologue(c2op,reglist);
4097 c2op_call_rgb_func(shift?gteINTPL_part_shift:gteINTPL_part_noshift,lm,need_ir,need_flags);
4100 c2op_prologue(c2op,reglist);
4101 emit_call((int)(shift?gteSQR_part_shift:gteSQR_part_noshift));
4102 if(need_flags||need_ir) {
4103 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
4104 c2op_call_MACtoIR(lm,need_flags);
4108 c2op_prologue(c2op,reglist);
4109 c2op_call_rgb_func(gteDCPL_part,lm,need_ir,need_flags);
4112 c2op_prologue(c2op,reglist);
4113 c2op_call_rgb_func(shift?gteGPF_part_shift:gteGPF_part_noshift,lm,need_ir,need_flags);
4116 c2op_prologue(c2op,reglist);
4117 c2op_call_rgb_func(shift?gteGPL_part_shift:gteGPL_part_noshift,lm,need_ir,need_flags);
4121 c2op_prologue(c2op,reglist);
4123 emit_movimm(source[i],1); // opcode
4124 emit_writeword(1,(int)&psxRegs.code);
4126 emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op]));
4129 c2op_epilogue(c2op,reglist);
4133 void cop1_unusable(int i,struct regstat *i_regs)
4135 // XXX: should just just do the exception instead
4139 add_stub(FP_STUB,jaddr,(int)out,i,0,(int)i_regs,is_delayslot,0);
4144 void cop1_assemble(int i,struct regstat *i_regs)
4146 cop1_unusable(i, i_regs);
4149 void fconv_assemble_arm(int i,struct regstat *i_regs)
4151 cop1_unusable(i, i_regs);
4153 #define fconv_assemble fconv_assemble_arm
4155 void fcomp_assemble(int i,struct regstat *i_regs)
4157 cop1_unusable(i, i_regs);
4160 void float_assemble(int i,struct regstat *i_regs)
4162 cop1_unusable(i, i_regs);
4165 void multdiv_assemble_arm(int i,struct regstat *i_regs)
4172 // case 0x1D: DMULTU
4177 if((opcode2[i]&4)==0) // 32-bit
4179 if(opcode2[i]==0x18) // MULT
4181 signed char m1=get_reg(i_regs->regmap,rs1[i]);
4182 signed char m2=get_reg(i_regs->regmap,rs2[i]);
4183 signed char hi=get_reg(i_regs->regmap,HIREG);
4184 signed char lo=get_reg(i_regs->regmap,LOREG);
4189 emit_smull(m1,m2,hi,lo);
4191 if(opcode2[i]==0x19) // MULTU
4193 signed char m1=get_reg(i_regs->regmap,rs1[i]);
4194 signed char m2=get_reg(i_regs->regmap,rs2[i]);
4195 signed char hi=get_reg(i_regs->regmap,HIREG);
4196 signed char lo=get_reg(i_regs->regmap,LOREG);
4201 emit_umull(m1,m2,hi,lo);
4203 if(opcode2[i]==0x1A) // DIV
4205 signed char d1=get_reg(i_regs->regmap,rs1[i]);
4206 signed char d2=get_reg(i_regs->regmap,rs2[i]);
4209 signed char quotient=get_reg(i_regs->regmap,LOREG);
4210 signed char remainder=get_reg(i_regs->regmap,HIREG);
4211 assert(quotient>=0);
4212 assert(remainder>=0);
4213 emit_movs(d1,remainder);
4214 emit_movimm(0xffffffff,quotient);
4215 emit_negmi(quotient,quotient); // .. quotient and ..
4216 emit_negmi(remainder,remainder); // .. remainder for div0 case (will be negated back after jump)
4217 emit_movs(d2,HOST_TEMPREG);
4218 emit_jeq((int)out+52); // Division by zero
4219 emit_negsmi(HOST_TEMPREG,HOST_TEMPREG);
4221 emit_clz(HOST_TEMPREG,quotient);
4222 emit_shl(HOST_TEMPREG,quotient,HOST_TEMPREG);
4224 emit_movimm(0,quotient);
4225 emit_addpl_imm(quotient,1,quotient);
4226 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
4227 emit_jns((int)out-2*4);
4229 emit_orimm(quotient,1<<31,quotient);
4230 emit_shr(quotient,quotient,quotient);
4231 emit_cmp(remainder,HOST_TEMPREG);
4232 emit_subcs(remainder,HOST_TEMPREG,remainder);
4233 emit_adcs(quotient,quotient,quotient);
4234 emit_shrimm(HOST_TEMPREG,1,HOST_TEMPREG);
4235 emit_jcc((int)out-16); // -4
4237 emit_negmi(quotient,quotient);
4239 emit_negmi(remainder,remainder);
4241 if(opcode2[i]==0x1B) // DIVU
4243 signed char d1=get_reg(i_regs->regmap,rs1[i]); // dividend
4244 signed char d2=get_reg(i_regs->regmap,rs2[i]); // divisor
4247 signed char quotient=get_reg(i_regs->regmap,LOREG);
4248 signed char remainder=get_reg(i_regs->regmap,HIREG);
4249 assert(quotient>=0);
4250 assert(remainder>=0);
4251 emit_mov(d1,remainder);
4252 emit_movimm(0xffffffff,quotient); // div0 case
4254 emit_jeq((int)out+40); // Division by zero
4256 emit_clz(d2,HOST_TEMPREG);
4257 emit_movimm(1<<31,quotient);
4258 emit_shl(d2,HOST_TEMPREG,d2);
4260 emit_movimm(0,HOST_TEMPREG);
4261 emit_addpl_imm(HOST_TEMPREG,1,HOST_TEMPREG);
4262 emit_lslpls_imm(d2,1,d2);
4263 emit_jns((int)out-2*4);
4264 emit_movimm(1<<31,quotient);
4266 emit_shr(quotient,HOST_TEMPREG,quotient);
4267 emit_cmp(remainder,d2);
4268 emit_subcs(remainder,d2,remainder);
4269 emit_adcs(quotient,quotient,quotient);
4270 emit_shrcc_imm(d2,1,d2);
4271 emit_jcc((int)out-16); // -4
4279 // Multiply by zero is zero.
4280 // MIPS does not have a divide by zero exception.
4281 // The result is undefined, we return zero.
4282 signed char hr=get_reg(i_regs->regmap,HIREG);
4283 signed char lr=get_reg(i_regs->regmap,LOREG);
4284 if(hr>=0) emit_zeroreg(hr);
4285 if(lr>=0) emit_zeroreg(lr);
4288 #define multdiv_assemble multdiv_assemble_arm
4290 void do_preload_rhash(int r) {
4291 // Don't need this for ARM. On x86, this puts the value 0xf8 into the
4292 // register. On ARM the hash can be done with a single instruction (below)
4295 void do_preload_rhtbl(int ht) {
4296 emit_addimm(FP,(int)&mini_ht-(int)&dynarec_local,ht);
4299 void do_rhash(int rs,int rh) {
4300 emit_andimm(rs,0xf8,rh);
4303 void do_miniht_load(int ht,int rh) {
4304 assem_debug("ldr %s,[%s,%s]!\n",regname[rh],regname[ht],regname[rh]);
4305 output_w32(0xe7b00000|rd_rn_rm(rh,ht,rh));
4308 void do_miniht_jump(int rs,int rh,int ht) {
4310 emit_ldreq_indexed(ht,4,15);
4311 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4313 emit_jmp(jump_vaddr_reg[7]);
4315 emit_jmp(jump_vaddr_reg[rs]);
4319 void do_miniht_insert(u_int return_address,int rt,int temp) {
4321 emit_movimm(return_address,rt); // PC into link register
4322 add_to_linker((int)out,return_address,1);
4323 emit_pcreladdr(temp);
4324 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4325 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4327 emit_movw(return_address&0x0000FFFF,rt);
4328 add_to_linker((int)out,return_address,1);
4329 emit_pcreladdr(temp);
4330 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4331 emit_movt(return_address&0xFFFF0000,rt);
4332 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4336 void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)
4338 //if(dirty_pre==dirty) return;
4340 for(hr=0;hr<HOST_REGS;hr++) {
4341 if(hr!=EXCLUDE_REG) {
4343 if(((~u)>>(reg&63))&1) {
4345 if(((dirty_pre&~dirty)>>hr)&1) {
4347 emit_storereg(reg,hr);
4348 if( ((is32_pre&~uu)>>reg)&1 ) {
4349 emit_sarimm(hr,31,HOST_TEMPREG);
4350 emit_storereg(reg|64,HOST_TEMPREG);
4354 emit_storereg(reg,hr);
4364 /* using strd could possibly help but you'd have to allocate registers in pairs
4365 void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,uint64_t u,uint64_t uu)
4369 for(hr=HOST_REGS-1;hr>=0;hr--) {
4370 if(hr!=EXCLUDE_REG) {
4371 if(pre[hr]!=entry[hr]) {
4374 if(get_reg(entry,pre[hr])<0) {
4376 if(!((u>>pre[hr])&1)) {
4377 if(hr<10&&(~hr&1)&&(pre[hr+1]<0||wrote==hr+1)) {
4378 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4379 emit_sarimm(hr,31,hr+1);
4380 emit_strdreg(pre[hr],hr);
4383 emit_storereg(pre[hr],hr);
4385 emit_storereg(pre[hr],hr);
4386 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4387 emit_sarimm(hr,31,hr);
4388 emit_storereg(pre[hr]|64,hr);
4393 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4394 emit_storereg(pre[hr],hr);
4404 for(hr=0;hr<HOST_REGS;hr++) {
4405 if(hr!=EXCLUDE_REG) {
4406 if(pre[hr]!=entry[hr]) {
4409 if((nr=get_reg(entry,pre[hr]))>=0) {
4417 #define wb_invalidate wb_invalidate_arm
4420 // Clearing the cache is rather slow on ARM Linux, so mark the areas
4421 // that need to be cleared, and then only clear these areas once.
4422 void do_clear_cache()
4425 for (i=0;i<(1<<(TARGET_SIZE_2-17));i++)
4427 u_int bitmap=needs_clear_cache[i];
4433 start=(u_int)BASE_ADDR+i*131072+j*4096;
4441 __clear_cache((void *)start,(void *)end);
4447 needs_clear_cache[i]=0;
4452 // CPU-architecture-specific initialization
4453 static void arch_init() {
4456 // vim:shiftwidth=2:expandtab