1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus/PCSX - assem_arm.c *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2011 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 extern int cycle_count;
23 extern int last_count;
25 extern int pending_exception;
26 extern int branch_target;
27 extern uint64_t readmem_dword;
29 extern precomp_instr fake_pc;
31 extern void *dynarec_local;
32 extern u_int memory_map[1048576];
33 extern u_int mini_ht[32][2];
34 extern u_int rounding_modes[4];
36 void indirect_jump_indexed();
49 void jump_vaddr_r10();
50 void jump_vaddr_r12();
52 const u_int jump_vaddr_reg[16] = {
70 void invalidate_addr_r0();
71 void invalidate_addr_r1();
72 void invalidate_addr_r2();
73 void invalidate_addr_r3();
74 void invalidate_addr_r4();
75 void invalidate_addr_r5();
76 void invalidate_addr_r6();
77 void invalidate_addr_r7();
78 void invalidate_addr_r8();
79 void invalidate_addr_r9();
80 void invalidate_addr_r10();
81 void invalidate_addr_r12();
83 const u_int invalidate_addr_reg[16] = {
84 (int)invalidate_addr_r0,
85 (int)invalidate_addr_r1,
86 (int)invalidate_addr_r2,
87 (int)invalidate_addr_r3,
88 (int)invalidate_addr_r4,
89 (int)invalidate_addr_r5,
90 (int)invalidate_addr_r6,
91 (int)invalidate_addr_r7,
92 (int)invalidate_addr_r8,
93 (int)invalidate_addr_r9,
94 (int)invalidate_addr_r10,
96 (int)invalidate_addr_r12,
103 unsigned int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
107 void set_jump_target(int addr,u_int target)
109 u_char *ptr=(u_char *)addr;
110 u_int *ptr2=(u_int *)ptr;
112 assert((target-(u_int)ptr2-8)<1024);
114 assert((target&3)==0);
115 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
116 //printf("target=%x addr=%x insn=%x\n",target,addr,*ptr2);
118 else if(ptr[3]==0x72) {
119 // generated by emit_jno_unlikely
120 if((target-(u_int)ptr2-8)<1024) {
122 assert((target&3)==0);
123 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
125 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
127 assert((target&3)==0);
128 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
130 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
133 assert((ptr[3]&0x0e)==0xa);
134 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
138 // This optionally copies the instruction from the target of the branch into
139 // the space before the branch. Works, but the difference in speed is
140 // usually insignificant.
141 void set_jump_target_fillslot(int addr,u_int target,int copy)
143 u_char *ptr=(u_char *)addr;
144 u_int *ptr2=(u_int *)ptr;
145 assert(!copy||ptr2[-1]==0xe28dd000);
148 assert((target-(u_int)ptr2-8)<4096);
149 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
152 assert((ptr[3]&0x0e)==0xa);
153 u_int target_insn=*(u_int *)target;
154 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
157 if((target_insn&0x0c100000)==0x04100000) { // Load
160 if(target_insn&0x08000000) {
164 ptr2[-1]=target_insn;
167 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
172 add_literal(int addr,int val)
174 assert(literalcount<sizeof(literals)/sizeof(literals[0]));
175 literals[literalcount][0]=addr;
176 literals[literalcount][1]=val;
180 void *kill_pointer(void *stub)
182 int *ptr=(int *)(stub+4);
183 assert((*ptr&0x0ff00000)==0x05900000);
184 u_int offset=*ptr&0xfff;
185 int **l_ptr=(void *)ptr+offset+8;
187 set_jump_target((int)i_ptr,(int)stub);
191 // find where external branch is liked to using addr of it's stub:
192 // get address that insn one after stub loads (dyna_linker arg1),
193 // treat it as a pointer to branch insn,
194 // return addr where that branch jumps to
195 int get_pointer(void *stub)
197 //printf("get_pointer(%x)\n",(int)stub);
198 int *ptr=(int *)(stub+4);
199 assert((*ptr&0x0fff0000)==0x059f0000);
200 u_int offset=*ptr&0xfff;
201 int **l_ptr=(void *)ptr+offset+8;
203 assert((*i_ptr&0x0f000000)==0x0a000000);
204 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
207 // Find the "clean" entry point from a "dirty" entry point
208 // by skipping past the call to verify_code
209 u_int get_clean_addr(int addr)
211 int *ptr=(int *)addr;
217 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
218 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
220 if((*ptr&0xFF000000)==0xea000000) {
221 return (int)ptr+((*ptr<<8)>>6)+8; // follow jump
226 int verify_dirty(int addr)
228 u_int *ptr=(u_int *)addr;
230 // get from literal pool
231 assert((*ptr&0xFFFF0000)==0xe59f0000);
232 u_int offset=*ptr&0xfff;
233 u_int *l_ptr=(void *)ptr+offset+8;
234 u_int source=l_ptr[0];
240 assert((*ptr&0xFFF00000)==0xe3000000);
241 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
242 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
243 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
246 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
247 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
248 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
249 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
250 unsigned int page=source>>12;
251 unsigned int map_value=memory_map[page];
252 if(map_value>=0x80000000) return 0;
253 while(page<((source+len-1)>>12)) {
254 if((memory_map[++page]<<2)!=(map_value<<2)) return 0;
256 source = source+(map_value<<2);
258 //printf("verify_dirty: %x %x %x\n",source,copy,len);
259 return !memcmp((void *)source,(void *)copy,len);
262 // This doesn't necessarily find all clean entry points, just
263 // guarantees that it's not dirty
264 int isclean(int addr)
267 int *ptr=((u_int *)addr)+4;
269 int *ptr=((u_int *)addr)+6;
271 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
272 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
273 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
274 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
275 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
279 void get_bounds(int addr,u_int *start,u_int *end)
281 u_int *ptr=(u_int *)addr;
283 // get from literal pool
284 assert((*ptr&0xFFFF0000)==0xe59f0000);
285 u_int offset=*ptr&0xfff;
286 u_int *l_ptr=(void *)ptr+offset+8;
287 u_int source=l_ptr[0];
288 //u_int copy=l_ptr[1];
293 assert((*ptr&0xFFF00000)==0xe3000000);
294 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
295 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
296 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
299 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
300 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
301 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
302 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
303 if(memory_map[source>>12]>=0x80000000) source = 0;
304 else source = source+(memory_map[source>>12]<<2);
310 /* Register allocation */
312 // Note: registers are allocated clean (unmodified state)
313 // if you intend to modify the register, you must call dirty_reg().
314 void alloc_reg(struct regstat *cur,int i,signed char reg)
317 int preferred_reg = (reg&7);
318 if(reg==CCREG) preferred_reg=HOST_CCREG;
319 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
321 // Don't allocate unused registers
322 if((cur->u>>reg)&1) return;
324 // see if it's already allocated
325 for(hr=0;hr<HOST_REGS;hr++)
327 if(cur->regmap[hr]==reg) return;
330 // Keep the same mapping if the register was already allocated in a loop
331 preferred_reg = loop_reg(i,reg,preferred_reg);
333 // Try to allocate the preferred register
334 if(cur->regmap[preferred_reg]==-1) {
335 cur->regmap[preferred_reg]=reg;
336 cur->dirty&=~(1<<preferred_reg);
337 cur->isconst&=~(1<<preferred_reg);
340 r=cur->regmap[preferred_reg];
341 if(r<64&&((cur->u>>r)&1)) {
342 cur->regmap[preferred_reg]=reg;
343 cur->dirty&=~(1<<preferred_reg);
344 cur->isconst&=~(1<<preferred_reg);
347 if(r>=64&&((cur->uu>>(r&63))&1)) {
348 cur->regmap[preferred_reg]=reg;
349 cur->dirty&=~(1<<preferred_reg);
350 cur->isconst&=~(1<<preferred_reg);
354 // Clear any unneeded registers
355 // We try to keep the mapping consistent, if possible, because it
356 // makes branches easier (especially loops). So we try to allocate
357 // first (see above) before removing old mappings. If this is not
358 // possible then go ahead and clear out the registers that are no
360 for(hr=0;hr<HOST_REGS;hr++)
365 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
369 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
373 // Try to allocate any available register, but prefer
374 // registers that have not been used recently.
376 for(hr=0;hr<HOST_REGS;hr++) {
377 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
378 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
380 cur->dirty&=~(1<<hr);
381 cur->isconst&=~(1<<hr);
387 // Try to allocate any available register
388 for(hr=0;hr<HOST_REGS;hr++) {
389 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
391 cur->dirty&=~(1<<hr);
392 cur->isconst&=~(1<<hr);
397 // Ok, now we have to evict someone
398 // Pick a register we hopefully won't need soon
399 u_char hsn[MAXREG+1];
400 memset(hsn,10,sizeof(hsn));
402 lsn(hsn,i,&preferred_reg);
403 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
404 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
406 // Don't evict the cycle count at entry points, otherwise the entry
407 // stub will have to write it.
408 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
409 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
412 // Alloc preferred register if available
413 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
414 for(hr=0;hr<HOST_REGS;hr++) {
415 // Evict both parts of a 64-bit register
416 if((cur->regmap[hr]&63)==r) {
418 cur->dirty&=~(1<<hr);
419 cur->isconst&=~(1<<hr);
422 cur->regmap[preferred_reg]=reg;
425 for(r=1;r<=MAXREG;r++)
427 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
428 for(hr=0;hr<HOST_REGS;hr++) {
429 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
430 if(cur->regmap[hr]==r+64) {
432 cur->dirty&=~(1<<hr);
433 cur->isconst&=~(1<<hr);
438 for(hr=0;hr<HOST_REGS;hr++) {
439 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
440 if(cur->regmap[hr]==r) {
442 cur->dirty&=~(1<<hr);
443 cur->isconst&=~(1<<hr);
454 for(r=1;r<=MAXREG;r++)
457 for(hr=0;hr<HOST_REGS;hr++) {
458 if(cur->regmap[hr]==r+64) {
460 cur->dirty&=~(1<<hr);
461 cur->isconst&=~(1<<hr);
465 for(hr=0;hr<HOST_REGS;hr++) {
466 if(cur->regmap[hr]==r) {
468 cur->dirty&=~(1<<hr);
469 cur->isconst&=~(1<<hr);
476 printf("This shouldn't happen (alloc_reg)");exit(1);
479 void alloc_reg64(struct regstat *cur,int i,signed char reg)
481 int preferred_reg = 8+(reg&1);
484 // allocate the lower 32 bits
485 alloc_reg(cur,i,reg);
487 // Don't allocate unused registers
488 if((cur->uu>>reg)&1) return;
490 // see if the upper half is already allocated
491 for(hr=0;hr<HOST_REGS;hr++)
493 if(cur->regmap[hr]==reg+64) return;
496 // Keep the same mapping if the register was already allocated in a loop
497 preferred_reg = loop_reg(i,reg,preferred_reg);
499 // Try to allocate the preferred register
500 if(cur->regmap[preferred_reg]==-1) {
501 cur->regmap[preferred_reg]=reg|64;
502 cur->dirty&=~(1<<preferred_reg);
503 cur->isconst&=~(1<<preferred_reg);
506 r=cur->regmap[preferred_reg];
507 if(r<64&&((cur->u>>r)&1)) {
508 cur->regmap[preferred_reg]=reg|64;
509 cur->dirty&=~(1<<preferred_reg);
510 cur->isconst&=~(1<<preferred_reg);
513 if(r>=64&&((cur->uu>>(r&63))&1)) {
514 cur->regmap[preferred_reg]=reg|64;
515 cur->dirty&=~(1<<preferred_reg);
516 cur->isconst&=~(1<<preferred_reg);
520 // Clear any unneeded registers
521 // We try to keep the mapping consistent, if possible, because it
522 // makes branches easier (especially loops). So we try to allocate
523 // first (see above) before removing old mappings. If this is not
524 // possible then go ahead and clear out the registers that are no
526 for(hr=HOST_REGS-1;hr>=0;hr--)
531 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
535 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
539 // Try to allocate any available register, but prefer
540 // registers that have not been used recently.
542 for(hr=0;hr<HOST_REGS;hr++) {
543 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
544 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
545 cur->regmap[hr]=reg|64;
546 cur->dirty&=~(1<<hr);
547 cur->isconst&=~(1<<hr);
553 // Try to allocate any available register
554 for(hr=0;hr<HOST_REGS;hr++) {
555 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
556 cur->regmap[hr]=reg|64;
557 cur->dirty&=~(1<<hr);
558 cur->isconst&=~(1<<hr);
563 // Ok, now we have to evict someone
564 // Pick a register we hopefully won't need soon
565 u_char hsn[MAXREG+1];
566 memset(hsn,10,sizeof(hsn));
568 lsn(hsn,i,&preferred_reg);
569 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
570 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
572 // Don't evict the cycle count at entry points, otherwise the entry
573 // stub will have to write it.
574 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
575 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
578 // Alloc preferred register if available
579 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
580 for(hr=0;hr<HOST_REGS;hr++) {
581 // Evict both parts of a 64-bit register
582 if((cur->regmap[hr]&63)==r) {
584 cur->dirty&=~(1<<hr);
585 cur->isconst&=~(1<<hr);
588 cur->regmap[preferred_reg]=reg|64;
591 for(r=1;r<=MAXREG;r++)
593 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
594 for(hr=0;hr<HOST_REGS;hr++) {
595 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
596 if(cur->regmap[hr]==r+64) {
597 cur->regmap[hr]=reg|64;
598 cur->dirty&=~(1<<hr);
599 cur->isconst&=~(1<<hr);
604 for(hr=0;hr<HOST_REGS;hr++) {
605 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
606 if(cur->regmap[hr]==r) {
607 cur->regmap[hr]=reg|64;
608 cur->dirty&=~(1<<hr);
609 cur->isconst&=~(1<<hr);
620 for(r=1;r<=MAXREG;r++)
623 for(hr=0;hr<HOST_REGS;hr++) {
624 if(cur->regmap[hr]==r+64) {
625 cur->regmap[hr]=reg|64;
626 cur->dirty&=~(1<<hr);
627 cur->isconst&=~(1<<hr);
631 for(hr=0;hr<HOST_REGS;hr++) {
632 if(cur->regmap[hr]==r) {
633 cur->regmap[hr]=reg|64;
634 cur->dirty&=~(1<<hr);
635 cur->isconst&=~(1<<hr);
642 printf("This shouldn't happen");exit(1);
645 // Allocate a temporary register. This is done without regard to
646 // dirty status or whether the register we request is on the unneeded list
647 // Note: This will only allocate one register, even if called multiple times
648 void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
651 int preferred_reg = -1;
653 // see if it's already allocated
654 for(hr=0;hr<HOST_REGS;hr++)
656 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
659 // Try to allocate any available register
660 for(hr=HOST_REGS-1;hr>=0;hr--) {
661 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
663 cur->dirty&=~(1<<hr);
664 cur->isconst&=~(1<<hr);
669 // Find an unneeded register
670 for(hr=HOST_REGS-1;hr>=0;hr--)
676 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
678 cur->dirty&=~(1<<hr);
679 cur->isconst&=~(1<<hr);
686 if((cur->uu>>(r&63))&1) {
687 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
689 cur->dirty&=~(1<<hr);
690 cur->isconst&=~(1<<hr);
698 // Ok, now we have to evict someone
699 // Pick a register we hopefully won't need soon
700 // TODO: we might want to follow unconditional jumps here
701 // TODO: get rid of dupe code and make this into a function
702 u_char hsn[MAXREG+1];
703 memset(hsn,10,sizeof(hsn));
705 lsn(hsn,i,&preferred_reg);
706 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
708 // Don't evict the cycle count at entry points, otherwise the entry
709 // stub will have to write it.
710 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
711 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
714 for(r=1;r<=MAXREG;r++)
716 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
717 for(hr=0;hr<HOST_REGS;hr++) {
718 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
719 if(cur->regmap[hr]==r+64) {
721 cur->dirty&=~(1<<hr);
722 cur->isconst&=~(1<<hr);
727 for(hr=0;hr<HOST_REGS;hr++) {
728 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
729 if(cur->regmap[hr]==r) {
731 cur->dirty&=~(1<<hr);
732 cur->isconst&=~(1<<hr);
743 for(r=1;r<=MAXREG;r++)
746 for(hr=0;hr<HOST_REGS;hr++) {
747 if(cur->regmap[hr]==r+64) {
749 cur->dirty&=~(1<<hr);
750 cur->isconst&=~(1<<hr);
754 for(hr=0;hr<HOST_REGS;hr++) {
755 if(cur->regmap[hr]==r) {
757 cur->dirty&=~(1<<hr);
758 cur->isconst&=~(1<<hr);
765 printf("This shouldn't happen");exit(1);
767 // Allocate a specific ARM register.
768 void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
773 // see if it's already allocated (and dealloc it)
774 for(n=0;n<HOST_REGS;n++)
776 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {
777 dirty=(cur->dirty>>n)&1;
783 cur->dirty&=~(1<<hr);
784 cur->dirty|=dirty<<hr;
785 cur->isconst&=~(1<<hr);
788 // Alloc cycle count into dedicated register
789 alloc_cc(struct regstat *cur,int i)
791 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
799 char regname[16][4] = {
817 void output_byte(u_char byte)
821 void output_modrm(u_char mod,u_char rm,u_char ext)
826 u_char byte=(mod<<6)|(ext<<3)|rm;
829 void output_sib(u_char scale,u_char index,u_char base)
834 u_char byte=(scale<<6)|(index<<3)|base;
837 void output_w32(u_int word)
839 *((u_int *)out)=word;
842 u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
847 return((rn<<16)|(rd<<12)|rm);
849 u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
854 assert((shift&1)==0);
855 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
857 u_int genimm(u_int imm,u_int *encoded)
865 *encoded=((i&30)<<7)|imm;
868 imm=(imm>>2)|(imm<<30);i-=2;
872 void genimm_checked(u_int imm,u_int *encoded)
874 u_int ret=genimm(imm,encoded);
877 u_int genjmp(u_int addr)
879 int offset=addr-(int)out-8;
880 if(offset<-33554432||offset>=33554432) {
882 printf("genjmp: out of range: %08x\n", offset);
887 return ((u_int)offset>>2)&0xffffff;
890 void emit_mov(int rs,int rt)
892 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
893 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
896 void emit_movs(int rs,int rt)
898 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
899 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
902 void emit_add(int rs1,int rs2,int rt)
904 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
905 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
908 void emit_adds(int rs1,int rs2,int rt)
910 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
911 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
914 void emit_adcs(int rs1,int rs2,int rt)
916 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
917 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
920 void emit_sbc(int rs1,int rs2,int rt)
922 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
923 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
926 void emit_sbcs(int rs1,int rs2,int rt)
928 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
929 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
932 void emit_neg(int rs, int rt)
934 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
935 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
938 void emit_negs(int rs, int rt)
940 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
941 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
944 void emit_sub(int rs1,int rs2,int rt)
946 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
947 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
950 void emit_subs(int rs1,int rs2,int rt)
952 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
953 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
956 void emit_zeroreg(int rt)
958 assem_debug("mov %s,#0\n",regname[rt]);
959 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
962 void emit_loadlp(u_int imm,u_int rt)
964 add_literal((int)out,imm);
965 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
966 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
968 void emit_movw(u_int imm,u_int rt)
971 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
972 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
974 void emit_movt(u_int imm,u_int rt)
976 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
977 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
979 void emit_movimm(u_int imm,u_int rt)
982 if(genimm(imm,&armval)) {
983 assem_debug("mov %s,#%d\n",regname[rt],imm);
984 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
985 }else if(genimm(~imm,&armval)) {
986 assem_debug("mvn %s,#%d\n",regname[rt],imm);
987 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
988 }else if(imm<65536) {
990 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
991 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
992 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
993 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1001 emit_movw(imm&0x0000FFFF,rt);
1002 emit_movt(imm&0xFFFF0000,rt);
1006 void emit_pcreladdr(u_int rt)
1008 assem_debug("add %s,pc,#?\n",regname[rt]);
1009 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
1012 void emit_loadreg(int r, int hr)
1016 printf("64bit load in 32bit mode!\n");
1024 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1025 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1026 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1027 if(r==CCREG) addr=(int)&cycle_count;
1028 if(r==CSREG) addr=(int)&Status;
1029 if(r==FSREG) addr=(int)&FCR31;
1030 if(r==INVCP) addr=(int)&invc_ptr;
1031 u_int offset = addr-(u_int)&dynarec_local;
1032 assert(offset<4096);
1033 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
1034 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
1037 void emit_storereg(int r, int hr)
1041 printf("64bit store in 32bit mode!\n");
1046 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1047 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1048 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1049 if(r==CCREG) addr=(int)&cycle_count;
1050 if(r==FSREG) addr=(int)&FCR31;
1051 u_int offset = addr-(u_int)&dynarec_local;
1052 assert(offset<4096);
1053 assem_debug("str %s,fp+%d\n",regname[hr],offset);
1054 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
1057 void emit_test(int rs, int rt)
1059 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
1060 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
1063 void emit_testimm(int rs,int imm)
1066 assem_debug("tst %s,#%d\n",regname[rs],imm);
1067 genimm_checked(imm,&armval);
1068 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
1071 void emit_testeqimm(int rs,int imm)
1074 assem_debug("tsteq %s,$%d\n",regname[rs],imm);
1075 genimm_checked(imm,&armval);
1076 output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
1079 void emit_not(int rs,int rt)
1081 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
1082 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
1085 void emit_mvnmi(int rs,int rt)
1087 assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
1088 output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
1091 void emit_and(u_int rs1,u_int rs2,u_int rt)
1093 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1094 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
1097 void emit_or(u_int rs1,u_int rs2,u_int rt)
1099 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1100 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
1102 void emit_or_and_set_flags(int rs1,int rs2,int rt)
1104 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1105 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
1108 void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
1113 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs],imm);
1114 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|(imm<<7));
1117 void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
1122 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm);
1123 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
1126 void emit_xor(u_int rs1,u_int rs2,u_int rt)
1128 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1129 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
1132 void emit_addimm(u_int rs,int imm,u_int rt)
1138 if(genimm(imm,&armval)) {
1139 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1140 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1141 }else if(genimm(-imm,&armval)) {
1142 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],imm);
1143 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1146 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1147 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1148 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1149 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1152 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1153 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1154 output_w32(0xe2800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1155 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1158 else if(rs!=rt) emit_mov(rs,rt);
1161 void emit_addimm_and_set_flags(int imm,int rt)
1163 assert(imm>-65536&&imm<65536);
1165 if(genimm(imm,&armval)) {
1166 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1167 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1168 }else if(genimm(-imm,&armval)) {
1169 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1170 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1172 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1173 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1174 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1175 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1177 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1178 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1179 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1180 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1183 void emit_addimm_no_flags(u_int imm,u_int rt)
1185 emit_addimm(rt,imm,rt);
1188 void emit_addnop(u_int r)
1191 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1192 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1195 void emit_adcimm(u_int rs,int imm,u_int rt)
1198 genimm_checked(imm,&armval);
1199 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1200 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1202 /*void emit_sbcimm(int imm,u_int rt)
1205 genimm_checked(imm,&armval);
1206 assem_debug("sbc %s,%s,#%d\n",regname[rt],regname[rt],imm);
1207 output_w32(0xe2c00000|rd_rn_rm(rt,rt,0)|armval);
1209 void emit_sbbimm(int imm,u_int rt)
1211 assem_debug("sbb $%d,%%%s\n",imm,regname[rt]);
1213 if(imm<128&&imm>=-128) {
1215 output_modrm(3,rt,3);
1221 output_modrm(3,rt,3);
1225 void emit_rscimm(int rs,int imm,u_int rt)
1229 genimm_checked(imm,&armval);
1230 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1231 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1234 void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1236 // TODO: if(genimm(imm,&armval)) ...
1238 emit_movimm(imm,HOST_TEMPREG);
1239 emit_adds(HOST_TEMPREG,rsl,rtl);
1240 emit_adcimm(rsh,0,rth);
1243 void emit_sbb(int rs1,int rs2)
1245 assem_debug("sbb %%%s,%%%s\n",regname[rs2],regname[rs1]);
1247 output_modrm(3,rs1,rs2);
1250 void emit_andimm(int rs,int imm,int rt)
1255 }else if(genimm(imm,&armval)) {
1256 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1257 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1258 }else if(genimm(~imm,&armval)) {
1259 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1260 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1261 }else if(imm==65535) {
1263 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1264 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1265 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1266 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1268 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1269 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1272 assert(imm>0&&imm<65535);
1274 assem_debug("mov r14,#%d\n",imm&0xFF00);
1275 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1276 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1277 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1279 emit_movw(imm,HOST_TEMPREG);
1281 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1282 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1286 void emit_orimm(int rs,int imm,int rt)
1290 if(rs!=rt) emit_mov(rs,rt);
1291 }else if(genimm(imm,&armval)) {
1292 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1293 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1295 assert(imm>0&&imm<65536);
1296 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1297 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1298 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1299 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1303 void emit_xorimm(int rs,int imm,int rt)
1307 if(rs!=rt) emit_mov(rs,rt);
1308 }else if(genimm(imm,&armval)) {
1309 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1310 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1312 assert(imm>0&&imm<65536);
1313 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1314 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1315 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1316 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1320 void emit_shlimm(int rs,u_int imm,int rt)
1325 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1326 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1329 void emit_lsls_imm(int rs,int imm,int rt)
1333 assem_debug("lsls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1334 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1337 void emit_shrimm(int rs,u_int imm,int rt)
1341 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1342 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1345 void emit_sarimm(int rs,u_int imm,int rt)
1349 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1350 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1353 void emit_rorimm(int rs,u_int imm,int rt)
1357 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1358 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1361 void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1363 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1367 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1368 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1369 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1370 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1373 void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1375 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1379 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1380 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1381 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1382 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1385 void emit_signextend16(int rs,int rt)
1388 emit_shlimm(rs,16,rt);
1389 emit_sarimm(rt,16,rt);
1391 assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
1392 output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
1396 void emit_signextend8(int rs,int rt)
1399 emit_shlimm(rs,24,rt);
1400 emit_sarimm(rt,24,rt);
1402 assem_debug("sxtb %s,%s\n",regname[rt],regname[rs]);
1403 output_w32(0xe6af0070|rd_rn_rm(rt,0,rs));
1407 void emit_shl(u_int rs,u_int shift,u_int rt)
1413 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1414 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1416 void emit_shr(u_int rs,u_int shift,u_int rt)
1421 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1422 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1424 void emit_sar(u_int rs,u_int shift,u_int rt)
1429 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1430 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1432 void emit_shlcl(int r)
1434 assem_debug("shl %%%s,%%cl\n",regname[r]);
1437 void emit_shrcl(int r)
1439 assem_debug("shr %%%s,%%cl\n",regname[r]);
1442 void emit_sarcl(int r)
1444 assem_debug("sar %%%s,%%cl\n",regname[r]);
1448 void emit_shldcl(int r1,int r2)
1450 assem_debug("shld %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1453 void emit_shrdcl(int r1,int r2)
1455 assem_debug("shrd %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1458 void emit_orrshl(u_int rs,u_int shift,u_int rt)
1463 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1464 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1466 void emit_orrshr(u_int rs,u_int shift,u_int rt)
1471 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1472 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1475 void emit_cmpimm(int rs,int imm)
1478 if(genimm(imm,&armval)) {
1479 assem_debug("cmp %s,#%d\n",regname[rs],imm);
1480 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1481 }else if(genimm(-imm,&armval)) {
1482 assem_debug("cmn %s,#%d\n",regname[rs],imm);
1483 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1487 emit_movimm(imm,HOST_TEMPREG);
1489 emit_movw(imm,HOST_TEMPREG);
1491 assem_debug("cmp %s,r14\n",regname[rs]);
1492 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1496 emit_movimm(-imm,HOST_TEMPREG);
1498 emit_movw(-imm,HOST_TEMPREG);
1500 assem_debug("cmn %s,r14\n",regname[rs]);
1501 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1505 void emit_cmovne(u_int *addr,int rt)
1507 assem_debug("cmovne %x,%%%s",(int)addr,regname[rt]);
1510 void emit_cmovl(u_int *addr,int rt)
1512 assem_debug("cmovl %x,%%%s",(int)addr,regname[rt]);
1515 void emit_cmovs(u_int *addr,int rt)
1517 assem_debug("cmovs %x,%%%s",(int)addr,regname[rt]);
1520 void emit_cmovne_imm(int imm,int rt)
1522 assem_debug("movne %s,#%d\n",regname[rt],imm);
1524 genimm_checked(imm,&armval);
1525 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1527 void emit_cmovl_imm(int imm,int rt)
1529 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1531 genimm_checked(imm,&armval);
1532 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1534 void emit_cmovb_imm(int imm,int rt)
1536 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1538 genimm_checked(imm,&armval);
1539 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1541 void emit_cmovs_imm(int imm,int rt)
1543 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1545 genimm_checked(imm,&armval);
1546 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1548 void emit_cmove_reg(int rs,int rt)
1550 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1551 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1553 void emit_cmovne_reg(int rs,int rt)
1555 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1556 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1558 void emit_cmovl_reg(int rs,int rt)
1560 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1561 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1563 void emit_cmovs_reg(int rs,int rt)
1565 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1566 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1569 void emit_slti32(int rs,int imm,int rt)
1571 if(rs!=rt) emit_zeroreg(rt);
1572 emit_cmpimm(rs,imm);
1573 if(rs==rt) emit_movimm(0,rt);
1574 emit_cmovl_imm(1,rt);
1576 void emit_sltiu32(int rs,int imm,int rt)
1578 if(rs!=rt) emit_zeroreg(rt);
1579 emit_cmpimm(rs,imm);
1580 if(rs==rt) emit_movimm(0,rt);
1581 emit_cmovb_imm(1,rt);
1583 void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1586 emit_slti32(rsl,imm,rt);
1590 emit_cmovne_imm(0,rt);
1591 emit_cmovs_imm(1,rt);
1595 emit_cmpimm(rsh,-1);
1596 emit_cmovne_imm(0,rt);
1597 emit_cmovl_imm(1,rt);
1600 void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1603 emit_sltiu32(rsl,imm,rt);
1607 emit_cmovne_imm(0,rt);
1611 emit_cmpimm(rsh,-1);
1612 emit_cmovne_imm(1,rt);
1616 void emit_cmp(int rs,int rt)
1618 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1619 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1621 void emit_set_gz32(int rs, int rt)
1623 //assem_debug("set_gz32\n");
1626 emit_cmovl_imm(0,rt);
1628 void emit_set_nz32(int rs, int rt)
1630 //assem_debug("set_nz32\n");
1631 if(rs!=rt) emit_movs(rs,rt);
1632 else emit_test(rs,rs);
1633 emit_cmovne_imm(1,rt);
1635 void emit_set_gz64_32(int rsh, int rsl, int rt)
1637 //assem_debug("set_gz64\n");
1638 emit_set_gz32(rsl,rt);
1640 emit_cmovne_imm(1,rt);
1641 emit_cmovs_imm(0,rt);
1643 void emit_set_nz64_32(int rsh, int rsl, int rt)
1645 //assem_debug("set_nz64\n");
1646 emit_or_and_set_flags(rsh,rsl,rt);
1647 emit_cmovne_imm(1,rt);
1649 void emit_set_if_less32(int rs1, int rs2, int rt)
1651 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1652 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1654 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1655 emit_cmovl_imm(1,rt);
1657 void emit_set_if_carry32(int rs1, int rs2, int rt)
1659 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1660 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1662 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1663 emit_cmovb_imm(1,rt);
1665 void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1667 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1672 emit_sbcs(u1,u2,HOST_TEMPREG);
1673 emit_cmovl_imm(1,rt);
1675 void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1677 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1682 emit_sbcs(u1,u2,HOST_TEMPREG);
1683 emit_cmovb_imm(1,rt);
1686 void emit_call(int a)
1688 assem_debug("bl %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1689 u_int offset=genjmp(a);
1690 output_w32(0xeb000000|offset);
1692 void emit_jmp(int a)
1694 assem_debug("b %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1695 u_int offset=genjmp(a);
1696 output_w32(0xea000000|offset);
1698 void emit_jne(int a)
1700 assem_debug("bne %x\n",a);
1701 u_int offset=genjmp(a);
1702 output_w32(0x1a000000|offset);
1704 void emit_jeq(int a)
1706 assem_debug("beq %x\n",a);
1707 u_int offset=genjmp(a);
1708 output_w32(0x0a000000|offset);
1712 assem_debug("bmi %x\n",a);
1713 u_int offset=genjmp(a);
1714 output_w32(0x4a000000|offset);
1716 void emit_jns(int a)
1718 assem_debug("bpl %x\n",a);
1719 u_int offset=genjmp(a);
1720 output_w32(0x5a000000|offset);
1724 assem_debug("blt %x\n",a);
1725 u_int offset=genjmp(a);
1726 output_w32(0xba000000|offset);
1728 void emit_jge(int a)
1730 assem_debug("bge %x\n",a);
1731 u_int offset=genjmp(a);
1732 output_w32(0xaa000000|offset);
1734 void emit_jno(int a)
1736 assem_debug("bvc %x\n",a);
1737 u_int offset=genjmp(a);
1738 output_w32(0x7a000000|offset);
1742 assem_debug("bcs %x\n",a);
1743 u_int offset=genjmp(a);
1744 output_w32(0x2a000000|offset);
1746 void emit_jcc(int a)
1748 assem_debug("bcc %x\n",a);
1749 u_int offset=genjmp(a);
1750 output_w32(0x3a000000|offset);
1753 void emit_pushimm(int imm)
1755 assem_debug("push $%x\n",imm);
1760 assem_debug("pusha\n");
1765 assem_debug("popa\n");
1768 void emit_pushreg(u_int r)
1770 assem_debug("push %%%s\n",regname[r]);
1773 void emit_popreg(u_int r)
1775 assem_debug("pop %%%s\n",regname[r]);
1778 void emit_callreg(u_int r)
1781 assem_debug("blx %s\n",regname[r]);
1782 output_w32(0xe12fff30|r);
1784 void emit_jmpreg(u_int r)
1786 assem_debug("mov pc,%s\n",regname[r]);
1787 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1790 void emit_readword_indexed(int offset, int rs, int rt)
1792 assert(offset>-4096&&offset<4096);
1793 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1795 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1797 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1800 void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1802 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1803 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1805 void emit_ldrcc_dualindexed(int rs1, int rs2, int rt)
1807 assem_debug("ldrcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1808 output_w32(0x37900000|rd_rn_rm(rt,rs1,rs2));
1810 void emit_ldrccb_dualindexed(int rs1, int rs2, int rt)
1812 assem_debug("ldrccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1813 output_w32(0x37d00000|rd_rn_rm(rt,rs1,rs2));
1815 void emit_ldrccsb_dualindexed(int rs1, int rs2, int rt)
1817 assem_debug("ldrccsb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1818 output_w32(0x319000d0|rd_rn_rm(rt,rs1,rs2));
1820 void emit_ldrcch_dualindexed(int rs1, int rs2, int rt)
1822 assem_debug("ldrcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1823 output_w32(0x319000b0|rd_rn_rm(rt,rs1,rs2));
1825 void emit_ldrccsh_dualindexed(int rs1, int rs2, int rt)
1827 assem_debug("ldrccsh %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1828 output_w32(0x319000f0|rd_rn_rm(rt,rs1,rs2));
1830 void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1832 if(map<0) emit_readword_indexed(addr, rs, rt);
1835 emit_readword_dualindexedx4(rs, map, rt);
1838 void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1841 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1842 emit_readword_indexed(addr+4, rs, rl);
1845 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1846 emit_addimm(map,1,map);
1847 emit_readword_indexed_tlb(addr, rs, map, rl);
1850 void emit_movsbl_indexed(int offset, int rs, int rt)
1852 assert(offset>-256&&offset<256);
1853 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1855 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1857 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1860 void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1862 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1865 emit_shlimm(map,2,map);
1866 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1867 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1869 assert(addr>-256&&addr<256);
1870 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1871 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1872 emit_movsbl_indexed(addr, rt, rt);
1876 void emit_movswl_indexed(int offset, int rs, int rt)
1878 assert(offset>-256&&offset<256);
1879 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1881 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1883 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1886 void emit_movzbl_indexed(int offset, int rs, int rt)
1888 assert(offset>-4096&&offset<4096);
1889 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1891 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1893 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1896 void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1898 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1899 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1901 void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1903 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1906 emit_movzbl_dualindexedx4(rs, map, rt);
1908 emit_addimm(rs,addr,rt);
1909 emit_movzbl_dualindexedx4(rt, map, rt);
1913 void emit_movzwl_indexed(int offset, int rs, int rt)
1915 assert(offset>-256&&offset<256);
1916 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1918 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1920 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1923 void emit_readword(int addr, int rt)
1925 u_int offset = addr-(u_int)&dynarec_local;
1926 assert(offset<4096);
1927 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1928 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1930 void emit_movsbl(int addr, int rt)
1932 u_int offset = addr-(u_int)&dynarec_local;
1934 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1935 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1937 void emit_movswl(int addr, int rt)
1939 u_int offset = addr-(u_int)&dynarec_local;
1941 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1942 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1944 void emit_movzbl(int addr, int rt)
1946 u_int offset = addr-(u_int)&dynarec_local;
1947 assert(offset<4096);
1948 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1949 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1951 void emit_movzwl(int addr, int rt)
1953 u_int offset = addr-(u_int)&dynarec_local;
1955 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1956 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1958 void emit_movzwl_reg(int rs, int rt)
1960 assem_debug("movzwl %%%s,%%%s\n",regname[rs]+1,regname[rt]);
1964 void emit_xchg(int rs, int rt)
1966 assem_debug("xchg %%%s,%%%s\n",regname[rs],regname[rt]);
1969 void emit_writeword_indexed(int rt, int offset, int rs)
1971 assert(offset>-4096&&offset<4096);
1972 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
1974 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
1976 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
1979 void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
1981 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1982 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
1984 void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1986 if(map<0) emit_writeword_indexed(rt, addr, rs);
1989 emit_writeword_dualindexedx4(rt, rs, map);
1992 void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
1995 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
1996 emit_writeword_indexed(rl, addr+4, rs);
1999 if(temp!=rs) emit_addimm(map,1,temp);
2000 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
2001 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
2003 emit_addimm(rs,4,rs);
2004 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
2008 void emit_writehword_indexed(int rt, int offset, int rs)
2010 assert(offset>-256&&offset<256);
2011 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
2013 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
2015 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
2018 void emit_writebyte_indexed(int rt, int offset, int rs)
2020 assert(offset>-4096&&offset<4096);
2021 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
2023 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
2025 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
2028 void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
2030 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
2031 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
2033 void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
2035 if(map<0) emit_writebyte_indexed(rt, addr, rs);
2038 emit_writebyte_dualindexedx4(rt, rs, map);
2040 emit_addimm(rs,addr,temp);
2041 emit_writebyte_dualindexedx4(rt, temp, map);
2045 void emit_strcc_dualindexed(int rs1, int rs2, int rt)
2047 assem_debug("strcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2048 output_w32(0x37800000|rd_rn_rm(rt,rs1,rs2));
2050 void emit_strccb_dualindexed(int rs1, int rs2, int rt)
2052 assem_debug("strccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2053 output_w32(0x37c00000|rd_rn_rm(rt,rs1,rs2));
2055 void emit_strcch_dualindexed(int rs1, int rs2, int rt)
2057 assem_debug("strcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2058 output_w32(0x318000b0|rd_rn_rm(rt,rs1,rs2));
2060 void emit_writeword(int rt, int addr)
2062 u_int offset = addr-(u_int)&dynarec_local;
2063 assert(offset<4096);
2064 assem_debug("str %s,fp+%d\n",regname[rt],offset);
2065 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
2067 void emit_writehword(int rt, int addr)
2069 u_int offset = addr-(u_int)&dynarec_local;
2071 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
2072 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
2074 void emit_writebyte(int rt, int addr)
2076 u_int offset = addr-(u_int)&dynarec_local;
2077 assert(offset<4096);
2078 assem_debug("strb %s,fp+%d\n",regname[rt],offset);
2079 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
2081 void emit_writeword_imm(int imm, int addr)
2083 assem_debug("movl $%x,%x\n",imm,addr);
2086 void emit_writebyte_imm(int imm, int addr)
2088 assem_debug("movb $%x,%x\n",imm,addr);
2092 void emit_mul(int rs)
2094 assem_debug("mul %%%s\n",regname[rs]);
2097 void emit_imul(int rs)
2099 assem_debug("imul %%%s\n",regname[rs]);
2102 void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2104 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2109 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2111 void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2113 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2118 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2121 void emit_div(int rs)
2123 assem_debug("div %%%s\n",regname[rs]);
2126 void emit_idiv(int rs)
2128 assem_debug("idiv %%%s\n",regname[rs]);
2133 assem_debug("cdq\n");
2137 void emit_clz(int rs,int rt)
2139 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
2140 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
2143 void emit_subcs(int rs1,int rs2,int rt)
2145 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2146 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
2149 void emit_shrcc_imm(int rs,u_int imm,int rt)
2153 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2154 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2157 void emit_negmi(int rs, int rt)
2159 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
2160 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2163 void emit_negsmi(int rs, int rt)
2165 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2166 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2169 void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2171 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2172 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2175 void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2177 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2178 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2181 void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2183 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2184 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2187 void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2189 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2190 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2193 void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2195 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2196 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2199 void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2201 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2202 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2205 void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2207 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2208 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2211 void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2213 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2214 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2217 void emit_teq(int rs, int rt)
2219 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2220 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2223 void emit_rsbimm(int rs, int imm, int rt)
2226 genimm_checked(imm,&armval);
2227 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2228 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2231 // Load 2 immediates optimizing for small code size
2232 void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2234 emit_movimm(imm1,rt1);
2236 if(genimm(imm2-imm1,&armval)) {
2237 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2238 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2239 }else if(genimm(imm1-imm2,&armval)) {
2240 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2241 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2243 else emit_movimm(imm2,rt2);
2246 // Conditionally select one of two immediates, optimizing for small code size
2247 // This will only be called if HAVE_CMOV_IMM is defined
2248 void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2251 if(genimm(imm2-imm1,&armval)) {
2252 emit_movimm(imm1,rt);
2253 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2254 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2255 }else if(genimm(imm1-imm2,&armval)) {
2256 emit_movimm(imm1,rt);
2257 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2258 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2262 emit_movimm(imm1,rt);
2263 add_literal((int)out,imm2);
2264 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2265 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2267 emit_movw(imm1&0x0000FFFF,rt);
2268 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2269 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2270 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2272 emit_movt(imm1&0xFFFF0000,rt);
2273 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2274 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2275 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2281 // special case for checking invalid_code
2282 void emit_cmpmem_indexedsr12_imm(int addr,int r,int imm)
2287 // special case for checking invalid_code
2288 void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2290 assert(imm<128&&imm>=0);
2292 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2293 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2294 emit_cmpimm(HOST_TEMPREG,imm);
2297 // special case for tlb mapping
2298 void emit_addsr12(int rs1,int rs2,int rt)
2300 assem_debug("add %s,%s,%s lsr #12\n",regname[rt],regname[rs1],regname[rs2]);
2301 output_w32(0xe0800620|rd_rn_rm(rt,rs1,rs2));
2304 void emit_callne(int a)
2306 assem_debug("blne %x\n",a);
2307 u_int offset=genjmp(a);
2308 output_w32(0x1b000000|offset);
2311 // Used to preload hash table entries
2312 void emit_prefetch(void *addr)
2314 assem_debug("prefetch %x\n",(int)addr);
2317 output_modrm(0,5,1);
2318 output_w32((int)addr);
2320 void emit_prefetchreg(int r)
2322 assem_debug("pld %s\n",regname[r]);
2323 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2326 // Special case for mini_ht
2327 void emit_ldreq_indexed(int rs, u_int offset, int rt)
2329 assert(offset<4096);
2330 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2331 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2334 void emit_flds(int r,int sr)
2336 assem_debug("flds s%d,[%s]\n",sr,regname[r]);
2337 output_w32(0xed900a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2340 void emit_vldr(int r,int vr)
2342 assem_debug("vldr d%d,[%s]\n",vr,regname[r]);
2343 output_w32(0xed900b00|(vr<<12)|(r<<16));
2346 void emit_fsts(int sr,int r)
2348 assem_debug("fsts s%d,[%s]\n",sr,regname[r]);
2349 output_w32(0xed800a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2352 void emit_vstr(int vr,int r)
2354 assem_debug("vstr d%d,[%s]\n",vr,regname[r]);
2355 output_w32(0xed800b00|(vr<<12)|(r<<16));
2358 void emit_ftosizs(int s,int d)
2360 assem_debug("ftosizs s%d,s%d\n",d,s);
2361 output_w32(0xeebd0ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2364 void emit_ftosizd(int s,int d)
2366 assem_debug("ftosizd s%d,d%d\n",d,s);
2367 output_w32(0xeebd0bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2370 void emit_fsitos(int s,int d)
2372 assem_debug("fsitos s%d,s%d\n",d,s);
2373 output_w32(0xeeb80ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2376 void emit_fsitod(int s,int d)
2378 assem_debug("fsitod d%d,s%d\n",d,s);
2379 output_w32(0xeeb80bc0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2382 void emit_fcvtds(int s,int d)
2384 assem_debug("fcvtds d%d,s%d\n",d,s);
2385 output_w32(0xeeb70ac0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2388 void emit_fcvtsd(int s,int d)
2390 assem_debug("fcvtsd s%d,d%d\n",d,s);
2391 output_w32(0xeeb70bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2394 void emit_fsqrts(int s,int d)
2396 assem_debug("fsqrts d%d,s%d\n",d,s);
2397 output_w32(0xeeb10ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2400 void emit_fsqrtd(int s,int d)
2402 assem_debug("fsqrtd s%d,d%d\n",d,s);
2403 output_w32(0xeeb10bc0|((d&7)<<12)|(s&7));
2406 void emit_fabss(int s,int d)
2408 assem_debug("fabss d%d,s%d\n",d,s);
2409 output_w32(0xeeb00ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2412 void emit_fabsd(int s,int d)
2414 assem_debug("fabsd s%d,d%d\n",d,s);
2415 output_w32(0xeeb00bc0|((d&7)<<12)|(s&7));
2418 void emit_fnegs(int s,int d)
2420 assem_debug("fnegs d%d,s%d\n",d,s);
2421 output_w32(0xeeb10a40|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2424 void emit_fnegd(int s,int d)
2426 assem_debug("fnegd s%d,d%d\n",d,s);
2427 output_w32(0xeeb10b40|((d&7)<<12)|(s&7));
2430 void emit_fadds(int s1,int s2,int d)
2432 assem_debug("fadds s%d,s%d,s%d\n",d,s1,s2);
2433 output_w32(0xee300a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2436 void emit_faddd(int s1,int s2,int d)
2438 assem_debug("faddd d%d,d%d,d%d\n",d,s1,s2);
2439 output_w32(0xee300b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2442 void emit_fsubs(int s1,int s2,int d)
2444 assem_debug("fsubs s%d,s%d,s%d\n",d,s1,s2);
2445 output_w32(0xee300a40|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2448 void emit_fsubd(int s1,int s2,int d)
2450 assem_debug("fsubd d%d,d%d,d%d\n",d,s1,s2);
2451 output_w32(0xee300b40|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2454 void emit_fmuls(int s1,int s2,int d)
2456 assem_debug("fmuls s%d,s%d,s%d\n",d,s1,s2);
2457 output_w32(0xee200a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2460 void emit_fmuld(int s1,int s2,int d)
2462 assem_debug("fmuld d%d,d%d,d%d\n",d,s1,s2);
2463 output_w32(0xee200b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2466 void emit_fdivs(int s1,int s2,int d)
2468 assem_debug("fdivs s%d,s%d,s%d\n",d,s1,s2);
2469 output_w32(0xee800a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2472 void emit_fdivd(int s1,int s2,int d)
2474 assem_debug("fdivd d%d,d%d,d%d\n",d,s1,s2);
2475 output_w32(0xee800b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2478 void emit_fcmps(int x,int y)
2480 assem_debug("fcmps s14, s15\n");
2481 output_w32(0xeeb47a67);
2484 void emit_fcmpd(int x,int y)
2486 assem_debug("fcmpd d6, d7\n");
2487 output_w32(0xeeb46b47);
2492 assem_debug("fmstat\n");
2493 output_w32(0xeef1fa10);
2496 void emit_bicne_imm(int rs,int imm,int rt)
2499 genimm_checked(imm,&armval);
2500 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2501 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2504 void emit_biccs_imm(int rs,int imm,int rt)
2507 genimm_checked(imm,&armval);
2508 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2509 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2512 void emit_bicvc_imm(int rs,int imm,int rt)
2515 genimm_checked(imm,&armval);
2516 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2517 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2520 void emit_bichi_imm(int rs,int imm,int rt)
2523 genimm_checked(imm,&armval);
2524 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2525 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2528 void emit_orrvs_imm(int rs,int imm,int rt)
2531 genimm_checked(imm,&armval);
2532 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2533 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2536 void emit_orrne_imm(int rs,int imm,int rt)
2539 genimm_checked(imm,&armval);
2540 assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2541 output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
2544 void emit_andne_imm(int rs,int imm,int rt)
2547 genimm_checked(imm,&armval);
2548 assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2549 output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
2552 void emit_jno_unlikely(int a)
2555 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2556 output_w32(0x72800000|rd_rn_rm(15,15,0));
2559 // Save registers before function call
2560 void save_regs(u_int reglist)
2562 reglist&=0x100f; // only save the caller-save registers, r0-r3, r12
2563 if(!reglist) return;
2564 assem_debug("stmia fp,{");
2565 if(reglist&1) assem_debug("r0, ");
2566 if(reglist&2) assem_debug("r1, ");
2567 if(reglist&4) assem_debug("r2, ");
2568 if(reglist&8) assem_debug("r3, ");
2569 if(reglist&0x1000) assem_debug("r12");
2571 output_w32(0xe88b0000|reglist);
2573 // Restore registers after function call
2574 void restore_regs(u_int reglist)
2576 reglist&=0x100f; // only restore the caller-save registers, r0-r3, r12
2577 if(!reglist) return;
2578 assem_debug("ldmia fp,{");
2579 if(reglist&1) assem_debug("r0, ");
2580 if(reglist&2) assem_debug("r1, ");
2581 if(reglist&4) assem_debug("r2, ");
2582 if(reglist&8) assem_debug("r3, ");
2583 if(reglist&0x1000) assem_debug("r12");
2585 output_w32(0xe89b0000|reglist);
2588 // Write back consts using r14 so we don't disturb the other registers
2589 void wb_consts(signed char i_regmap[],uint64_t i_is32,u_int i_dirty,int i)
2592 for(hr=0;hr<HOST_REGS;hr++) {
2593 if(hr!=EXCLUDE_REG&&i_regmap[hr]>=0&&((i_dirty>>hr)&1)) {
2594 if(((regs[i].isconst>>hr)&1)&&i_regmap[hr]>0) {
2595 if(i_regmap[hr]<64 || !((i_is32>>(i_regmap[hr]&63))&1) ) {
2596 int value=constmap[i][hr];
2598 emit_zeroreg(HOST_TEMPREG);
2601 emit_movimm(value,HOST_TEMPREG);
2603 emit_storereg(i_regmap[hr],HOST_TEMPREG);
2605 if((i_is32>>i_regmap[hr])&1) {
2606 if(value!=-1&&value!=0) emit_sarimm(HOST_TEMPREG,31,HOST_TEMPREG);
2607 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
2616 /* Stubs/epilogue */
2618 void literal_pool(int n)
2620 if(!literalcount) return;
2622 if((int)out-literals[0][0]<4096-n) return;
2626 for(i=0;i<literalcount;i++)
2628 ptr=(u_int *)literals[i][0];
2629 u_int offset=(u_int)out-(u_int)ptr-8;
2630 assert(offset<4096);
2631 assert(!(offset&3));
2633 output_w32(literals[i][1]);
2638 void literal_pool_jumpover(int n)
2640 if(!literalcount) return;
2642 if((int)out-literals[0][0]<4096-n) return;
2647 set_jump_target(jaddr,(int)out);
2650 emit_extjump2(int addr, int target, int linker)
2652 u_char *ptr=(u_char *)addr;
2653 assert((ptr[3]&0x0e)==0xa);
2654 emit_loadlp(target,0);
2655 emit_loadlp(addr,1);
2656 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
2657 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2659 #ifdef DEBUG_CYCLE_COUNT
2660 emit_readword((int)&last_count,ECX);
2661 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2662 emit_readword((int)&next_interupt,ECX);
2663 emit_writeword(HOST_CCREG,(int)&Count);
2664 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2665 emit_writeword(ECX,(int)&last_count);
2671 emit_extjump(int addr, int target)
2673 emit_extjump2(addr, target, (int)dyna_linker);
2675 emit_extjump_ds(int addr, int target)
2677 emit_extjump2(addr, target, (int)dyna_linker_ds);
2681 #include "pcsxmem_inline.c"
2685 static void pass_args(int a0, int a1)
2689 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2691 else if(a0!=0&&a1==0) {
2693 if (a0>=0) emit_mov(a0,0);
2696 if(a0>=0&&a0!=0) emit_mov(a0,0);
2697 if(a1>=0&&a1!=1) emit_mov(a1,1);
2703 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2705 set_jump_target(stubs[n][1],(int)out);
2706 int type=stubs[n][0];
2709 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2710 u_int reglist=stubs[n][7];
2711 signed char *i_regmap=i_regs->regmap;
2712 int addr=get_reg(i_regmap,AGEN1+(i&1));
2715 if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
2716 rth=get_reg(i_regmap,FTEMP|64);
2717 rt=get_reg(i_regmap,FTEMP);
2719 rth=get_reg(i_regmap,rt1[i]|64);
2720 rt=get_reg(i_regmap,rt1[i]);
2724 int r,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0;
2726 for(r=0;r<=12;r++) {
2727 if(((1<<r)&0x13ff)&&((1<<r)®list)==0) {
2738 if((regs_saved||(reglist&2)==0)&&temp!=1&&rs!=1)
2740 emit_readword((int)&mem_rtab,temp);
2741 emit_shrimm(rs,12,temp2);
2742 emit_readword_dualindexedx4(temp,temp2,temp2);
2743 emit_lsls_imm(temp2,1,temp2);
2744 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2746 case LOADB_STUB: emit_ldrccsb_dualindexed(temp2,rs,rt); break;
2747 case LOADBU_STUB: emit_ldrccb_dualindexed(temp2,rs,rt); break;
2748 case LOADH_STUB: emit_ldrccsh_dualindexed(temp2,rs,rt); break;
2749 case LOADHU_STUB: emit_ldrcch_dualindexed(temp2,rs,rt); break;
2750 case LOADW_STUB: emit_ldrcc_dualindexed(temp2,rs,rt); break;
2754 restore_jump=(int)out;
2755 emit_jcc(0); // jump to reg restore
2758 emit_jcc(stubs[n][2]); // return address
2763 if(type==LOADB_STUB||type==LOADBU_STUB)
2764 handler=(int)jump_handler_read8;
2765 if(type==LOADH_STUB||type==LOADHU_STUB)
2766 handler=(int)jump_handler_read16;
2767 if(type==LOADW_STUB)
2768 handler=(int)jump_handler_read32;
2770 pass_args(rs,temp2);
2771 int cc=get_reg(i_regmap,CCREG);
2773 emit_loadreg(CCREG,2);
2774 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*stubs[n][6]+2,2);
2776 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2778 case LOADB_STUB: emit_signextend8(0,rt); break;
2779 case LOADBU_STUB: emit_andimm(0,0xff,rt); break;
2780 case LOADH_STUB: emit_signextend16(0,rt); break;
2781 case LOADHU_STUB: emit_andimm(0,0xffff,rt); break;
2782 case LOADW_STUB: if(rt!=0) emit_mov(0,rt); break;
2786 set_jump_target(restore_jump,(int)out);
2787 restore_regs(reglist);
2788 emit_jmp(stubs[n][2]); // return address
2791 if(addr<0&&itype[i]!=C1LS&&itype[i]!=C2LS&&itype[i]!=LOADLR) addr=get_reg(i_regmap,-1);
2794 if(type==LOADB_STUB||type==LOADBU_STUB)
2795 ftable=(int)readmemb;
2796 if(type==LOADH_STUB||type==LOADHU_STUB)
2797 ftable=(int)readmemh;
2798 if(type==LOADW_STUB)
2799 ftable=(int)readmem;
2801 if(type==LOADD_STUB)
2802 ftable=(int)readmemd;
2805 emit_writeword(rs,(int)&address);
2809 ds=i_regs!=®s[i];
2810 int real_rs=(itype[i]==LOADLR)?-1:get_reg(i_regmap,rs1[i]);
2811 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2812 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2813 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2814 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2816 emit_shrimm(rs,16,1);
2817 int cc=get_reg(i_regmap,CCREG);
2819 emit_loadreg(CCREG,2);
2821 emit_movimm(ftable,0);
2822 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2824 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2826 //emit_readword((int)&last_count,temp);
2827 //emit_add(cc,temp,cc);
2828 //emit_writeword(cc,(int)&Count);
2830 emit_call((int)&indirect_jump_indexed);
2832 //emit_readword_dualindexedx4(rs,HOST_TEMPREG,15);
2834 // We really shouldn't need to update the count here,
2835 // but not doing so causes random crashes...
2836 emit_readword((int)&Count,HOST_TEMPREG);
2837 emit_readword((int)&next_interupt,2);
2838 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2839 emit_writeword(2,(int)&last_count);
2840 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2842 emit_storereg(CCREG,HOST_TEMPREG);
2846 restore_regs(reglist);
2847 //if((cc=get_reg(regmap,CCREG))>=0) {
2848 // emit_loadreg(CCREG,cc);
2850 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2852 if(type==LOADB_STUB)
2853 emit_movsbl((int)&readmem_dword,rt);
2854 if(type==LOADBU_STUB)
2855 emit_movzbl((int)&readmem_dword,rt);
2856 if(type==LOADH_STUB)
2857 emit_movswl((int)&readmem_dword,rt);
2858 if(type==LOADHU_STUB)
2859 emit_movzwl((int)&readmem_dword,rt);
2860 if(type==LOADW_STUB)
2861 emit_readword((int)&readmem_dword,rt);
2862 if(type==LOADD_STUB) {
2863 emit_readword((int)&readmem_dword,rt);
2864 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2867 emit_jmp(stubs[n][2]); // return address
2872 // return memhandler, or get directly accessable address and return 0
2873 u_int get_direct_memhandler(void *table,u_int addr,int type,u_int *addr_host)
2876 l1=((u_int *)table)[addr>>12];
2877 if((l1&(1<<31))==0) {
2884 if(type==LOADB_STUB||type==LOADBU_STUB||type==STOREB_STUB)
2885 l2=((u_int *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2886 else if(type==LOADH_STUB||type==LOADHU_STUB||type==STOREH_STUB)
2887 l2=((u_int *)l1)[0x1000/4 + (addr&0xfff)/2];
2889 l2=((u_int *)l1)[(addr&0xfff)/4];
2890 if((l2&(1<<31))==0) {
2892 *addr_host=v+(addr&0xfff);
2900 inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2902 int rs=get_reg(regmap,target);
2903 int rth=get_reg(regmap,target|64);
2904 int rt=get_reg(regmap,target);
2905 if(rs<0) rs=get_reg(regmap,-1);
2908 u_int handler,host_addr=0;
2909 if(pcsx_direct_read(type,addr,target?rs:-1,rt))
2911 handler=get_direct_memhandler(mem_rtab,addr,type,&host_addr);
2915 if(target==0||addr!=host_addr)
2916 emit_movimm(host_addr,rs);
2918 case LOADB_STUB: emit_movsbl_indexed(0,rs,rt); break;
2919 case LOADBU_STUB: emit_movzbl_indexed(0,rs,rt); break;
2920 case LOADH_STUB: emit_movswl_indexed(0,rs,rt); break;
2921 case LOADHU_STUB: emit_movzwl_indexed(0,rs,rt); break;
2922 case LOADW_STUB: emit_readword_indexed(0,rs,rt); break;
2928 // call a memhandler
2933 emit_movimm(addr,0);
2936 int cc=get_reg(regmap,CCREG);
2938 emit_loadreg(CCREG,2);
2939 emit_readword((int)&last_count,3);
2940 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
2942 emit_writeword(3,(int)&Count);
2944 int offset=(int)handler-(int)out-8;
2945 if(offset<-33554432||offset>=33554432) {
2946 // unreachable memhandler, a plugin func perhaps
2947 emit_movimm(handler,1);
2954 case LOADB_STUB: emit_signextend8(0,rt); break;
2955 case LOADBU_STUB: emit_andimm(0,0xff,rt); break;
2956 case LOADH_STUB: emit_signextend16(0,rt); break;
2957 case LOADHU_STUB: emit_andimm(0,0xffff,rt); break;
2958 case LOADW_STUB: if(rt!=0) emit_mov(0,rt); break;
2962 restore_regs(reglist);
2965 if(type==LOADB_STUB||type==LOADBU_STUB)
2966 ftable=(int)readmemb;
2967 if(type==LOADH_STUB||type==LOADHU_STUB)
2968 ftable=(int)readmemh;
2969 if(type==LOADW_STUB)
2970 ftable=(int)readmem;
2972 if(type==LOADD_STUB)
2973 ftable=(int)readmemd;
2977 emit_movimm(addr,rs);
2978 emit_writeword(rs,(int)&address);
2982 if((signed int)addr>=(signed int)0xC0000000) {
2983 // Theoretically we can have a pagefault here, if the TLB has never
2984 // been enabled and the address is outside the range 80000000..BFFFFFFF
2985 // Write out the registers so the pagefault can be handled. This is
2986 // a very rare case and likely represents a bug.
2987 int ds=regmap!=regs[i].regmap;
2988 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
2989 if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
2990 else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty);
2993 //emit_shrimm(rs,16,1);
2994 int cc=get_reg(regmap,CCREG);
2996 emit_loadreg(CCREG,2);
2998 //emit_movimm(ftable,0);
2999 emit_movimm(((u_int *)ftable)[addr>>16],0);
3000 //emit_readword((int)&last_count,12);
3001 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
3003 if((signed int)addr>=(signed int)0xC0000000) {
3004 // Pagefault address
3005 int ds=regmap!=regs[i].regmap;
3006 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3010 //emit_writeword(2,(int)&Count);
3011 //emit_call(((u_int *)ftable)[addr>>16]);
3012 emit_call((int)&indirect_jump);
3014 // We really shouldn't need to update the count here,
3015 // but not doing so causes random crashes...
3016 emit_readword((int)&Count,HOST_TEMPREG);
3017 emit_readword((int)&next_interupt,2);
3018 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
3019 emit_writeword(2,(int)&last_count);
3020 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3022 emit_storereg(CCREG,HOST_TEMPREG);
3026 restore_regs(reglist);
3028 if(type==LOADB_STUB)
3029 emit_movsbl((int)&readmem_dword,rt);
3030 if(type==LOADBU_STUB)
3031 emit_movzbl((int)&readmem_dword,rt);
3032 if(type==LOADH_STUB)
3033 emit_movswl((int)&readmem_dword,rt);
3034 if(type==LOADHU_STUB)
3035 emit_movzwl((int)&readmem_dword,rt);
3036 if(type==LOADW_STUB)
3037 emit_readword((int)&readmem_dword,rt);
3038 if(type==LOADD_STUB) {
3039 emit_readword((int)&readmem_dword,rt);
3040 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
3048 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
3050 set_jump_target(stubs[n][1],(int)out);
3051 int type=stubs[n][0];
3054 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3055 u_int reglist=stubs[n][7];
3056 signed char *i_regmap=i_regs->regmap;
3057 int addr=get_reg(i_regmap,AGEN1+(i&1));
3060 if(itype[i]==C1LS||itype[i]==C2LS) {
3061 rth=get_reg(i_regmap,FTEMP|64);
3062 rt=get_reg(i_regmap,r=FTEMP);
3064 rth=get_reg(i_regmap,rs2[i]|64);
3065 rt=get_reg(i_regmap,r=rs2[i]);
3070 int rtmp,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0,ra;
3071 int reglist2=reglist|(1<<rs)|(1<<rt);
3072 for(rtmp=0;rtmp<=12;rtmp++) {
3073 if(((1<<rtmp)&0x13ff)&&((1<<rtmp)®list2)==0) {
3080 for(rtmp=0;rtmp<=3;rtmp++)
3081 if(rtmp!=rs&&rtmp!=rt)
3084 if((regs_saved||(reglist2&8)==0)&&temp!=3&&rs!=3&&rt!=3)
3086 emit_readword((int)&mem_wtab,temp);
3087 emit_shrimm(rs,12,temp2);
3088 emit_readword_dualindexedx4(temp,temp2,temp2);
3089 emit_lsls_imm(temp2,1,temp2);
3091 case STOREB_STUB: emit_strccb_dualindexed(temp2,rs,rt); break;
3092 case STOREH_STUB: emit_strcch_dualindexed(temp2,rs,rt); break;
3093 case STOREW_STUB: emit_strcc_dualindexed(temp2,rs,rt); break;
3097 restore_jump=(int)out;
3098 emit_jcc(0); // jump to reg restore
3101 emit_jcc(stubs[n][2]); // return address (invcode check)
3107 case STOREB_STUB: handler=(int)jump_handler_write8; break;
3108 case STOREH_STUB: handler=(int)jump_handler_write16; break;
3109 case STOREW_STUB: handler=(int)jump_handler_write32; break;
3115 int cc=get_reg(i_regmap,CCREG);
3117 emit_loadreg(CCREG,2);
3118 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*stubs[n][6]+2,2);
3119 // returns new cycle_count
3121 emit_addimm(0,-CLOCK_DIVIDER*stubs[n][6]-2,cc<0?2:cc);
3123 emit_storereg(CCREG,2);
3125 set_jump_target(restore_jump,(int)out);
3126 restore_regs(reglist);
3128 if(!restore_jump) ra+=4*3; // skip invcode check
3131 if(addr<0) addr=get_reg(i_regmap,-1);
3134 if(type==STOREB_STUB)
3135 ftable=(int)writememb;
3136 if(type==STOREH_STUB)
3137 ftable=(int)writememh;
3138 if(type==STOREW_STUB)
3139 ftable=(int)writemem;
3141 if(type==STORED_STUB)
3142 ftable=(int)writememd;
3145 emit_writeword(rs,(int)&address);
3146 //emit_shrimm(rs,16,rs);
3147 //emit_movmem_indexedx4(ftable,rs,rs);
3148 if(type==STOREB_STUB)
3149 emit_writebyte(rt,(int)&byte);
3150 if(type==STOREH_STUB)
3151 emit_writehword(rt,(int)&hword);
3152 if(type==STOREW_STUB)
3153 emit_writeword(rt,(int)&word);
3154 if(type==STORED_STUB) {
3156 emit_writeword(rt,(int)&dword);
3157 emit_writeword(r?rth:rt,(int)&dword+4);
3159 printf("STORED_STUB\n");
3165 ds=i_regs!=®s[i];
3166 int real_rs=get_reg(i_regmap,rs1[i]);
3167 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
3168 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
3169 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
3170 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
3172 emit_shrimm(rs,16,1);
3173 int cc=get_reg(i_regmap,CCREG);
3175 emit_loadreg(CCREG,2);
3177 emit_movimm(ftable,0);
3178 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
3180 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3182 //emit_readword((int)&last_count,temp);
3183 //emit_addimm(cc,2*stubs[n][5]+2,cc);
3184 //emit_add(cc,temp,cc);
3185 //emit_writeword(cc,(int)&Count);
3186 emit_call((int)&indirect_jump_indexed);
3188 emit_readword((int)&Count,HOST_TEMPREG);
3189 emit_readword((int)&next_interupt,2);
3190 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
3191 emit_writeword(2,(int)&last_count);
3192 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3194 emit_storereg(CCREG,HOST_TEMPREG);
3197 restore_regs(reglist);
3198 //if((cc=get_reg(regmap,CCREG))>=0) {
3199 // emit_loadreg(CCREG,cc);
3201 emit_jmp(stubs[n][2]); // return address
3205 inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
3207 int rs=get_reg(regmap,-1);
3208 int rth=get_reg(regmap,target|64);
3209 int rt=get_reg(regmap,target);
3213 u_int handler,host_addr=0;
3214 if(pcsx_direct_write(type,addr,rs,rt,regmap))
3216 handler=get_direct_memhandler(mem_wtab,addr,type,&host_addr);
3218 if(target==0||addr!=host_addr)
3219 emit_movimm(host_addr,rs);
3221 case STOREB_STUB: emit_writebyte_indexed(rt,0,rs); break;
3222 case STOREH_STUB: emit_writehword_indexed(rt,0,rs); break;
3223 case STOREW_STUB: emit_writeword_indexed(rt,0,rs); break;
3229 // call a memhandler
3231 pass_args(target!=0?rs:-1,rt);
3233 emit_movimm(addr,0);
3234 int cc=get_reg(regmap,CCREG);
3236 emit_loadreg(CCREG,2);
3237 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
3238 emit_movimm(handler,3);
3239 // returns new cycle_count
3240 emit_call((int)jump_handler_write_h);
3241 emit_addimm(0,-CLOCK_DIVIDER*(adj+1),cc<0?2:cc);
3243 emit_storereg(CCREG,2);
3244 restore_regs(reglist);
3247 if(type==STOREB_STUB)
3248 ftable=(int)writememb;
3249 if(type==STOREH_STUB)
3250 ftable=(int)writememh;
3251 if(type==STOREW_STUB)
3252 ftable=(int)writemem;
3254 if(type==STORED_STUB)
3255 ftable=(int)writememd;
3258 emit_writeword(rs,(int)&address);
3259 //emit_shrimm(rs,16,rs);
3260 //emit_movmem_indexedx4(ftable,rs,rs);
3261 if(type==STOREB_STUB)
3262 emit_writebyte(rt,(int)&byte);
3263 if(type==STOREH_STUB)
3264 emit_writehword(rt,(int)&hword);
3265 if(type==STOREW_STUB)
3266 emit_writeword(rt,(int)&word);
3267 if(type==STORED_STUB) {
3269 emit_writeword(rt,(int)&dword);
3270 emit_writeword(target?rth:rt,(int)&dword+4);
3272 printf("STORED_STUB\n");
3278 // rearmed note: load_all_consts prevents BIOS boot, some bug?
3279 if((signed int)addr>=(signed int)0xC0000000) {
3280 // Theoretically we can have a pagefault here, if the TLB has never
3281 // been enabled and the address is outside the range 80000000..BFFFFFFF
3282 // Write out the registers so the pagefault can be handled. This is
3283 // a very rare case and likely represents a bug.
3284 int ds=regmap!=regs[i].regmap;
3285 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3286 if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3287 else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty);
3290 //emit_shrimm(rs,16,1);
3291 int cc=get_reg(regmap,CCREG);
3293 emit_loadreg(CCREG,2);
3295 //emit_movimm(ftable,0);
3296 emit_movimm(((u_int *)ftable)[addr>>16],0);
3297 //emit_readword((int)&last_count,12);
3298 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
3300 if((signed int)addr>=(signed int)0xC0000000) {
3301 // Pagefault address
3302 int ds=regmap!=regs[i].regmap;
3303 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3307 //emit_writeword(2,(int)&Count);
3308 //emit_call(((u_int *)ftable)[addr>>16]);
3309 emit_call((int)&indirect_jump);
3310 emit_readword((int)&Count,HOST_TEMPREG);
3311 emit_readword((int)&next_interupt,2);
3312 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
3313 emit_writeword(2,(int)&last_count);
3314 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3316 emit_storereg(CCREG,HOST_TEMPREG);
3319 restore_regs(reglist);
3323 do_unalignedwritestub(int n)
3325 assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
3327 set_jump_target(stubs[n][1],(int)out);
3330 struct regstat *i_regs=(struct regstat *)stubs[n][4];
3331 int addr=stubs[n][5];
3332 u_int reglist=stubs[n][7];
3333 signed char *i_regmap=i_regs->regmap;
3334 int temp2=get_reg(i_regmap,FTEMP);
3337 rt=get_reg(i_regmap,rs2[i]);
3340 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
3342 reglist&=~(1<<temp2);
3345 // don't bother with it and call write handler
3348 int cc=get_reg(i_regmap,CCREG);
3350 emit_loadreg(CCREG,2);
3351 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*stubs[n][6]+2,2);
3352 emit_call((int)(opcode[i]==0x2a?jump_handle_swl:jump_handle_swr));
3353 emit_addimm(0,-CLOCK_DIVIDER*stubs[n][6]-2,cc<0?2:cc);
3355 emit_storereg(CCREG,2);
3356 restore_regs(reglist);
3357 emit_jmp(stubs[n][2]); // return address
3359 emit_andimm(addr,0xfffffffc,temp2);
3360 emit_writeword(temp2,(int)&address);
3364 ds=i_regs!=®s[i];
3365 real_rs=get_reg(i_regmap,rs1[i]);
3366 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
3367 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
3368 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
3369 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
3371 emit_shrimm(addr,16,1);
3372 int cc=get_reg(i_regmap,CCREG);
3374 emit_loadreg(CCREG,2);
3376 emit_movimm((u_int)readmem,0);
3377 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
3379 // pagefault address
3380 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3382 emit_call((int)&indirect_jump_indexed);
3383 restore_regs(reglist);
3385 emit_readword((int)&readmem_dword,temp2);
3386 int temp=addr; //hmh
3387 emit_shlimm(addr,3,temp);
3388 emit_andimm(temp,24,temp);
3389 #ifdef BIG_ENDIAN_MIPS
3390 if (opcode[i]==0x2e) // SWR
3392 if (opcode[i]==0x2a) // SWL
3394 emit_xorimm(temp,24,temp);
3395 emit_movimm(-1,HOST_TEMPREG);
3396 if (opcode[i]==0x2a) { // SWL
3397 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
3398 emit_orrshr(rt,temp,temp2);
3400 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
3401 emit_orrshl(rt,temp,temp2);
3403 emit_readword((int)&address,addr);
3404 emit_writeword(temp2,(int)&word);
3405 //save_regs(reglist); // don't need to, no state changes
3406 emit_shrimm(addr,16,1);
3407 emit_movimm((u_int)writemem,0);
3408 //emit_call((int)&indirect_jump_indexed);
3410 emit_readword_dualindexedx4(0,1,15);
3411 emit_readword((int)&Count,HOST_TEMPREG);
3412 emit_readword((int)&next_interupt,2);
3413 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
3414 emit_writeword(2,(int)&last_count);
3415 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3417 emit_storereg(CCREG,HOST_TEMPREG);
3419 restore_regs(reglist);
3420 emit_jmp(stubs[n][2]); // return address
3424 void printregs(int edi,int esi,int ebp,int esp,int b,int d,int c,int a)
3426 printf("regs: %x %x %x %x %x %x %x (%x)\n",a,b,c,d,ebp,esi,edi,(&edi)[-1]);
3432 u_int reglist=stubs[n][3];
3433 set_jump_target(stubs[n][1],(int)out);
3435 if(stubs[n][4]!=0) emit_mov(stubs[n][4],0);
3436 emit_call((int)&invalidate_addr);
3437 restore_regs(reglist);
3438 emit_jmp(stubs[n][2]); // return address
3441 int do_dirty_stub(int i)
3443 assem_debug("do_dirty_stub %x\n",start+i*4);
3444 u_int addr=(int)start<(int)0xC0000000?(u_int)source:(u_int)start;
3448 // Careful about the code output here, verify_dirty needs to parse it.
3450 emit_loadlp(addr,1);
3451 emit_loadlp((int)copy,2);
3452 emit_loadlp(slen*4,3);
3454 emit_movw(addr&0x0000FFFF,1);
3455 emit_movw(((u_int)copy)&0x0000FFFF,2);
3456 emit_movt(addr&0xFFFF0000,1);
3457 emit_movt(((u_int)copy)&0xFFFF0000,2);
3458 emit_movw(slen*4,3);
3460 emit_movimm(start+i*4,0);
3461 emit_call((int)start<(int)0xC0000000?(int)&verify_code:(int)&verify_code_vm);
3464 if(entry==(int)out) entry=instr_addr[i];
3465 emit_jmp(instr_addr[i]);
3469 void do_dirty_stub_ds()
3471 // Careful about the code output here, verify_dirty needs to parse it.
3473 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
3474 emit_loadlp((int)copy,2);
3475 emit_loadlp(slen*4,3);
3477 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
3478 emit_movw(((u_int)copy)&0x0000FFFF,2);
3479 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
3480 emit_movt(((u_int)copy)&0xFFFF0000,2);
3481 emit_movw(slen*4,3);
3483 emit_movimm(start+1,0);
3484 emit_call((int)&verify_code_ds);
3490 assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
3491 set_jump_target(stubs[n][1],(int)out);
3493 // int rs=stubs[n][4];
3494 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3497 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3498 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3500 //else {printf("fp exception in delay slot\n");}
3501 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty);
3502 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3503 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3504 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3505 emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
3510 int do_tlb_r(int s,int ar,int map,int x,int a,int shift,int c,u_int addr)
3513 if((signed int)addr>=(signed int)0xC0000000) {
3514 // address_generation already loaded the const
3515 emit_readword_dualindexedx4(FP,map,map);
3518 return -1; // No mapping
3522 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3523 emit_addsr12(map,s,map);
3524 // Schedule this while we wait on the load
3525 //if(x) emit_xorimm(s,x,ar);
3526 if(shift>=0) emit_shlimm(s,3,shift);
3527 if(~a) emit_andimm(s,a,ar);
3528 emit_readword_dualindexedx4(FP,map,map);
3532 int do_tlb_r_branch(int map, int c, u_int addr, int *jaddr)
3534 if(!c||(signed int)addr>=(signed int)0xC0000000) {
3542 int gen_tlb_addr_r(int ar, int map) {
3544 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3545 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3549 int do_tlb_w(int s,int ar,int map,int x,int c,u_int addr)
3552 if(addr<0x80800000||addr>=0xC0000000) {
3553 // address_generation already loaded the const
3554 emit_readword_dualindexedx4(FP,map,map);
3557 return -1; // No mapping
3561 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3562 emit_addsr12(map,s,map);
3563 // Schedule this while we wait on the load
3564 //if(x) emit_xorimm(s,x,ar);