1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - assem_arm.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
21 extern int cycle_count;
22 extern int last_count;
24 extern int pending_exception;
25 extern int branch_target;
26 extern uint64_t readmem_dword;
28 extern precomp_instr fake_pc;
30 extern void *dynarec_local;
31 extern u_int memory_map[1048576];
32 extern u_int mini_ht[32][2];
33 extern u_int rounding_modes[4];
35 void indirect_jump_indexed();
48 void jump_vaddr_r10();
49 void jump_vaddr_r12();
51 const u_int jump_vaddr_reg[16] = {
73 void set_jump_target(int addr,u_int target)
75 u_char *ptr=(u_char *)addr;
76 u_int *ptr2=(u_int *)ptr;
78 assert((target-(u_int)ptr2-8)<1024);
80 assert((target&3)==0);
81 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
82 //printf("target=%x addr=%x insn=%x\n",target,addr,*ptr2);
84 else if(ptr[3]==0x72) {
85 // generated by emit_jno_unlikely
86 if((target-(u_int)ptr2-8)<1024) {
88 assert((target&3)==0);
89 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
91 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
93 assert((target&3)==0);
94 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
96 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
99 assert((ptr[3]&0x0e)==0xa);
100 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
104 // This optionally copies the instruction from the target of the branch into
105 // the space before the branch. Works, but the difference in speed is
106 // usually insignificant.
107 void set_jump_target_fillslot(int addr,u_int target,int copy)
109 u_char *ptr=(u_char *)addr;
110 u_int *ptr2=(u_int *)ptr;
111 assert(!copy||ptr2[-1]==0xe28dd000);
114 assert((target-(u_int)ptr2-8)<4096);
115 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
118 assert((ptr[3]&0x0e)==0xa);
119 u_int target_insn=*(u_int *)target;
120 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
123 if((target_insn&0x0c100000)==0x04100000) { // Load
126 if(target_insn&0x08000000) {
130 ptr2[-1]=target_insn;
133 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
138 add_literal(int addr,int val)
140 literals[literalcount][0]=addr;
141 literals[literalcount][1]=val;
145 void kill_pointer(void *stub)
147 int *ptr=(int *)(stub+4);
148 assert((*ptr&0x0ff00000)==0x05900000);
149 u_int offset=*ptr&0xfff;
150 int **l_ptr=(void *)ptr+offset+8;
152 set_jump_target((int)i_ptr,(int)stub);
155 int get_pointer(void *stub)
157 //printf("get_pointer(%x)\n",(int)stub);
158 int *ptr=(int *)(stub+4);
159 assert((*ptr&0x0ff00000)==0x05900000);
160 u_int offset=*ptr&0xfff;
161 int **l_ptr=(void *)ptr+offset+8;
163 assert((*i_ptr&0x0f000000)==0x0a000000);
164 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
167 // Find the "clean" entry point from a "dirty" entry point
168 // by skipping past the call to verify_code
169 u_int get_clean_addr(int addr)
171 int *ptr=(int *)addr;
177 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
178 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
180 if((*ptr&0xFF000000)==0xea000000) {
181 return (int)ptr+((*ptr<<8)>>6)+8; // follow jump
186 int verify_dirty(int addr)
188 u_int *ptr=(u_int *)addr;
190 // get from literal pool
191 assert((*ptr&0xFFF00000)==0xe5900000);
192 u_int offset=*ptr&0xfff;
193 u_int *l_ptr=(void *)ptr+offset+8;
194 u_int source=l_ptr[0];
200 assert((*ptr&0xFFF00000)==0xe3000000);
201 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
202 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
203 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
206 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
207 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
208 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
209 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
210 unsigned int page=source>>12;
211 unsigned int map_value=memory_map[page];
212 if(map_value>=0x80000000) return 0;
213 while(page<((source+len-1)>>12)) {
214 if((memory_map[++page]<<2)!=(map_value<<2)) return 0;
216 source = source+(map_value<<2);
218 //printf("verify_dirty: %x %x %x\n",source,copy,len);
219 return !memcmp((void *)source,(void *)copy,len);
222 // This doesn't necessarily find all clean entry points, just
223 // guarantees that it's not dirty
224 int isclean(int addr)
227 int *ptr=((u_int *)addr)+4;
229 int *ptr=((u_int *)addr)+6;
231 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
232 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
233 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
234 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
235 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
239 void get_bounds(int addr,u_int *start,u_int *end)
241 u_int *ptr=(u_int *)addr;
243 // get from literal pool
244 assert((*ptr&0xFFF00000)==0xe5900000);
245 u_int offset=*ptr&0xfff;
246 u_int *l_ptr=(void *)ptr+offset+8;
247 u_int source=l_ptr[0];
248 //u_int copy=l_ptr[1];
253 assert((*ptr&0xFFF00000)==0xe3000000);
254 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
255 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
256 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
259 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
260 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
261 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
262 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
263 if(memory_map[source>>12]>=0x80000000) source = 0;
264 else source = source+(memory_map[source>>12]<<2);
270 /* Register allocation */
272 // Note: registers are allocated clean (unmodified state)
273 // if you intend to modify the register, you must call dirty_reg().
274 void alloc_reg(struct regstat *cur,int i,signed char reg)
277 int preferred_reg = (reg&7);
278 if(reg==CCREG) preferred_reg=HOST_CCREG;
279 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
281 // Don't allocate unused registers
282 if((cur->u>>reg)&1) return;
284 // see if it's already allocated
285 for(hr=0;hr<HOST_REGS;hr++)
287 if(cur->regmap[hr]==reg) return;
290 // Keep the same mapping if the register was already allocated in a loop
291 preferred_reg = loop_reg(i,reg,preferred_reg);
293 // Try to allocate the preferred register
294 if(cur->regmap[preferred_reg]==-1) {
295 cur->regmap[preferred_reg]=reg;
296 cur->dirty&=~(1<<preferred_reg);
297 cur->isconst&=~(1<<preferred_reg);
300 r=cur->regmap[preferred_reg];
301 if(r<64&&((cur->u>>r)&1)) {
302 cur->regmap[preferred_reg]=reg;
303 cur->dirty&=~(1<<preferred_reg);
304 cur->isconst&=~(1<<preferred_reg);
307 if(r>=64&&((cur->uu>>(r&63))&1)) {
308 cur->regmap[preferred_reg]=reg;
309 cur->dirty&=~(1<<preferred_reg);
310 cur->isconst&=~(1<<preferred_reg);
314 // Clear any unneeded registers
315 // We try to keep the mapping consistent, if possible, because it
316 // makes branches easier (especially loops). So we try to allocate
317 // first (see above) before removing old mappings. If this is not
318 // possible then go ahead and clear out the registers that are no
320 for(hr=0;hr<HOST_REGS;hr++)
325 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
329 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
333 // Try to allocate any available register, but prefer
334 // registers that have not been used recently.
336 for(hr=0;hr<HOST_REGS;hr++) {
337 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
338 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
340 cur->dirty&=~(1<<hr);
341 cur->isconst&=~(1<<hr);
347 // Try to allocate any available register
348 for(hr=0;hr<HOST_REGS;hr++) {
349 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
351 cur->dirty&=~(1<<hr);
352 cur->isconst&=~(1<<hr);
357 // Ok, now we have to evict someone
358 // Pick a register we hopefully won't need soon
359 u_char hsn[MAXREG+1];
360 memset(hsn,10,sizeof(hsn));
362 lsn(hsn,i,&preferred_reg);
363 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
364 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
366 // Don't evict the cycle count at entry points, otherwise the entry
367 // stub will have to write it.
368 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
369 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
372 // Alloc preferred register if available
373 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
374 for(hr=0;hr<HOST_REGS;hr++) {
375 // Evict both parts of a 64-bit register
376 if((cur->regmap[hr]&63)==r) {
378 cur->dirty&=~(1<<hr);
379 cur->isconst&=~(1<<hr);
382 cur->regmap[preferred_reg]=reg;
385 for(r=1;r<=MAXREG;r++)
387 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
388 for(hr=0;hr<HOST_REGS;hr++) {
389 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
390 if(cur->regmap[hr]==r+64) {
392 cur->dirty&=~(1<<hr);
393 cur->isconst&=~(1<<hr);
398 for(hr=0;hr<HOST_REGS;hr++) {
399 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
400 if(cur->regmap[hr]==r) {
402 cur->dirty&=~(1<<hr);
403 cur->isconst&=~(1<<hr);
414 for(r=1;r<=MAXREG;r++)
417 for(hr=0;hr<HOST_REGS;hr++) {
418 if(cur->regmap[hr]==r+64) {
420 cur->dirty&=~(1<<hr);
421 cur->isconst&=~(1<<hr);
425 for(hr=0;hr<HOST_REGS;hr++) {
426 if(cur->regmap[hr]==r) {
428 cur->dirty&=~(1<<hr);
429 cur->isconst&=~(1<<hr);
436 printf("This shouldn't happen (alloc_reg)");exit(1);
439 void alloc_reg64(struct regstat *cur,int i,signed char reg)
441 int preferred_reg = 8+(reg&1);
444 // allocate the lower 32 bits
445 alloc_reg(cur,i,reg);
447 // Don't allocate unused registers
448 if((cur->uu>>reg)&1) return;
450 // see if the upper half is already allocated
451 for(hr=0;hr<HOST_REGS;hr++)
453 if(cur->regmap[hr]==reg+64) return;
456 // Keep the same mapping if the register was already allocated in a loop
457 preferred_reg = loop_reg(i,reg,preferred_reg);
459 // Try to allocate the preferred register
460 if(cur->regmap[preferred_reg]==-1) {
461 cur->regmap[preferred_reg]=reg|64;
462 cur->dirty&=~(1<<preferred_reg);
463 cur->isconst&=~(1<<preferred_reg);
466 r=cur->regmap[preferred_reg];
467 if(r<64&&((cur->u>>r)&1)) {
468 cur->regmap[preferred_reg]=reg|64;
469 cur->dirty&=~(1<<preferred_reg);
470 cur->isconst&=~(1<<preferred_reg);
473 if(r>=64&&((cur->uu>>(r&63))&1)) {
474 cur->regmap[preferred_reg]=reg|64;
475 cur->dirty&=~(1<<preferred_reg);
476 cur->isconst&=~(1<<preferred_reg);
480 // Clear any unneeded registers
481 // We try to keep the mapping consistent, if possible, because it
482 // makes branches easier (especially loops). So we try to allocate
483 // first (see above) before removing old mappings. If this is not
484 // possible then go ahead and clear out the registers that are no
486 for(hr=HOST_REGS-1;hr>=0;hr--)
491 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
495 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
499 // Try to allocate any available register, but prefer
500 // registers that have not been used recently.
502 for(hr=0;hr<HOST_REGS;hr++) {
503 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
504 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
505 cur->regmap[hr]=reg|64;
506 cur->dirty&=~(1<<hr);
507 cur->isconst&=~(1<<hr);
513 // Try to allocate any available register
514 for(hr=0;hr<HOST_REGS;hr++) {
515 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
516 cur->regmap[hr]=reg|64;
517 cur->dirty&=~(1<<hr);
518 cur->isconst&=~(1<<hr);
523 // Ok, now we have to evict someone
524 // Pick a register we hopefully won't need soon
525 u_char hsn[MAXREG+1];
526 memset(hsn,10,sizeof(hsn));
528 lsn(hsn,i,&preferred_reg);
529 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
530 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
532 // Don't evict the cycle count at entry points, otherwise the entry
533 // stub will have to write it.
534 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
535 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
538 // Alloc preferred register if available
539 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
540 for(hr=0;hr<HOST_REGS;hr++) {
541 // Evict both parts of a 64-bit register
542 if((cur->regmap[hr]&63)==r) {
544 cur->dirty&=~(1<<hr);
545 cur->isconst&=~(1<<hr);
548 cur->regmap[preferred_reg]=reg|64;
551 for(r=1;r<=MAXREG;r++)
553 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
554 for(hr=0;hr<HOST_REGS;hr++) {
555 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
556 if(cur->regmap[hr]==r+64) {
557 cur->regmap[hr]=reg|64;
558 cur->dirty&=~(1<<hr);
559 cur->isconst&=~(1<<hr);
564 for(hr=0;hr<HOST_REGS;hr++) {
565 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
566 if(cur->regmap[hr]==r) {
567 cur->regmap[hr]=reg|64;
568 cur->dirty&=~(1<<hr);
569 cur->isconst&=~(1<<hr);
580 for(r=1;r<=MAXREG;r++)
583 for(hr=0;hr<HOST_REGS;hr++) {
584 if(cur->regmap[hr]==r+64) {
585 cur->regmap[hr]=reg|64;
586 cur->dirty&=~(1<<hr);
587 cur->isconst&=~(1<<hr);
591 for(hr=0;hr<HOST_REGS;hr++) {
592 if(cur->regmap[hr]==r) {
593 cur->regmap[hr]=reg|64;
594 cur->dirty&=~(1<<hr);
595 cur->isconst&=~(1<<hr);
602 printf("This shouldn't happen");exit(1);
605 // Allocate a temporary register. This is done without regard to
606 // dirty status or whether the register we request is on the unneeded list
607 // Note: This will only allocate one register, even if called multiple times
608 void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
611 int preferred_reg = -1;
613 // see if it's already allocated
614 for(hr=0;hr<HOST_REGS;hr++)
616 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
619 // Try to allocate any available register
620 for(hr=HOST_REGS-1;hr>=0;hr--) {
621 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
623 cur->dirty&=~(1<<hr);
624 cur->isconst&=~(1<<hr);
629 // Find an unneeded register
630 for(hr=HOST_REGS-1;hr>=0;hr--)
636 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
638 cur->dirty&=~(1<<hr);
639 cur->isconst&=~(1<<hr);
646 if((cur->uu>>(r&63))&1) {
647 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
649 cur->dirty&=~(1<<hr);
650 cur->isconst&=~(1<<hr);
658 // Ok, now we have to evict someone
659 // Pick a register we hopefully won't need soon
660 // TODO: we might want to follow unconditional jumps here
661 // TODO: get rid of dupe code and make this into a function
662 u_char hsn[MAXREG+1];
663 memset(hsn,10,sizeof(hsn));
665 lsn(hsn,i,&preferred_reg);
666 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
668 // Don't evict the cycle count at entry points, otherwise the entry
669 // stub will have to write it.
670 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
671 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
674 for(r=1;r<=MAXREG;r++)
676 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
677 for(hr=0;hr<HOST_REGS;hr++) {
678 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
679 if(cur->regmap[hr]==r+64) {
681 cur->dirty&=~(1<<hr);
682 cur->isconst&=~(1<<hr);
687 for(hr=0;hr<HOST_REGS;hr++) {
688 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
689 if(cur->regmap[hr]==r) {
691 cur->dirty&=~(1<<hr);
692 cur->isconst&=~(1<<hr);
703 for(r=1;r<=MAXREG;r++)
706 for(hr=0;hr<HOST_REGS;hr++) {
707 if(cur->regmap[hr]==r+64) {
709 cur->dirty&=~(1<<hr);
710 cur->isconst&=~(1<<hr);
714 for(hr=0;hr<HOST_REGS;hr++) {
715 if(cur->regmap[hr]==r) {
717 cur->dirty&=~(1<<hr);
718 cur->isconst&=~(1<<hr);
725 printf("This shouldn't happen");exit(1);
727 // Allocate a specific ARM register.
728 void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
732 // see if it's already allocated (and dealloc it)
733 for(n=0;n<HOST_REGS;n++)
735 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {cur->regmap[n]=-1;}
739 cur->dirty&=~(1<<hr);
740 cur->isconst&=~(1<<hr);
743 // Alloc cycle count into dedicated register
744 alloc_cc(struct regstat *cur,int i)
746 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
754 char regname[16][4] = {
772 void output_byte(u_char byte)
776 void output_modrm(u_char mod,u_char rm,u_char ext)
781 u_char byte=(mod<<6)|(ext<<3)|rm;
784 void output_sib(u_char scale,u_char index,u_char base)
789 u_char byte=(scale<<6)|(index<<3)|base;
792 void output_w32(u_int word)
794 *((u_int *)out)=word;
797 u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
802 return((rn<<16)|(rd<<12)|rm);
804 u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
809 assert((shift&1)==0);
810 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
812 u_int genimm(u_int imm,u_int *encoded)
814 if(imm==0) {*encoded=0;return 1;}
819 *encoded=((i&30)<<7)|imm;
822 imm=(imm>>2)|(imm<<30);i-=2;
826 u_int genjmp(u_int addr)
828 int offset=addr-(int)out-8;
829 if(offset<-33554432||offset>=33554432) {
831 printf("genjmp: out of range: %08x\n", offset);
836 return ((u_int)offset>>2)&0xffffff;
839 void emit_mov(int rs,int rt)
841 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
842 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
845 void emit_movs(int rs,int rt)
847 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
848 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
851 void emit_add(int rs1,int rs2,int rt)
853 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
854 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
857 void emit_adds(int rs1,int rs2,int rt)
859 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
860 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
863 void emit_adcs(int rs1,int rs2,int rt)
865 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
866 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
869 void emit_sbc(int rs1,int rs2,int rt)
871 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
872 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
875 void emit_sbcs(int rs1,int rs2,int rt)
877 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
878 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
881 void emit_neg(int rs, int rt)
883 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
884 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
887 void emit_negs(int rs, int rt)
889 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
890 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
893 void emit_sub(int rs1,int rs2,int rt)
895 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
896 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
899 void emit_subs(int rs1,int rs2,int rt)
901 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
902 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
905 void emit_zeroreg(int rt)
907 assem_debug("mov %s,#0\n",regname[rt]);
908 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
911 void emit_loadreg(int r, int hr)
915 printf("64bit load in 32bit mode!\n");
922 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
923 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
924 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
925 if(r==CCREG) addr=(int)&cycle_count;
926 if(r==CSREG) addr=(int)&Status;
927 if(r==FSREG) addr=(int)&FCR31;
928 if(r==INVCP) addr=(int)&invc_ptr;
929 u_int offset = addr-(u_int)&dynarec_local;
931 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
932 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
935 void emit_storereg(int r, int hr)
939 printf("64bit store in 32bit mode!\n");
943 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
944 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
945 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
946 if(r==CCREG) addr=(int)&cycle_count;
947 if(r==FSREG) addr=(int)&FCR31;
948 u_int offset = addr-(u_int)&dynarec_local;
950 assem_debug("str %s,fp+%d\n",regname[hr],offset);
951 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
954 void emit_test(int rs, int rt)
956 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
957 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
960 void emit_testimm(int rs,int imm)
963 assem_debug("tst %s,$%d\n",regname[rs],imm);
964 assert(genimm(imm,&armval));
965 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
968 void emit_not(int rs,int rt)
970 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
971 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
974 void emit_and(u_int rs1,u_int rs2,u_int rt)
976 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
977 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
980 void emit_or(u_int rs1,u_int rs2,u_int rt)
982 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
983 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
985 void emit_or_and_set_flags(int rs1,int rs2,int rt)
987 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
988 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
991 void emit_xor(u_int rs1,u_int rs2,u_int rt)
993 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
994 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
997 void emit_loadlp(u_int imm,u_int rt)
999 add_literal((int)out,imm);
1000 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
1001 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
1003 void emit_movw(u_int imm,u_int rt)
1006 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
1007 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
1009 void emit_movt(u_int imm,u_int rt)
1011 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
1012 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
1014 void emit_movimm(u_int imm,u_int rt)
1017 if(genimm(imm,&armval)) {
1018 assem_debug("mov %s,#%d\n",regname[rt],imm);
1019 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
1020 }else if(genimm(~imm,&armval)) {
1021 assem_debug("mvn %s,#%d\n",regname[rt],imm);
1022 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
1023 }else if(imm<65536) {
1025 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
1026 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
1027 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1028 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1034 emit_loadlp(imm,rt);
1036 emit_movw(imm&0x0000FFFF,rt);
1037 emit_movt(imm&0xFFFF0000,rt);
1041 void emit_pcreladdr(u_int rt)
1043 assem_debug("add %s,pc,#?\n",regname[rt]);
1044 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
1047 void emit_addimm(u_int rs,int imm,u_int rt)
1052 assert(imm>-65536&&imm<65536);
1054 if(genimm(imm,&armval)) {
1055 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1056 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1057 }else if(genimm(-imm,&armval)) {
1058 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],imm);
1059 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1061 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1062 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1063 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1064 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1066 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1067 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1068 output_w32(0xe2800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1069 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1072 else if(rs!=rt) emit_mov(rs,rt);
1075 void emit_addimm_and_set_flags(int imm,int rt)
1077 assert(imm>-65536&&imm<65536);
1079 if(genimm(imm,&armval)) {
1080 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1081 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1082 }else if(genimm(-imm,&armval)) {
1083 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1084 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1086 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1087 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1088 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1089 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1091 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1092 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1093 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1094 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1097 void emit_addimm_no_flags(u_int imm,u_int rt)
1099 emit_addimm(rt,imm,rt);
1102 void emit_addnop(u_int r)
1105 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1106 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1109 void emit_adcimm(u_int rs,int imm,u_int rt)
1112 assert(genimm(imm,&armval));
1113 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1114 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1116 /*void emit_sbcimm(int imm,u_int rt)
1119 assert(genimm(imm,&armval));
1120 assem_debug("sbc %s,%s,#%d\n",regname[rt],regname[rt],imm);
1121 output_w32(0xe2c00000|rd_rn_rm(rt,rt,0)|armval);
1123 void emit_sbbimm(int imm,u_int rt)
1125 assem_debug("sbb $%d,%%%s\n",imm,regname[rt]);
1127 if(imm<128&&imm>=-128) {
1129 output_modrm(3,rt,3);
1135 output_modrm(3,rt,3);
1139 void emit_rscimm(int rs,int imm,u_int rt)
1143 assert(genimm(imm,&armval));
1144 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1145 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1148 void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1150 // TODO: if(genimm(imm,&armval)) ...
1152 emit_movimm(imm,HOST_TEMPREG);
1153 emit_adds(HOST_TEMPREG,rsl,rtl);
1154 emit_adcimm(rsh,0,rth);
1157 void emit_sbb(int rs1,int rs2)
1159 assem_debug("sbb %%%s,%%%s\n",regname[rs2],regname[rs1]);
1161 output_modrm(3,rs1,rs2);
1164 void emit_andimm(int rs,int imm,int rt)
1167 if(genimm(imm,&armval)) {
1168 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1169 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1170 }else if(genimm(~imm,&armval)) {
1171 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1172 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1173 }else if(imm==65535) {
1175 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1176 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1177 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1178 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1180 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1181 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1184 assert(imm>0&&imm<65535);
1186 assem_debug("mov r14,#%d\n",imm&0xFF00);
1187 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1188 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1189 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1191 emit_movw(imm,HOST_TEMPREG);
1193 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1194 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1198 void emit_orimm(int rs,int imm,int rt)
1201 if(genimm(imm,&armval)) {
1202 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1203 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1205 assert(imm>0&&imm<65536);
1206 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1207 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1208 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1209 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1213 void emit_xorimm(int rs,int imm,int rt)
1215 assert(imm>0&&imm<65536);
1217 if(genimm(imm,&armval)) {
1218 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1219 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1222 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1223 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1224 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1225 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1229 void emit_shlimm(int rs,u_int imm,int rt)
1234 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1235 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1238 void emit_shrimm(int rs,u_int imm,int rt)
1242 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1243 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1246 void emit_sarimm(int rs,u_int imm,int rt)
1250 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1251 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1254 void emit_rorimm(int rs,u_int imm,int rt)
1258 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1259 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1262 void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1264 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1268 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1269 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1270 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1271 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1274 void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1276 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1280 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1281 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1282 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1283 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1286 void emit_shl(u_int rs,u_int shift,u_int rt)
1292 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1293 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1295 void emit_shr(u_int rs,u_int shift,u_int rt)
1300 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1301 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1303 void emit_sar(u_int rs,u_int shift,u_int rt)
1308 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1309 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1311 void emit_shlcl(int r)
1313 assem_debug("shl %%%s,%%cl\n",regname[r]);
1316 void emit_shrcl(int r)
1318 assem_debug("shr %%%s,%%cl\n",regname[r]);
1321 void emit_sarcl(int r)
1323 assem_debug("sar %%%s,%%cl\n",regname[r]);
1327 void emit_shldcl(int r1,int r2)
1329 assem_debug("shld %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1332 void emit_shrdcl(int r1,int r2)
1334 assem_debug("shrd %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1337 void emit_orrshl(u_int rs,u_int shift,u_int rt)
1342 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1343 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1345 void emit_orrshr(u_int rs,u_int shift,u_int rt)
1350 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1351 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1354 void emit_cmpimm(int rs,int imm)
1357 if(genimm(imm,&armval)) {
1358 assem_debug("cmp %s,$%d\n",regname[rs],imm);
1359 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1360 }else if(genimm(-imm,&armval)) {
1361 assem_debug("cmn %s,$%d\n",regname[rs],imm);
1362 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1366 emit_movimm(imm,HOST_TEMPREG);
1368 emit_movw(imm,HOST_TEMPREG);
1370 assem_debug("cmp %s,r14\n",regname[rs]);
1371 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1375 emit_movimm(-imm,HOST_TEMPREG);
1377 emit_movw(-imm,HOST_TEMPREG);
1379 assem_debug("cmn %s,r14\n",regname[rs]);
1380 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1384 void emit_cmovne(u_int *addr,int rt)
1386 assem_debug("cmovne %x,%%%s",(int)addr,regname[rt]);
1389 void emit_cmovl(u_int *addr,int rt)
1391 assem_debug("cmovl %x,%%%s",(int)addr,regname[rt]);
1394 void emit_cmovs(u_int *addr,int rt)
1396 assem_debug("cmovs %x,%%%s",(int)addr,regname[rt]);
1399 void emit_cmovne_imm(int imm,int rt)
1401 assem_debug("movne %s,#%d\n",regname[rt],imm);
1403 assert(genimm(imm,&armval));
1404 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1406 void emit_cmovl_imm(int imm,int rt)
1408 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1410 assert(genimm(imm,&armval));
1411 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1413 void emit_cmovb_imm(int imm,int rt)
1415 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1417 assert(genimm(imm,&armval));
1418 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1420 void emit_cmovs_imm(int imm,int rt)
1422 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1424 assert(genimm(imm,&armval));
1425 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1427 void emit_cmove_reg(int rs,int rt)
1429 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1430 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1432 void emit_cmovne_reg(int rs,int rt)
1434 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1435 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1437 void emit_cmovl_reg(int rs,int rt)
1439 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1440 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1442 void emit_cmovs_reg(int rs,int rt)
1444 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1445 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1448 void emit_slti32(int rs,int imm,int rt)
1450 if(rs!=rt) emit_zeroreg(rt);
1451 emit_cmpimm(rs,imm);
1452 if(rs==rt) emit_movimm(0,rt);
1453 emit_cmovl_imm(1,rt);
1455 void emit_sltiu32(int rs,int imm,int rt)
1457 if(rs!=rt) emit_zeroreg(rt);
1458 emit_cmpimm(rs,imm);
1459 if(rs==rt) emit_movimm(0,rt);
1460 emit_cmovb_imm(1,rt);
1462 void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1465 emit_slti32(rsl,imm,rt);
1469 emit_cmovne_imm(0,rt);
1470 emit_cmovs_imm(1,rt);
1474 emit_cmpimm(rsh,-1);
1475 emit_cmovne_imm(0,rt);
1476 emit_cmovl_imm(1,rt);
1479 void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1482 emit_sltiu32(rsl,imm,rt);
1486 emit_cmovne_imm(0,rt);
1490 emit_cmpimm(rsh,-1);
1491 emit_cmovne_imm(1,rt);
1495 void emit_cmp(int rs,int rt)
1497 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1498 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1500 void emit_set_gz32(int rs, int rt)
1502 //assem_debug("set_gz32\n");
1505 emit_cmovl_imm(0,rt);
1507 void emit_set_nz32(int rs, int rt)
1509 //assem_debug("set_nz32\n");
1510 if(rs!=rt) emit_movs(rs,rt);
1511 else emit_test(rs,rs);
1512 emit_cmovne_imm(1,rt);
1514 void emit_set_gz64_32(int rsh, int rsl, int rt)
1516 //assem_debug("set_gz64\n");
1517 emit_set_gz32(rsl,rt);
1519 emit_cmovne_imm(1,rt);
1520 emit_cmovs_imm(0,rt);
1522 void emit_set_nz64_32(int rsh, int rsl, int rt)
1524 //assem_debug("set_nz64\n");
1525 emit_or_and_set_flags(rsh,rsl,rt);
1526 emit_cmovne_imm(1,rt);
1528 void emit_set_if_less32(int rs1, int rs2, int rt)
1530 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1531 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1533 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1534 emit_cmovl_imm(1,rt);
1536 void emit_set_if_carry32(int rs1, int rs2, int rt)
1538 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1539 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1541 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1542 emit_cmovb_imm(1,rt);
1544 void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1546 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1551 emit_sbcs(u1,u2,HOST_TEMPREG);
1552 emit_cmovl_imm(1,rt);
1554 void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1556 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1561 emit_sbcs(u1,u2,HOST_TEMPREG);
1562 emit_cmovb_imm(1,rt);
1565 void emit_call(int a)
1567 assem_debug("bl %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1568 u_int offset=genjmp(a);
1569 output_w32(0xeb000000|offset);
1571 void emit_jmp(int a)
1573 assem_debug("b %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1574 u_int offset=genjmp(a);
1575 output_w32(0xea000000|offset);
1577 void emit_jne(int a)
1579 assem_debug("bne %x\n",a);
1580 u_int offset=genjmp(a);
1581 output_w32(0x1a000000|offset);
1583 void emit_jeq(int a)
1585 assem_debug("beq %x\n",a);
1586 u_int offset=genjmp(a);
1587 output_w32(0x0a000000|offset);
1591 assem_debug("bmi %x\n",a);
1592 u_int offset=genjmp(a);
1593 output_w32(0x4a000000|offset);
1595 void emit_jns(int a)
1597 assem_debug("bpl %x\n",a);
1598 u_int offset=genjmp(a);
1599 output_w32(0x5a000000|offset);
1603 assem_debug("blt %x\n",a);
1604 u_int offset=genjmp(a);
1605 output_w32(0xba000000|offset);
1607 void emit_jge(int a)
1609 assem_debug("bge %x\n",a);
1610 u_int offset=genjmp(a);
1611 output_w32(0xaa000000|offset);
1613 void emit_jno(int a)
1615 assem_debug("bvc %x\n",a);
1616 u_int offset=genjmp(a);
1617 output_w32(0x7a000000|offset);
1621 assem_debug("bcs %x\n",a);
1622 u_int offset=genjmp(a);
1623 output_w32(0x2a000000|offset);
1625 void emit_jcc(int a)
1627 assem_debug("bcc %x\n",a);
1628 u_int offset=genjmp(a);
1629 output_w32(0x3a000000|offset);
1632 void emit_pushimm(int imm)
1634 assem_debug("push $%x\n",imm);
1639 assem_debug("pusha\n");
1644 assem_debug("popa\n");
1647 void emit_pushreg(u_int r)
1649 assem_debug("push %%%s\n",regname[r]);
1652 void emit_popreg(u_int r)
1654 assem_debug("pop %%%s\n",regname[r]);
1657 void emit_callreg(u_int r)
1659 assem_debug("call *%%%s\n",regname[r]);
1662 void emit_jmpreg(u_int r)
1664 assem_debug("mov pc,%s\n",regname[r]);
1665 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1668 void emit_readword_indexed(int offset, int rs, int rt)
1670 assert(offset>-4096&&offset<4096);
1671 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1673 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1675 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1678 void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1680 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1681 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1683 void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1685 if(map<0) emit_readword_indexed(addr, rs, rt);
1688 emit_readword_dualindexedx4(rs, map, rt);
1691 void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1694 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1695 emit_readword_indexed(addr+4, rs, rl);
1698 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1699 emit_addimm(map,1,map);
1700 emit_readword_indexed_tlb(addr, rs, map, rl);
1703 void emit_movsbl_indexed(int offset, int rs, int rt)
1705 assert(offset>-256&&offset<256);
1706 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1708 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1710 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1713 void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1715 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1718 emit_shlimm(map,2,map);
1719 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1720 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1722 assert(addr>-256&&addr<256);
1723 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1724 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1725 emit_movsbl_indexed(addr, rt, rt);
1729 void emit_movswl_indexed(int offset, int rs, int rt)
1731 assert(offset>-256&&offset<256);
1732 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1734 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1736 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1739 void emit_movzbl_indexed(int offset, int rs, int rt)
1741 assert(offset>-4096&&offset<4096);
1742 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1744 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1746 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1749 void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1751 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1752 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1754 void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1756 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1759 emit_movzbl_dualindexedx4(rs, map, rt);
1761 emit_addimm(rs,addr,rt);
1762 emit_movzbl_dualindexedx4(rt, map, rt);
1766 void emit_movzwl_indexed(int offset, int rs, int rt)
1768 assert(offset>-256&&offset<256);
1769 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1771 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1773 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1776 void emit_readword(int addr, int rt)
1778 u_int offset = addr-(u_int)&dynarec_local;
1779 assert(offset<4096);
1780 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1781 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1783 void emit_movsbl(int addr, int rt)
1785 u_int offset = addr-(u_int)&dynarec_local;
1787 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1788 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1790 void emit_movswl(int addr, int rt)
1792 u_int offset = addr-(u_int)&dynarec_local;
1794 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1795 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1797 void emit_movzbl(int addr, int rt)
1799 u_int offset = addr-(u_int)&dynarec_local;
1800 assert(offset<4096);
1801 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1802 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1804 void emit_movzwl(int addr, int rt)
1806 u_int offset = addr-(u_int)&dynarec_local;
1808 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1809 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1811 void emit_movzwl_reg(int rs, int rt)
1813 assem_debug("movzwl %%%s,%%%s\n",regname[rs]+1,regname[rt]);
1817 void emit_xchg(int rs, int rt)
1819 assem_debug("xchg %%%s,%%%s\n",regname[rs],regname[rt]);
1822 void emit_writeword_indexed(int rt, int offset, int rs)
1824 assert(offset>-4096&&offset<4096);
1825 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
1827 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
1829 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
1832 void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
1834 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1835 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
1837 void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1839 if(map<0) emit_writeword_indexed(rt, addr, rs);
1842 emit_writeword_dualindexedx4(rt, rs, map);
1845 void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
1848 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
1849 emit_writeword_indexed(rl, addr+4, rs);
1852 if(temp!=rs) emit_addimm(map,1,temp);
1853 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
1854 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
1856 emit_addimm(rs,4,rs);
1857 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
1861 void emit_writehword_indexed(int rt, int offset, int rs)
1863 assert(offset>-256&&offset<256);
1864 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
1866 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1868 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1871 void emit_writebyte_indexed(int rt, int offset, int rs)
1873 assert(offset>-4096&&offset<4096);
1874 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
1876 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
1878 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
1881 void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
1883 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1884 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1886 void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1888 if(map<0) emit_writebyte_indexed(rt, addr, rs);
1891 emit_writebyte_dualindexedx4(rt, rs, map);
1893 emit_addimm(rs,addr,temp);
1894 emit_writebyte_dualindexedx4(rt, temp, map);
1898 void emit_writeword(int rt, int addr)
1900 u_int offset = addr-(u_int)&dynarec_local;
1901 assert(offset<4096);
1902 assem_debug("str %s,fp+%d\n",regname[rt],offset);
1903 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
1905 void emit_writehword(int rt, int addr)
1907 u_int offset = addr-(u_int)&dynarec_local;
1909 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
1910 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1912 void emit_writebyte(int rt, int addr)
1914 u_int offset = addr-(u_int)&dynarec_local;
1915 assert(offset<4096);
1916 assem_debug("str %s,fp+%d\n",regname[rt],offset);
1917 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
1919 void emit_writeword_imm(int imm, int addr)
1921 assem_debug("movl $%x,%x\n",imm,addr);
1924 void emit_writebyte_imm(int imm, int addr)
1926 assem_debug("movb $%x,%x\n",imm,addr);
1930 void emit_mul(int rs)
1932 assem_debug("mul %%%s\n",regname[rs]);
1935 void emit_imul(int rs)
1937 assem_debug("imul %%%s\n",regname[rs]);
1940 void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
1942 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
1947 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
1949 void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
1951 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
1956 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
1959 void emit_div(int rs)
1961 assem_debug("div %%%s\n",regname[rs]);
1964 void emit_idiv(int rs)
1966 assem_debug("idiv %%%s\n",regname[rs]);
1971 assem_debug("cdq\n");
1975 void emit_clz(int rs,int rt)
1977 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
1978 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
1981 void emit_subcs(int rs1,int rs2,int rt)
1983 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1984 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
1987 void emit_shrcc_imm(int rs,u_int imm,int rt)
1991 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1992 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1995 void emit_negmi(int rs, int rt)
1997 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
1998 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2001 void emit_negsmi(int rs, int rt)
2003 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2004 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2007 void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2009 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2010 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2013 void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2015 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2016 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2019 void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2021 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2022 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2025 void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2027 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2028 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2031 void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2033 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2034 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2037 void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2039 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2040 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2043 void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2045 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2046 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2049 void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2051 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2052 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2055 void emit_teq(int rs, int rt)
2057 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2058 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2061 void emit_rsbimm(int rs, int imm, int rt)
2064 assert(genimm(imm,&armval));
2065 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2066 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2069 // Load 2 immediates optimizing for small code size
2070 void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2072 emit_movimm(imm1,rt1);
2074 if(genimm(imm2-imm1,&armval)) {
2075 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2076 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2077 }else if(genimm(imm1-imm2,&armval)) {
2078 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2079 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2081 else emit_movimm(imm2,rt2);
2084 // Conditionally select one of two immediates, optimizing for small code size
2085 // This will only be called if HAVE_CMOV_IMM is defined
2086 void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2089 if(genimm(imm2-imm1,&armval)) {
2090 emit_movimm(imm1,rt);
2091 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2092 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2093 }else if(genimm(imm1-imm2,&armval)) {
2094 emit_movimm(imm1,rt);
2095 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2096 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2100 emit_movimm(imm1,rt);
2101 add_literal((int)out,imm2);
2102 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2103 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2105 emit_movw(imm1&0x0000FFFF,rt);
2106 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2107 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2108 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2110 emit_movt(imm1&0xFFFF0000,rt);
2111 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2112 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2113 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2119 // special case for checking invalid_code
2120 void emit_cmpmem_indexedsr12_imm(int addr,int r,int imm)
2125 // special case for checking invalid_code
2126 void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2128 assert(imm<128&&imm>=0);
2130 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2131 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2132 emit_cmpimm(HOST_TEMPREG,imm);
2135 // special case for tlb mapping
2136 void emit_addsr12(int rs1,int rs2,int rt)
2138 assem_debug("add %s,%s,%s lsr #12\n",regname[rt],regname[rs1],regname[rs2]);
2139 output_w32(0xe0800620|rd_rn_rm(rt,rs1,rs2));
2142 // Used to preload hash table entries
2143 void emit_prefetch(void *addr)
2145 assem_debug("prefetch %x\n",(int)addr);
2148 output_modrm(0,5,1);
2149 output_w32((int)addr);
2151 void emit_prefetchreg(int r)
2153 assem_debug("pld %s\n",regname[r]);
2154 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2157 // Special case for mini_ht
2158 void emit_ldreq_indexed(int rs, u_int offset, int rt)
2160 assert(offset<4096);
2161 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2162 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2165 void emit_flds(int r,int sr)
2167 assem_debug("flds s%d,[%s]\n",sr,regname[r]);
2168 output_w32(0xed900a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2171 void emit_vldr(int r,int vr)
2173 assem_debug("vldr d%d,[%s]\n",vr,regname[r]);
2174 output_w32(0xed900b00|(vr<<12)|(r<<16));
2177 void emit_fsts(int sr,int r)
2179 assem_debug("fsts s%d,[%s]\n",sr,regname[r]);
2180 output_w32(0xed800a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2183 void emit_vstr(int vr,int r)
2185 assem_debug("vstr d%d,[%s]\n",vr,regname[r]);
2186 output_w32(0xed800b00|(vr<<12)|(r<<16));
2189 void emit_ftosizs(int s,int d)
2191 assem_debug("ftosizs s%d,s%d\n",d,s);
2192 output_w32(0xeebd0ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2195 void emit_ftosizd(int s,int d)
2197 assem_debug("ftosizd s%d,d%d\n",d,s);
2198 output_w32(0xeebd0bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2201 void emit_fsitos(int s,int d)
2203 assem_debug("fsitos s%d,s%d\n",d,s);
2204 output_w32(0xeeb80ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2207 void emit_fsitod(int s,int d)
2209 assem_debug("fsitod d%d,s%d\n",d,s);
2210 output_w32(0xeeb80bc0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2213 void emit_fcvtds(int s,int d)
2215 assem_debug("fcvtds d%d,s%d\n",d,s);
2216 output_w32(0xeeb70ac0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2219 void emit_fcvtsd(int s,int d)
2221 assem_debug("fcvtsd s%d,d%d\n",d,s);
2222 output_w32(0xeeb70bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2225 void emit_fsqrts(int s,int d)
2227 assem_debug("fsqrts d%d,s%d\n",d,s);
2228 output_w32(0xeeb10ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2231 void emit_fsqrtd(int s,int d)
2233 assem_debug("fsqrtd s%d,d%d\n",d,s);
2234 output_w32(0xeeb10bc0|((d&7)<<12)|(s&7));
2237 void emit_fabss(int s,int d)
2239 assem_debug("fabss d%d,s%d\n",d,s);
2240 output_w32(0xeeb00ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2243 void emit_fabsd(int s,int d)
2245 assem_debug("fabsd s%d,d%d\n",d,s);
2246 output_w32(0xeeb00bc0|((d&7)<<12)|(s&7));
2249 void emit_fnegs(int s,int d)
2251 assem_debug("fnegs d%d,s%d\n",d,s);
2252 output_w32(0xeeb10a40|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2255 void emit_fnegd(int s,int d)
2257 assem_debug("fnegd s%d,d%d\n",d,s);
2258 output_w32(0xeeb10b40|((d&7)<<12)|(s&7));
2261 void emit_fadds(int s1,int s2,int d)
2263 assem_debug("fadds s%d,s%d,s%d\n",d,s1,s2);
2264 output_w32(0xee300a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2267 void emit_faddd(int s1,int s2,int d)
2269 assem_debug("faddd d%d,d%d,d%d\n",d,s1,s2);
2270 output_w32(0xee300b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2273 void emit_fsubs(int s1,int s2,int d)
2275 assem_debug("fsubs s%d,s%d,s%d\n",d,s1,s2);
2276 output_w32(0xee300a40|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2279 void emit_fsubd(int s1,int s2,int d)
2281 assem_debug("fsubd d%d,d%d,d%d\n",d,s1,s2);
2282 output_w32(0xee300b40|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2285 void emit_fmuls(int s1,int s2,int d)
2287 assem_debug("fmuls s%d,s%d,s%d\n",d,s1,s2);
2288 output_w32(0xee200a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2291 void emit_fmuld(int s1,int s2,int d)
2293 assem_debug("fmuld d%d,d%d,d%d\n",d,s1,s2);
2294 output_w32(0xee200b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2297 void emit_fdivs(int s1,int s2,int d)
2299 assem_debug("fdivs s%d,s%d,s%d\n",d,s1,s2);
2300 output_w32(0xee800a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2303 void emit_fdivd(int s1,int s2,int d)
2305 assem_debug("fdivd d%d,d%d,d%d\n",d,s1,s2);
2306 output_w32(0xee800b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2309 void emit_fcmps(int x,int y)
2311 assem_debug("fcmps s14, s15\n");
2312 output_w32(0xeeb47a67);
2315 void emit_fcmpd(int x,int y)
2317 assem_debug("fcmpd d6, d7\n");
2318 output_w32(0xeeb46b47);
2323 assem_debug("fmstat\n");
2324 output_w32(0xeef1fa10);
2327 void emit_bicne_imm(int rs,int imm,int rt)
2330 assert(genimm(imm,&armval));
2331 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2332 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2335 void emit_biccs_imm(int rs,int imm,int rt)
2338 assert(genimm(imm,&armval));
2339 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2340 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2343 void emit_bicvc_imm(int rs,int imm,int rt)
2346 assert(genimm(imm,&armval));
2347 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2348 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2351 void emit_bichi_imm(int rs,int imm,int rt)
2354 assert(genimm(imm,&armval));
2355 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2356 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2359 void emit_orrvs_imm(int rs,int imm,int rt)
2362 assert(genimm(imm,&armval));
2363 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2364 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2367 void emit_jno_unlikely(int a)
2370 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2371 output_w32(0x72800000|rd_rn_rm(15,15,0));
2374 // Save registers before function call
2375 void save_regs(u_int reglist)
2377 reglist&=0x100f; // only save the caller-save registers, r0-r3, r12
2378 if(!reglist) return;
2379 assem_debug("stmia fp,{");
2380 if(reglist&1) assem_debug("r0, ");
2381 if(reglist&2) assem_debug("r1, ");
2382 if(reglist&4) assem_debug("r2, ");
2383 if(reglist&8) assem_debug("r3, ");
2384 if(reglist&0x1000) assem_debug("r12");
2386 output_w32(0xe88b0000|reglist);
2388 // Restore registers after function call
2389 void restore_regs(u_int reglist)
2391 reglist&=0x100f; // only restore the caller-save registers, r0-r3, r12
2392 if(!reglist) return;
2393 assem_debug("ldmia fp,{");
2394 if(reglist&1) assem_debug("r0, ");
2395 if(reglist&2) assem_debug("r1, ");
2396 if(reglist&4) assem_debug("r2, ");
2397 if(reglist&8) assem_debug("r3, ");
2398 if(reglist&0x1000) assem_debug("r12");
2400 output_w32(0xe89b0000|reglist);
2403 // Write back consts using r14 so we don't disturb the other registers
2404 void wb_consts(signed char i_regmap[],uint64_t i_is32,u_int i_dirty,int i)
2407 for(hr=0;hr<HOST_REGS;hr++) {
2408 if(hr!=EXCLUDE_REG&&i_regmap[hr]>=0&&((i_dirty>>hr)&1)) {
2409 if(((regs[i].isconst>>hr)&1)&&i_regmap[hr]>0) {
2410 if(i_regmap[hr]<64 || !((i_is32>>(i_regmap[hr]&63))&1) ) {
2411 int value=constmap[i][hr];
2413 emit_zeroreg(HOST_TEMPREG);
2416 emit_movimm(value,HOST_TEMPREG);
2418 emit_storereg(i_regmap[hr],HOST_TEMPREG);
2420 if((i_is32>>i_regmap[hr])&1) {
2421 if(value!=-1&&value!=0) emit_sarimm(HOST_TEMPREG,31,HOST_TEMPREG);
2422 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
2431 /* Stubs/epilogue */
2433 void literal_pool(int n)
2435 if(!literalcount) return;
2437 if((int)out-literals[0][0]<4096-n) return;
2441 for(i=0;i<literalcount;i++)
2443 ptr=(u_int *)literals[i][0];
2444 u_int offset=(u_int)out-(u_int)ptr-8;
2445 assert(offset<4096);
2446 assert(!(offset&3));
2448 output_w32(literals[i][1]);
2453 void literal_pool_jumpover(int n)
2455 if(!literalcount) return;
2457 if((int)out-literals[0][0]<4096-n) return;
2462 set_jump_target(jaddr,(int)out);
2465 emit_extjump2(int addr, int target, int linker)
2467 u_char *ptr=(u_char *)addr;
2468 assert((ptr[3]&0x0e)==0xa);
2469 emit_loadlp(target,0);
2470 emit_loadlp(addr,1);
2471 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
2472 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2474 #ifdef DEBUG_CYCLE_COUNT
2475 emit_readword((int)&last_count,ECX);
2476 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2477 emit_readword((int)&next_interupt,ECX);
2478 emit_writeword(HOST_CCREG,(int)&Count);
2479 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2480 emit_writeword(ECX,(int)&last_count);
2486 emit_extjump(int addr, int target)
2488 emit_extjump2(addr, target, (int)dyna_linker);
2490 emit_extjump_ds(int addr, int target)
2492 emit_extjump2(addr, target, (int)dyna_linker_ds);
2497 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2499 set_jump_target(stubs[n][1],(int)out);
2500 int type=stubs[n][0];
2503 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2504 u_int reglist=stubs[n][7];
2505 signed char *i_regmap=i_regs->regmap;
2506 int addr=get_reg(i_regmap,AGEN1+(i&1));
2509 if(itype[i]==C1LS||itype[i]==LOADLR) {
2510 rth=get_reg(i_regmap,FTEMP|64);
2511 rt=get_reg(i_regmap,FTEMP);
2513 rth=get_reg(i_regmap,rt1[i]|64);
2514 rt=get_reg(i_regmap,rt1[i]);
2521 if(type==LOADB_STUB||type==LOADBU_STUB)
2522 ftable=(int)readmemb;
2523 if(type==LOADH_STUB||type==LOADHU_STUB)
2524 ftable=(int)readmemh;
2525 if(type==LOADW_STUB)
2526 ftable=(int)readmem;
2528 if(type==LOADD_STUB)
2529 ftable=(int)readmemd;
2532 emit_writeword(rs,(int)&address);
2535 ds=i_regs!=®s[i];
2536 int real_rs=(itype[i]==LOADLR)?-1:get_reg(i_regmap,rs1[i]);
2537 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2538 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2539 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2540 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2541 emit_shrimm(rs,16,1);
2542 int cc=get_reg(i_regmap,CCREG);
2544 emit_loadreg(CCREG,2);
2546 emit_movimm(ftable,0);
2547 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2548 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2549 //emit_readword((int)&last_count,temp);
2550 //emit_add(cc,temp,cc);
2551 //emit_writeword(cc,(int)&Count);
2553 emit_call((int)&indirect_jump_indexed);
2555 //emit_readword_dualindexedx4(rs,HOST_TEMPREG,15);
2556 // We really shouldn't need to update the count here,
2557 // but not doing so causes random crashes...
2558 emit_readword((int)&Count,HOST_TEMPREG);
2559 emit_readword((int)&next_interupt,2);
2560 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2561 emit_writeword(2,(int)&last_count);
2562 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2564 emit_storereg(CCREG,HOST_TEMPREG);
2567 restore_regs(reglist);
2568 //if((cc=get_reg(regmap,CCREG))>=0) {
2569 // emit_loadreg(CCREG,cc);
2571 if(type==LOADB_STUB)
2572 emit_movsbl((int)&readmem_dword,rt);
2573 if(type==LOADBU_STUB)
2574 emit_movzbl((int)&readmem_dword,rt);
2575 if(type==LOADH_STUB)
2576 emit_movswl((int)&readmem_dword,rt);
2577 if(type==LOADHU_STUB)
2578 emit_movzwl((int)&readmem_dword,rt);
2579 if(type==LOADW_STUB)
2580 emit_readword((int)&readmem_dword,rt);
2581 if(type==LOADD_STUB) {
2582 emit_readword((int)&readmem_dword,rt);
2583 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2585 emit_jmp(stubs[n][2]); // return address
2588 inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2590 int rs=get_reg(regmap,target);
2591 int rth=get_reg(regmap,target|64);
2592 int rt=get_reg(regmap,target);
2596 if(type==LOADB_STUB||type==LOADBU_STUB)
2597 ftable=(int)readmemb;
2598 if(type==LOADH_STUB||type==LOADHU_STUB)
2599 ftable=(int)readmemh;
2600 if(type==LOADW_STUB)
2601 ftable=(int)readmem;
2603 if(type==LOADD_STUB)
2604 ftable=(int)readmemd;
2607 emit_writeword(rs,(int)&address);
2610 //emit_shrimm(rs,16,1);
2611 int cc=get_reg(regmap,CCREG);
2613 emit_loadreg(CCREG,2);
2615 //emit_movimm(ftable,0);
2616 emit_movimm(((u_int *)ftable)[addr>>16],0);
2617 //emit_readword((int)&last_count,12);
2618 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
2619 if((signed int)addr>=(signed int)0xC0000000) {
2620 // Pagefault address
2621 int ds=regmap!=regs[i].regmap;
2622 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2625 //emit_writeword(2,(int)&Count);
2626 //emit_call(((u_int *)ftable)[addr>>16]);
2627 emit_call((int)&indirect_jump);
2628 // We really shouldn't need to update the count here,
2629 // but not doing so causes random crashes...
2630 emit_readword((int)&Count,HOST_TEMPREG);
2631 emit_readword((int)&next_interupt,2);
2632 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
2633 emit_writeword(2,(int)&last_count);
2634 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2636 emit_storereg(CCREG,HOST_TEMPREG);
2639 restore_regs(reglist);
2640 if(type==LOADB_STUB)
2641 emit_movsbl((int)&readmem_dword,rt);
2642 if(type==LOADBU_STUB)
2643 emit_movzbl((int)&readmem_dword,rt);
2644 if(type==LOADH_STUB)
2645 emit_movswl((int)&readmem_dword,rt);
2646 if(type==LOADHU_STUB)
2647 emit_movzwl((int)&readmem_dword,rt);
2648 if(type==LOADW_STUB)
2649 emit_readword((int)&readmem_dword,rt);
2650 if(type==LOADD_STUB) {
2651 emit_readword((int)&readmem_dword,rt);
2652 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2658 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
2660 set_jump_target(stubs[n][1],(int)out);
2661 int type=stubs[n][0];
2664 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2665 u_int reglist=stubs[n][7];
2666 signed char *i_regmap=i_regs->regmap;
2667 int addr=get_reg(i_regmap,AGEN1+(i&1));
2670 if(itype[i]==C1LS) {
2671 rth=get_reg(i_regmap,FTEMP|64);
2672 rt=get_reg(i_regmap,r=FTEMP);
2674 rth=get_reg(i_regmap,rs2[i]|64);
2675 rt=get_reg(i_regmap,r=rs2[i]);
2679 if(addr<0) addr=get_reg(i_regmap,-1);
2682 if(type==STOREB_STUB)
2683 ftable=(int)writememb;
2684 if(type==STOREH_STUB)
2685 ftable=(int)writememh;
2686 if(type==STOREW_STUB)
2687 ftable=(int)writemem;
2689 if(type==STORED_STUB)
2690 ftable=(int)writememd;
2693 emit_writeword(rs,(int)&address);
2694 //emit_shrimm(rs,16,rs);
2695 //emit_movmem_indexedx4(ftable,rs,rs);
2696 if(type==STOREB_STUB)
2697 emit_writebyte(rt,(int)&byte);
2698 if(type==STOREH_STUB)
2699 emit_writehword(rt,(int)&hword);
2700 if(type==STOREW_STUB)
2701 emit_writeword(rt,(int)&word);
2702 if(type==STORED_STUB) {
2704 emit_writeword(rt,(int)&dword);
2705 emit_writeword(r?rth:rt,(int)&dword+4);
2707 printf("STORED_STUB\n");
2712 ds=i_regs!=®s[i];
2713 int real_rs=get_reg(i_regmap,rs1[i]);
2714 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2715 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2716 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2717 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2718 emit_shrimm(rs,16,1);
2719 int cc=get_reg(i_regmap,CCREG);
2721 emit_loadreg(CCREG,2);
2723 emit_movimm(ftable,0);
2724 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2725 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2726 //emit_readword((int)&last_count,temp);
2727 //emit_addimm(cc,2*stubs[n][5]+2,cc);
2728 //emit_add(cc,temp,cc);
2729 //emit_writeword(cc,(int)&Count);
2730 emit_call((int)&indirect_jump_indexed);
2732 emit_readword((int)&Count,HOST_TEMPREG);
2733 emit_readword((int)&next_interupt,2);
2734 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2735 emit_writeword(2,(int)&last_count);
2736 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2738 emit_storereg(CCREG,HOST_TEMPREG);
2741 restore_regs(reglist);
2742 //if((cc=get_reg(regmap,CCREG))>=0) {
2743 // emit_loadreg(CCREG,cc);
2745 emit_jmp(stubs[n][2]); // return address
2748 inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2750 int rs=get_reg(regmap,-1);
2751 int rth=get_reg(regmap,target|64);
2752 int rt=get_reg(regmap,target);
2756 if(type==STOREB_STUB)
2757 ftable=(int)writememb;
2758 if(type==STOREH_STUB)
2759 ftable=(int)writememh;
2760 if(type==STOREW_STUB)
2761 ftable=(int)writemem;
2763 if(type==STORED_STUB)
2764 ftable=(int)writememd;
2767 emit_writeword(rs,(int)&address);
2768 //emit_shrimm(rs,16,rs);
2769 //emit_movmem_indexedx4(ftable,rs,rs);
2770 if(type==STOREB_STUB)
2771 emit_writebyte(rt,(int)&byte);
2772 if(type==STOREH_STUB)
2773 emit_writehword(rt,(int)&hword);
2774 if(type==STOREW_STUB)
2775 emit_writeword(rt,(int)&word);
2776 if(type==STORED_STUB) {
2778 emit_writeword(rt,(int)&dword);
2779 emit_writeword(target?rth:rt,(int)&dword+4);
2781 printf("STORED_STUB\n");
2786 //emit_shrimm(rs,16,1);
2787 int cc=get_reg(regmap,CCREG);
2789 emit_loadreg(CCREG,2);
2791 //emit_movimm(ftable,0);
2792 emit_movimm(((u_int *)ftable)[addr>>16],0);
2793 //emit_readword((int)&last_count,12);
2794 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
2795 if((signed int)addr>=(signed int)0xC0000000) {
2796 // Pagefault address
2797 int ds=regmap!=regs[i].regmap;
2798 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2801 //emit_writeword(2,(int)&Count);
2802 //emit_call(((u_int *)ftable)[addr>>16]);
2803 emit_call((int)&indirect_jump);
2804 emit_readword((int)&Count,HOST_TEMPREG);
2805 emit_readword((int)&next_interupt,2);
2806 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
2807 emit_writeword(2,(int)&last_count);
2808 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2810 emit_storereg(CCREG,HOST_TEMPREG);
2813 restore_regs(reglist);
2816 do_unalignedwritestub(int n)
2818 set_jump_target(stubs[n][1],(int)out);
2819 output_w32(0xef000000);
2820 emit_jmp(stubs[n][2]); // return address
2823 void printregs(int edi,int esi,int ebp,int esp,int b,int d,int c,int a)
2825 printf("regs: %x %x %x %x %x %x %x (%x)\n",a,b,c,d,ebp,esi,edi,(&edi)[-1]);
2831 u_int reglist=stubs[n][3];
2832 set_jump_target(stubs[n][1],(int)out);
2834 if(stubs[n][4]!=0) emit_mov(stubs[n][4],0);
2835 emit_call((int)&invalidate_addr);
2836 restore_regs(reglist);
2837 emit_jmp(stubs[n][2]); // return address
2840 int do_dirty_stub(int i)
2842 assem_debug("do_dirty_stub %x\n",start+i*4);
2843 // Careful about the code output here, verify_dirty needs to parse it.
2845 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
2846 emit_loadlp((int)copy,2);
2847 emit_loadlp(slen*4,3);
2849 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
2850 emit_movw(((u_int)copy)&0x0000FFFF,2);
2851 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
2852 emit_movt(((u_int)copy)&0xFFFF0000,2);
2853 emit_movw(slen*4,3);
2855 emit_movimm(start+i*4,0);
2856 emit_call((int)start<(int)0xC0000000?(int)&verify_code:(int)&verify_code_vm);
2859 if(entry==(int)out) entry=instr_addr[i];
2860 emit_jmp(instr_addr[i]);
2864 void do_dirty_stub_ds()
2866 // Careful about the code output here, verify_dirty needs to parse it.
2868 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
2869 emit_loadlp((int)copy,2);
2870 emit_loadlp(slen*4,3);
2872 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
2873 emit_movw(((u_int)copy)&0x0000FFFF,2);
2874 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
2875 emit_movt(((u_int)copy)&0xFFFF0000,2);
2876 emit_movw(slen*4,3);
2878 emit_movimm(start+1,0);
2879 emit_call((int)&verify_code_ds);
2885 assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
2886 set_jump_target(stubs[n][1],(int)out);
2888 // int rs=stubs[n][4];
2889 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2892 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
2893 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
2895 //else {printf("fp exception in delay slot\n");}
2896 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty);
2897 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
2898 emit_movimm(start+(i-ds)*4,EAX); // Get PC
2899 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
2900 emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
2905 int do_tlb_r(int s,int ar,int map,int x,int a,int shift,int c,u_int addr)
2908 if((signed int)addr>=(signed int)0xC0000000) {
2909 // address_generation already loaded the const
2910 emit_readword_dualindexedx4(FP,map,map);
2913 return -1; // No mapping
2917 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
2918 emit_addsr12(map,s,map);
2919 // Schedule this while we wait on the load
2920 //if(x) emit_xorimm(s,x,ar);
2921 if(shift>=0) emit_shlimm(s,3,shift);
2922 if(~a) emit_andimm(s,a,ar);
2923 emit_readword_dualindexedx4(FP,map,map);
2927 int do_tlb_r_branch(int map, int c, u_int addr, int *jaddr)
2929 if(!c||(signed int)addr>=(signed int)0xC0000000) {
2937 int gen_tlb_addr_r(int ar, int map) {
2939 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
2940 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
2944 int do_tlb_w(int s,int ar,int map,int x,int c,u_int addr)
2947 if(addr<0x80800000||addr>=0xC0000000) {
2948 // address_generation already loaded the const
2949 emit_readword_dualindexedx4(FP,map,map);
2952 return -1; // No mapping
2956 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
2957 emit_addsr12(map,s,map);
2958 // Schedule this while we wait on the load
2959 //if(x) emit_xorimm(s,x,ar);
2960 emit_readword_dualindexedx4(FP,map,map);
2964 int do_tlb_w_branch(int map, int c, u_int addr, int *jaddr)
2966 if(!c||addr<0x80800000||addr>=0xC0000000) {
2967 emit_testimm(map,0x40000000);
2973 int gen_tlb_addr_w(int ar, int map) {
2975 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
2976 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
2980 // Generate the address of the memory_map entry, relative to dynarec_local
2981 generate_map_const(u_int addr,int reg) {
2982 //printf("generate_map_const(%x,%s)\n",addr,regname[reg]);
2983 emit_movimm((addr>>12)+(((u_int)memory_map-(u_int)&dynarec_local)>>2),reg);
2988 void shift_assemble_arm(int i,struct regstat *i_regs)
2991 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
2993 signed char s,t,shift;
2994 t=get_reg(i_regs->regmap,rt1[i]);
2995 s=get_reg(i_regs->regmap,rs1[i]);
2996 shift=get_reg(i_regs->regmap,rs2[i]);
3005 if(s!=t) emit_mov(s,t);
3009 emit_andimm(shift,31,HOST_TEMPREG);
3010 if(opcode2[i]==4) // SLLV
3012 emit_shl(s,HOST_TEMPREG,t);
3014 if(opcode2[i]==6) // SRLV
3016 emit_shr(s,HOST_TEMPREG,t);
3018 if(opcode2[i]==7) // SRAV
3020 emit_sar(s,HOST_TEMPREG,t);
3024 } else { // DSLLV/DSRLV/DSRAV
3025 signed char sh,sl,th,tl,shift;
3026 th=get_reg(i_regs->regmap,rt1[i]|64);
3027 tl=get_reg(i_regs->regmap,rt1[i]);
3028 sh=get_reg(i_regs->regmap,rs1[i]|64);
3029 sl=get_reg(i_regs->regmap,rs1[i]);
3030 shift=get_reg(i_regs->regmap,rs2[i]);
3035 if(th>=0) emit_zeroreg(th);
3040 if(sl!=tl) emit_mov(sl,tl);
3041 if(th>=0&&sh!=th) emit_mov(sh,th);
3045 // FIXME: What if shift==tl ?
3047 int temp=get_reg(i_regs->regmap,-1);
3049 if(th<0&&opcode2[i]!=0x14) {th=temp;} // DSLLV doesn't need a temporary register
3052 emit_andimm(shift,31,HOST_TEMPREG);
3053 if(opcode2[i]==0x14) // DSLLV
3055 if(th>=0) emit_shl(sh,HOST_TEMPREG,th);
3056 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3057 emit_orrshr(sl,HOST_TEMPREG,th);
3058 emit_andimm(shift,31,HOST_TEMPREG);
3059 emit_testimm(shift,32);
3060 emit_shl(sl,HOST_TEMPREG,tl);
3061 if(th>=0) emit_cmovne_reg(tl,th);
3062 emit_cmovne_imm(0,tl);
3064 if(opcode2[i]==0x16) // DSRLV
3067 emit_shr(sl,HOST_TEMPREG,tl);
3068 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3069 emit_orrshl(sh,HOST_TEMPREG,tl);
3070 emit_andimm(shift,31,HOST_TEMPREG);
3071 emit_testimm(shift,32);
3072 emit_shr(sh,HOST_TEMPREG,th);
3073 emit_cmovne_reg(th,tl);
3074 if(real_th>=0) emit_cmovne_imm(0,th);
3076 if(opcode2[i]==0x17) // DSRAV
3079 emit_shr(sl,HOST_TEMPREG,tl);
3080 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3083 emit_sarimm(th,31,temp);
3085 emit_orrshl(sh,HOST_TEMPREG,tl);
3086 emit_andimm(shift,31,HOST_TEMPREG);
3087 emit_testimm(shift,32);
3088 emit_sar(sh,HOST_TEMPREG,th);
3089 emit_cmovne_reg(th,tl);
3090 if(real_th>=0) emit_cmovne_reg(temp,th);
3097 #define shift_assemble shift_assemble_arm
3099 void loadlr_assemble_arm(int i,struct regstat *i_regs)
3101 int s,th,tl,temp,temp2,addr,map=-1;
3106 th=get_reg(i_regs->regmap,rt1[i]|64);
3107 tl=get_reg(i_regs->regmap,rt1[i]);
3108 s=get_reg(i_regs->regmap,rs1[i]);
3109 temp=get_reg(i_regs->regmap,-1);
3110 temp2=get_reg(i_regs->regmap,FTEMP);
3111 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3114 for(hr=0;hr<HOST_REGS;hr++) {
3115 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3118 if(offset||s<0||c) addr=temp2;
3121 c=(i_regs->wasconst>>s)&1;
3122 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3123 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3130 emit_shlimm(addr,3,temp);
3131 if (opcode[i]==0x22||opcode[i]==0x26) {
3132 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3134 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3136 emit_cmpimm(addr,0x800000);
3141 if (opcode[i]==0x22||opcode[i]==0x26) {
3142 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3144 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3151 }else if (opcode[i]==0x22||opcode[i]==0x26) {
3152 a=0xFFFFFFFC; // LWL/LWR
3154 a=0xFFFFFFF8; // LDL/LDR
3156 map=get_reg(i_regs->regmap,TLREG);
3158 map=do_tlb_r(addr,temp2,map,0,a,c?-1:temp,c,constmap[i][s]+offset);
3160 if (opcode[i]==0x22||opcode[i]==0x26) {
3161 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3163 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3166 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
3168 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
3170 //emit_readword_indexed((int)rdram-0x80000000,temp2,temp2);
3171 emit_readword_indexed_tlb((int)rdram-0x80000000,temp2,map,temp2);
3172 if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3175 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
3176 emit_andimm(temp,24,temp);
3177 #ifdef BIG_ENDIAN_MIPS
3178 if (opcode[i]==0x26) // LWR
3180 if (opcode[i]==0x22) // LWL
3182 emit_xorimm(temp,24,temp);
3183 emit_movimm(-1,HOST_TEMPREG);
3184 if (opcode[i]==0x26) {
3185 emit_shr(temp2,temp,temp2);
3186 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3188 emit_shl(temp2,temp,temp2);
3189 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3191 emit_or(temp2,tl,tl);
3192 //emit_storereg(rt1[i],tl); // DEBUG
3194 if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
3195 // FIXME: little endian
3196 int temp2h=get_reg(i_regs->regmap,FTEMP|64);
3198 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
3199 //emit_readword_indexed((int)rdram-0x7FFFFFFC,temp2,temp2);
3200 emit_readdword_indexed_tlb((int)rdram-0x80000000,temp2,map,temp2h,temp2);
3201 if(jaddr) add_stub(LOADD_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3204 inline_readstub(LOADD_STUB,i,(constmap[i][s]+offset)&0xFFFFFFF8,i_regs->regmap,FTEMP,ccadj[i],reglist);
3205 emit_testimm(temp,32);
3206 emit_andimm(temp,24,temp);
3207 if (opcode[i]==0x1A) { // LDL
3208 emit_rsbimm(temp,32,HOST_TEMPREG);
3209 emit_shl(temp2h,temp,temp2h);
3210 emit_orrshr(temp2,HOST_TEMPREG,temp2h);
3211 emit_movimm(-1,HOST_TEMPREG);
3212 emit_shl(temp2,temp,temp2);
3213 emit_cmove_reg(temp2h,th);
3214 emit_biceq_lsl(tl,HOST_TEMPREG,temp,tl);
3215 emit_bicne_lsl(th,HOST_TEMPREG,temp,th);
3216 emit_orreq(temp2,tl,tl);
3217 emit_orrne(temp2,th,th);
3219 if (opcode[i]==0x1B) { // LDR
3220 emit_xorimm(temp,24,temp);
3221 emit_rsbimm(temp,32,HOST_TEMPREG);
3222 emit_shr(temp2,temp,temp2);
3223 emit_orrshl(temp2h,HOST_TEMPREG,temp2);
3224 emit_movimm(-1,HOST_TEMPREG);
3225 emit_shr(temp2h,temp,temp2h);
3226 emit_cmovne_reg(temp2,tl);
3227 emit_bicne_lsr(th,HOST_TEMPREG,temp,th);
3228 emit_biceq_lsr(tl,HOST_TEMPREG,temp,tl);
3229 emit_orrne(temp2h,th,th);
3230 emit_orreq(temp2h,tl,tl);
3235 #define loadlr_assemble loadlr_assemble_arm
3237 void cop0_assemble(int i,struct regstat *i_regs)
3239 if(opcode2[i]==0) // MFC0
3241 signed char t=get_reg(i_regs->regmap,rt1[i]);
3242 char copr=(source[i]>>11)&0x1f;
3243 //assert(t>=0); // Why does this happen? OOT is weird
3245 #ifdef MUPEN64 /// FIXME
3246 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
3247 emit_movimm((source[i]>>11)&0x1f,1);
3248 emit_writeword(0,(int)&PC);
3249 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
3252 emit_readword((int)&last_count,ECX);
3253 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3254 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3255 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3256 emit_writeword(HOST_CCREG,(int)&Count);
3258 emit_call((int)MFC0);
3259 emit_readword((int)&readmem_dword,t);
3262 else if(opcode2[i]==4) // MTC0
3264 signed char s=get_reg(i_regs->regmap,rs1[i]);
3265 char copr=(source[i]>>11)&0x1f;
3267 emit_writeword(s,(int)&readmem_dword);
3268 wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
3269 #ifdef MUPEN64 /// FIXME
3270 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
3271 emit_movimm((source[i]>>11)&0x1f,1);
3272 emit_writeword(0,(int)&PC);
3273 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
3275 if(copr==9||copr==11||copr==12) {
3276 emit_readword((int)&last_count,ECX);
3277 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3278 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3279 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3280 emit_writeword(HOST_CCREG,(int)&Count);
3282 // What a mess. The status register (12) can enable interrupts,
3283 // so needs a special case to handle a pending interrupt.
3284 // The interrupt must be taken immediately, because a subsequent
3285 // instruction might disable interrupts again.
3286 if(copr==12&&!is_delayslot) {
3287 emit_movimm(start+i*4+4,0);
3289 emit_writeword(0,(int)&pcaddr);
3290 emit_writeword(1,(int)&pending_exception);
3292 //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
3294 emit_call((int)MTC0);
3295 if(copr==9||copr==11||copr==12) {
3296 emit_readword((int)&Count,HOST_CCREG);
3297 emit_readword((int)&next_interupt,ECX);
3298 emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3299 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
3300 emit_writeword(ECX,(int)&last_count);
3301 emit_storereg(CCREG,HOST_CCREG);
3304 assert(!is_delayslot);
3305 emit_readword((int)&pending_exception,14);
3307 emit_loadreg(rs1[i],s);
3308 if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
3309 emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
3312 emit_jne((int)&do_interrupt);
3318 assert(opcode2[i]==0x10);
3320 if((source[i]&0x3f)==0x01) // TLBR
3321 emit_call((int)TLBR);
3322 if((source[i]&0x3f)==0x02) // TLBWI
3323 emit_call((int)TLBWI_new);
3324 if((source[i]&0x3f)==0x06) { // TLBWR
3325 // The TLB entry written by TLBWR is dependent on the count,
3326 // so update the cycle count
3327 emit_readword((int)&last_count,ECX);
3328 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3329 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3330 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3331 emit_writeword(HOST_CCREG,(int)&Count);
3332 emit_call((int)TLBWR_new);
3334 if((source[i]&0x3f)==0x08) // TLBP
3335 emit_call((int)TLBP);
3337 if((source[i]&0x3f)==0x18) // ERET
3340 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3341 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*count,HOST_CCREG); // TODO: Should there be an extra cycle here?
3342 emit_jmp((int)jump_eret);
3347 void cop1_unusable(int i, struct regstat *i_regs)
3349 // XXX: should just just do the exception instead
3353 add_stub(FP_STUB,jaddr,(int)out,i,0,(int)i_regs,is_delayslot,0);
3358 void cop1_assemble(int i,struct regstat *i_regs)
3360 #ifndef DISABLE_COP1
3361 // Check cop1 unusable
3363 signed char rs=get_reg(i_regs->regmap,CSREG);
3365 emit_testimm(rs,0x20000000);
3368 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3371 if (opcode2[i]==0) { // MFC1
3372 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3374 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],tl);
3375 emit_readword_indexed(0,tl,tl);
3378 else if (opcode2[i]==1) { // DMFC1
3379 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3380 signed char th=get_reg(i_regs->regmap,rt1[i]|64);
3382 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],tl);
3383 if(th>=0) emit_readword_indexed(4,tl,th);
3384 emit_readword_indexed(0,tl,tl);
3387 else if (opcode2[i]==4) { // MTC1
3388 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3389 signed char temp=get_reg(i_regs->regmap,-1);
3390 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3391 emit_writeword_indexed(sl,0,temp);
3393 else if (opcode2[i]==5) { // DMTC1
3394 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3395 signed char sh=rs1[i]>0?get_reg(i_regs->regmap,rs1[i]|64):sl;
3396 signed char temp=get_reg(i_regs->regmap,-1);
3397 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3398 emit_writeword_indexed(sh,4,temp);
3399 emit_writeword_indexed(sl,0,temp);
3401 else if (opcode2[i]==2) // CFC1
3403 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3405 u_int copr=(source[i]>>11)&0x1f;
3406 if(copr==0) emit_readword((int)&FCR0,tl);
3407 if(copr==31) emit_readword((int)&FCR31,tl);
3410 else if (opcode2[i]==6) // CTC1
3412 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3413 u_int copr=(source[i]>>11)&0x1f;
3417 emit_writeword(sl,(int)&FCR31);
3418 // Set the rounding mode
3420 //char temp=get_reg(i_regs->regmap,-1);
3421 //emit_andimm(sl,3,temp);
3422 //emit_fldcw_indexed((int)&rounding_modes,temp);
3426 cop1_unusable(i, i_regs);
3430 void fconv_assemble_arm(int i,struct regstat *i_regs)
3432 #ifndef DISABLE_COP1
3433 signed char temp=get_reg(i_regs->regmap,-1);
3435 // Check cop1 unusable
3437 signed char rs=get_reg(i_regs->regmap,CSREG);
3439 emit_testimm(rs,0x20000000);
3442 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3446 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
3447 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) { // trunc_w_s
3448 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3450 emit_ftosizs(15,15); // float->int, truncate
3451 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
3452 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3456 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) { // trunc_w_d
3457 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3459 emit_ftosizd(7,13); // double->int, truncate
3460 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3465 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) { // cvt_s_w
3466 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3468 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
3469 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3474 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) { // cvt_d_w
3475 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3477 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
3483 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) { // cvt_d_s
3484 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3486 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
3491 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) { // cvt_s_d
3492 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3494 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3504 for(hr=0;hr<HOST_REGS;hr++) {
3505 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3509 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) {
3510 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3511 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3512 emit_call((int)cvt_s_w);
3514 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) {
3515 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3516 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3517 emit_call((int)cvt_d_w);
3519 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x20) {
3520 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3521 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3522 emit_call((int)cvt_s_l);
3524 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x21) {
3525 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3526 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3527 emit_call((int)cvt_d_l);
3530 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) {
3531 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3532 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);