1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
25 #include "emu_if.h" //emulator interface
30 #include "assem_x86.h"
33 #include "assem_x64.h"
36 #include "assem_arm.h"
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
55 uint64_t constmap[HOST_REGS];
63 struct ll_entry *next;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
85 char likely[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
110 u_int stubs[MAXBLOCK*3][8];
112 u_int literals[1024][2];
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
129 /* registers that may be allocated */
131 #define HIREG 32 // hi
132 #define LOREG 33 // lo
133 #define FSREG 34 // FPU status (FCSR)
134 #define CSREG 35 // Coprocessor status
135 #define CCREG 36 // Cycle count
136 #define INVCP 37 // Pointer to invalid_code
138 #define FTEMP 38 // FPU/LDL/LDR temporary register
139 #define PTEMP 39 // Prefetch temporary register
140 #define TLREG 40 // TLB mapping offset
141 #define RHASH 41 // Return address hash
142 #define RHTBL 42 // Return address hash table address
143 #define RTEMP 43 // JR/JALR address register
145 #define AGEN1 44 // Address generation temporary register
146 #define AGEN2 45 // Address generation temporary register
147 #define MGEN1 46 // Maptable address generation temporary register
148 #define MGEN2 47 // Maptable address generation temporary register
149 #define BTREG 48 // Branch target temporary register
151 /* instruction types */
152 #define NOP 0 // No operation
153 #define LOAD 1 // Load
154 #define STORE 2 // Store
155 #define LOADLR 3 // Unaligned load
156 #define STORELR 4 // Unaligned store
157 #define MOV 5 // Move
158 #define ALU 6 // Arithmetic/logic
159 #define MULTDIV 7 // Multiply/divide
160 #define SHIFT 8 // Shift by register
161 #define SHIFTIMM 9// Shift by immediate
162 #define IMM16 10 // 16-bit immediate
163 #define RJUMP 11 // Unconditional jump to register
164 #define UJUMP 12 // Unconditional jump
165 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166 #define SJUMP 14 // Conditional branch (regimm format)
167 #define COP0 15 // Coprocessor 0
168 #define COP1 16 // Coprocessor 1
169 #define C1LS 17 // Coprocessor 1 load/store
170 #define FJUMP 18 // Conditional branch (floating point)
171 #define FLOAT 19 // Floating point unit
172 #define FCONV 20 // Convert integer to float
173 #define FCOMP 21 // Floating point compare (sets FSREG)
174 #define SYSCALL 22// SYSCALL
175 #define OTHER 23 // Other
176 #define SPAN 24 // Branch/delay slot spans 2 pages
177 #define NI 25 // Not implemented
178 #define HLECALL 26// PCSX fake opcodes for HLE
179 #define COP2 27 // Coprocessor 2 move
180 #define C2LS 28 // Coprocessor 2 load/store
181 #define C2OP 29 // Coprocessor 2 operation
182 #define INTCALL 30// Call interpreter to handle rare corner cases
191 #define LOADBU_STUB 7
192 #define LOADHU_STUB 8
193 #define STOREB_STUB 9
194 #define STOREH_STUB 10
195 #define STOREW_STUB 11
196 #define STORED_STUB 12
197 #define STORELR_STUB 13
198 #define INVCODE_STUB 14
206 int new_recompile_block(int addr);
207 void *get_addr_ht(u_int vaddr);
208 void invalidate_block(u_int block);
209 void invalidate_addr(u_int addr);
210 void remove_hash(int vaddr);
213 void dyna_linker_ds();
215 void verify_code_vm();
216 void verify_code_ds();
219 void fp_exception_ds();
221 void jump_syscall_hle();
225 void new_dyna_leave();
230 void read_nomem_new();
231 void read_nomemb_new();
232 void read_nomemh_new();
233 void read_nomemd_new();
234 void write_nomem_new();
235 void write_nomemb_new();
236 void write_nomemh_new();
237 void write_nomemd_new();
238 void write_rdram_new();
239 void write_rdramb_new();
240 void write_rdramh_new();
241 void write_rdramd_new();
242 extern u_int memory_map[1048576];
244 // Needed by assembler
245 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
246 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
247 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
248 void load_all_regs(signed char i_regmap[]);
249 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
250 void load_regs_entry(int t);
251 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
255 //#define DEBUG_CYCLE_COUNT 1
258 //#define assem_debug printf
259 //#define inv_debug printf
260 #define assem_debug nullf
261 #define inv_debug nullf
263 static void tlb_hacks()
267 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
271 switch (ROM_HEADER->Country_code&0xFF)
283 // Unknown country code
287 u_int rom_addr=(u_int)rom;
289 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
290 // in the lower 4G of memory to use this hack. Copy it if necessary.
291 if((void *)rom>(void *)0xffffffff) {
292 munmap(ROM_COPY, 67108864);
293 if(mmap(ROM_COPY, 12582912,
294 PROT_READ | PROT_WRITE,
295 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
296 -1, 0) <= 0) {printf("mmap() failed\n");}
297 memcpy(ROM_COPY,rom,12582912);
298 rom_addr=(u_int)ROM_COPY;
302 for(n=0x7F000;n<0x80000;n++) {
303 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
310 static u_int get_page(u_int vaddr)
312 u_int page=(vaddr^0x80000000)>>12;
314 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
316 if(page>2048) page=2048+(page&2047);
320 static u_int get_vpage(u_int vaddr)
322 u_int vpage=(vaddr^0x80000000)>>12;
324 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
326 if(vpage>2048) vpage=2048+(vpage&2047);
330 // Get address from virtual address
331 // This is called from the recompiled JR/JALR instructions
332 void *get_addr(u_int vaddr)
334 u_int page=get_page(vaddr);
335 u_int vpage=get_vpage(vaddr);
336 struct ll_entry *head;
337 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
340 if(head->vaddr==vaddr&&head->reg32==0) {
341 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
342 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
345 ht_bin[1]=(int)head->addr;
351 head=jump_dirty[vpage];
353 if(head->vaddr==vaddr&&head->reg32==0) {
354 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
355 // Don't restore blocks which are about to expire from the cache
356 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
357 if(verify_dirty(head->addr)) {
358 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
359 invalid_code[vaddr>>12]=0;
360 memory_map[vaddr>>12]|=0x40000000;
363 if(tlb_LUT_r[vaddr>>12]) {
364 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
365 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
368 restore_candidate[vpage>>3]|=1<<(vpage&7);
370 else restore_candidate[page>>3]|=1<<(page&7);
371 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
372 if(ht_bin[0]==vaddr) {
373 ht_bin[1]=(int)head->addr; // Replace existing entry
379 ht_bin[1]=(int)head->addr;
387 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
388 int r=new_recompile_block(vaddr);
389 if(r==0) return get_addr(vaddr);
390 // Execute in unmapped page, generate pagefault execption
392 Cause=(vaddr<<31)|0x8;
393 EPC=(vaddr&1)?vaddr-5:vaddr;
395 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
396 EntryHi=BadVAddr&0xFFFFE000;
397 return get_addr_ht(0x80000000);
399 // Look up address in hash table first
400 void *get_addr_ht(u_int vaddr)
402 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
403 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
404 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
405 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
406 return get_addr(vaddr);
409 void *get_addr_32(u_int vaddr,u_int flags)
412 return get_addr(vaddr);
414 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
415 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
416 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
417 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
418 u_int page=get_page(vaddr);
419 u_int vpage=get_vpage(vaddr);
420 struct ll_entry *head;
423 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
424 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
426 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
428 ht_bin[1]=(int)head->addr;
430 }else if(ht_bin[2]==-1) {
431 ht_bin[3]=(int)head->addr;
434 //ht_bin[3]=ht_bin[1];
435 //ht_bin[2]=ht_bin[0];
436 //ht_bin[1]=(int)head->addr;
443 head=jump_dirty[vpage];
445 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
446 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
447 // Don't restore blocks which are about to expire from the cache
448 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
449 if(verify_dirty(head->addr)) {
450 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
451 invalid_code[vaddr>>12]=0;
452 memory_map[vaddr>>12]|=0x40000000;
455 if(tlb_LUT_r[vaddr>>12]) {
456 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
457 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
460 restore_candidate[vpage>>3]|=1<<(vpage&7);
462 else restore_candidate[page>>3]|=1<<(page&7);
464 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
466 ht_bin[1]=(int)head->addr;
468 }else if(ht_bin[2]==-1) {
469 ht_bin[3]=(int)head->addr;
472 //ht_bin[3]=ht_bin[1];
473 //ht_bin[2]=ht_bin[0];
474 //ht_bin[1]=(int)head->addr;
482 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
483 int r=new_recompile_block(vaddr);
484 if(r==0) return get_addr(vaddr);
485 // Execute in unmapped page, generate pagefault execption
487 Cause=(vaddr<<31)|0x8;
488 EPC=(vaddr&1)?vaddr-5:vaddr;
490 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
491 EntryHi=BadVAddr&0xFFFFE000;
492 return get_addr_ht(0x80000000);
496 void clear_all_regs(signed char regmap[])
499 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
502 signed char get_reg(signed char regmap[],int r)
505 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
509 // Find a register that is available for two consecutive cycles
510 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
513 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
517 int count_free_regs(signed char regmap[])
521 for(hr=0;hr<HOST_REGS;hr++)
523 if(hr!=EXCLUDE_REG) {
524 if(regmap[hr]<0) count++;
530 void dirty_reg(struct regstat *cur,signed char reg)
534 for (hr=0;hr<HOST_REGS;hr++) {
535 if((cur->regmap[hr]&63)==reg) {
541 // If we dirty the lower half of a 64 bit register which is now being
542 // sign-extended, we need to dump the upper half.
543 // Note: Do this only after completion of the instruction, because
544 // some instructions may need to read the full 64-bit value even if
545 // overwriting it (eg SLTI, DSRA32).
546 static void flush_dirty_uppers(struct regstat *cur)
549 for (hr=0;hr<HOST_REGS;hr++) {
550 if((cur->dirty>>hr)&1) {
553 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
558 void set_const(struct regstat *cur,signed char reg,uint64_t value)
562 for (hr=0;hr<HOST_REGS;hr++) {
563 if(cur->regmap[hr]==reg) {
565 cur->constmap[hr]=value;
567 else if((cur->regmap[hr]^64)==reg) {
569 cur->constmap[hr]=value>>32;
574 void clear_const(struct regstat *cur,signed char reg)
578 for (hr=0;hr<HOST_REGS;hr++) {
579 if((cur->regmap[hr]&63)==reg) {
580 cur->isconst&=~(1<<hr);
585 int is_const(struct regstat *cur,signed char reg)
589 for (hr=0;hr<HOST_REGS;hr++) {
590 if((cur->regmap[hr]&63)==reg) {
591 return (cur->isconst>>hr)&1;
596 uint64_t get_const(struct regstat *cur,signed char reg)
600 for (hr=0;hr<HOST_REGS;hr++) {
601 if(cur->regmap[hr]==reg) {
602 return cur->constmap[hr];
605 printf("Unknown constant in r%d\n",reg);
609 // Least soon needed registers
610 // Look at the next ten instructions and see which registers
611 // will be used. Try not to reallocate these.
612 void lsn(u_char hsn[], int i, int *preferred_reg)
622 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
624 // Don't go past an unconditonal jump
631 if(rs1[i+j]) hsn[rs1[i+j]]=j;
632 if(rs2[i+j]) hsn[rs2[i+j]]=j;
633 if(rt1[i+j]) hsn[rt1[i+j]]=j;
634 if(rt2[i+j]) hsn[rt2[i+j]]=j;
635 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
636 // Stores can allocate zero
640 // On some architectures stores need invc_ptr
641 #if defined(HOST_IMM8)
642 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
646 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
654 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
656 // Follow first branch
657 int t=(ba[i+b]-start)>>2;
658 j=7-b;if(t+j>=slen) j=slen-t-1;
661 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
662 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
663 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
664 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
667 // TODO: preferred register based on backward branch
669 // Delay slot should preferably not overwrite branch conditions or cycle count
670 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
671 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
672 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
678 // Coprocessor load/store needs FTEMP, even if not declared
679 if(itype[i]==C1LS||itype[i]==C2LS) {
682 // Load L/R also uses FTEMP as a temporary register
683 if(itype[i]==LOADLR) {
686 // Also SWL/SWR/SDL/SDR
687 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
690 // Don't remove the TLB registers either
691 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
694 // Don't remove the miniht registers
695 if(itype[i]==UJUMP||itype[i]==RJUMP)
702 // We only want to allocate registers if we're going to use them again soon
703 int needed_again(int r, int i)
709 u_char hsn[MAXREG+1];
712 memset(hsn,10,sizeof(hsn));
713 lsn(hsn,i,&preferred_reg);
715 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
717 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
718 return 0; // Don't need any registers if exiting the block
726 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
728 // Don't go past an unconditonal jump
732 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
739 if(rs1[i+j]==r) rn=j;
740 if(rs2[i+j]==r) rn=j;
741 if((unneeded_reg[i+j]>>r)&1) rn=10;
742 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
750 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
752 // Follow first branch
754 int t=(ba[i+b]-start)>>2;
755 j=7-b;if(t+j>=slen) j=slen-t-1;
758 if(!((unneeded_reg[t+j]>>r)&1)) {
759 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
760 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
766 for(hr=0;hr<HOST_REGS;hr++) {
767 if(hr!=EXCLUDE_REG) {
768 if(rn<hsn[hr]) return 1;
774 // Try to match register allocations at the end of a loop with those
776 int loop_reg(int i, int r, int hr)
785 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
787 // Don't go past an unconditonal jump
794 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
799 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
800 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
801 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
803 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
805 int t=(ba[i+k]-start)>>2;
806 int reg=get_reg(regs[t].regmap_entry,r);
807 if(reg>=0) return reg;
808 //reg=get_reg(regs[t+1].regmap_entry,r);
809 //if(reg>=0) return reg;
817 // Allocate every register, preserving source/target regs
818 void alloc_all(struct regstat *cur,int i)
822 for(hr=0;hr<HOST_REGS;hr++) {
823 if(hr!=EXCLUDE_REG) {
824 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
825 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
828 cur->dirty&=~(1<<hr);
831 if((cur->regmap[hr]&63)==0)
834 cur->dirty&=~(1<<hr);
841 void div64(int64_t dividend,int64_t divisor)
845 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
846 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
848 void divu64(uint64_t dividend,uint64_t divisor)
852 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
853 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
856 void mult64(uint64_t m1,uint64_t m2)
858 unsigned long long int op1, op2, op3, op4;
859 unsigned long long int result1, result2, result3, result4;
860 unsigned long long int temp1, temp2, temp3, temp4;
876 op1 = op2 & 0xFFFFFFFF;
877 op2 = (op2 >> 32) & 0xFFFFFFFF;
878 op3 = op4 & 0xFFFFFFFF;
879 op4 = (op4 >> 32) & 0xFFFFFFFF;
882 temp2 = (temp1 >> 32) + op1 * op4;
884 temp4 = (temp3 >> 32) + op2 * op4;
886 result1 = temp1 & 0xFFFFFFFF;
887 result2 = temp2 + (temp3 & 0xFFFFFFFF);
888 result3 = (result2 >> 32) + temp4;
889 result4 = (result3 >> 32);
891 lo = result1 | (result2 << 32);
892 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
901 void multu64(uint64_t m1,uint64_t m2)
903 unsigned long long int op1, op2, op3, op4;
904 unsigned long long int result1, result2, result3, result4;
905 unsigned long long int temp1, temp2, temp3, temp4;
907 op1 = m1 & 0xFFFFFFFF;
908 op2 = (m1 >> 32) & 0xFFFFFFFF;
909 op3 = m2 & 0xFFFFFFFF;
910 op4 = (m2 >> 32) & 0xFFFFFFFF;
913 temp2 = (temp1 >> 32) + op1 * op4;
915 temp4 = (temp3 >> 32) + op2 * op4;
917 result1 = temp1 & 0xFFFFFFFF;
918 result2 = temp2 + (temp3 & 0xFFFFFFFF);
919 result3 = (result2 >> 32) + temp4;
920 result4 = (result3 >> 32);
922 lo = result1 | (result2 << 32);
923 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
925 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
926 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
929 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
937 else original=loaded;
940 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
943 original>>=64-(bits^56);
944 original<<=64-(bits^56);
948 else original=loaded;
953 #include "assem_x86.c"
956 #include "assem_x64.c"
959 #include "assem_arm.c"
962 // Add virtual address mapping to linked list
963 void ll_add(struct ll_entry **head,int vaddr,void *addr)
965 struct ll_entry *new_entry;
966 new_entry=malloc(sizeof(struct ll_entry));
967 assert(new_entry!=NULL);
968 new_entry->vaddr=vaddr;
970 new_entry->addr=addr;
971 new_entry->next=*head;
975 // Add virtual address mapping for 32-bit compiled block
976 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
978 ll_add(head,vaddr,addr);
980 (*head)->reg32=reg32;
984 // Check if an address is already compiled
985 // but don't return addresses which are about to expire from the cache
986 void *check_addr(u_int vaddr)
988 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
989 if(ht_bin[0]==vaddr) {
990 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
991 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
993 if(ht_bin[2]==vaddr) {
994 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
995 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
997 u_int page=get_page(vaddr);
998 struct ll_entry *head;
1001 if(head->vaddr==vaddr&&head->reg32==0) {
1002 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1003 // Update existing entry with current address
1004 if(ht_bin[0]==vaddr) {
1005 ht_bin[1]=(int)head->addr;
1008 if(ht_bin[2]==vaddr) {
1009 ht_bin[3]=(int)head->addr;
1012 // Insert into hash table with low priority.
1013 // Don't evict existing entries, as they are probably
1014 // addresses that are being accessed frequently.
1016 ht_bin[1]=(int)head->addr;
1018 }else if(ht_bin[2]==-1) {
1019 ht_bin[3]=(int)head->addr;
1030 void remove_hash(int vaddr)
1032 //printf("remove hash: %x\n",vaddr);
1033 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1034 if(ht_bin[2]==vaddr) {
1035 ht_bin[2]=ht_bin[3]=-1;
1037 if(ht_bin[0]==vaddr) {
1038 ht_bin[0]=ht_bin[2];
1039 ht_bin[1]=ht_bin[3];
1040 ht_bin[2]=ht_bin[3]=-1;
1044 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1046 struct ll_entry *next;
1048 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1049 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1051 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1052 remove_hash((*head)->vaddr);
1059 head=&((*head)->next);
1064 // Remove all entries from linked list
1065 void ll_clear(struct ll_entry **head)
1067 struct ll_entry *cur;
1068 struct ll_entry *next;
1079 // Dereference the pointers and remove if it matches
1080 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1082 u_int old_host_addr=0;
1084 int ptr=get_pointer(head->addr);
1085 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1086 if(((ptr>>shift)==(addr>>shift)) ||
1087 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1089 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1090 u_int host_addr=(u_int)kill_pointer(head->addr);
1092 if((host_addr>>12)!=(old_host_addr>>12)) {
1094 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1096 old_host_addr=host_addr;
1103 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1107 // This is called when we write to a compiled block (see do_invstub)
1108 void invalidate_page(u_int page)
1110 struct ll_entry *head;
1111 struct ll_entry *next;
1112 u_int old_host_addr=0;
1116 inv_debug("INVALIDATE: %x\n",head->vaddr);
1117 remove_hash(head->vaddr);
1122 head=jump_out[page];
1125 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1126 u_int host_addr=(u_int)kill_pointer(head->addr);
1128 if((host_addr>>12)!=(old_host_addr>>12)) {
1130 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1132 old_host_addr=host_addr;
1140 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1143 void invalidate_block(u_int block)
1145 u_int page=get_page(block<<12);
1146 u_int vpage=get_vpage(block<<12);
1147 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1148 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1151 struct ll_entry *head;
1152 head=jump_dirty[vpage];
1153 //printf("page=%d vpage=%d\n",page,vpage);
1156 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1157 get_bounds((int)head->addr,&start,&end);
1158 //printf("start: %x end: %x\n",start,end);
1159 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1160 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1161 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1162 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1166 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1167 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1168 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1169 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1176 //printf("first=%d last=%d\n",first,last);
1177 invalidate_page(page);
1178 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1179 assert(last<page+5);
1180 // Invalidate the adjacent pages if a block crosses a 4K boundary
1182 invalidate_page(first);
1185 for(first=page+1;first<last;first++) {
1186 invalidate_page(first);
1189 // Don't trap writes
1190 invalid_code[block]=1;
1192 // If there is a valid TLB entry for this page, remove write protect
1193 if(tlb_LUT_w[block]) {
1194 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1195 // CHECK: Is this right?
1196 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1197 u_int real_block=tlb_LUT_w[block]>>12;
1198 invalid_code[real_block]=1;
1199 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1201 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1205 memset(mini_ht,-1,sizeof(mini_ht));
1208 void invalidate_addr(u_int addr)
1210 invalidate_block(addr>>12);
1212 void invalidate_all_pages()
1215 for(page=0;page<4096;page++)
1216 invalidate_page(page);
1217 for(page=0;page<1048576;page++)
1218 if(!invalid_code[page]) {
1219 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1220 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1223 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1226 memset(mini_ht,-1,sizeof(mini_ht));
1230 for(page=0;page<0x100000;page++) {
1231 if(tlb_LUT_r[page]) {
1232 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1233 if(!tlb_LUT_w[page]||!invalid_code[page])
1234 memory_map[page]|=0x40000000; // Write protect
1236 else memory_map[page]=-1;
1237 if(page==0x80000) page=0xC0000;
1243 // Add an entry to jump_out after making a link
1244 void add_link(u_int vaddr,void *src)
1246 u_int page=get_page(vaddr);
1247 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1248 ll_add(jump_out+page,vaddr,src);
1249 //int ptr=get_pointer(src);
1250 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1253 // If a code block was found to be unmodified (bit was set in
1254 // restore_candidate) and it remains unmodified (bit is clear
1255 // in invalid_code) then move the entries for that 4K page from
1256 // the dirty list to the clean list.
1257 void clean_blocks(u_int page)
1259 struct ll_entry *head;
1260 inv_debug("INV: clean_blocks page=%d\n",page);
1261 head=jump_dirty[page];
1263 if(!invalid_code[head->vaddr>>12]) {
1264 // Don't restore blocks which are about to expire from the cache
1265 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1267 if(verify_dirty((int)head->addr)) {
1268 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1271 get_bounds((int)head->addr,&start,&end);
1272 if(start-(u_int)rdram<RAM_SIZE) {
1273 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1274 inv|=invalid_code[i];
1277 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1278 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1279 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1280 if(addr<start||addr>=end) inv=1;
1282 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1286 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1287 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1290 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1292 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1293 //printf("page=%x, addr=%x\n",page,head->vaddr);
1294 //assert(head->vaddr>>12==(page|0x80000));
1295 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1296 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1298 if(ht_bin[0]==head->vaddr) {
1299 ht_bin[1]=(int)clean_addr; // Replace existing entry
1301 if(ht_bin[2]==head->vaddr) {
1302 ht_bin[3]=(int)clean_addr; // Replace existing entry
1315 void mov_alloc(struct regstat *current,int i)
1317 // Note: Don't need to actually alloc the source registers
1318 if((~current->is32>>rs1[i])&1) {
1319 //alloc_reg64(current,i,rs1[i]);
1320 alloc_reg64(current,i,rt1[i]);
1321 current->is32&=~(1LL<<rt1[i]);
1323 //alloc_reg(current,i,rs1[i]);
1324 alloc_reg(current,i,rt1[i]);
1325 current->is32|=(1LL<<rt1[i]);
1327 clear_const(current,rs1[i]);
1328 clear_const(current,rt1[i]);
1329 dirty_reg(current,rt1[i]);
1332 void shiftimm_alloc(struct regstat *current,int i)
1334 clear_const(current,rs1[i]);
1335 clear_const(current,rt1[i]);
1336 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1339 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1341 alloc_reg(current,i,rt1[i]);
1342 current->is32|=1LL<<rt1[i];
1343 dirty_reg(current,rt1[i]);
1346 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1349 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1350 alloc_reg64(current,i,rt1[i]);
1351 current->is32&=~(1LL<<rt1[i]);
1352 dirty_reg(current,rt1[i]);
1355 if(opcode2[i]==0x3c) // DSLL32
1358 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1359 alloc_reg64(current,i,rt1[i]);
1360 current->is32&=~(1LL<<rt1[i]);
1361 dirty_reg(current,rt1[i]);
1364 if(opcode2[i]==0x3e) // DSRL32
1367 alloc_reg64(current,i,rs1[i]);
1369 alloc_reg64(current,i,rt1[i]);
1370 current->is32&=~(1LL<<rt1[i]);
1372 alloc_reg(current,i,rt1[i]);
1373 current->is32|=1LL<<rt1[i];
1375 dirty_reg(current,rt1[i]);
1378 if(opcode2[i]==0x3f) // DSRA32
1381 alloc_reg64(current,i,rs1[i]);
1382 alloc_reg(current,i,rt1[i]);
1383 current->is32|=1LL<<rt1[i];
1384 dirty_reg(current,rt1[i]);
1389 void shift_alloc(struct regstat *current,int i)
1392 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1394 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1395 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1396 alloc_reg(current,i,rt1[i]);
1397 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1398 current->is32|=1LL<<rt1[i];
1399 } else { // DSLLV/DSRLV/DSRAV
1400 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1401 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1402 alloc_reg64(current,i,rt1[i]);
1403 current->is32&=~(1LL<<rt1[i]);
1404 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1405 alloc_reg_temp(current,i,-1);
1407 clear_const(current,rs1[i]);
1408 clear_const(current,rs2[i]);
1409 clear_const(current,rt1[i]);
1410 dirty_reg(current,rt1[i]);
1414 void alu_alloc(struct regstat *current,int i)
1416 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1418 if(rs1[i]&&rs2[i]) {
1419 alloc_reg(current,i,rs1[i]);
1420 alloc_reg(current,i,rs2[i]);
1423 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1424 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1426 alloc_reg(current,i,rt1[i]);
1428 current->is32|=1LL<<rt1[i];
1430 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1432 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1434 alloc_reg64(current,i,rs1[i]);
1435 alloc_reg64(current,i,rs2[i]);
1436 alloc_reg(current,i,rt1[i]);
1438 alloc_reg(current,i,rs1[i]);
1439 alloc_reg(current,i,rs2[i]);
1440 alloc_reg(current,i,rt1[i]);
1443 current->is32|=1LL<<rt1[i];
1445 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1447 if(rs1[i]&&rs2[i]) {
1448 alloc_reg(current,i,rs1[i]);
1449 alloc_reg(current,i,rs2[i]);
1453 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1454 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1456 alloc_reg(current,i,rt1[i]);
1457 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1459 if(!((current->uu>>rt1[i])&1)) {
1460 alloc_reg64(current,i,rt1[i]);
1462 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1463 if(rs1[i]&&rs2[i]) {
1464 alloc_reg64(current,i,rs1[i]);
1465 alloc_reg64(current,i,rs2[i]);
1469 // Is is really worth it to keep 64-bit values in registers?
1471 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1472 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1476 current->is32&=~(1LL<<rt1[i]);
1478 current->is32|=1LL<<rt1[i];
1482 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1484 if(rs1[i]&&rs2[i]) {
1485 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1486 alloc_reg64(current,i,rs1[i]);
1487 alloc_reg64(current,i,rs2[i]);
1488 alloc_reg64(current,i,rt1[i]);
1490 alloc_reg(current,i,rs1[i]);
1491 alloc_reg(current,i,rs2[i]);
1492 alloc_reg(current,i,rt1[i]);
1496 alloc_reg(current,i,rt1[i]);
1497 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1498 // DADD used as move, or zeroing
1499 // If we have a 64-bit source, then make the target 64 bits too
1500 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1501 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1502 alloc_reg64(current,i,rt1[i]);
1503 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1504 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1505 alloc_reg64(current,i,rt1[i]);
1507 if(opcode2[i]>=0x2e&&rs2[i]) {
1508 // DSUB used as negation - 64-bit result
1509 // If we have a 32-bit register, extend it to 64 bits
1510 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1511 alloc_reg64(current,i,rt1[i]);
1515 if(rs1[i]&&rs2[i]) {
1516 current->is32&=~(1LL<<rt1[i]);
1518 current->is32&=~(1LL<<rt1[i]);
1519 if((current->is32>>rs1[i])&1)
1520 current->is32|=1LL<<rt1[i];
1522 current->is32&=~(1LL<<rt1[i]);
1523 if((current->is32>>rs2[i])&1)
1524 current->is32|=1LL<<rt1[i];
1526 current->is32|=1LL<<rt1[i];
1530 clear_const(current,rs1[i]);
1531 clear_const(current,rs2[i]);
1532 clear_const(current,rt1[i]);
1533 dirty_reg(current,rt1[i]);
1536 void imm16_alloc(struct regstat *current,int i)
1538 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1540 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1541 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1542 current->is32&=~(1LL<<rt1[i]);
1543 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1544 // TODO: Could preserve the 32-bit flag if the immediate is zero
1545 alloc_reg64(current,i,rt1[i]);
1546 alloc_reg64(current,i,rs1[i]);
1548 clear_const(current,rs1[i]);
1549 clear_const(current,rt1[i]);
1551 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1552 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1553 current->is32|=1LL<<rt1[i];
1554 clear_const(current,rs1[i]);
1555 clear_const(current,rt1[i]);
1557 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1558 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1559 if(rs1[i]!=rt1[i]) {
1560 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1561 alloc_reg64(current,i,rt1[i]);
1562 current->is32&=~(1LL<<rt1[i]);
1565 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1566 if(is_const(current,rs1[i])) {
1567 int v=get_const(current,rs1[i]);
1568 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1569 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1570 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1572 else clear_const(current,rt1[i]);
1574 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1575 if(is_const(current,rs1[i])) {
1576 int v=get_const(current,rs1[i]);
1577 set_const(current,rt1[i],v+imm[i]);
1579 else clear_const(current,rt1[i]);
1580 current->is32|=1LL<<rt1[i];
1583 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1584 current->is32|=1LL<<rt1[i];
1586 dirty_reg(current,rt1[i]);
1589 void load_alloc(struct regstat *current,int i)
1591 clear_const(current,rt1[i]);
1592 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1593 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1594 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1596 alloc_reg(current,i,rt1[i]);
1597 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1599 current->is32&=~(1LL<<rt1[i]);
1600 alloc_reg64(current,i,rt1[i]);
1602 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1604 current->is32&=~(1LL<<rt1[i]);
1605 alloc_reg64(current,i,rt1[i]);
1606 alloc_all(current,i);
1607 alloc_reg64(current,i,FTEMP);
1609 else current->is32|=1LL<<rt1[i];
1610 dirty_reg(current,rt1[i]);
1611 // If using TLB, need a register for pointer to the mapping table
1612 if(using_tlb) alloc_reg(current,i,TLREG);
1613 // LWL/LWR need a temporary register for the old value
1614 if(opcode[i]==0x22||opcode[i]==0x26)
1616 alloc_reg(current,i,FTEMP);
1617 alloc_reg_temp(current,i,-1);
1622 // Load to r0 (dummy load)
1623 // but we still need a register to calculate the address
1624 alloc_reg_temp(current,i,-1);
1628 void store_alloc(struct regstat *current,int i)
1630 clear_const(current,rs2[i]);
1631 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1632 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1633 alloc_reg(current,i,rs2[i]);
1634 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1635 alloc_reg64(current,i,rs2[i]);
1636 if(rs2[i]) alloc_reg(current,i,FTEMP);
1638 // If using TLB, need a register for pointer to the mapping table
1639 if(using_tlb) alloc_reg(current,i,TLREG);
1640 #if defined(HOST_IMM8)
1641 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1642 else alloc_reg(current,i,INVCP);
1644 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1645 alloc_reg(current,i,FTEMP);
1647 // We need a temporary register for address generation
1648 alloc_reg_temp(current,i,-1);
1651 void c1ls_alloc(struct regstat *current,int i)
1653 //clear_const(current,rs1[i]); // FIXME
1654 clear_const(current,rt1[i]);
1655 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1656 alloc_reg(current,i,CSREG); // Status
1657 alloc_reg(current,i,FTEMP);
1658 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1659 alloc_reg64(current,i,FTEMP);
1661 // If using TLB, need a register for pointer to the mapping table
1662 if(using_tlb) alloc_reg(current,i,TLREG);
1663 #if defined(HOST_IMM8)
1664 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1665 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1666 alloc_reg(current,i,INVCP);
1668 // We need a temporary register for address generation
1669 alloc_reg_temp(current,i,-1);
1672 void c2ls_alloc(struct regstat *current,int i)
1674 clear_const(current,rt1[i]);
1675 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1676 alloc_reg(current,i,FTEMP);
1677 // If using TLB, need a register for pointer to the mapping table
1678 if(using_tlb) alloc_reg(current,i,TLREG);
1679 #if defined(HOST_IMM8)
1680 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1681 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1682 alloc_reg(current,i,INVCP);
1684 // We need a temporary register for address generation
1685 alloc_reg_temp(current,i,-1);
1688 #ifndef multdiv_alloc
1689 void multdiv_alloc(struct regstat *current,int i)
1696 // case 0x1D: DMULTU
1699 clear_const(current,rs1[i]);
1700 clear_const(current,rs2[i]);
1703 if((opcode2[i]&4)==0) // 32-bit
1705 current->u&=~(1LL<<HIREG);
1706 current->u&=~(1LL<<LOREG);
1707 alloc_reg(current,i,HIREG);
1708 alloc_reg(current,i,LOREG);
1709 alloc_reg(current,i,rs1[i]);
1710 alloc_reg(current,i,rs2[i]);
1711 current->is32|=1LL<<HIREG;
1712 current->is32|=1LL<<LOREG;
1713 dirty_reg(current,HIREG);
1714 dirty_reg(current,LOREG);
1718 current->u&=~(1LL<<HIREG);
1719 current->u&=~(1LL<<LOREG);
1720 current->uu&=~(1LL<<HIREG);
1721 current->uu&=~(1LL<<LOREG);
1722 alloc_reg64(current,i,HIREG);
1723 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1724 alloc_reg64(current,i,rs1[i]);
1725 alloc_reg64(current,i,rs2[i]);
1726 alloc_all(current,i);
1727 current->is32&=~(1LL<<HIREG);
1728 current->is32&=~(1LL<<LOREG);
1729 dirty_reg(current,HIREG);
1730 dirty_reg(current,LOREG);
1735 // Multiply by zero is zero.
1736 // MIPS does not have a divide by zero exception.
1737 // The result is undefined, we return zero.
1738 alloc_reg(current,i,HIREG);
1739 alloc_reg(current,i,LOREG);
1740 current->is32|=1LL<<HIREG;
1741 current->is32|=1LL<<LOREG;
1742 dirty_reg(current,HIREG);
1743 dirty_reg(current,LOREG);
1748 void cop0_alloc(struct regstat *current,int i)
1750 if(opcode2[i]==0) // MFC0
1753 clear_const(current,rt1[i]);
1754 alloc_all(current,i);
1755 alloc_reg(current,i,rt1[i]);
1756 current->is32|=1LL<<rt1[i];
1757 dirty_reg(current,rt1[i]);
1760 else if(opcode2[i]==4) // MTC0
1763 clear_const(current,rs1[i]);
1764 alloc_reg(current,i,rs1[i]);
1765 alloc_all(current,i);
1768 alloc_all(current,i); // FIXME: Keep r0
1770 alloc_reg(current,i,0);
1775 // TLBR/TLBWI/TLBWR/TLBP/ERET
1776 assert(opcode2[i]==0x10);
1777 alloc_all(current,i);
1781 void cop1_alloc(struct regstat *current,int i)
1783 alloc_reg(current,i,CSREG); // Load status
1784 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1787 clear_const(current,rt1[i]);
1789 alloc_reg64(current,i,rt1[i]); // DMFC1
1790 current->is32&=~(1LL<<rt1[i]);
1792 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1793 current->is32|=1LL<<rt1[i];
1795 dirty_reg(current,rt1[i]);
1796 alloc_reg_temp(current,i,-1);
1798 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1801 clear_const(current,rs1[i]);
1803 alloc_reg64(current,i,rs1[i]); // DMTC1
1805 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1806 alloc_reg_temp(current,i,-1);
1810 alloc_reg(current,i,0);
1811 alloc_reg_temp(current,i,-1);
1815 void fconv_alloc(struct regstat *current,int i)
1817 alloc_reg(current,i,CSREG); // Load status
1818 alloc_reg_temp(current,i,-1);
1820 void float_alloc(struct regstat *current,int i)
1822 alloc_reg(current,i,CSREG); // Load status
1823 alloc_reg_temp(current,i,-1);
1825 void c2op_alloc(struct regstat *current,int i)
1827 alloc_reg_temp(current,i,-1);
1829 void fcomp_alloc(struct regstat *current,int i)
1831 alloc_reg(current,i,CSREG); // Load status
1832 alloc_reg(current,i,FSREG); // Load flags
1833 dirty_reg(current,FSREG); // Flag will be modified
1834 alloc_reg_temp(current,i,-1);
1837 void syscall_alloc(struct regstat *current,int i)
1839 alloc_cc(current,i);
1840 dirty_reg(current,CCREG);
1841 alloc_all(current,i);
1845 void delayslot_alloc(struct regstat *current,int i)
1856 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1857 printf("Disabled speculative precompilation\n");
1861 imm16_alloc(current,i);
1865 load_alloc(current,i);
1869 store_alloc(current,i);
1872 alu_alloc(current,i);
1875 shift_alloc(current,i);
1878 multdiv_alloc(current,i);
1881 shiftimm_alloc(current,i);
1884 mov_alloc(current,i);
1887 cop0_alloc(current,i);
1891 cop1_alloc(current,i);
1894 c1ls_alloc(current,i);
1897 c2ls_alloc(current,i);
1900 fconv_alloc(current,i);
1903 float_alloc(current,i);
1906 fcomp_alloc(current,i);
1909 c2op_alloc(current,i);
1914 // Special case where a branch and delay slot span two pages in virtual memory
1915 static void pagespan_alloc(struct regstat *current,int i)
1918 current->wasconst=0;
1920 alloc_all(current,i);
1921 alloc_cc(current,i);
1922 dirty_reg(current,CCREG);
1923 if(opcode[i]==3) // JAL
1925 alloc_reg(current,i,31);
1926 dirty_reg(current,31);
1928 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1930 alloc_reg(current,i,rs1[i]);
1932 alloc_reg(current,i,rt1[i]);
1933 dirty_reg(current,rt1[i]);
1936 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1938 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1939 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1940 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1942 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1943 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1947 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1949 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1950 if(!((current->is32>>rs1[i])&1))
1952 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1956 if(opcode[i]==0x11) // BC1
1958 alloc_reg(current,i,FSREG);
1959 alloc_reg(current,i,CSREG);
1964 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1966 stubs[stubcount][0]=type;
1967 stubs[stubcount][1]=addr;
1968 stubs[stubcount][2]=retaddr;
1969 stubs[stubcount][3]=a;
1970 stubs[stubcount][4]=b;
1971 stubs[stubcount][5]=c;
1972 stubs[stubcount][6]=d;
1973 stubs[stubcount][7]=e;
1977 // Write out a single register
1978 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1981 for(hr=0;hr<HOST_REGS;hr++) {
1982 if(hr!=EXCLUDE_REG) {
1983 if((regmap[hr]&63)==r) {
1986 emit_storereg(r,hr);
1988 if((is32>>regmap[hr])&1) {
1989 emit_sarimm(hr,31,hr);
1990 emit_storereg(r|64,hr);
1994 emit_storereg(r|64,hr);
2004 //if(!tracedebug) return 0;
2007 for(i=0;i<2097152;i++) {
2008 unsigned int temp=sum;
2011 sum^=((u_int *)rdram)[i];
2020 sum^=((u_int *)reg)[i];
2028 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2030 #ifndef DISABLE_COP1
2033 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2043 void memdebug(int i)
2045 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2046 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2049 //if(Count>=-2084597794) {
2050 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2052 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2053 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2054 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2057 printf("TRACE: %x\n",(&i)[-1]);
2061 printf("TRACE: %x \n",(&j)[10]);
2062 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2066 //printf("TRACE: %x\n",(&i)[-1]);
2069 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2071 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2074 void alu_assemble(int i,struct regstat *i_regs)
2076 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2078 signed char s1,s2,t;
2079 t=get_reg(i_regs->regmap,rt1[i]);
2081 s1=get_reg(i_regs->regmap,rs1[i]);
2082 s2=get_reg(i_regs->regmap,rs2[i]);
2083 if(rs1[i]&&rs2[i]) {
2086 if(opcode2[i]&2) emit_sub(s1,s2,t);
2087 else emit_add(s1,s2,t);
2090 if(s1>=0) emit_mov(s1,t);
2091 else emit_loadreg(rs1[i],t);
2095 if(opcode2[i]&2) emit_neg(s2,t);
2096 else emit_mov(s2,t);
2099 emit_loadreg(rs2[i],t);
2100 if(opcode2[i]&2) emit_neg(t,t);
2103 else emit_zeroreg(t);
2107 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2109 signed char s1l,s2l,s1h,s2h,tl,th;
2110 tl=get_reg(i_regs->regmap,rt1[i]);
2111 th=get_reg(i_regs->regmap,rt1[i]|64);
2113 s1l=get_reg(i_regs->regmap,rs1[i]);
2114 s2l=get_reg(i_regs->regmap,rs2[i]);
2115 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2116 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2117 if(rs1[i]&&rs2[i]) {
2120 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2121 else emit_adds(s1l,s2l,tl);
2123 #ifdef INVERTED_CARRY
2124 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2126 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2128 else emit_add(s1h,s2h,th);
2132 if(s1l>=0) emit_mov(s1l,tl);
2133 else emit_loadreg(rs1[i],tl);
2135 if(s1h>=0) emit_mov(s1h,th);
2136 else emit_loadreg(rs1[i]|64,th);
2141 if(opcode2[i]&2) emit_negs(s2l,tl);
2142 else emit_mov(s2l,tl);
2145 emit_loadreg(rs2[i],tl);
2146 if(opcode2[i]&2) emit_negs(tl,tl);
2149 #ifdef INVERTED_CARRY
2150 if(s2h>=0) emit_mov(s2h,th);
2151 else emit_loadreg(rs2[i]|64,th);
2153 emit_adcimm(-1,th); // x86 has inverted carry flag
2158 if(s2h>=0) emit_rscimm(s2h,0,th);
2160 emit_loadreg(rs2[i]|64,th);
2161 emit_rscimm(th,0,th);
2164 if(s2h>=0) emit_mov(s2h,th);
2165 else emit_loadreg(rs2[i]|64,th);
2172 if(th>=0) emit_zeroreg(th);
2177 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2179 signed char s1l,s1h,s2l,s2h,t;
2180 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2182 t=get_reg(i_regs->regmap,rt1[i]);
2185 s1l=get_reg(i_regs->regmap,rs1[i]);
2186 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2187 s2l=get_reg(i_regs->regmap,rs2[i]);
2188 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2189 if(rs2[i]==0) // rx<r0
2192 if(opcode2[i]==0x2a) // SLT
2193 emit_shrimm(s1h,31,t);
2194 else // SLTU (unsigned can not be less than zero)
2197 else if(rs1[i]==0) // r0<rx
2200 if(opcode2[i]==0x2a) // SLT
2201 emit_set_gz64_32(s2h,s2l,t);
2202 else // SLTU (set if not zero)
2203 emit_set_nz64_32(s2h,s2l,t);
2206 assert(s1l>=0);assert(s1h>=0);
2207 assert(s2l>=0);assert(s2h>=0);
2208 if(opcode2[i]==0x2a) // SLT
2209 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2211 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2215 t=get_reg(i_regs->regmap,rt1[i]);
2218 s1l=get_reg(i_regs->regmap,rs1[i]);
2219 s2l=get_reg(i_regs->regmap,rs2[i]);
2220 if(rs2[i]==0) // rx<r0
2223 if(opcode2[i]==0x2a) // SLT
2224 emit_shrimm(s1l,31,t);
2225 else // SLTU (unsigned can not be less than zero)
2228 else if(rs1[i]==0) // r0<rx
2231 if(opcode2[i]==0x2a) // SLT
2232 emit_set_gz32(s2l,t);
2233 else // SLTU (set if not zero)
2234 emit_set_nz32(s2l,t);
2237 assert(s1l>=0);assert(s2l>=0);
2238 if(opcode2[i]==0x2a) // SLT
2239 emit_set_if_less32(s1l,s2l,t);
2241 emit_set_if_carry32(s1l,s2l,t);
2247 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2249 signed char s1l,s1h,s2l,s2h,th,tl;
2250 tl=get_reg(i_regs->regmap,rt1[i]);
2251 th=get_reg(i_regs->regmap,rt1[i]|64);
2252 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2256 s1l=get_reg(i_regs->regmap,rs1[i]);
2257 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2258 s2l=get_reg(i_regs->regmap,rs2[i]);
2259 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2260 if(rs1[i]&&rs2[i]) {
2261 assert(s1l>=0);assert(s1h>=0);
2262 assert(s2l>=0);assert(s2h>=0);
2263 if(opcode2[i]==0x24) { // AND
2264 emit_and(s1l,s2l,tl);
2265 emit_and(s1h,s2h,th);
2267 if(opcode2[i]==0x25) { // OR
2268 emit_or(s1l,s2l,tl);
2269 emit_or(s1h,s2h,th);
2271 if(opcode2[i]==0x26) { // XOR
2272 emit_xor(s1l,s2l,tl);
2273 emit_xor(s1h,s2h,th);
2275 if(opcode2[i]==0x27) { // NOR
2276 emit_or(s1l,s2l,tl);
2277 emit_or(s1h,s2h,th);
2284 if(opcode2[i]==0x24) { // AND
2288 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2290 if(s1l>=0) emit_mov(s1l,tl);
2291 else emit_loadreg(rs1[i],tl);
2292 if(s1h>=0) emit_mov(s1h,th);
2293 else emit_loadreg(rs1[i]|64,th);
2297 if(s2l>=0) emit_mov(s2l,tl);
2298 else emit_loadreg(rs2[i],tl);
2299 if(s2h>=0) emit_mov(s2h,th);
2300 else emit_loadreg(rs2[i]|64,th);
2307 if(opcode2[i]==0x27) { // NOR
2309 if(s1l>=0) emit_not(s1l,tl);
2311 emit_loadreg(rs1[i],tl);
2314 if(s1h>=0) emit_not(s1h,th);
2316 emit_loadreg(rs1[i]|64,th);
2322 if(s2l>=0) emit_not(s2l,tl);
2324 emit_loadreg(rs2[i],tl);
2327 if(s2h>=0) emit_not(s2h,th);
2329 emit_loadreg(rs2[i]|64,th);
2345 s1l=get_reg(i_regs->regmap,rs1[i]);
2346 s2l=get_reg(i_regs->regmap,rs2[i]);
2347 if(rs1[i]&&rs2[i]) {
2350 if(opcode2[i]==0x24) { // AND
2351 emit_and(s1l,s2l,tl);
2353 if(opcode2[i]==0x25) { // OR
2354 emit_or(s1l,s2l,tl);
2356 if(opcode2[i]==0x26) { // XOR
2357 emit_xor(s1l,s2l,tl);
2359 if(opcode2[i]==0x27) { // NOR
2360 emit_or(s1l,s2l,tl);
2366 if(opcode2[i]==0x24) { // AND
2369 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2371 if(s1l>=0) emit_mov(s1l,tl);
2372 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2376 if(s2l>=0) emit_mov(s2l,tl);
2377 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2379 else emit_zeroreg(tl);
2381 if(opcode2[i]==0x27) { // NOR
2383 if(s1l>=0) emit_not(s1l,tl);
2385 emit_loadreg(rs1[i],tl);
2391 if(s2l>=0) emit_not(s2l,tl);
2393 emit_loadreg(rs2[i],tl);
2397 else emit_movimm(-1,tl);
2406 void imm16_assemble(int i,struct regstat *i_regs)
2408 if (opcode[i]==0x0f) { // LUI
2411 t=get_reg(i_regs->regmap,rt1[i]);
2414 if(!((i_regs->isconst>>t)&1))
2415 emit_movimm(imm[i]<<16,t);
2419 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2422 t=get_reg(i_regs->regmap,rt1[i]);
2423 s=get_reg(i_regs->regmap,rs1[i]);
2428 if(!((i_regs->isconst>>t)&1)) {
2430 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2431 emit_addimm(t,imm[i],t);
2433 if(!((i_regs->wasconst>>s)&1))
2434 emit_addimm(s,imm[i],t);
2436 emit_movimm(constmap[i][s]+imm[i],t);
2442 if(!((i_regs->isconst>>t)&1))
2443 emit_movimm(imm[i],t);
2448 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2450 signed char sh,sl,th,tl;
2451 th=get_reg(i_regs->regmap,rt1[i]|64);
2452 tl=get_reg(i_regs->regmap,rt1[i]);
2453 sh=get_reg(i_regs->regmap,rs1[i]|64);
2454 sl=get_reg(i_regs->regmap,rs1[i]);
2460 emit_addimm64_32(sh,sl,imm[i],th,tl);
2463 emit_addimm(sl,imm[i],tl);
2466 emit_movimm(imm[i],tl);
2467 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2472 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2474 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2475 signed char sh,sl,t;
2476 t=get_reg(i_regs->regmap,rt1[i]);
2477 sh=get_reg(i_regs->regmap,rs1[i]|64);
2478 sl=get_reg(i_regs->regmap,rs1[i]);
2482 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2483 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2484 if(opcode[i]==0x0a) { // SLTI
2486 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2487 emit_slti32(t,imm[i],t);
2489 emit_slti32(sl,imm[i],t);
2494 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2495 emit_sltiu32(t,imm[i],t);
2497 emit_sltiu32(sl,imm[i],t);
2502 if(opcode[i]==0x0a) // SLTI
2503 emit_slti64_32(sh,sl,imm[i],t);
2505 emit_sltiu64_32(sh,sl,imm[i],t);
2508 // SLTI(U) with r0 is just stupid,
2509 // nonetheless examples can be found
2510 if(opcode[i]==0x0a) // SLTI
2511 if(0<imm[i]) emit_movimm(1,t);
2512 else emit_zeroreg(t);
2515 if(imm[i]) emit_movimm(1,t);
2516 else emit_zeroreg(t);
2522 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2524 signed char sh,sl,th,tl;
2525 th=get_reg(i_regs->regmap,rt1[i]|64);
2526 tl=get_reg(i_regs->regmap,rt1[i]);
2527 sh=get_reg(i_regs->regmap,rs1[i]|64);
2528 sl=get_reg(i_regs->regmap,rs1[i]);
2529 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2530 if(opcode[i]==0x0c) //ANDI
2534 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2535 emit_andimm(tl,imm[i],tl);
2537 if(!((i_regs->wasconst>>sl)&1))
2538 emit_andimm(sl,imm[i],tl);
2540 emit_movimm(constmap[i][sl]&imm[i],tl);
2545 if(th>=0) emit_zeroreg(th);
2551 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2555 emit_loadreg(rs1[i]|64,th);
2560 if(opcode[i]==0x0d) //ORI
2562 emit_orimm(tl,imm[i],tl);
2564 if(!((i_regs->wasconst>>sl)&1))
2565 emit_orimm(sl,imm[i],tl);
2567 emit_movimm(constmap[i][sl]|imm[i],tl);
2569 if(opcode[i]==0x0e) //XORI
2571 emit_xorimm(tl,imm[i],tl);
2573 if(!((i_regs->wasconst>>sl)&1))
2574 emit_xorimm(sl,imm[i],tl);
2576 emit_movimm(constmap[i][sl]^imm[i],tl);
2580 emit_movimm(imm[i],tl);
2581 if(th>=0) emit_zeroreg(th);
2589 void shiftimm_assemble(int i,struct regstat *i_regs)
2591 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2595 t=get_reg(i_regs->regmap,rt1[i]);
2596 s=get_reg(i_regs->regmap,rs1[i]);
2605 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2607 if(opcode2[i]==0) // SLL
2609 emit_shlimm(s<0?t:s,imm[i],t);
2611 if(opcode2[i]==2) // SRL
2613 emit_shrimm(s<0?t:s,imm[i],t);
2615 if(opcode2[i]==3) // SRA
2617 emit_sarimm(s<0?t:s,imm[i],t);
2621 if(s>=0 && s!=t) emit_mov(s,t);
2625 //emit_storereg(rt1[i],t); //DEBUG
2628 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2631 signed char sh,sl,th,tl;
2632 th=get_reg(i_regs->regmap,rt1[i]|64);
2633 tl=get_reg(i_regs->regmap,rt1[i]);
2634 sh=get_reg(i_regs->regmap,rs1[i]|64);
2635 sl=get_reg(i_regs->regmap,rs1[i]);
2640 if(th>=0) emit_zeroreg(th);
2647 if(opcode2[i]==0x38) // DSLL
2649 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2650 emit_shlimm(sl,imm[i],tl);
2652 if(opcode2[i]==0x3a) // DSRL
2654 emit_shrdimm(sl,sh,imm[i],tl);
2655 if(th>=0) emit_shrimm(sh,imm[i],th);
2657 if(opcode2[i]==0x3b) // DSRA
2659 emit_shrdimm(sl,sh,imm[i],tl);
2660 if(th>=0) emit_sarimm(sh,imm[i],th);
2664 if(sl!=tl) emit_mov(sl,tl);
2665 if(th>=0&&sh!=th) emit_mov(sh,th);
2671 if(opcode2[i]==0x3c) // DSLL32
2674 signed char sl,tl,th;
2675 tl=get_reg(i_regs->regmap,rt1[i]);
2676 th=get_reg(i_regs->regmap,rt1[i]|64);
2677 sl=get_reg(i_regs->regmap,rs1[i]);
2686 emit_shlimm(th,imm[i]&31,th);
2691 if(opcode2[i]==0x3e) // DSRL32
2694 signed char sh,tl,th;
2695 tl=get_reg(i_regs->regmap,rt1[i]);
2696 th=get_reg(i_regs->regmap,rt1[i]|64);
2697 sh=get_reg(i_regs->regmap,rs1[i]|64);
2701 if(th>=0) emit_zeroreg(th);
2704 emit_shrimm(tl,imm[i]&31,tl);
2709 if(opcode2[i]==0x3f) // DSRA32
2713 tl=get_reg(i_regs->regmap,rt1[i]);
2714 sh=get_reg(i_regs->regmap,rs1[i]|64);
2720 emit_sarimm(tl,imm[i]&31,tl);
2727 #ifndef shift_assemble
2728 void shift_assemble(int i,struct regstat *i_regs)
2730 printf("Need shift_assemble for this architecture.\n");
2735 void load_assemble(int i,struct regstat *i_regs)
2737 int s,th,tl,addr,map=-1;
2740 int memtarget=0,c=0;
2742 th=get_reg(i_regs->regmap,rt1[i]|64);
2743 tl=get_reg(i_regs->regmap,rt1[i]);
2744 s=get_reg(i_regs->regmap,rs1[i]);
2746 for(hr=0;hr<HOST_REGS;hr++) {
2747 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2749 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2751 c=(i_regs->wasconst>>s)&1;
2752 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2753 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2755 //printf("load_assemble: c=%d\n",c);
2756 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2757 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2759 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2761 // could be FIFO, must perform the read
2763 assem_debug("(forced read)\n");
2764 tl=get_reg(i_regs->regmap,-1);
2768 if(offset||s<0||c) addr=tl;
2774 if(th>=0) reglist&=~(1<<th);
2777 //#define R29_HACK 1
2779 // Strmnnrmn's speed hack
2780 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2783 emit_cmpimm(addr,RAM_SIZE);
2785 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2786 // Hint to branch predictor that the branch is unlikely to be taken
2788 emit_jno_unlikely(0);
2796 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2797 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2798 map=get_reg(i_regs->regmap,TLREG);
2800 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2801 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2803 if (opcode[i]==0x20) { // LB
2805 #ifdef HOST_IMM_ADDR32
2807 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2811 //emit_xorimm(addr,3,tl);
2812 //gen_tlb_addr_r(tl,map);
2813 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2815 #ifdef BIG_ENDIAN_MIPS
2816 if(!c) emit_xorimm(addr,3,tl);
2817 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2819 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2820 else if (tl!=addr) emit_mov(addr,tl);
2822 emit_movsbl_indexed_tlb(x,tl,map,tl);
2825 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2828 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2830 if (opcode[i]==0x21) { // LH
2832 #ifdef HOST_IMM_ADDR32
2834 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2839 #ifdef BIG_ENDIAN_MIPS
2840 if(!c) emit_xorimm(addr,2,tl);
2841 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2843 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2844 else if (tl!=addr) emit_mov(addr,tl);
2847 //emit_movswl_indexed_tlb(x,tl,map,tl);
2850 gen_tlb_addr_r(tl,map);
2851 emit_movswl_indexed(x,tl,tl);
2853 emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2856 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2859 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2861 if (opcode[i]==0x23) { // LW
2863 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2864 #ifdef HOST_IMM_ADDR32
2866 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2869 emit_readword_indexed_tlb(0,addr,map,tl);
2871 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2874 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2876 if (opcode[i]==0x24) { // LBU
2878 #ifdef HOST_IMM_ADDR32
2880 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2884 //emit_xorimm(addr,3,tl);
2885 //gen_tlb_addr_r(tl,map);
2886 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2888 #ifdef BIG_ENDIAN_MIPS
2889 if(!c) emit_xorimm(addr,3,tl);
2890 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2892 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2893 else if (tl!=addr) emit_mov(addr,tl);
2895 emit_movzbl_indexed_tlb(x,tl,map,tl);
2898 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2901 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2903 if (opcode[i]==0x25) { // LHU
2905 #ifdef HOST_IMM_ADDR32
2907 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2912 #ifdef BIG_ENDIAN_MIPS
2913 if(!c) emit_xorimm(addr,2,tl);
2914 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2916 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2917 else if (tl!=addr) emit_mov(addr,tl);
2920 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2923 gen_tlb_addr_r(tl,map);
2924 emit_movzwl_indexed(x,tl,tl);
2926 emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2928 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2932 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2934 if (opcode[i]==0x27) { // LWU
2937 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2938 #ifdef HOST_IMM_ADDR32
2940 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2943 emit_readword_indexed_tlb(0,addr,map,tl);
2945 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2948 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2952 if (opcode[i]==0x37) { // LD
2954 //gen_tlb_addr_r(tl,map);
2955 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2956 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2957 #ifdef HOST_IMM_ADDR32
2959 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2962 emit_readdword_indexed_tlb(0,addr,map,th,tl);
2964 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2967 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2969 //emit_storereg(rt1[i],tl); // DEBUG
2971 //if(opcode[i]==0x23)
2972 //if(opcode[i]==0x24)
2973 //if(opcode[i]==0x23||opcode[i]==0x24)
2974 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2978 emit_readword((int)&last_count,ECX);
2980 if(get_reg(i_regs->regmap,CCREG)<0)
2981 emit_loadreg(CCREG,HOST_CCREG);
2982 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2983 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2984 emit_writeword(HOST_CCREG,(int)&Count);
2987 if(get_reg(i_regs->regmap,CCREG)<0)
2988 emit_loadreg(CCREG,0);
2990 emit_mov(HOST_CCREG,0);
2992 emit_addimm(0,2*ccadj[i],0);
2993 emit_writeword(0,(int)&Count);
2995 emit_call((int)memdebug);
2997 restore_regs(0x100f);
3001 #ifndef loadlr_assemble
3002 void loadlr_assemble(int i,struct regstat *i_regs)
3004 printf("Need loadlr_assemble for this architecture.\n");
3009 void store_assemble(int i,struct regstat *i_regs)
3014 int jaddr=0,jaddr2,type;
3015 int memtarget=0,c=0;
3016 int agr=AGEN1+(i&1);
3018 th=get_reg(i_regs->regmap,rs2[i]|64);
3019 tl=get_reg(i_regs->regmap,rs2[i]);
3020 s=get_reg(i_regs->regmap,rs1[i]);
3021 temp=get_reg(i_regs->regmap,agr);
3022 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3025 c=(i_regs->wasconst>>s)&1;
3026 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3027 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3031 for(hr=0;hr<HOST_REGS;hr++) {
3032 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3034 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3035 if(offset||s<0||c) addr=temp;
3040 // Strmnnrmn's speed hack
3042 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3044 emit_cmpimm(addr,RAM_SIZE);
3045 #ifdef DESTRUCTIVE_SHIFT
3046 if(s==addr) emit_mov(s,temp);
3049 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3053 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3054 // Hint to branch predictor that the branch is unlikely to be taken
3056 emit_jno_unlikely(0);
3064 if (opcode[i]==0x28) x=3; // SB
3065 if (opcode[i]==0x29) x=2; // SH
3066 map=get_reg(i_regs->regmap,TLREG);
3068 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3069 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3072 if (opcode[i]==0x28) { // SB
3075 #ifdef BIG_ENDIAN_MIPS
3076 if(!c) emit_xorimm(addr,3,temp);
3077 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3079 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3080 else if (addr!=temp) emit_mov(addr,temp);
3082 //gen_tlb_addr_w(temp,map);
3083 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3084 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3088 if (opcode[i]==0x29) { // SH
3091 #ifdef BIG_ENDIAN_MIPS
3092 if(!c) emit_xorimm(addr,2,temp);
3093 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3095 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3096 else if (addr!=temp) emit_mov(addr,temp);
3099 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3102 gen_tlb_addr_w(temp,map);
3103 emit_writehword_indexed(tl,x,temp);
3105 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3109 if (opcode[i]==0x2B) { // SW
3111 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3112 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3115 if (opcode[i]==0x3F) { // SD
3119 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3120 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3121 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3124 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3125 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3126 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3131 if(!using_tlb&&(!c||memtarget))
3132 // addr could be a temp, make sure it survives STORE*_STUB
3135 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3136 } else if(!memtarget) {
3137 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3141 #ifdef DESTRUCTIVE_SHIFT
3142 // The x86 shift operation is 'destructive'; it overwrites the
3143 // source register, so we need to make a copy first and use that.
3146 #if defined(HOST_IMM8)
3147 int ir=get_reg(i_regs->regmap,INVCP);
3149 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3151 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3155 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3158 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3159 //if(opcode[i]==0x2B || opcode[i]==0x28)
3160 //if(opcode[i]==0x2B || opcode[i]==0x29)
3161 //if(opcode[i]==0x2B)
3162 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3166 emit_readword((int)&last_count,ECX);
3168 if(get_reg(i_regs->regmap,CCREG)<0)
3169 emit_loadreg(CCREG,HOST_CCREG);
3170 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3171 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3172 emit_writeword(HOST_CCREG,(int)&Count);
3175 if(get_reg(i_regs->regmap,CCREG)<0)
3176 emit_loadreg(CCREG,0);
3178 emit_mov(HOST_CCREG,0);
3180 emit_addimm(0,2*ccadj[i],0);
3181 emit_writeword(0,(int)&Count);
3183 emit_call((int)memdebug);
3185 restore_regs(0x100f);
3189 void storelr_assemble(int i,struct regstat *i_regs)
3196 int case1,case2,case3;
3197 int done0,done1,done2;
3199 int agr=AGEN1+(i&1);
3201 th=get_reg(i_regs->regmap,rs2[i]|64);
3202 tl=get_reg(i_regs->regmap,rs2[i]);
3203 s=get_reg(i_regs->regmap,rs1[i]);
3204 temp=get_reg(i_regs->regmap,agr);
3205 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3208 c=(i_regs->isconst>>s)&1;
3209 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3210 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3213 for(hr=0;hr<HOST_REGS;hr++) {
3214 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3220 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3221 if(!offset&&s!=temp) emit_mov(s,temp);
3227 if(!memtarget||!rs1[i]) {
3232 if((u_int)rdram!=0x80000000)
3233 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3235 int map=get_reg(i_regs->regmap,TLREG);
3237 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3238 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3239 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3240 if(!jaddr&&!memtarget) {
3244 gen_tlb_addr_w(temp,map);
3247 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3248 temp2=get_reg(i_regs->regmap,FTEMP);
3249 if(!rs2[i]) temp2=th=tl;
3252 #ifndef BIG_ENDIAN_MIPS
3253 emit_xorimm(temp,3,temp);
3255 emit_testimm(temp,2);
3258 emit_testimm(temp,1);
3262 if (opcode[i]==0x2A) { // SWL
3263 emit_writeword_indexed(tl,0,temp);
3265 if (opcode[i]==0x2E) { // SWR
3266 emit_writebyte_indexed(tl,3,temp);
3268 if (opcode[i]==0x2C) { // SDL
3269 emit_writeword_indexed(th,0,temp);
3270 if(rs2[i]) emit_mov(tl,temp2);
3272 if (opcode[i]==0x2D) { // SDR
3273 emit_writebyte_indexed(tl,3,temp);
3274 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3279 set_jump_target(case1,(int)out);
3280 if (opcode[i]==0x2A) { // SWL
3281 // Write 3 msb into three least significant bytes
3282 if(rs2[i]) emit_rorimm(tl,8,tl);
3283 emit_writehword_indexed(tl,-1,temp);
3284 if(rs2[i]) emit_rorimm(tl,16,tl);
3285 emit_writebyte_indexed(tl,1,temp);
3286 if(rs2[i]) emit_rorimm(tl,8,tl);
3288 if (opcode[i]==0x2E) { // SWR
3289 // Write two lsb into two most significant bytes
3290 emit_writehword_indexed(tl,1,temp);
3292 if (opcode[i]==0x2C) { // SDL
3293 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3294 // Write 3 msb into three least significant bytes
3295 if(rs2[i]) emit_rorimm(th,8,th);
3296 emit_writehword_indexed(th,-1,temp);
3297 if(rs2[i]) emit_rorimm(th,16,th);
3298 emit_writebyte_indexed(th,1,temp);
3299 if(rs2[i]) emit_rorimm(th,8,th);
3301 if (opcode[i]==0x2D) { // SDR
3302 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3303 // Write two lsb into two most significant bytes
3304 emit_writehword_indexed(tl,1,temp);
3309 set_jump_target(case2,(int)out);
3310 emit_testimm(temp,1);
3313 if (opcode[i]==0x2A) { // SWL
3314 // Write two msb into two least significant bytes
3315 if(rs2[i]) emit_rorimm(tl,16,tl);
3316 emit_writehword_indexed(tl,-2,temp);
3317 if(rs2[i]) emit_rorimm(tl,16,tl);
3319 if (opcode[i]==0x2E) { // SWR
3320 // Write 3 lsb into three most significant bytes
3321 emit_writebyte_indexed(tl,-1,temp);
3322 if(rs2[i]) emit_rorimm(tl,8,tl);
3323 emit_writehword_indexed(tl,0,temp);
3324 if(rs2[i]) emit_rorimm(tl,24,tl);
3326 if (opcode[i]==0x2C) { // SDL
3327 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3328 // Write two msb into two least significant bytes
3329 if(rs2[i]) emit_rorimm(th,16,th);
3330 emit_writehword_indexed(th,-2,temp);
3331 if(rs2[i]) emit_rorimm(th,16,th);
3333 if (opcode[i]==0x2D) { // SDR
3334 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3335 // Write 3 lsb into three most significant bytes
3336 emit_writebyte_indexed(tl,-1,temp);
3337 if(rs2[i]) emit_rorimm(tl,8,tl);
3338 emit_writehword_indexed(tl,0,temp);
3339 if(rs2[i]) emit_rorimm(tl,24,tl);
3344 set_jump_target(case3,(int)out);
3345 if (opcode[i]==0x2A) { // SWL
3346 // Write msb into least significant byte
3347 if(rs2[i]) emit_rorimm(tl,24,tl);
3348 emit_writebyte_indexed(tl,-3,temp);
3349 if(rs2[i]) emit_rorimm(tl,8,tl);
3351 if (opcode[i]==0x2E) { // SWR
3352 // Write entire word
3353 emit_writeword_indexed(tl,-3,temp);
3355 if (opcode[i]==0x2C) { // SDL
3356 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3357 // Write msb into least significant byte
3358 if(rs2[i]) emit_rorimm(th,24,th);
3359 emit_writebyte_indexed(th,-3,temp);
3360 if(rs2[i]) emit_rorimm(th,8,th);
3362 if (opcode[i]==0x2D) { // SDR
3363 if(rs2[i]) emit_mov(th,temp2);
3364 // Write entire word
3365 emit_writeword_indexed(tl,-3,temp);
3367 set_jump_target(done0,(int)out);
3368 set_jump_target(done1,(int)out);
3369 set_jump_target(done2,(int)out);
3370 if (opcode[i]==0x2C) { // SDL
3371 emit_testimm(temp,4);