drc: implement memory access speculation
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2  *   Mupen64plus - new_dynarec.c                                           *
3  *   Copyright (C) 2009-2011 Ari64                                         *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21 #include <stdlib.h>
22 #include <stdint.h> //include for uint64_t
23 #include <assert.h>
24 #include <sys/mman.h>
25
26 #include "emu_if.h" //emulator interface
27
28 //#define DISASM
29 //#define assem_debug printf
30 //#define inv_debug printf
31 #define assem_debug(...)
32 #define inv_debug(...)
33
34 #ifdef __i386__
35 #include "assem_x86.h"
36 #endif
37 #ifdef __x86_64__
38 #include "assem_x64.h"
39 #endif
40 #ifdef __arm__
41 #include "assem_arm.h"
42 #endif
43
44 #define MAXBLOCK 4096
45 #define MAX_OUTPUT_BLOCK_SIZE 262144
46 #define CLOCK_DIVIDER 2
47
48 struct regstat
49 {
50   signed char regmap_entry[HOST_REGS];
51   signed char regmap[HOST_REGS];
52   uint64_t was32;
53   uint64_t is32;
54   uint64_t wasdirty;
55   uint64_t dirty;
56   uint64_t u;
57   uint64_t uu;
58   u_int wasconst;
59   u_int isconst;
60   uint64_t constmap[HOST_REGS];
61 };
62
63 struct ll_entry
64 {
65   u_int vaddr;
66   u_int reg32;
67   void *addr;
68   struct ll_entry *next;
69 };
70
71   u_int start;
72   u_int *source;
73   u_int pagelimit;
74   char insn[MAXBLOCK][10];
75   u_char itype[MAXBLOCK];
76   u_char opcode[MAXBLOCK];
77   u_char opcode2[MAXBLOCK];
78   u_char bt[MAXBLOCK];
79   u_char rs1[MAXBLOCK];
80   u_char rs2[MAXBLOCK];
81   u_char rt1[MAXBLOCK];
82   u_char rt2[MAXBLOCK];
83   u_char us1[MAXBLOCK];
84   u_char us2[MAXBLOCK];
85   u_char dep1[MAXBLOCK];
86   u_char dep2[MAXBLOCK];
87   u_char lt1[MAXBLOCK];
88   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
89   static uint64_t gte_rt[MAXBLOCK];
90   static uint64_t gte_unneeded[MAXBLOCK];
91   static int gte_reads_flags; // gte flag read encountered
92   static u_int smrv[32]; // speculated MIPS register values
93   static u_int smrv_strong; // mask or regs that are likely to have correct values
94   static u_int smrv_weak; // same, but somewhat less likely
95   static u_int smrv_strong_next; // same, but after current insn executes
96   static u_int smrv_weak_next;
97   int imm[MAXBLOCK];
98   u_int ba[MAXBLOCK];
99   char likely[MAXBLOCK];
100   char is_ds[MAXBLOCK];
101   char ooo[MAXBLOCK];
102   uint64_t unneeded_reg[MAXBLOCK];
103   uint64_t unneeded_reg_upper[MAXBLOCK];
104   uint64_t branch_unneeded_reg[MAXBLOCK];
105   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
106   uint64_t p32[MAXBLOCK];
107   uint64_t pr32[MAXBLOCK];
108   signed char regmap_pre[MAXBLOCK][HOST_REGS];
109   signed char regmap[MAXBLOCK][HOST_REGS];
110   signed char regmap_entry[MAXBLOCK][HOST_REGS];
111   uint64_t constmap[MAXBLOCK][HOST_REGS];
112   struct regstat regs[MAXBLOCK];
113   struct regstat branch_regs[MAXBLOCK];
114   signed char minimum_free_regs[MAXBLOCK];
115   u_int needed_reg[MAXBLOCK];
116   uint64_t requires_32bit[MAXBLOCK];
117   u_int wont_dirty[MAXBLOCK];
118   u_int will_dirty[MAXBLOCK];
119   int ccadj[MAXBLOCK];
120   int slen;
121   u_int instr_addr[MAXBLOCK];
122   u_int link_addr[MAXBLOCK][3];
123   int linkcount;
124   u_int stubs[MAXBLOCK*3][8];
125   int stubcount;
126   u_int literals[1024][2];
127   int literalcount;
128   int is_delayslot;
129   int cop1_usable;
130   u_char *out;
131   struct ll_entry *jump_in[4096];
132   struct ll_entry *jump_out[4096];
133   struct ll_entry *jump_dirty[4096];
134   u_int hash_table[65536][4]  __attribute__((aligned(16)));
135   char shadow[1048576]  __attribute__((aligned(16)));
136   void *copy;
137   int expirep;
138 #ifndef PCSX
139   u_int using_tlb;
140 #else
141   static const u_int using_tlb=0;
142 #endif
143   int new_dynarec_did_compile;
144   u_int stop_after_jal;
145   extern u_char restore_candidate[512];
146   extern int cycle_count;
147
148   /* registers that may be allocated */
149   /* 1-31 gpr */
150 #define HIREG 32 // hi
151 #define LOREG 33 // lo
152 #define FSREG 34 // FPU status (FCSR)
153 #define CSREG 35 // Coprocessor status
154 #define CCREG 36 // Cycle count
155 #define INVCP 37 // Pointer to invalid_code
156 #define MMREG 38 // Pointer to memory_map
157 #define ROREG 39 // ram offset (if rdram!=0x80000000)
158 #define TEMPREG 40
159 #define FTEMP 40 // FPU temporary register
160 #define PTEMP 41 // Prefetch temporary register
161 #define TLREG 42 // TLB mapping offset
162 #define RHASH 43 // Return address hash
163 #define RHTBL 44 // Return address hash table address
164 #define RTEMP 45 // JR/JALR address register
165 #define MAXREG 45
166 #define AGEN1 46 // Address generation temporary register
167 #define AGEN2 47 // Address generation temporary register
168 #define MGEN1 48 // Maptable address generation temporary register
169 #define MGEN2 49 // Maptable address generation temporary register
170 #define BTREG 50 // Branch target temporary register
171
172   /* instruction types */
173 #define NOP 0     // No operation
174 #define LOAD 1    // Load
175 #define STORE 2   // Store
176 #define LOADLR 3  // Unaligned load
177 #define STORELR 4 // Unaligned store
178 #define MOV 5     // Move 
179 #define ALU 6     // Arithmetic/logic
180 #define MULTDIV 7 // Multiply/divide
181 #define SHIFT 8   // Shift by register
182 #define SHIFTIMM 9// Shift by immediate
183 #define IMM16 10  // 16-bit immediate
184 #define RJUMP 11  // Unconditional jump to register
185 #define UJUMP 12  // Unconditional jump
186 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
187 #define SJUMP 14  // Conditional branch (regimm format)
188 #define COP0 15   // Coprocessor 0
189 #define COP1 16   // Coprocessor 1
190 #define C1LS 17   // Coprocessor 1 load/store
191 #define FJUMP 18  // Conditional branch (floating point)
192 #define FLOAT 19  // Floating point unit
193 #define FCONV 20  // Convert integer to float
194 #define FCOMP 21  // Floating point compare (sets FSREG)
195 #define SYSCALL 22// SYSCALL
196 #define OTHER 23  // Other
197 #define SPAN 24   // Branch/delay slot spans 2 pages
198 #define NI 25     // Not implemented
199 #define HLECALL 26// PCSX fake opcodes for HLE
200 #define COP2 27   // Coprocessor 2 move
201 #define C2LS 28   // Coprocessor 2 load/store
202 #define C2OP 29   // Coprocessor 2 operation
203 #define INTCALL 30// Call interpreter to handle rare corner cases
204
205   /* stubs */
206 #define CC_STUB 1
207 #define FP_STUB 2
208 #define LOADB_STUB 3
209 #define LOADH_STUB 4
210 #define LOADW_STUB 5
211 #define LOADD_STUB 6
212 #define LOADBU_STUB 7
213 #define LOADHU_STUB 8
214 #define STOREB_STUB 9
215 #define STOREH_STUB 10
216 #define STOREW_STUB 11
217 #define STORED_STUB 12
218 #define STORELR_STUB 13
219 #define INVCODE_STUB 14
220
221   /* branch codes */
222 #define TAKEN 1
223 #define NOTTAKEN 2
224 #define NULLDS 3
225
226 // asm linkage
227 int new_recompile_block(int addr);
228 void *get_addr_ht(u_int vaddr);
229 void invalidate_block(u_int block);
230 void invalidate_addr(u_int addr);
231 void remove_hash(int vaddr);
232 void jump_vaddr();
233 void dyna_linker();
234 void dyna_linker_ds();
235 void verify_code();
236 void verify_code_vm();
237 void verify_code_ds();
238 void cc_interrupt();
239 void fp_exception();
240 void fp_exception_ds();
241 void jump_syscall();
242 void jump_syscall_hle();
243 void jump_eret();
244 void jump_hlecall();
245 void jump_intcall();
246 void new_dyna_leave();
247
248 // TLB
249 void TLBWI_new();
250 void TLBWR_new();
251 void read_nomem_new();
252 void read_nomemb_new();
253 void read_nomemh_new();
254 void read_nomemd_new();
255 void write_nomem_new();
256 void write_nomemb_new();
257 void write_nomemh_new();
258 void write_nomemd_new();
259 void write_rdram_new();
260 void write_rdramb_new();
261 void write_rdramh_new();
262 void write_rdramd_new();
263 extern u_int memory_map[1048576];
264
265 // Needed by assembler
266 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
267 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
268 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
269 void load_all_regs(signed char i_regmap[]);
270 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
271 void load_regs_entry(int t);
272 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
273
274 int tracedebug=0;
275
276 //#define DEBUG_CYCLE_COUNT 1
277
278 static void tlb_hacks()
279 {
280 #ifndef DISABLE_TLB
281   // Goldeneye hack
282   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
283   {
284     u_int addr;
285     int n;
286     switch (ROM_HEADER->Country_code&0xFF) 
287     {
288       case 0x45: // U
289         addr=0x34b30;
290         break;                   
291       case 0x4A: // J 
292         addr=0x34b70;    
293         break;    
294       case 0x50: // E 
295         addr=0x329f0;
296         break;                        
297       default: 
298         // Unknown country code
299         addr=0;
300         break;
301     }
302     u_int rom_addr=(u_int)rom;
303     #ifdef ROM_COPY
304     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
305     // in the lower 4G of memory to use this hack.  Copy it if necessary.
306     if((void *)rom>(void *)0xffffffff) {
307       munmap(ROM_COPY, 67108864);
308       if(mmap(ROM_COPY, 12582912,
309               PROT_READ | PROT_WRITE,
310               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
311               -1, 0) <= 0) {printf("mmap() failed\n");}
312       memcpy(ROM_COPY,rom,12582912);
313       rom_addr=(u_int)ROM_COPY;
314     }
315     #endif
316     if(addr) {
317       for(n=0x7F000;n<0x80000;n++) {
318         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
319       }
320     }
321   }
322 #endif
323 }
324
325 static u_int get_page(u_int vaddr)
326 {
327 #ifndef PCSX
328   u_int page=(vaddr^0x80000000)>>12;
329 #else
330   u_int page=vaddr&~0xe0000000;
331   if (page < 0x1000000)
332     page &= ~0x0e00000; // RAM mirrors
333   page>>=12;
334 #endif
335 #ifndef DISABLE_TLB
336   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
337 #endif
338   if(page>2048) page=2048+(page&2047);
339   return page;
340 }
341
342 static u_int get_vpage(u_int vaddr)
343 {
344   u_int vpage=(vaddr^0x80000000)>>12;
345 #ifndef DISABLE_TLB
346   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
347 #endif
348   if(vpage>2048) vpage=2048+(vpage&2047);
349   return vpage;
350 }
351
352 // Get address from virtual address
353 // This is called from the recompiled JR/JALR instructions
354 void *get_addr(u_int vaddr)
355 {
356   u_int page=get_page(vaddr);
357   u_int vpage=get_vpage(vaddr);
358   struct ll_entry *head;
359   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
360   head=jump_in[page];
361   while(head!=NULL) {
362     if(head->vaddr==vaddr&&head->reg32==0) {
363   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
364       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
365       ht_bin[3]=ht_bin[1];
366       ht_bin[2]=ht_bin[0];
367       ht_bin[1]=(int)head->addr;
368       ht_bin[0]=vaddr;
369       return head->addr;
370     }
371     head=head->next;
372   }
373   head=jump_dirty[vpage];
374   while(head!=NULL) {
375     if(head->vaddr==vaddr&&head->reg32==0) {
376       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
377       // Don't restore blocks which are about to expire from the cache
378       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
379       if(verify_dirty(head->addr)) {
380         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
381         invalid_code[vaddr>>12]=0;
382         inv_code_start=inv_code_end=~0;
383         memory_map[vaddr>>12]|=0x40000000;
384         if(vpage<2048) {
385 #ifndef DISABLE_TLB
386           if(tlb_LUT_r[vaddr>>12]) {
387             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
388             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
389           }
390 #endif
391           restore_candidate[vpage>>3]|=1<<(vpage&7);
392         }
393         else restore_candidate[page>>3]|=1<<(page&7);
394         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
395         if(ht_bin[0]==vaddr) {
396           ht_bin[1]=(int)head->addr; // Replace existing entry
397         }
398         else
399         {
400           ht_bin[3]=ht_bin[1];
401           ht_bin[2]=ht_bin[0];
402           ht_bin[1]=(int)head->addr;
403           ht_bin[0]=vaddr;
404         }
405         return head->addr;
406       }
407     }
408     head=head->next;
409   }
410   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
411   int r=new_recompile_block(vaddr);
412   if(r==0) return get_addr(vaddr);
413   // Execute in unmapped page, generate pagefault execption
414   Status|=2;
415   Cause=(vaddr<<31)|0x8;
416   EPC=(vaddr&1)?vaddr-5:vaddr;
417   BadVAddr=(vaddr&~1);
418   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
419   EntryHi=BadVAddr&0xFFFFE000;
420   return get_addr_ht(0x80000000);
421 }
422 // Look up address in hash table first
423 void *get_addr_ht(u_int vaddr)
424 {
425   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
426   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
427   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
428   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
429   return get_addr(vaddr);
430 }
431
432 void *get_addr_32(u_int vaddr,u_int flags)
433 {
434 #ifdef FORCE32
435   return get_addr(vaddr);
436 #else
437   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
438   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
439   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
440   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
441   u_int page=get_page(vaddr);
442   u_int vpage=get_vpage(vaddr);
443   struct ll_entry *head;
444   head=jump_in[page];
445   while(head!=NULL) {
446     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
447       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
448       if(head->reg32==0) {
449         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
450         if(ht_bin[0]==-1) {
451           ht_bin[1]=(int)head->addr;
452           ht_bin[0]=vaddr;
453         }else if(ht_bin[2]==-1) {
454           ht_bin[3]=(int)head->addr;
455           ht_bin[2]=vaddr;
456         }
457         //ht_bin[3]=ht_bin[1];
458         //ht_bin[2]=ht_bin[0];
459         //ht_bin[1]=(int)head->addr;
460         //ht_bin[0]=vaddr;
461       }
462       return head->addr;
463     }
464     head=head->next;
465   }
466   head=jump_dirty[vpage];
467   while(head!=NULL) {
468     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
469       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
470       // Don't restore blocks which are about to expire from the cache
471       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
472       if(verify_dirty(head->addr)) {
473         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
474         invalid_code[vaddr>>12]=0;
475         inv_code_start=inv_code_end=~0;
476         memory_map[vaddr>>12]|=0x40000000;
477         if(vpage<2048) {
478 #ifndef DISABLE_TLB
479           if(tlb_LUT_r[vaddr>>12]) {
480             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
481             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
482           }
483 #endif
484           restore_candidate[vpage>>3]|=1<<(vpage&7);
485         }
486         else restore_candidate[page>>3]|=1<<(page&7);
487         if(head->reg32==0) {
488           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
489           if(ht_bin[0]==-1) {
490             ht_bin[1]=(int)head->addr;
491             ht_bin[0]=vaddr;
492           }else if(ht_bin[2]==-1) {
493             ht_bin[3]=(int)head->addr;
494             ht_bin[2]=vaddr;
495           }
496           //ht_bin[3]=ht_bin[1];
497           //ht_bin[2]=ht_bin[0];
498           //ht_bin[1]=(int)head->addr;
499           //ht_bin[0]=vaddr;
500         }
501         return head->addr;
502       }
503     }
504     head=head->next;
505   }
506   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
507   int r=new_recompile_block(vaddr);
508   if(r==0) return get_addr(vaddr);
509   // Execute in unmapped page, generate pagefault execption
510   Status|=2;
511   Cause=(vaddr<<31)|0x8;
512   EPC=(vaddr&1)?vaddr-5:vaddr;
513   BadVAddr=(vaddr&~1);
514   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
515   EntryHi=BadVAddr&0xFFFFE000;
516   return get_addr_ht(0x80000000);
517 #endif
518 }
519
520 void clear_all_regs(signed char regmap[])
521 {
522   int hr;
523   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
524 }
525
526 signed char get_reg(signed char regmap[],int r)
527 {
528   int hr;
529   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
530   return -1;
531 }
532
533 // Find a register that is available for two consecutive cycles
534 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
535 {
536   int hr;
537   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
538   return -1;
539 }
540
541 int count_free_regs(signed char regmap[])
542 {
543   int count=0;
544   int hr;
545   for(hr=0;hr<HOST_REGS;hr++)
546   {
547     if(hr!=EXCLUDE_REG) {
548       if(regmap[hr]<0) count++;
549     }
550   }
551   return count;
552 }
553
554 void dirty_reg(struct regstat *cur,signed char reg)
555 {
556   int hr;
557   if(!reg) return;
558   for (hr=0;hr<HOST_REGS;hr++) {
559     if((cur->regmap[hr]&63)==reg) {
560       cur->dirty|=1<<hr;
561     }
562   }
563 }
564
565 // If we dirty the lower half of a 64 bit register which is now being
566 // sign-extended, we need to dump the upper half.
567 // Note: Do this only after completion of the instruction, because
568 // some instructions may need to read the full 64-bit value even if
569 // overwriting it (eg SLTI, DSRA32).
570 static void flush_dirty_uppers(struct regstat *cur)
571 {
572   int hr,reg;
573   for (hr=0;hr<HOST_REGS;hr++) {
574     if((cur->dirty>>hr)&1) {
575       reg=cur->regmap[hr];
576       if(reg>=64) 
577         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
578     }
579   }
580 }
581
582 void set_const(struct regstat *cur,signed char reg,uint64_t value)
583 {
584   int hr;
585   if(!reg) return;
586   for (hr=0;hr<HOST_REGS;hr++) {
587     if(cur->regmap[hr]==reg) {
588       cur->isconst|=1<<hr;
589       cur->constmap[hr]=value;
590     }
591     else if((cur->regmap[hr]^64)==reg) {
592       cur->isconst|=1<<hr;
593       cur->constmap[hr]=value>>32;
594     }
595   }
596 }
597
598 void clear_const(struct regstat *cur,signed char reg)
599 {
600   int hr;
601   if(!reg) return;
602   for (hr=0;hr<HOST_REGS;hr++) {
603     if((cur->regmap[hr]&63)==reg) {
604       cur->isconst&=~(1<<hr);
605     }
606   }
607 }
608
609 int is_const(struct regstat *cur,signed char reg)
610 {
611   int hr;
612   if(reg<0) return 0;
613   if(!reg) return 1;
614   for (hr=0;hr<HOST_REGS;hr++) {
615     if((cur->regmap[hr]&63)==reg) {
616       return (cur->isconst>>hr)&1;
617     }
618   }
619   return 0;
620 }
621 uint64_t get_const(struct regstat *cur,signed char reg)
622 {
623   int hr;
624   if(!reg) return 0;
625   for (hr=0;hr<HOST_REGS;hr++) {
626     if(cur->regmap[hr]==reg) {
627       return cur->constmap[hr];
628     }
629   }
630   printf("Unknown constant in r%d\n",reg);
631   exit(1);
632 }
633
634 // Least soon needed registers
635 // Look at the next ten instructions and see which registers
636 // will be used.  Try not to reallocate these.
637 void lsn(u_char hsn[], int i, int *preferred_reg)
638 {
639   int j;
640   int b=-1;
641   for(j=0;j<9;j++)
642   {
643     if(i+j>=slen) {
644       j=slen-i-1;
645       break;
646     }
647     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
648     {
649       // Don't go past an unconditonal jump
650       j++;
651       break;
652     }
653   }
654   for(;j>=0;j--)
655   {
656     if(rs1[i+j]) hsn[rs1[i+j]]=j;
657     if(rs2[i+j]) hsn[rs2[i+j]]=j;
658     if(rt1[i+j]) hsn[rt1[i+j]]=j;
659     if(rt2[i+j]) hsn[rt2[i+j]]=j;
660     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
661       // Stores can allocate zero
662       hsn[rs1[i+j]]=j;
663       hsn[rs2[i+j]]=j;
664     }
665     // On some architectures stores need invc_ptr
666     #if defined(HOST_IMM8)
667     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
668       hsn[INVCP]=j;
669     }
670     #endif
671     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
672     {
673       hsn[CCREG]=j;
674       b=j;
675     }
676   }
677   if(b>=0)
678   {
679     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
680     {
681       // Follow first branch
682       int t=(ba[i+b]-start)>>2;
683       j=7-b;if(t+j>=slen) j=slen-t-1;
684       for(;j>=0;j--)
685       {
686         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
687         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
688         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
689         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
690       }
691     }
692     // TODO: preferred register based on backward branch
693   }
694   // Delay slot should preferably not overwrite branch conditions or cycle count
695   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
696     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
697     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
698     hsn[CCREG]=1;
699     // ...or hash tables
700     hsn[RHASH]=1;
701     hsn[RHTBL]=1;
702   }
703   // Coprocessor load/store needs FTEMP, even if not declared
704   if(itype[i]==C1LS||itype[i]==C2LS) {
705     hsn[FTEMP]=0;
706   }
707   // Load L/R also uses FTEMP as a temporary register
708   if(itype[i]==LOADLR) {
709     hsn[FTEMP]=0;
710   }
711   // Also SWL/SWR/SDL/SDR
712   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
713     hsn[FTEMP]=0;
714   }
715   // Don't remove the TLB registers either
716   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
717     hsn[TLREG]=0;
718   }
719   // Don't remove the miniht registers
720   if(itype[i]==UJUMP||itype[i]==RJUMP)
721   {
722     hsn[RHASH]=0;
723     hsn[RHTBL]=0;
724   }
725 }
726
727 // We only want to allocate registers if we're going to use them again soon
728 int needed_again(int r, int i)
729 {
730   int j;
731   int b=-1;
732   int rn=10;
733   
734   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
735   {
736     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
737       return 0; // Don't need any registers if exiting the block
738   }
739   for(j=0;j<9;j++)
740   {
741     if(i+j>=slen) {
742       j=slen-i-1;
743       break;
744     }
745     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
746     {
747       // Don't go past an unconditonal jump
748       j++;
749       break;
750     }
751     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
752     {
753       break;
754     }
755   }
756   for(;j>=1;j--)
757   {
758     if(rs1[i+j]==r) rn=j;
759     if(rs2[i+j]==r) rn=j;
760     if((unneeded_reg[i+j]>>r)&1) rn=10;
761     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
762     {
763       b=j;
764     }
765   }
766   /*
767   if(b>=0)
768   {
769     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
770     {
771       // Follow first branch
772       int o=rn;
773       int t=(ba[i+b]-start)>>2;
774       j=7-b;if(t+j>=slen) j=slen-t-1;
775       for(;j>=0;j--)
776       {
777         if(!((unneeded_reg[t+j]>>r)&1)) {
778           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
779           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
780         }
781         else rn=o;
782       }
783     }
784   }*/
785   if(rn<10) return 1;
786   return 0;
787 }
788
789 // Try to match register allocations at the end of a loop with those
790 // at the beginning
791 int loop_reg(int i, int r, int hr)
792 {
793   int j,k;
794   for(j=0;j<9;j++)
795   {
796     if(i+j>=slen) {
797       j=slen-i-1;
798       break;
799     }
800     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
801     {
802       // Don't go past an unconditonal jump
803       j++;
804       break;
805     }
806   }
807   k=0;
808   if(i>0){
809     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
810       k--;
811   }
812   for(;k<j;k++)
813   {
814     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
815     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
816     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
817     {
818       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
819       {
820         int t=(ba[i+k]-start)>>2;
821         int reg=get_reg(regs[t].regmap_entry,r);
822         if(reg>=0) return reg;
823         //reg=get_reg(regs[t+1].regmap_entry,r);
824         //if(reg>=0) return reg;
825       }
826     }
827   }
828   return hr;
829 }
830
831
832 // Allocate every register, preserving source/target regs
833 void alloc_all(struct regstat *cur,int i)
834 {
835   int hr;
836   
837   for(hr=0;hr<HOST_REGS;hr++) {
838     if(hr!=EXCLUDE_REG) {
839       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
840          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
841       {
842         cur->regmap[hr]=-1;
843         cur->dirty&=~(1<<hr);
844       }
845       // Don't need zeros
846       if((cur->regmap[hr]&63)==0)
847       {
848         cur->regmap[hr]=-1;
849         cur->dirty&=~(1<<hr);
850       }
851     }
852   }
853 }
854
855 #ifndef FORCE32
856 void div64(int64_t dividend,int64_t divisor)
857 {
858   lo=dividend/divisor;
859   hi=dividend%divisor;
860   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
861   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
862 }
863 void divu64(uint64_t dividend,uint64_t divisor)
864 {
865   lo=dividend/divisor;
866   hi=dividend%divisor;
867   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
868   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
869 }
870
871 void mult64(uint64_t m1,uint64_t m2)
872 {
873    unsigned long long int op1, op2, op3, op4;
874    unsigned long long int result1, result2, result3, result4;
875    unsigned long long int temp1, temp2, temp3, temp4;
876    int sign = 0;
877    
878    if (m1 < 0)
879      {
880     op2 = -m1;
881     sign = 1 - sign;
882      }
883    else op2 = m1;
884    if (m2 < 0)
885      {
886     op4 = -m2;
887     sign = 1 - sign;
888      }
889    else op4 = m2;
890    
891    op1 = op2 & 0xFFFFFFFF;
892    op2 = (op2 >> 32) & 0xFFFFFFFF;
893    op3 = op4 & 0xFFFFFFFF;
894    op4 = (op4 >> 32) & 0xFFFFFFFF;
895    
896    temp1 = op1 * op3;
897    temp2 = (temp1 >> 32) + op1 * op4;
898    temp3 = op2 * op3;
899    temp4 = (temp3 >> 32) + op2 * op4;
900    
901    result1 = temp1 & 0xFFFFFFFF;
902    result2 = temp2 + (temp3 & 0xFFFFFFFF);
903    result3 = (result2 >> 32) + temp4;
904    result4 = (result3 >> 32);
905    
906    lo = result1 | (result2 << 32);
907    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
908    if (sign)
909      {
910     hi = ~hi;
911     if (!lo) hi++;
912     else lo = ~lo + 1;
913      }
914 }
915
916 void multu64(uint64_t m1,uint64_t m2)
917 {
918    unsigned long long int op1, op2, op3, op4;
919    unsigned long long int result1, result2, result3, result4;
920    unsigned long long int temp1, temp2, temp3, temp4;
921    
922    op1 = m1 & 0xFFFFFFFF;
923    op2 = (m1 >> 32) & 0xFFFFFFFF;
924    op3 = m2 & 0xFFFFFFFF;
925    op4 = (m2 >> 32) & 0xFFFFFFFF;
926    
927    temp1 = op1 * op3;
928    temp2 = (temp1 >> 32) + op1 * op4;
929    temp3 = op2 * op3;
930    temp4 = (temp3 >> 32) + op2 * op4;
931    
932    result1 = temp1 & 0xFFFFFFFF;
933    result2 = temp2 + (temp3 & 0xFFFFFFFF);
934    result3 = (result2 >> 32) + temp4;
935    result4 = (result3 >> 32);
936    
937    lo = result1 | (result2 << 32);
938    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
939    
940   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
941   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
942 }
943
944 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
945 {
946   if(bits) {
947     original<<=64-bits;
948     original>>=64-bits;
949     loaded<<=bits;
950     original|=loaded;
951   }
952   else original=loaded;
953   return original;
954 }
955 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
956 {
957   if(bits^56) {
958     original>>=64-(bits^56);
959     original<<=64-(bits^56);
960     loaded>>=bits^56;
961     original|=loaded;
962   }
963   else original=loaded;
964   return original;
965 }
966 #endif
967
968 #ifdef __i386__
969 #include "assem_x86.c"
970 #endif
971 #ifdef __x86_64__
972 #include "assem_x64.c"
973 #endif
974 #ifdef __arm__
975 #include "assem_arm.c"
976 #endif
977
978 // Add virtual address mapping to linked list
979 void ll_add(struct ll_entry **head,int vaddr,void *addr)
980 {
981   struct ll_entry *new_entry;
982   new_entry=malloc(sizeof(struct ll_entry));
983   assert(new_entry!=NULL);
984   new_entry->vaddr=vaddr;
985   new_entry->reg32=0;
986   new_entry->addr=addr;
987   new_entry->next=*head;
988   *head=new_entry;
989 }
990
991 // Add virtual address mapping for 32-bit compiled block
992 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
993 {
994   ll_add(head,vaddr,addr);
995 #ifndef FORCE32
996   (*head)->reg32=reg32;
997 #endif
998 }
999
1000 // Check if an address is already compiled
1001 // but don't return addresses which are about to expire from the cache
1002 void *check_addr(u_int vaddr)
1003 {
1004   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1005   if(ht_bin[0]==vaddr) {
1006     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1007       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1008   }
1009   if(ht_bin[2]==vaddr) {
1010     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1011       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1012   }
1013   u_int page=get_page(vaddr);
1014   struct ll_entry *head;
1015   head=jump_in[page];
1016   while(head!=NULL) {
1017     if(head->vaddr==vaddr&&head->reg32==0) {
1018       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1019         // Update existing entry with current address
1020         if(ht_bin[0]==vaddr) {
1021           ht_bin[1]=(int)head->addr;
1022           return head->addr;
1023         }
1024         if(ht_bin[2]==vaddr) {
1025           ht_bin[3]=(int)head->addr;
1026           return head->addr;
1027         }
1028         // Insert into hash table with low priority.
1029         // Don't evict existing entries, as they are probably
1030         // addresses that are being accessed frequently.
1031         if(ht_bin[0]==-1) {
1032           ht_bin[1]=(int)head->addr;
1033           ht_bin[0]=vaddr;
1034         }else if(ht_bin[2]==-1) {
1035           ht_bin[3]=(int)head->addr;
1036           ht_bin[2]=vaddr;
1037         }
1038         return head->addr;
1039       }
1040     }
1041     head=head->next;
1042   }
1043   return 0;
1044 }
1045
1046 void remove_hash(int vaddr)
1047 {
1048   //printf("remove hash: %x\n",vaddr);
1049   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1050   if(ht_bin[2]==vaddr) {
1051     ht_bin[2]=ht_bin[3]=-1;
1052   }
1053   if(ht_bin[0]==vaddr) {
1054     ht_bin[0]=ht_bin[2];
1055     ht_bin[1]=ht_bin[3];
1056     ht_bin[2]=ht_bin[3]=-1;
1057   }
1058 }
1059
1060 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1061 {
1062   struct ll_entry *next;
1063   while(*head) {
1064     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) || 
1065        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1066     {
1067       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1068       remove_hash((*head)->vaddr);
1069       next=(*head)->next;
1070       free(*head);
1071       *head=next;
1072     }
1073     else
1074     {
1075       head=&((*head)->next);
1076     }
1077   }
1078 }
1079
1080 // Remove all entries from linked list
1081 void ll_clear(struct ll_entry **head)
1082 {
1083   struct ll_entry *cur;
1084   struct ll_entry *next;
1085   if(cur=*head) {
1086     *head=0;
1087     while(cur) {
1088       next=cur->next;
1089       free(cur);
1090       cur=next;
1091     }
1092   }
1093 }
1094
1095 // Dereference the pointers and remove if it matches
1096 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1097 {
1098   while(head) {
1099     int ptr=get_pointer(head->addr);
1100     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1101     if(((ptr>>shift)==(addr>>shift)) ||
1102        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1103     {
1104       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1105       u_int host_addr=(u_int)kill_pointer(head->addr);
1106       #ifdef __arm__
1107         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1108       #endif
1109     }
1110     head=head->next;
1111   }
1112 }
1113
1114 // This is called when we write to a compiled block (see do_invstub)
1115 void invalidate_page(u_int page)
1116 {
1117   struct ll_entry *head;
1118   struct ll_entry *next;
1119   head=jump_in[page];
1120   jump_in[page]=0;
1121   while(head!=NULL) {
1122     inv_debug("INVALIDATE: %x\n",head->vaddr);
1123     remove_hash(head->vaddr);
1124     next=head->next;
1125     free(head);
1126     head=next;
1127   }
1128   head=jump_out[page];
1129   jump_out[page]=0;
1130   while(head!=NULL) {
1131     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1132     u_int host_addr=(u_int)kill_pointer(head->addr);
1133     #ifdef __arm__
1134       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1135     #endif
1136     next=head->next;
1137     free(head);
1138     head=next;
1139   }
1140 }
1141
1142 static void invalidate_block_range(u_int block, u_int first, u_int last)
1143 {
1144   u_int page=get_page(block<<12);
1145   //printf("first=%d last=%d\n",first,last);
1146   invalidate_page(page);
1147   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1148   assert(last<page+5);
1149   // Invalidate the adjacent pages if a block crosses a 4K boundary
1150   while(first<page) {
1151     invalidate_page(first);
1152     first++;
1153   }
1154   for(first=page+1;first<last;first++) {
1155     invalidate_page(first);
1156   }
1157   #ifdef __arm__
1158     do_clear_cache();
1159   #endif
1160   
1161   // Don't trap writes
1162   invalid_code[block]=1;
1163 #ifndef DISABLE_TLB
1164   // If there is a valid TLB entry for this page, remove write protect
1165   if(tlb_LUT_w[block]) {
1166     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1167     // CHECK: Is this right?
1168     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1169     u_int real_block=tlb_LUT_w[block]>>12;
1170     invalid_code[real_block]=1;
1171     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1172   }
1173   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1174 #endif
1175
1176   #ifdef USE_MINI_HT
1177   memset(mini_ht,-1,sizeof(mini_ht));
1178   #endif
1179 }
1180
1181 void invalidate_block(u_int block)
1182 {
1183   u_int page=get_page(block<<12);
1184   u_int vpage=get_vpage(block<<12);
1185   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1186   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1187   u_int first,last;
1188   first=last=page;
1189   struct ll_entry *head;
1190   head=jump_dirty[vpage];
1191   //printf("page=%d vpage=%d\n",page,vpage);
1192   while(head!=NULL) {
1193     u_int start,end;
1194     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1195       get_bounds((int)head->addr,&start,&end);
1196       //printf("start: %x end: %x\n",start,end);
1197       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1198         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1199           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1200           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1201         }
1202       }
1203 #ifndef DISABLE_TLB
1204       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1205         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1206           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1207           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1208         }
1209       }
1210 #endif
1211     }
1212     head=head->next;
1213   }
1214   invalidate_block_range(block,first,last);
1215 }
1216
1217 void invalidate_addr(u_int addr)
1218 {
1219 #ifdef PCSX
1220   //static int rhits;
1221   // this check is done by the caller
1222   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1223   u_int page=get_page(addr);
1224   if(page<2048) { // RAM
1225     struct ll_entry *head;
1226     u_int addr_min=~0, addr_max=0;
1227     int mask=RAM_SIZE-1;
1228     int pg1;
1229     inv_code_start=addr&~0xfff;
1230     inv_code_end=addr|0xfff;
1231     pg1=page;
1232     if (pg1>0) {
1233       // must check previous page too because of spans..
1234       pg1--;
1235       inv_code_start-=0x1000;
1236     }
1237     for(;pg1<=page;pg1++) {
1238       for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1239         u_int start,end;
1240         get_bounds((int)head->addr,&start,&end);
1241         if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1242           if(start<addr_min) addr_min=start;
1243           if(end>addr_max) addr_max=end;
1244         }
1245         else if(addr<start) {
1246           if(start<inv_code_end)
1247             inv_code_end=start-1;
1248         }
1249         else {
1250           if(end>inv_code_start)
1251             inv_code_start=end;
1252         }
1253       }
1254     }
1255     if (addr_min!=~0) {
1256       inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1257       inv_code_start=inv_code_end=~0;
1258       invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1259       return;
1260     }
1261     else {
1262       inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1263     }
1264     //rhits=0;
1265     if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1266       return;
1267   }
1268 #endif
1269   invalidate_block(addr>>12);
1270 }
1271
1272 // This is called when loading a save state.
1273 // Anything could have changed, so invalidate everything.
1274 void invalidate_all_pages()
1275 {
1276   u_int page,n;
1277   for(page=0;page<4096;page++)
1278     invalidate_page(page);
1279   for(page=0;page<1048576;page++)
1280     if(!invalid_code[page]) {
1281       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1282       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1283     }
1284   #ifdef __arm__
1285   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1286   #endif
1287   #ifdef USE_MINI_HT
1288   memset(mini_ht,-1,sizeof(mini_ht));
1289   #endif
1290   #ifndef DISABLE_TLB
1291   // TLB
1292   for(page=0;page<0x100000;page++) {
1293     if(tlb_LUT_r[page]) {
1294       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1295       if(!tlb_LUT_w[page]||!invalid_code[page])
1296         memory_map[page]|=0x40000000; // Write protect
1297     }
1298     else memory_map[page]=-1;
1299     if(page==0x80000) page=0xC0000;
1300   }
1301   tlb_hacks();
1302   #endif
1303 }
1304
1305 // Add an entry to jump_out after making a link
1306 void add_link(u_int vaddr,void *src)
1307 {
1308   u_int page=get_page(vaddr);
1309   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1310   int *ptr=(int *)(src+4);
1311   assert((*ptr&0x0fff0000)==0x059f0000);
1312   ll_add(jump_out+page,vaddr,src);
1313   //int ptr=get_pointer(src);
1314   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1315 }
1316
1317 // If a code block was found to be unmodified (bit was set in
1318 // restore_candidate) and it remains unmodified (bit is clear
1319 // in invalid_code) then move the entries for that 4K page from
1320 // the dirty list to the clean list.
1321 void clean_blocks(u_int page)
1322 {
1323   struct ll_entry *head;
1324   inv_debug("INV: clean_blocks page=%d\n",page);
1325   head=jump_dirty[page];
1326   while(head!=NULL) {
1327     if(!invalid_code[head->vaddr>>12]) {
1328       // Don't restore blocks which are about to expire from the cache
1329       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1330         u_int start,end;
1331         if(verify_dirty((int)head->addr)) {
1332           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1333           u_int i;
1334           u_int inv=0;
1335           get_bounds((int)head->addr,&start,&end);
1336           if(start-(u_int)rdram<RAM_SIZE) {
1337             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1338               inv|=invalid_code[i];
1339             }
1340           }
1341           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1342             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1343             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1344             if(addr<start||addr>=end) inv=1;
1345           }
1346           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1347             inv=1;
1348           }
1349           if(!inv) {
1350             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1351             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1352               u_int ppage=page;
1353 #ifndef DISABLE_TLB
1354               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1355 #endif
1356               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1357               //printf("page=%x, addr=%x\n",page,head->vaddr);
1358               //assert(head->vaddr>>12==(page|0x80000));
1359               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1360               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1361               if(!head->reg32) {
1362                 if(ht_bin[0]==head->vaddr) {
1363                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1364                 }
1365                 if(ht_bin[2]==head->vaddr) {
1366                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1367                 }
1368               }
1369             }
1370           }
1371         }
1372       }
1373     }
1374     head=head->next;
1375   }
1376 }
1377
1378
1379 void mov_alloc(struct regstat *current,int i)
1380 {
1381   // Note: Don't need to actually alloc the source registers
1382   if((~current->is32>>rs1[i])&1) {
1383     //alloc_reg64(current,i,rs1[i]);
1384     alloc_reg64(current,i,rt1[i]);
1385     current->is32&=~(1LL<<rt1[i]);
1386   } else {
1387     //alloc_reg(current,i,rs1[i]);
1388     alloc_reg(current,i,rt1[i]);
1389     current->is32|=(1LL<<rt1[i]);
1390   }
1391   clear_const(current,rs1[i]);
1392   clear_const(current,rt1[i]);
1393   dirty_reg(current,rt1[i]);
1394 }
1395
1396 void shiftimm_alloc(struct regstat *current,int i)
1397 {
1398   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1399   {
1400     if(rt1[i]) {
1401       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1402       else lt1[i]=rs1[i];
1403       alloc_reg(current,i,rt1[i]);
1404       current->is32|=1LL<<rt1[i];
1405       dirty_reg(current,rt1[i]);
1406       if(is_const(current,rs1[i])) {
1407         int v=get_const(current,rs1[i]);
1408         if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1409         if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1410         if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1411       }
1412       else clear_const(current,rt1[i]);
1413     }
1414   }
1415   else
1416   {
1417     clear_const(current,rs1[i]);
1418     clear_const(current,rt1[i]);
1419   }
1420
1421   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1422   {
1423     if(rt1[i]) {
1424       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1425       alloc_reg64(current,i,rt1[i]);
1426       current->is32&=~(1LL<<rt1[i]);
1427       dirty_reg(current,rt1[i]);
1428     }
1429   }
1430   if(opcode2[i]==0x3c) // DSLL32
1431   {
1432     if(rt1[i]) {
1433       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1434       alloc_reg64(current,i,rt1[i]);
1435       current->is32&=~(1LL<<rt1[i]);
1436       dirty_reg(current,rt1[i]);
1437     }
1438   }
1439   if(opcode2[i]==0x3e) // DSRL32
1440   {
1441     if(rt1[i]) {
1442       alloc_reg64(current,i,rs1[i]);
1443       if(imm[i]==32) {
1444         alloc_reg64(current,i,rt1[i]);
1445         current->is32&=~(1LL<<rt1[i]);
1446       } else {
1447         alloc_reg(current,i,rt1[i]);
1448         current->is32|=1LL<<rt1[i];
1449       }
1450       dirty_reg(current,rt1[i]);
1451     }
1452   }
1453   if(opcode2[i]==0x3f) // DSRA32
1454   {
1455     if(rt1[i]) {
1456       alloc_reg64(current,i,rs1[i]);
1457       alloc_reg(current,i,rt1[i]);
1458       current->is32|=1LL<<rt1[i];
1459       dirty_reg(current,rt1[i]);
1460     }
1461   }
1462 }
1463
1464 void shift_alloc(struct regstat *current,int i)
1465 {
1466   if(rt1[i]) {
1467     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1468     {
1469       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1470       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1471       alloc_reg(current,i,rt1[i]);
1472       if(rt1[i]==rs2[i]) {
1473         alloc_reg_temp(current,i,-1);
1474         minimum_free_regs[i]=1;
1475       }
1476       current->is32|=1LL<<rt1[i];
1477     } else { // DSLLV/DSRLV/DSRAV
1478       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1479       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1480       alloc_reg64(current,i,rt1[i]);
1481       current->is32&=~(1LL<<rt1[i]);
1482       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1483       {
1484         alloc_reg_temp(current,i,-1);
1485         minimum_free_regs[i]=1;
1486       }
1487     }
1488     clear_const(current,rs1[i]);
1489     clear_const(current,rs2[i]);
1490     clear_const(current,rt1[i]);
1491     dirty_reg(current,rt1[i]);
1492   }
1493 }
1494
1495 void alu_alloc(struct regstat *current,int i)
1496 {
1497   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1498     if(rt1[i]) {
1499       if(rs1[i]&&rs2[i]) {
1500         alloc_reg(current,i,rs1[i]);
1501         alloc_reg(current,i,rs2[i]);
1502       }
1503       else {
1504         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1505         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1506       }
1507       alloc_reg(current,i,rt1[i]);
1508     }
1509     current->is32|=1LL<<rt1[i];
1510   }
1511   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1512     if(rt1[i]) {
1513       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1514       {
1515         alloc_reg64(current,i,rs1[i]);
1516         alloc_reg64(current,i,rs2[i]);
1517         alloc_reg(current,i,rt1[i]);
1518       } else {
1519         alloc_reg(current,i,rs1[i]);
1520         alloc_reg(current,i,rs2[i]);
1521         alloc_reg(current,i,rt1[i]);
1522       }
1523     }
1524     current->is32|=1LL<<rt1[i];
1525   }
1526   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1527     if(rt1[i]) {
1528       if(rs1[i]&&rs2[i]) {
1529         alloc_reg(current,i,rs1[i]);
1530         alloc_reg(current,i,rs2[i]);
1531       }
1532       else
1533       {
1534         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1535         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1536       }
1537       alloc_reg(current,i,rt1[i]);
1538       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1539       {
1540         if(!((current->uu>>rt1[i])&1)) {
1541           alloc_reg64(current,i,rt1[i]);
1542         }
1543         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1544           if(rs1[i]&&rs2[i]) {
1545             alloc_reg64(current,i,rs1[i]);
1546             alloc_reg64(current,i,rs2[i]);
1547           }
1548           else
1549           {
1550             // Is is really worth it to keep 64-bit values in registers?
1551             #ifdef NATIVE_64BIT
1552             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1553             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1554             #endif
1555           }
1556         }
1557         current->is32&=~(1LL<<rt1[i]);
1558       } else {
1559         current->is32|=1LL<<rt1[i];
1560       }
1561     }
1562   }
1563   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1564     if(rt1[i]) {
1565       if(rs1[i]&&rs2[i]) {
1566         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1567           alloc_reg64(current,i,rs1[i]);
1568           alloc_reg64(current,i,rs2[i]);
1569           alloc_reg64(current,i,rt1[i]);
1570         } else {
1571           alloc_reg(current,i,rs1[i]);
1572           alloc_reg(current,i,rs2[i]);
1573           alloc_reg(current,i,rt1[i]);
1574         }
1575       }
1576       else {
1577         alloc_reg(current,i,rt1[i]);
1578         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1579           // DADD used as move, or zeroing
1580           // If we have a 64-bit source, then make the target 64 bits too
1581           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1582             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1583             alloc_reg64(current,i,rt1[i]);
1584           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1585             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1586             alloc_reg64(current,i,rt1[i]);
1587           }
1588           if(opcode2[i]>=0x2e&&rs2[i]) {
1589             // DSUB used as negation - 64-bit result
1590             // If we have a 32-bit register, extend it to 64 bits
1591             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1592             alloc_reg64(current,i,rt1[i]);
1593           }
1594         }
1595       }
1596       if(rs1[i]&&rs2[i]) {
1597         current->is32&=~(1LL<<rt1[i]);
1598       } else if(rs1[i]) {
1599         current->is32&=~(1LL<<rt1[i]);
1600         if((current->is32>>rs1[i])&1)
1601           current->is32|=1LL<<rt1[i];
1602       } else if(rs2[i]) {
1603         current->is32&=~(1LL<<rt1[i]);
1604         if((current->is32>>rs2[i])&1)
1605           current->is32|=1LL<<rt1[i];
1606       } else {
1607         current->is32|=1LL<<rt1[i];
1608       }
1609     }
1610   }
1611   clear_const(current,rs1[i]);
1612   clear_const(current,rs2[i]);
1613   clear_const(current,rt1[i]);
1614   dirty_reg(current,rt1[i]);
1615 }
1616
1617 void imm16_alloc(struct regstat *current,int i)
1618 {
1619   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1620   else lt1[i]=rs1[i];
1621   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1622   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1623     current->is32&=~(1LL<<rt1[i]);
1624     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1625       // TODO: Could preserve the 32-bit flag if the immediate is zero
1626       alloc_reg64(current,i,rt1[i]);
1627       alloc_reg64(current,i,rs1[i]);
1628     }
1629     clear_const(current,rs1[i]);
1630     clear_const(current,rt1[i]);
1631   }
1632   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1633     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1634     current->is32|=1LL<<rt1[i];
1635     clear_const(current,rs1[i]);
1636     clear_const(current,rt1[i]);
1637   }
1638   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1639     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1640       if(rs1[i]!=rt1[i]) {
1641         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1642         alloc_reg64(current,i,rt1[i]);
1643         current->is32&=~(1LL<<rt1[i]);
1644       }
1645     }
1646     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1647     if(is_const(current,rs1[i])) {
1648       int v=get_const(current,rs1[i]);
1649       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1650       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1651       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1652     }
1653     else clear_const(current,rt1[i]);
1654   }
1655   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1656     if(is_const(current,rs1[i])) {
1657       int v=get_const(current,rs1[i]);
1658       set_const(current,rt1[i],v+imm[i]);
1659     }
1660     else clear_const(current,rt1[i]);
1661     current->is32|=1LL<<rt1[i];
1662   }
1663   else {
1664     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1665     current->is32|=1LL<<rt1[i];
1666   }
1667   dirty_reg(current,rt1[i]);
1668 }
1669
1670 void load_alloc(struct regstat *current,int i)
1671 {
1672   clear_const(current,rt1[i]);
1673   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1674   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1675   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1676   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1677     alloc_reg(current,i,rt1[i]);
1678     assert(get_reg(current->regmap,rt1[i])>=0);
1679     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1680     {
1681       current->is32&=~(1LL<<rt1[i]);
1682       alloc_reg64(current,i,rt1[i]);
1683     }
1684     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1685     {
1686       current->is32&=~(1LL<<rt1[i]);
1687       alloc_reg64(current,i,rt1[i]);
1688       alloc_all(current,i);
1689       alloc_reg64(current,i,FTEMP);
1690       minimum_free_regs[i]=HOST_REGS;
1691     }
1692     else current->is32|=1LL<<rt1[i];
1693     dirty_reg(current,rt1[i]);
1694     // If using TLB, need a register for pointer to the mapping table
1695     if(using_tlb) alloc_reg(current,i,TLREG);
1696     // LWL/LWR need a temporary register for the old value
1697     if(opcode[i]==0x22||opcode[i]==0x26)
1698     {
1699       alloc_reg(current,i,FTEMP);
1700       alloc_reg_temp(current,i,-1);
1701       minimum_free_regs[i]=1;
1702     }
1703   }
1704   else
1705   {
1706     // Load to r0 or unneeded register (dummy load)
1707     // but we still need a register to calculate the address
1708     if(opcode[i]==0x22||opcode[i]==0x26)
1709     {
1710       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1711     }
1712     // If using TLB, need a register for pointer to the mapping table
1713     if(using_tlb) alloc_reg(current,i,TLREG);
1714     alloc_reg_temp(current,i,-1);
1715     minimum_free_regs[i]=1;
1716     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1717     {
1718       alloc_all(current,i);
1719       alloc_reg64(current,i,FTEMP);
1720       minimum_free_regs[i]=HOST_REGS;
1721     }
1722   }
1723 }
1724
1725 void store_alloc(struct regstat *current,int i)
1726 {
1727   clear_const(current,rs2[i]);
1728   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1729   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1730   alloc_reg(current,i,rs2[i]);
1731   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1732     alloc_reg64(current,i,rs2[i]);
1733     if(rs2[i]) alloc_reg(current,i,FTEMP);
1734   }
1735   // If using TLB, need a register for pointer to the mapping table
1736   if(using_tlb) alloc_reg(current,i,TLREG);
1737   #if defined(HOST_IMM8)
1738   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1739   else alloc_reg(current,i,INVCP);
1740   #endif
1741   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1742     alloc_reg(current,i,FTEMP);
1743   }
1744   // We need a temporary register for address generation
1745   alloc_reg_temp(current,i,-1);
1746   minimum_free_regs[i]=1;
1747 }
1748
1749 void c1ls_alloc(struct regstat *current,int i)
1750 {
1751   //clear_const(current,rs1[i]); // FIXME
1752   clear_const(current,rt1[i]);
1753   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1754   alloc_reg(current,i,CSREG); // Status
1755   alloc_reg(current,i,FTEMP);
1756   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1757     alloc_reg64(current,i,FTEMP);
1758   }
1759   // If using TLB, need a register for pointer to the mapping table
1760   if(using_tlb) alloc_reg(current,i,TLREG);
1761   #if defined(HOST_IMM8)
1762   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1763   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1764     alloc_reg(current,i,INVCP);
1765   #endif
1766   // We need a temporary register for address generation
1767   alloc_reg_temp(current,i,-1);
1768 }
1769
1770 void c2ls_alloc(struct regstat *current,int i)
1771 {
1772   clear_const(current,rt1[i]);
1773   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1774   alloc_reg(current,i,FTEMP);
1775   // If using TLB, need a register for pointer to the mapping table
1776   if(using_tlb) alloc_reg(current,i,TLREG);
1777   #if defined(HOST_IMM8)
1778   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1779   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1780     alloc_reg(current,i,INVCP);
1781   #endif
1782   // We need a temporary register for address generation
1783   alloc_reg_temp(current,i,-1);
1784   minimum_free_regs[i]=1;
1785 }
1786
1787 #ifndef multdiv_alloc
1788 void multdiv_alloc(struct regstat *current,int i)
1789 {
1790   //  case 0x18: MULT
1791   //  case 0x19: MULTU
1792   //  case 0x1A: DIV
1793   //  case 0x1B: DIVU
1794   //  case 0x1C: DMULT
1795   //  case 0x1D: DMULTU
1796   //  case 0x1E: DDIV
1797   //  case 0x1F: DDIVU
1798   clear_const(current,rs1[i]);
1799   clear_const(current,rs2[i]);
1800   if(rs1[i]&&rs2[i])
1801   {
1802     if((opcode2[i]&4)==0) // 32-bit
1803     {
1804       current->u&=~(1LL<<HIREG);
1805       current->u&=~(1LL<<LOREG);
1806       alloc_reg(current,i,HIREG);
1807       alloc_reg(current,i,LOREG);
1808       alloc_reg(current,i,rs1[i]);
1809       alloc_reg(current,i,rs2[i]);
1810       current->is32|=1LL<<HIREG;
1811       current->is32|=1LL<<LOREG;
1812       dirty_reg(current,HIREG);
1813       dirty_reg(current,LOREG);
1814     }
1815     else // 64-bit
1816     {
1817       current->u&=~(1LL<<HIREG);
1818       current->u&=~(1LL<<LOREG);
1819       current->uu&=~(1LL<<HIREG);
1820       current->uu&=~(1LL<<LOREG);
1821       alloc_reg64(current,i,HIREG);
1822       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1823       alloc_reg64(current,i,rs1[i]);
1824       alloc_reg64(current,i,rs2[i]);
1825       alloc_all(current,i);
1826       current->is32&=~(1LL<<HIREG);
1827       current->is32&=~(1LL<<LOREG);
1828       dirty_reg(current,HIREG);
1829       dirty_reg(current,LOREG);
1830       minimum_free_regs[i]=HOST_REGS;
1831     }
1832   }
1833   else
1834   {
1835     // Multiply by zero is zero.
1836     // MIPS does not have a divide by zero exception.
1837     // The result is undefined, we return zero.
1838     alloc_reg(current,i,HIREG);
1839     alloc_reg(current,i,LOREG);
1840     current->is32|=1LL<<HIREG;
1841     current->is32|=1LL<<LOREG;
1842     dirty_reg(current,HIREG);
1843     dirty_reg(current,LOREG);
1844   }
1845 }
1846 #endif
1847
1848 void cop0_alloc(struct regstat *current,int i)
1849 {
1850   if(opcode2[i]==0) // MFC0
1851   {
1852     if(rt1[i]) {
1853       clear_const(current,rt1[i]);
1854       alloc_all(current,i);
1855       alloc_reg(current,i,rt1[i]);
1856       current->is32|=1LL<<rt1[i];
1857       dirty_reg(current,rt1[i]);
1858     }
1859   }
1860   else if(opcode2[i]==4) // MTC0
1861   {
1862     if(rs1[i]){
1863       clear_const(current,rs1[i]);
1864       alloc_reg(current,i,rs1[i]);
1865       alloc_all(current,i);
1866     }
1867     else {
1868       alloc_all(current,i); // FIXME: Keep r0
1869       current->u&=~1LL;
1870       alloc_reg(current,i,0);
1871     }
1872   }
1873   else
1874   {
1875     // TLBR/TLBWI/TLBWR/TLBP/ERET
1876     assert(opcode2[i]==0x10);
1877     alloc_all(current,i);
1878   }
1879   minimum_free_regs[i]=HOST_REGS;
1880 }
1881
1882 void cop1_alloc(struct regstat *current,int i)
1883 {
1884   alloc_reg(current,i,CSREG); // Load status
1885   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1886   {
1887     if(rt1[i]){
1888       clear_const(current,rt1[i]);
1889       if(opcode2[i]==1) {
1890         alloc_reg64(current,i,rt1[i]); // DMFC1
1891         current->is32&=~(1LL<<rt1[i]);
1892       }else{
1893         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1894         current->is32|=1LL<<rt1[i];
1895       }
1896       dirty_reg(current,rt1[i]);
1897     }
1898     alloc_reg_temp(current,i,-1);
1899   }
1900   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1901   {
1902     if(rs1[i]){
1903       clear_const(current,rs1[i]);
1904       if(opcode2[i]==5)
1905         alloc_reg64(current,i,rs1[i]); // DMTC1
1906       else
1907         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1908       alloc_reg_temp(current,i,-1);
1909     }
1910     else {
1911       current->u&=~1LL;
1912       alloc_reg(current,i,0);
1913       alloc_reg_temp(current,i,-1);
1914     }
1915   }
1916   minimum_free_regs[i]=1;
1917 }
1918 void fconv_alloc(struct regstat *current,int i)
1919 {
1920   alloc_reg(current,i,CSREG); // Load status
1921   alloc_reg_temp(current,i,-1);
1922   minimum_free_regs[i]=1;
1923 }
1924 void float_alloc(struct regstat *current,int i)
1925 {
1926   alloc_reg(current,i,CSREG); // Load status
1927   alloc_reg_temp(current,i,-1);
1928   minimum_free_regs[i]=1;
1929 }
1930 void c2op_alloc(struct regstat *current,int i)
1931 {
1932   alloc_reg_temp(current,i,-1);
1933 }
1934 void fcomp_alloc(struct regstat *current,int i)
1935 {
1936   alloc_reg(current,i,CSREG); // Load status
1937   alloc_reg(current,i,FSREG); // Load flags
1938   dirty_reg(current,FSREG); // Flag will be modified
1939   alloc_reg_temp(current,i,-1);
1940   minimum_free_regs[i]=1;
1941 }
1942
1943 void syscall_alloc(struct regstat *current,int i)
1944 {
1945   alloc_cc(current,i);
1946   dirty_reg(current,CCREG);
1947   alloc_all(current,i);
1948   minimum_free_regs[i]=HOST_REGS;
1949   current->isconst=0;
1950 }
1951
1952 void delayslot_alloc(struct regstat *current,int i)
1953 {
1954   switch(itype[i]) {
1955     case UJUMP:
1956     case CJUMP:
1957     case SJUMP:
1958     case RJUMP:
1959     case FJUMP:
1960     case SYSCALL:
1961     case HLECALL:
1962     case SPAN:
1963       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1964       printf("Disabled speculative precompilation\n");
1965       stop_after_jal=1;
1966       break;
1967     case IMM16:
1968       imm16_alloc(current,i);
1969       break;
1970     case LOAD:
1971     case LOADLR:
1972       load_alloc(current,i);
1973       break;
1974     case STORE:
1975     case STORELR:
1976       store_alloc(current,i);
1977       break;
1978     case ALU:
1979       alu_alloc(current,i);
1980       break;
1981     case SHIFT:
1982       shift_alloc(current,i);
1983       break;
1984     case MULTDIV:
1985       multdiv_alloc(current,i);
1986       break;
1987     case SHIFTIMM:
1988       shiftimm_alloc(current,i);
1989       break;
1990     case MOV:
1991       mov_alloc(current,i);
1992       break;
1993     case COP0:
1994       cop0_alloc(current,i);
1995       break;
1996     case COP1:
1997     case COP2:
1998       cop1_alloc(current,i);
1999       break;
2000     case C1LS:
2001       c1ls_alloc(current,i);
2002       break;
2003     case C2LS:
2004       c2ls_alloc(current,i);
2005       break;
2006     case FCONV:
2007       fconv_alloc(current,i);
2008       break;
2009     case FLOAT:
2010       float_alloc(current,i);
2011       break;
2012     case FCOMP:
2013       fcomp_alloc(current,i);
2014       break;
2015     case C2OP:
2016       c2op_alloc(current,i);
2017       break;
2018   }
2019 }
2020
2021 // Special case where a branch and delay slot span two pages in virtual memory
2022 static void pagespan_alloc(struct regstat *current,int i)
2023 {
2024   current->isconst=0;
2025   current->wasconst=0;
2026   regs[i].wasconst=0;
2027   minimum_free_regs[i]=HOST_REGS;
2028   alloc_all(current,i);
2029   alloc_cc(current,i);
2030   dirty_reg(current,CCREG);
2031   if(opcode[i]==3) // JAL
2032   {
2033     alloc_reg(current,i,31);
2034     dirty_reg(current,31);
2035   }
2036   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2037   {
2038     alloc_reg(current,i,rs1[i]);
2039     if (rt1[i]!=0) {
2040       alloc_reg(current,i,rt1[i]);
2041       dirty_reg(current,rt1[i]);
2042     }
2043   }
2044   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2045   {
2046     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2047     if(rs2[i]) alloc_reg(current,i,rs2[i]);
2048     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2049     {
2050       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2051       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2052     }
2053   }
2054   else
2055   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2056   {
2057     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2058     if(!((current->is32>>rs1[i])&1))
2059     {
2060       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2061     }
2062   }
2063   else
2064   if(opcode[i]==0x11) // BC1
2065   {
2066     alloc_reg(current,i,FSREG);
2067     alloc_reg(current,i,CSREG);
2068   }
2069   //else ...
2070 }
2071
2072 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2073 {
2074   stubs[stubcount][0]=type;
2075   stubs[stubcount][1]=addr;
2076   stubs[stubcount][2]=retaddr;
2077   stubs[stubcount][3]=a;
2078   stubs[stubcount][4]=b;
2079   stubs[stubcount][5]=c;
2080   stubs[stubcount][6]=d;
2081   stubs[stubcount][7]=e;
2082   stubcount++;
2083 }
2084
2085 // Write out a single register
2086 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2087 {
2088   int hr;
2089   for(hr=0;hr<HOST_REGS;hr++) {
2090     if(hr!=EXCLUDE_REG) {
2091       if((regmap[hr]&63)==r) {
2092         if((dirty>>hr)&1) {
2093           if(regmap[hr]<64) {
2094             emit_storereg(r,hr);
2095 #ifndef FORCE32
2096             if((is32>>regmap[hr])&1) {
2097               emit_sarimm(hr,31,hr);
2098               emit_storereg(r|64,hr);
2099             }
2100 #endif
2101           }else{
2102             emit_storereg(r|64,hr);
2103           }
2104         }
2105       }
2106     }
2107   }
2108 }
2109
2110 int mchecksum()
2111 {
2112   //if(!tracedebug) return 0;
2113   int i;
2114   int sum=0;
2115   for(i=0;i<2097152;i++) {
2116     unsigned int temp=sum;
2117     sum<<=1;
2118     sum|=(~temp)>>31;
2119     sum^=((u_int *)rdram)[i];
2120   }
2121   return sum;
2122 }
2123 int rchecksum()
2124 {
2125   int i;
2126   int sum=0;
2127   for(i=0;i<64;i++)
2128     sum^=((u_int *)reg)[i];
2129   return sum;
2130 }
2131 void rlist()
2132 {
2133   int i;
2134   printf("TRACE: ");
2135   for(i=0;i<32;i++)
2136     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2137   printf("\n");
2138 #ifndef DISABLE_COP1
2139   printf("TRACE: ");
2140   for(i=0;i<32;i++)
2141     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2142   printf("\n");
2143 #endif
2144 }
2145
2146 void enabletrace()
2147 {
2148   tracedebug=1;
2149 }
2150
2151 void memdebug(int i)
2152 {
2153   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2154   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2155   //rlist();
2156   //if(tracedebug) {
2157   //if(Count>=-2084597794) {
2158   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2159   //if(0) {
2160     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2161     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2162     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2163     rlist();
2164     #ifdef __i386__
2165     printf("TRACE: %x\n",(&i)[-1]);
2166     #endif
2167     #ifdef __arm__
2168     int j;
2169     printf("TRACE: %x \n",(&j)[10]);
2170     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2171     #endif
2172     //fflush(stdout);
2173   }
2174   //printf("TRACE: %x\n",(&i)[-1]);
2175 }
2176
2177 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2178 {
2179   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2180 }
2181
2182 void alu_assemble(int i,struct regstat *i_regs)
2183 {
2184   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2185     if(rt1[i]) {
2186       signed char s1,s2,t;
2187       t=get_reg(i_regs->regmap,rt1[i]);
2188       if(t>=0) {
2189         s1=get_reg(i_regs->regmap,rs1[i]);
2190         s2=get_reg(i_regs->regmap,rs2[i]);
2191         if(rs1[i]&&rs2[i]) {
2192           assert(s1>=0);
2193           assert(s2>=0);
2194           if(opcode2[i]&2) emit_sub(s1,s2,t);
2195           else emit_add(s1,s2,t);
2196         }
2197         else if(rs1[i]) {
2198           if(s1>=0) emit_mov(s1,t);
2199           else emit_loadreg(rs1[i],t);
2200         }
2201         else if(rs2[i]) {
2202           if(s2>=0) {
2203             if(opcode2[i]&2) emit_neg(s2,t);
2204             else emit_mov(s2,t);
2205           }
2206           else {
2207             emit_loadreg(rs2[i],t);
2208             if(opcode2[i]&2) emit_neg(t,t);
2209           }
2210         }
2211         else emit_zeroreg(t);
2212       }
2213     }
2214   }
2215   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2216     if(rt1[i]) {
2217       signed char s1l,s2l,s1h,s2h,tl,th;
2218       tl=get_reg(i_regs->regmap,rt1[i]);
2219       th=get_reg(i_regs->regmap,rt1[i]|64);
2220       if(tl>=0) {
2221         s1l=get_reg(i_regs->regmap,rs1[i]);
2222         s2l=get_reg(i_regs->regmap,rs2[i]);
2223         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2224         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2225         if(rs1[i]&&rs2[i]) {
2226           assert(s1l>=0);
2227           assert(s2l>=0);
2228           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2229           else emit_adds(s1l,s2l,tl);
2230           if(th>=0) {
2231             #ifdef INVERTED_CARRY
2232             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2233             #else
2234             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2235             #endif
2236             else emit_add(s1h,s2h,th);
2237           }
2238         }
2239         else if(rs1[i]) {
2240           if(s1l>=0) emit_mov(s1l,tl);
2241           else emit_loadreg(rs1[i],tl);
2242           if(th>=0) {
2243             if(s1h>=0) emit_mov(s1h,th);
2244             else emit_loadreg(rs1[i]|64,th);
2245           }
2246         }
2247         else if(rs2[i]) {
2248           if(s2l>=0) {
2249             if(opcode2[i]&2) emit_negs(s2l,tl);
2250             else emit_mov(s2l,tl);
2251           }
2252           else {
2253             emit_loadreg(rs2[i],tl);
2254             if(opcode2[i]&2) emit_negs(tl,tl);
2255           }
2256           if(th>=0) {
2257             #ifdef INVERTED_CARRY
2258             if(s2h>=0) emit_mov(s2h,th);
2259             else emit_loadreg(rs2[i]|64,th);
2260             if(opcode2[i]&2) {
2261               emit_adcimm(-1,th); // x86 has inverted carry flag
2262               emit_not(th,th);
2263             }
2264             #else
2265             if(opcode2[i]&2) {
2266               if(s2h>=0) emit_rscimm(s2h,0,th);
2267               else {
2268                 emit_loadreg(rs2[i]|64,th);
2269                 emit_rscimm(th,0,th);
2270               }
2271             }else{
2272               if(s2h>=0) emit_mov(s2h,th);
2273               else emit_loadreg(rs2[i]|64,th);
2274             }
2275             #endif
2276           }
2277         }
2278         else {
2279           emit_zeroreg(tl);
2280           if(th>=0) emit_zeroreg(th);
2281         }
2282       }
2283     }
2284   }
2285   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2286     if(rt1[i]) {
2287       signed char s1l,s1h,s2l,s2h,t;
2288       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2289       {
2290         t=get_reg(i_regs->regmap,rt1[i]);
2291         //assert(t>=0);
2292         if(t>=0) {
2293           s1l=get_reg(i_regs->regmap,rs1[i]);
2294           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2295           s2l=get_reg(i_regs->regmap,rs2[i]);
2296           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2297           if(rs2[i]==0) // rx<r0
2298           {
2299             assert(s1h>=0);
2300             if(opcode2[i]==0x2a) // SLT
2301               emit_shrimm(s1h,31,t);
2302             else // SLTU (unsigned can not be less than zero)
2303               emit_zeroreg(t);
2304           }
2305           else if(rs1[i]==0) // r0<rx
2306           {
2307             assert(s2h>=0);
2308             if(opcode2[i]==0x2a) // SLT
2309               emit_set_gz64_32(s2h,s2l,t);
2310             else // SLTU (set if not zero)
2311               emit_set_nz64_32(s2h,s2l,t);
2312           }
2313           else {
2314             assert(s1l>=0);assert(s1h>=0);
2315             assert(s2l>=0);assert(s2h>=0);
2316             if(opcode2[i]==0x2a) // SLT
2317               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2318             else // SLTU
2319               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2320           }
2321         }
2322       } else {
2323         t=get_reg(i_regs->regmap,rt1[i]);
2324         //assert(t>=0);
2325         if(t>=0) {
2326           s1l=get_reg(i_regs->regmap,rs1[i]);
2327           s2l=get_reg(i_regs->regmap,rs2[i]);
2328           if(rs2[i]==0) // rx<r0
2329           {
2330             assert(s1l>=0);
2331             if(opcode2[i]==0x2a) // SLT
2332               emit_shrimm(s1l,31,t);
2333             else // SLTU (unsigned can not be less than zero)
2334               emit_zeroreg(t);
2335           }
2336           else if(rs1[i]==0) // r0<rx
2337           {
2338             assert(s2l>=0);
2339             if(opcode2[i]==0x2a) // SLT
2340               emit_set_gz32(s2l,t);
2341             else // SLTU (set if not zero)
2342               emit_set_nz32(s2l,t);
2343           }
2344           else{
2345             assert(s1l>=0);assert(s2l>=0);
2346             if(opcode2[i]==0x2a) // SLT
2347               emit_set_if_less32(s1l,s2l,t);
2348             else // SLTU
2349               emit_set_if_carry32(s1l,s2l,t);
2350           }
2351         }
2352       }
2353     }
2354   }
2355   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2356     if(rt1[i]) {
2357       signed char s1l,s1h,s2l,s2h,th,tl;
2358       tl=get_reg(i_regs->regmap,rt1[i]);
2359       th=get_reg(i_regs->regmap,rt1[i]|64);
2360       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2361       {
2362         assert(tl>=0);
2363         if(tl>=0) {
2364           s1l=get_reg(i_regs->regmap,rs1[i]);
2365           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2366           s2l=get_reg(i_regs->regmap,rs2[i]);
2367           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2368           if(rs1[i]&&rs2[i]) {
2369             assert(s1l>=0);assert(s1h>=0);
2370             assert(s2l>=0);assert(s2h>=0);
2371             if(opcode2[i]==0x24) { // AND
2372               emit_and(s1l,s2l,tl);
2373               emit_and(s1h,s2h,th);
2374             } else
2375             if(opcode2[i]==0x25) { // OR
2376               emit_or(s1l,s2l,tl);
2377               emit_or(s1h,s2h,th);
2378             } else
2379             if(opcode2[i]==0x26) { // XOR
2380               emit_xor(s1l,s2l,tl);
2381               emit_xor(s1h,s2h,th);
2382             } else
2383             if(opcode2[i]==0x27) { // NOR
2384               emit_or(s1l,s2l,tl);
2385               emit_or(s1h,s2h,th);
2386               emit_not(tl,tl);
2387               emit_not(th,th);
2388             }
2389           }
2390           else
2391           {
2392             if(opcode2[i]==0x24) { // AND
2393               emit_zeroreg(tl);
2394               emit_zeroreg(th);
2395             } else
2396             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2397               if(rs1[i]){
2398                 if(s1l>=0) emit_mov(s1l,tl);
2399                 else emit_loadreg(rs1[i],tl);
2400                 if(s1h>=0) emit_mov(s1h,th);
2401                 else emit_loadreg(rs1[i]|64,th);
2402               }
2403               else
2404               if(rs2[i]){
2405                 if(s2l>=0) emit_mov(s2l,tl);
2406                 else emit_loadreg(rs2[i],tl);
2407                 if(s2h>=0) emit_mov(s2h,th);
2408                 else emit_loadreg(rs2[i]|64,th);
2409               }
2410               else{
2411                 emit_zeroreg(tl);
2412                 emit_zeroreg(th);
2413               }
2414             } else
2415             if(opcode2[i]==0x27) { // NOR
2416               if(rs1[i]){
2417                 if(s1l>=0) emit_not(s1l,tl);
2418                 else{
2419                   emit_loadreg(rs1[i],tl);
2420                   emit_not(tl,tl);
2421                 }
2422                 if(s1h>=0) emit_not(s1h,th);
2423                 else{
2424                   emit_loadreg(rs1[i]|64,th);
2425                   emit_not(th,th);
2426                 }
2427               }
2428               else
2429               if(rs2[i]){
2430                 if(s2l>=0) emit_not(s2l,tl);
2431                 else{
2432                   emit_loadreg(rs2[i],tl);
2433                   emit_not(tl,tl);
2434                 }
2435                 if(s2h>=0) emit_not(s2h,th);
2436                 else{
2437                   emit_loadreg(rs2[i]|64,th);
2438                   emit_not(th,th);
2439                 }
2440               }
2441               else {
2442                 emit_movimm(-1,tl);
2443                 emit_movimm(-1,th);
2444               }
2445             }
2446           }
2447         }
2448       }
2449       else
2450       {
2451         // 32 bit
2452         if(tl>=0) {
2453           s1l=get_reg(i_regs->regmap,rs1[i]);
2454           s2l=get_reg(i_regs->regmap,rs2[i]);
2455           if(rs1[i]&&rs2[i]) {
2456             assert(s1l>=0);
2457             assert(s2l>=0);
2458             if(opcode2[i]==0x24) { // AND
2459               emit_and(s1l,s2l,tl);
2460             } else
2461             if(opcode2[i]==0x25) { // OR
2462               emit_or(s1l,s2l,tl);
2463             } else
2464             if(opcode2[i]==0x26) { // XOR
2465               emit_xor(s1l,s2l,tl);
2466             } else
2467             if(opcode2[i]==0x27) { // NOR
2468               emit_or(s1l,s2l,tl);
2469               emit_not(tl,tl);
2470             }
2471           }
2472           else
2473           {
2474             if(opcode2[i]==0x24) { // AND
2475               emit_zeroreg(tl);
2476             } else
2477             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2478               if(rs1[i]){
2479                 if(s1l>=0) emit_mov(s1l,tl);
2480                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2481               }
2482               else
2483               if(rs2[i]){
2484                 if(s2l>=0) emit_mov(s2l,tl);
2485                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2486               }
2487               else emit_zeroreg(tl);
2488             } else
2489             if(opcode2[i]==0x27) { // NOR
2490               if(rs1[i]){
2491                 if(s1l>=0) emit_not(s1l,tl);
2492                 else {
2493                   emit_loadreg(rs1[i],tl);
2494                   emit_not(tl,tl);
2495                 }
2496               }
2497               else
2498               if(rs2[i]){
2499                 if(s2l>=0) emit_not(s2l,tl);
2500                 else {
2501                   emit_loadreg(rs2[i],tl);
2502                   emit_not(tl,tl);
2503                 }
2504               }
2505               else emit_movimm(-1,tl);
2506             }
2507           }
2508         }
2509       }
2510     }
2511   }
2512 }
2513
2514 void imm16_assemble(int i,struct regstat *i_regs)
2515 {
2516   if (opcode[i]==0x0f) { // LUI
2517     if(rt1[i]) {
2518       signed char t;
2519       t=get_reg(i_regs->regmap,rt1[i]);
2520       //assert(t>=0);
2521       if(t>=0) {
2522         if(!((i_regs->isconst>>t)&1))
2523           emit_movimm(imm[i]<<16,t);
2524       }
2525     }
2526   }
2527   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2528     if(rt1[i]) {
2529       signed char s,t;
2530       t=get_reg(i_regs->regmap,rt1[i]);
2531       s=get_reg(i_regs->regmap,rs1[i]);
2532       if(rs1[i]) {
2533         //assert(t>=0);
2534         //assert(s>=0);
2535         if(t>=0) {
2536           if(!((i_regs->isconst>>t)&1)) {
2537             if(s<0) {
2538               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2539               emit_addimm(t,imm[i],t);
2540             }else{
2541               if(!((i_regs->wasconst>>s)&1))
2542                 emit_addimm(s,imm[i],t);
2543               else
2544                 emit_movimm(constmap[i][s]+imm[i],t);
2545             }
2546           }
2547         }
2548       } else {
2549         if(t>=0) {
2550           if(!((i_regs->isconst>>t)&1))
2551             emit_movimm(imm[i],t);
2552         }
2553       }
2554     }
2555   }
2556   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2557     if(rt1[i]) {
2558       signed char sh,sl,th,tl;
2559       th=get_reg(i_regs->regmap,rt1[i]|64);
2560       tl=get_reg(i_regs->regmap,rt1[i]);
2561       sh=get_reg(i_regs->regmap,rs1[i]|64);
2562       sl=get_reg(i_regs->regmap,rs1[i]);
2563       if(tl>=0) {
2564         if(rs1[i]) {
2565           assert(sh>=0);
2566           assert(sl>=0);
2567           if(th>=0) {
2568             emit_addimm64_32(sh,sl,imm[i],th,tl);
2569           }
2570           else {
2571             emit_addimm(sl,imm[i],tl);
2572           }
2573         } else {
2574           emit_movimm(imm[i],tl);
2575           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2576         }
2577       }
2578     }
2579   }
2580   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2581     if(rt1[i]) {
2582       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2583       signed char sh,sl,t;
2584       t=get_reg(i_regs->regmap,rt1[i]);
2585       sh=get_reg(i_regs->regmap,rs1[i]|64);
2586       sl=get_reg(i_regs->regmap,rs1[i]);
2587       //assert(t>=0);
2588       if(t>=0) {
2589         if(rs1[i]>0) {
2590           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2591           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2592             if(opcode[i]==0x0a) { // SLTI
2593               if(sl<0) {
2594                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2595                 emit_slti32(t,imm[i],t);
2596               }else{
2597                 emit_slti32(sl,imm[i],t);
2598               }
2599             }
2600             else { // SLTIU
2601               if(sl<0) {
2602                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2603                 emit_sltiu32(t,imm[i],t);
2604               }else{
2605                 emit_sltiu32(sl,imm[i],t);
2606               }
2607             }
2608           }else{ // 64-bit
2609             assert(sl>=0);
2610             if(opcode[i]==0x0a) // SLTI
2611               emit_slti64_32(sh,sl,imm[i],t);
2612             else // SLTIU
2613               emit_sltiu64_32(sh,sl,imm[i],t);
2614           }
2615         }else{
2616           // SLTI(U) with r0 is just stupid,
2617           // nonetheless examples can be found
2618           if(opcode[i]==0x0a) // SLTI
2619             if(0<imm[i]) emit_movimm(1,t);
2620             else emit_zeroreg(t);
2621           else // SLTIU
2622           {
2623             if(imm[i]) emit_movimm(1,t);
2624             else emit_zeroreg(t);
2625           }
2626         }
2627       }
2628     }
2629   }
2630   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2631     if(rt1[i]) {
2632       signed char sh,sl,th,tl;
2633       th=get_reg(i_regs->regmap,rt1[i]|64);
2634       tl=get_reg(i_regs->regmap,rt1[i]);
2635       sh=get_reg(i_regs->regmap,rs1[i]|64);
2636       sl=get_reg(i_regs->regmap,rs1[i]);
2637       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2638         if(opcode[i]==0x0c) //ANDI
2639         {
2640           if(rs1[i]) {
2641             if(sl<0) {
2642               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2643               emit_andimm(tl,imm[i],tl);
2644             }else{
2645               if(!((i_regs->wasconst>>sl)&1))
2646                 emit_andimm(sl,imm[i],tl);
2647               else
2648                 emit_movimm(constmap[i][sl]&imm[i],tl);
2649             }
2650           }
2651           else
2652             emit_zeroreg(tl);
2653           if(th>=0) emit_zeroreg(th);
2654         }
2655         else
2656         {
2657           if(rs1[i]) {
2658             if(sl<0) {
2659               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2660             }
2661             if(th>=0) {
2662               if(sh<0) {
2663                 emit_loadreg(rs1[i]|64,th);
2664               }else{
2665                 emit_mov(sh,th);
2666               }
2667             }
2668             if(opcode[i]==0x0d) //ORI
2669             if(sl<0) {
2670               emit_orimm(tl,imm[i],tl);
2671             }else{
2672               if(!((i_regs->wasconst>>sl)&1))
2673                 emit_orimm(sl,imm[i],tl);
2674               else
2675                 emit_movimm(constmap[i][sl]|imm[i],tl);
2676             }
2677             if(opcode[i]==0x0e) //XORI
2678             if(sl<0) {
2679               emit_xorimm(tl,imm[i],tl);
2680             }else{
2681               if(!((i_regs->wasconst>>sl)&1))
2682                 emit_xorimm(sl,imm[i],tl);
2683               else
2684                 emit_movimm(constmap[i][sl]^imm[i],tl);
2685             }
2686           }
2687           else {
2688             emit_movimm(imm[i],tl);
2689             if(th>=0) emit_zeroreg(th);
2690           }
2691         }
2692       }
2693     }
2694   }
2695 }
2696
2697 void shiftimm_assemble(int i,struct regstat *i_regs)
2698 {
2699   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2700   {
2701     if(rt1[i]) {
2702       signed char s,t;
2703       t=get_reg(i_regs->regmap,rt1[i]);
2704       s=get_reg(i_regs->regmap,rs1[i]);
2705       //assert(t>=0);
2706       if(t>=0&&!((i_regs->isconst>>t)&1)){
2707         if(rs1[i]==0)
2708         {
2709           emit_zeroreg(t);
2710         }
2711         else
2712         {
2713           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2714           if(imm[i]) {
2715             if(opcode2[i]==0) // SLL
2716             {
2717               emit_shlimm(s<0?t:s,imm[i],t);
2718             }
2719             if(opcode2[i]==2) // SRL
2720             {
2721               emit_shrimm(s<0?t:s,imm[i],t);
2722             }
2723             if(opcode2[i]==3) // SRA
2724             {
2725               emit_sarimm(s<0?t:s,imm[i],t);
2726             }
2727           }else{
2728             // Shift by zero
2729             if(s>=0 && s!=t) emit_mov(s,t);
2730           }
2731         }
2732       }
2733       //emit_storereg(rt1[i],t); //DEBUG
2734     }
2735   }
2736   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2737   {
2738     if(rt1[i]) {
2739       signed char sh,sl,th,tl;
2740       th=get_reg(i_regs->regmap,rt1[i]|64);
2741       tl=get_reg(i_regs->regmap,rt1[i]);
2742       sh=get_reg(i_regs->regmap,rs1[i]|64);
2743       sl=get_reg(i_regs->regmap,rs1[i]);
2744       if(tl>=0) {
2745         if(rs1[i]==0)
2746         {
2747           emit_zeroreg(tl);
2748           if(th>=0) emit_zeroreg(th);
2749         }
2750         else
2751         {
2752           assert(sl>=0);
2753           assert(sh>=0);
2754           if(imm[i]) {
2755             if(opcode2[i]==0x38) // DSLL
2756             {
2757               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2758               emit_shlimm(sl,imm[i],tl);
2759             }
2760             if(opcode2[i]==0x3a) // DSRL
2761             {
2762               emit_shrdimm(sl,sh,imm[i],tl);
2763               if(th>=0) emit_shrimm(sh,imm[i],th);
2764             }
2765             if(opcode2[i]==0x3b) // DSRA
2766             {
2767               emit_shrdimm(sl,sh,imm[i],tl);
2768               if(th>=0) emit_sarimm(sh,imm[i],th);
2769             }
2770           }else{
2771             // Shift by zero
2772             if(sl!=tl) emit_mov(sl,tl);
2773             if(th>=0&&sh!=th) emit_mov(sh,th);
2774           }
2775         }
2776       }
2777     }
2778   }
2779   if(opcode2[i]==0x3c) // DSLL32
2780   {
2781     if(rt1[i]) {
2782       signed char sl,tl,th;
2783       tl=get_reg(i_regs->regmap,rt1[i]);
2784       th=get_reg(i_regs->regmap,rt1[i]|64);
2785       sl=get_reg(i_regs->regmap,rs1[i]);
2786       if(th>=0||tl>=0){
2787         assert(tl>=0);
2788         assert(th>=0);
2789         assert(sl>=0);
2790         emit_mov(sl,th);
2791         emit_zeroreg(tl);
2792         if(imm[i]>32)
2793         {
2794           emit_shlimm(th,imm[i]&31,th);
2795         }
2796       }
2797     }
2798   }
2799   if(opcode2[i]==0x3e) // DSRL32
2800   {
2801     if(rt1[i]) {
2802       signed char sh,tl,th;
2803       tl=get_reg(i_regs->regmap,rt1[i]);
2804       th=get_reg(i_regs->regmap,rt1[i]|64);
2805       sh=get_reg(i_regs->regmap,rs1[i]|64);
2806       if(tl>=0){
2807         assert(sh>=0);
2808         emit_mov(sh,tl);
2809         if(th>=0) emit_zeroreg(th);
2810         if(imm[i]>32)
2811         {
2812           emit_shrimm(tl,imm[i]&31,tl);
2813         }
2814       }
2815     }
2816   }
2817   if(opcode2[i]==0x3f) // DSRA32
2818   {
2819     if(rt1[i]) {
2820       signed char sh,tl;
2821       tl=get_reg(i_regs->regmap,rt1[i]);
2822       sh=get_reg(i_regs->regmap,rs1[i]|64);
2823       if(tl>=0){
2824         assert(sh>=0);
2825         emit_mov(sh,tl);
2826         if(imm[i]>32)
2827         {
2828           emit_sarimm(tl,imm[i]&31,tl);
2829         }
2830       }
2831     }
2832   }
2833 }
2834
2835 #ifndef shift_assemble
2836 void shift_assemble(int i,struct regstat *i_regs)
2837 {
2838   printf("Need shift_assemble for this architecture.\n");
2839   exit(1);
2840 }
2841 #endif
2842
2843 void load_assemble(int i,struct regstat *i_regs)
2844 {
2845   int s,th,tl,addr,map=-1;
2846   int offset;
2847   int jaddr=0;
2848   int memtarget=0,c=0;
2849   int fastload_reg_override=0;
2850   u_int hr,reglist=0;
2851   th=get_reg(i_regs->regmap,rt1[i]|64);
2852   tl=get_reg(i_regs->regmap,rt1[i]);
2853   s=get_reg(i_regs->regmap,rs1[i]);
2854   offset=imm[i];
2855   for(hr=0;hr<HOST_REGS;hr++) {
2856     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2857   }
2858   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2859   if(s>=0) {
2860     c=(i_regs->wasconst>>s)&1;
2861     if (c) {
2862       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2863       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2864     }
2865   }
2866   //printf("load_assemble: c=%d\n",c);
2867   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2868   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2869 #ifdef PCSX
2870   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2871     ||rt1[i]==0) {
2872       // could be FIFO, must perform the read
2873       // ||dummy read
2874       assem_debug("(forced read)\n");
2875       tl=get_reg(i_regs->regmap,-1);
2876       assert(tl>=0);
2877   }
2878 #endif
2879   if(offset||s<0||c) addr=tl;
2880   else addr=s;
2881   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2882  if(tl>=0) {
2883   //printf("load_assemble: c=%d\n",c);
2884   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2885   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2886   reglist&=~(1<<tl);
2887   if(th>=0) reglist&=~(1<<th);
2888   if(!using_tlb) {
2889     if(!c) {
2890       #ifdef RAM_OFFSET
2891       map=get_reg(i_regs->regmap,ROREG);
2892       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2893       #endif
2894 //#define R29_HACK 1
2895       #ifdef R29_HACK
2896       // Strmnnrmn's speed hack
2897       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2898       #endif
2899       {
2900         jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2901       }
2902     }
2903   }else{ // using tlb
2904     int x=0;
2905     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2906     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2907     map=get_reg(i_regs->regmap,TLREG);
2908     assert(map>=0);
2909     reglist&=~(1<<map);
2910     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2911     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2912   }
2913   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2914   if (opcode[i]==0x20) { // LB
2915     if(!c||memtarget) {
2916       if(!dummy) {
2917         #ifdef HOST_IMM_ADDR32
2918         if(c)
2919           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2920         else
2921         #endif
2922         {
2923           //emit_xorimm(addr,3,tl);
2924           //gen_tlb_addr_r(tl,map);
2925           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2926           int x=0,a=tl;
2927 #ifdef BIG_ENDIAN_MIPS
2928           if(!c) emit_xorimm(addr,3,tl);
2929           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2930 #else
2931           if(!c) a=addr;
2932 #endif
2933           if(fastload_reg_override) a=fastload_reg_override;
2934
2935           emit_movsbl_indexed_tlb(x,a,map,tl);
2936         }
2937       }
2938       if(jaddr)
2939         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2940     }
2941     else
2942       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2943   }
2944   if (opcode[i]==0x21) { // LH
2945     if(!c||memtarget) {
2946       if(!dummy) {
2947         #ifdef HOST_IMM_ADDR32
2948         if(c)
2949           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2950         else
2951         #endif
2952         {
2953           int x=0,a=tl;
2954 #ifdef BIG_ENDIAN_MIPS
2955           if(!c) emit_xorimm(addr,2,tl);
2956           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2957 #else
2958           if(!c) a=addr;
2959 #endif
2960           if(fastload_reg_override) a=fastload_reg_override;
2961           //#ifdef
2962           //emit_movswl_indexed_tlb(x,tl,map,tl);
2963           //else
2964           if(map>=0) {
2965             gen_tlb_addr_r(a,map);
2966             emit_movswl_indexed(x,a,tl);
2967           }else{
2968             #ifdef RAM_OFFSET
2969             emit_movswl_indexed(x,a,tl);
2970             #else
2971             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2972             #endif
2973           }
2974         }
2975       }
2976       if(jaddr)
2977         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2978     }
2979     else
2980       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2981   }
2982   if (opcode[i]==0x23) { // LW
2983     if(!c||memtarget) {
2984       if(!dummy) {
2985         int a=addr;
2986         if(fastload_reg_override) a=fastload_reg_override;
2987         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2988         #ifdef HOST_IMM_ADDR32
2989         if(c)
2990           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2991         else
2992         #endif
2993         emit_readword_indexed_tlb(0,a,map,tl);
2994       }
2995       if(jaddr)
2996         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2997     }
2998     else
2999       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3000   }
3001   if (opcode[i]==0x24) { // LBU
3002     if(!c||memtarget) {
3003       if(!dummy) {
3004         #ifdef HOST_IMM_ADDR32
3005         if(c)
3006           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3007         else
3008         #endif
3009         {
3010           //emit_xorimm(addr,3,tl);
3011           //gen_tlb_addr_r(tl,map);
3012           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3013           int x=0,a=tl;
3014 #ifdef BIG_ENDIAN_MIPS
3015           if(!c) emit_xorimm(addr,3,tl);
3016           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3017 #else
3018           if(!c) a=addr;
3019 #endif
3020           if(fastload_reg_override) a=fastload_reg_override;
3021
3022           emit_movzbl_indexed_tlb(x,a,map,tl);
3023         }
3024       }
3025       if(jaddr)
3026         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3027     }
3028     else
3029       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3030   }
3031   if (opcode[i]==0x25) { // LHU
3032     if(!c||memtarget) {
3033       if(!dummy) {
3034         #ifdef HOST_IMM_ADDR32
3035         if(c)
3036           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3037         else
3038         #endif
3039         {
3040           int x=0,a=tl;
3041 #ifdef BIG_ENDIAN_MIPS
3042           if(!c) emit_xorimm(addr,2,tl);
3043           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3044 #else
3045           if(!c) a=addr;
3046 #endif
3047           if(fastload_reg_override) a=fastload_reg_override;
3048           //#ifdef
3049           //emit_movzwl_indexed_tlb(x,tl,map,tl);
3050           //#else
3051           if(map>=0) {
3052             gen_tlb_addr_r(a,map);
3053             emit_movzwl_indexed(x,a,tl);
3054           }else{
3055             #ifdef RAM_OFFSET
3056             emit_movzwl_indexed(x,a,tl);
3057             #else
3058             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3059             #endif
3060           }
3061         }
3062       }
3063       if(jaddr)
3064         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3065     }
3066     else
3067       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3068   }
3069   if (opcode[i]==0x27) { // LWU
3070     assert(th>=0);
3071     if(!c||memtarget) {
3072       if(!dummy) {
3073         int a=addr;
3074         if(fastload_reg_override) a=fastload_reg_override;
3075         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3076         #ifdef HOST_IMM_ADDR32
3077         if(c)
3078           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3079         else
3080         #endif
3081         emit_readword_indexed_tlb(0,a,map,tl);
3082       }
3083       if(jaddr)
3084         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3085     }
3086     else {
3087       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3088     }
3089     emit_zeroreg(th);
3090   }
3091   if (opcode[i]==0x37) { // LD
3092     if(!c||memtarget) {
3093       if(!dummy) {
3094         int a=addr;
3095         if(fastload_reg_override) a=fastload_reg_override;
3096         //gen_tlb_addr_r(tl,map);
3097         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3098         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3099         #ifdef HOST_IMM_ADDR32
3100         if(c)
3101           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3102         else
3103         #endif
3104         emit_readdword_indexed_tlb(0,a,map,th,tl);
3105       }
3106       if(jaddr)
3107         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3108     }
3109     else
3110       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3111   }
3112  }
3113   //emit_storereg(rt1[i],tl); // DEBUG
3114   //if(opcode[i]==0x23)
3115   //if(opcode[i]==0x24)
3116   //if(opcode[i]==0x23||opcode[i]==0x24)
3117   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3118   {
3119     //emit_pusha();
3120     save_regs(0x100f);
3121         emit_readword((int)&last_count,ECX);
3122         #ifdef __i386__
3123         if(get_reg(i_regs->regmap,CCREG)<0)
3124           emit_loadreg(CCREG,HOST_CCREG);
3125         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3126         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3127         emit_writeword(HOST_CCREG,(int)&Count);
3128         #endif
3129         #ifdef __arm__
3130         if(get_reg(i_regs->regmap,CCREG)<0)
3131           emit_loadreg(CCREG,0);
3132         else
3133           emit_mov(HOST_CCREG,0);
3134         emit_add(0,ECX,0);
3135         emit_addimm(0,2*ccadj[i],0);
3136         emit_writeword(0,(int)&Count);
3137         #endif
3138     emit_call((int)memdebug);
3139     //emit_popa();
3140     restore_regs(0x100f);
3141   }/**/
3142 }
3143
3144 #ifndef loadlr_assemble
3145 void loadlr_assemble(int i,struct regstat *i_regs)
3146 {
3147   printf("Need loadlr_assemble for this architecture.\n");
3148   exit(1);
3149 }
3150 #endif
3151
3152 void store_assemble(int i,struct regstat *i_regs)
3153 {
3154   int s,th,tl,map=-1;
3155   int addr,temp;
3156   int offset;
3157   int jaddr=0,jaddr2,type;
3158   int memtarget=0,c=0;
3159   int agr=AGEN1+(i&1);
3160   int faststore_reg_override=0;
3161   u_int hr,reglist=0;
3162   th=get_reg(i_regs->regmap,rs2[i]|64);
3163   tl=get_reg(i_regs->regmap,rs2[i]);
3164   s=get_reg(i_regs->regmap,rs1[i]);
3165   temp=get_reg(i_regs->regmap,agr);
3166   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3167   offset=imm[i];
3168   if(s>=0) {
3169     c=(i_regs->wasconst>>s)&1;
3170     if(c) {
3171       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3172       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3173     }
3174   }
3175   assert(tl>=0);
3176   assert(temp>=0);
3177   for(hr=0;hr<HOST_REGS;hr++) {
3178     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3179   }
3180   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3181   if(offset||s<0||c) addr=temp;
3182   else addr=s;
3183   if(!using_tlb) {
3184     if(!c) {
3185       #ifndef PCSX
3186       #ifdef R29_HACK
3187       // Strmnnrmn's speed hack
3188       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3189       #endif
3190       emit_cmpimm(addr,RAM_SIZE);
3191       #ifdef DESTRUCTIVE_SHIFT
3192       if(s==addr) emit_mov(s,temp);
3193       #endif
3194       #ifdef R29_HACK
3195       memtarget=1;
3196       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3197       #endif
3198       {
3199         jaddr=(int)out;
3200         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3201         // Hint to branch predictor that the branch is unlikely to be taken
3202         if(rs1[i]>=28)
3203           emit_jno_unlikely(0);
3204         else
3205         #endif
3206         emit_jno(0);
3207       }
3208       #else
3209         jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3210       #endif
3211     }
3212   }else{ // using tlb
3213     int x=0;
3214     if (opcode[i]==0x28) x=3; // SB
3215     if (opcode[i]==0x29) x=2; // SH
3216     map=get_reg(i_regs->regmap,TLREG);
3217     assert(map>=0);
3218     reglist&=~(1<<map);
3219     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3220     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3221   }
3222
3223   if (opcode[i]==0x28) { // SB
3224     if(!c||memtarget) {
3225       int x=0,a=temp;
3226 #ifdef BIG_ENDIAN_MIPS
3227       if(!c) emit_xorimm(addr,3,temp);
3228       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3229 #else
3230       if(!c) a=addr;
3231 #endif
3232       if(faststore_reg_override) a=faststore_reg_override;
3233       //gen_tlb_addr_w(temp,map);
3234       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3235       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3236     }
3237     type=STOREB_STUB;
3238   }
3239   if (opcode[i]==0x29) { // SH
3240     if(!c||memtarget) {
3241       int x=0,a=temp;
3242 #ifdef BIG_ENDIAN_MIPS
3243       if(!c) emit_xorimm(addr,2,temp);
3244       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3245 #else
3246       if(!c) a=addr;
3247 #endif
3248       if(faststore_reg_override) a=faststore_reg_override;
3249       //#ifdef
3250       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3251       //#else
3252       if(map>=0) {
3253         gen_tlb_addr_w(a,map);
3254         emit_writehword_indexed(tl,x,a);
3255       }else
3256         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3257     }
3258     type=STOREH_STUB;
3259   }
3260   if (opcode[i]==0x2B) { // SW
3261     if(!c||memtarget) {
3262       int a=addr;
3263       if(faststore_reg_override) a=faststore_reg_override;
3264       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3265       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3266     }
3267     type=STOREW_STUB;
3268   }
3269   if (opcode[i]==0x3F) { // SD
3270     if(!c||memtarget) {
3271       int a=addr;
3272       if(faststore_reg_override) a=faststore_reg_override;
3273       if(rs2[i]) {
3274         assert(th>=0);
3275         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3276         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3277         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3278       }else{
3279         // Store zero
3280         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3281         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3282         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3283       }
3284     }
3285     type=STORED_STUB;
3286   }
3287 #ifdef PCSX
3288   if(jaddr) {
3289     // PCSX store handlers don't check invcode again
3290     reglist|=1<<addr;
3291     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3292     jaddr=0;
3293   }
3294 #endif
3295   if(!using_tlb) {
3296     if(!c||memtarget) {
3297       #ifdef DESTRUCTIVE_SHIFT
3298       // The x86 shift operation is 'destructive'; it overwrites the
3299       // source register, so we need to make a copy first and use that.
3300       addr=temp;
3301       #endif
3302       #if defined(HOST_IMM8)
3303       int ir=get_reg(i_regs->regmap,INVCP);
3304       assert(ir>=0);
3305       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3306       #else
3307       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3308       #endif
3309       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3310       emit_callne(invalidate_addr_reg[addr]);
3311       #else
3312       jaddr2=(int)out;
3313       emit_jne(0);
3314       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3315       #endif
3316     }
3317   }
3318   if(jaddr) {
3319     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3320   } else if(c&&!memtarget) {
3321     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3322   }
3323   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3324   //if(opcode[i]==0x2B || opcode[i]==0x28)
3325   //if(opcode[i]==0x2B || opcode[i]==0x29)
3326   //if(opcode[i]==0x2B)
3327   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3328   {
3329     #ifdef __i386__
3330     emit_pusha();
3331     #endif
3332     #ifdef __arm__
3333     save_regs(0x100f);
3334     #endif
3335         emit_readword((int)&last_count,ECX);
3336         #ifdef __i386__
3337         if(get_reg(i_regs->regmap,CCREG)<0)
3338           emit_loadreg(CCREG,HOST_CCREG);
3339         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3340         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3341         emit_writeword(HOST_CCREG,(int)&Count);
3342         #endif
3343         #ifdef __arm__
3344         if(get_reg(i_regs->regmap,CCREG)<0)
3345           emit_loadreg(CCREG,0);
3346         else
3347           emit_mov(HOST_CCREG,0);
3348         emit_add(0,ECX,0);
3349         emit_addimm(0,2*ccadj[i],0);
3350         emit_writeword(0,(int)&Count);
3351         #endif
3352     emit_call((int)memdebug);
3353     #ifdef __i386__
3354     emit_popa();
3355     #endif
3356     #ifdef __arm__
3357     restore_regs(0x100f);
3358     #endif
3359   }/**/
3360 }
3361
3362 void storelr_assemble(int i,struct regstat *i_regs)
3363 {
3364   int s,th,tl;
3365   int temp;
3366   int temp2;
3367   int offset;
3368   int jaddr=0,jaddr2;
3369   int case1,case2,case3;
3370   int done0,done1,done2;
3371   int memtarget=0,c=0;
3372   int agr=AGEN1+(i&1);
3373   u_int hr,reglist=0;
3374   th=get_reg(i_regs->regmap,rs2[i]|64);
3375   tl=get_reg(i_regs->regmap,rs2[i]);