libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24 #include <sys/mman.h>
  25
  26 #include "emu_if.h" //emulator interface
  27
  28 //#define DISASM
  29 //#define assem_debug printf
  30 //#define inv_debug printf
  31 #define assem_debug(...)
  32 #define inv_debug(...)
  33
  34 #ifdef __i386__
  35 #include "assem_x86.h"
  36 #endif
  37 #ifdef __x86_64__
  38 #include "assem_x64.h"
  39 #endif
  40 #ifdef __arm__
  41 #include "assem_arm.h"
  42 #endif
  43
  44 #define MAXBLOCK 4096
  45 #define MAX_OUTPUT_BLOCK_SIZE 262144
  46
  47 int cycle_multiplier; // 100 for 1.0
  48 #define CLOCK_ADJUST(x) (((x) * cycle_multiplier + 50) / 100)
  49
  50 struct regstat
  51 {
  52   signed char regmap_entry[HOST_REGS];
  53   signed char regmap[HOST_REGS];
  54   uint64_t was32;
  55   uint64_t is32;
  56   uint64_t wasdirty;
  57   uint64_t dirty;
  58   uint64_t u;
  59   uint64_t uu;
  60   u_int wasconst;
  61   u_int isconst;
  62   u_int loadedconst;             // host regs that have constants loaded
  63   u_int waswritten;              // MIPS regs that were used as store base before
  64   uint64_t constmap[HOST_REGS];
  65 };
  66
  67 struct ll_entry
  68 {
  69   u_int vaddr;
  70   u_int reg32;
  71   void *addr;
  72   struct ll_entry *next;
  73 };
  74
  75   u_int start;
  76   u_int *source;
  77   u_int pagelimit;
  78   char insn[MAXBLOCK][10];
  79   u_char itype[MAXBLOCK];
  80   u_char opcode[MAXBLOCK];
  81   u_char opcode2[MAXBLOCK];
  82   u_char bt[MAXBLOCK];
  83   u_char rs1[MAXBLOCK];
  84   u_char rs2[MAXBLOCK];
  85   u_char rt1[MAXBLOCK];
  86   u_char rt2[MAXBLOCK];
  87   u_char us1[MAXBLOCK];
  88   u_char us2[MAXBLOCK];
  89   u_char dep1[MAXBLOCK];
  90   u_char dep2[MAXBLOCK];
  91   u_char lt1[MAXBLOCK];
  92   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
  93   static uint64_t gte_rt[MAXBLOCK];
  94   static uint64_t gte_unneeded[MAXBLOCK];
  95   static int gte_reads_flags; // gte flag read encountered
  96   static u_int smrv[32]; // speculated MIPS register values
  97   static u_int smrv_strong; // mask or regs that are likely to have correct values
  98   static u_int smrv_weak; // same, but somewhat less likely
  99   static u_int smrv_strong_next; // same, but after current insn executes
 100   static u_int smrv_weak_next;
 101   int imm[MAXBLOCK];
 102   u_int ba[MAXBLOCK];
 103   char likely[MAXBLOCK];
 104   char is_ds[MAXBLOCK];
 105   char ooo[MAXBLOCK];
 106   uint64_t unneeded_reg[MAXBLOCK];
 107   uint64_t unneeded_reg_upper[MAXBLOCK];
 108   uint64_t branch_unneeded_reg[MAXBLOCK];
 109   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
 110   uint64_t p32[MAXBLOCK];
 111   uint64_t pr32[MAXBLOCK];
 112   signed char regmap_pre[MAXBLOCK][HOST_REGS];
 113   signed char regmap[MAXBLOCK][HOST_REGS];
 114   signed char regmap_entry[MAXBLOCK][HOST_REGS];
 115   uint64_t constmap[MAXBLOCK][HOST_REGS];
 116   struct regstat regs[MAXBLOCK];
 117   struct regstat branch_regs[MAXBLOCK];
 118   signed char minimum_free_regs[MAXBLOCK];
 119   u_int needed_reg[MAXBLOCK];
 120   uint64_t requires_32bit[MAXBLOCK];
 121   u_int wont_dirty[MAXBLOCK];
 122   u_int will_dirty[MAXBLOCK];
 123   int ccadj[MAXBLOCK];
 124   int slen;
 125   u_int instr_addr[MAXBLOCK];
 126   u_int link_addr[MAXBLOCK][3];
 127   int linkcount;
 128   u_int stubs[MAXBLOCK*3][8];
 129   int stubcount;
 130   u_int literals[1024][2];
 131   int literalcount;
 132   int is_delayslot;
 133   int cop1_usable;
 134   u_char *out;
 135   struct ll_entry *jump_in[4096];
 136   struct ll_entry *jump_out[4096];
 137   struct ll_entry *jump_dirty[4096];
 138   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 139   char shadow[1048576]  __attribute__((aligned(16)));
 140   void *copy;
 141   int expirep;
 142 #ifndef PCSX
 143   u_int using_tlb;
 144 #else
 145   static const u_int using_tlb=0;
 146 #endif
 147   int new_dynarec_did_compile;
 148   u_int stop_after_jal;
 149   extern u_char restore_candidate[512];
 150   extern int cycle_count;
 151
 152   /* registers that may be allocated */
 153   /* 1-31 gpr */
 154 #define HIREG 32 // hi
 155 #define LOREG 33 // lo
 156 #define FSREG 34 // FPU status (FCSR)
 157 #define CSREG 35 // Coprocessor status
 158 #define CCREG 36 // Cycle count
 159 #define INVCP 37 // Pointer to invalid_code
 160 #define MMREG 38 // Pointer to memory_map
 161 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 162 #define TEMPREG 40
 163 #define FTEMP 40 // FPU temporary register
 164 #define PTEMP 41 // Prefetch temporary register
 165 #define TLREG 42 // TLB mapping offset
 166 #define RHASH 43 // Return address hash
 167 #define RHTBL 44 // Return address hash table address
 168 #define RTEMP 45 // JR/JALR address register
 169 #define MAXREG 45
 170 #define AGEN1 46 // Address generation temporary register
 171 #define AGEN2 47 // Address generation temporary register
 172 #define MGEN1 48 // Maptable address generation temporary register
 173 #define MGEN2 49 // Maptable address generation temporary register
 174 #define BTREG 50 // Branch target temporary register
 175
 176   /* instruction types */
 177 #define NOP 0     // No operation
 178 #define LOAD 1    // Load
 179 #define STORE 2   // Store
 180 #define LOADLR 3  // Unaligned load
 181 #define STORELR 4 // Unaligned store
 182 #define MOV 5     // Move
 183 #define ALU 6     // Arithmetic/logic
 184 #define MULTDIV 7 // Multiply/divide
 185 #define SHIFT 8   // Shift by register
 186 #define SHIFTIMM 9// Shift by immediate
 187 #define IMM16 10  // 16-bit immediate
 188 #define RJUMP 11  // Unconditional jump to register
 189 #define UJUMP 12  // Unconditional jump
 190 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 191 #define SJUMP 14  // Conditional branch (regimm format)
 192 #define COP0 15   // Coprocessor 0
 193 #define COP1 16   // Coprocessor 1
 194 #define C1LS 17   // Coprocessor 1 load/store
 195 #define FJUMP 18  // Conditional branch (floating point)
 196 #define FLOAT 19  // Floating point unit
 197 #define FCONV 20  // Convert integer to float
 198 #define FCOMP 21  // Floating point compare (sets FSREG)
 199 #define SYSCALL 22// SYSCALL
 200 #define OTHER 23  // Other
 201 #define SPAN 24   // Branch/delay slot spans 2 pages
 202 #define NI 25     // Not implemented
 203 #define HLECALL 26// PCSX fake opcodes for HLE
 204 #define COP2 27   // Coprocessor 2 move
 205 #define C2LS 28   // Coprocessor 2 load/store
 206 #define C2OP 29   // Coprocessor 2 operation
 207 #define INTCALL 30// Call interpreter to handle rare corner cases
 208
 209   /* stubs */
 210 #define CC_STUB 1
 211 #define FP_STUB 2
 212 #define LOADB_STUB 3
 213 #define LOADH_STUB 4
 214 #define LOADW_STUB 5
 215 #define LOADD_STUB 6
 216 #define LOADBU_STUB 7
 217 #define LOADHU_STUB 8
 218 #define STOREB_STUB 9
 219 #define STOREH_STUB 10
 220 #define STOREW_STUB 11
 221 #define STORED_STUB 12
 222 #define STORELR_STUB 13
 223 #define INVCODE_STUB 14
 224
 225   /* branch codes */
 226 #define TAKEN 1
 227 #define NOTTAKEN 2
 228 #define NULLDS 3
 229
 230 // asm linkage
 231 int new_recompile_block(int addr);
 232 void *get_addr_ht(u_int vaddr);
 233 void invalidate_block(u_int block);
 234 void invalidate_addr(u_int addr);
 235 void remove_hash(int vaddr);
 236 void jump_vaddr();
 237 void dyna_linker();
 238 void dyna_linker_ds();
 239 void verify_code();
 240 void verify_code_vm();
 241 void verify_code_ds();
 242 void cc_interrupt();
 243 void fp_exception();
 244 void fp_exception_ds();
 245 void jump_syscall();
 246 void jump_syscall_hle();
 247 void jump_eret();
 248 void jump_hlecall();
 249 void jump_intcall();
 250 void new_dyna_leave();
 251
 252 // TLB
 253 void TLBWI_new();
 254 void TLBWR_new();
 255 void read_nomem_new();
 256 void read_nomemb_new();
 257 void read_nomemh_new();
 258 void read_nomemd_new();
 259 void write_nomem_new();
 260 void write_nomemb_new();
 261 void write_nomemh_new();
 262 void write_nomemd_new();
 263 void write_rdram_new();
 264 void write_rdramb_new();
 265 void write_rdramh_new();
 266 void write_rdramd_new();
 267 extern u_int memory_map[1048576];
 268
 269 // Needed by assembler
 270 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 271 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 272 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 273 void load_all_regs(signed char i_regmap[]);
 274 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 275 void load_regs_entry(int t);
 276 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 277
 278 int tracedebug=0;
 279
 280 //#define DEBUG_CYCLE_COUNT 1
 281
 282 static void tlb_hacks()
 283 {
 284 #ifndef DISABLE_TLB
 285   // Goldeneye hack
 286   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 287   {
 288     u_int addr;
 289     int n;
 290     switch (ROM_HEADER->Country_code&0xFF)
 291     {
 292       case 0x45: // U
 293         addr=0x34b30;
 294         break;
 295       case 0x4A: // J
 296         addr=0x34b70;
 297         break;
 298       case 0x50: // E
 299         addr=0x329f0;
 300         break;
 301       default:
 302         // Unknown country code
 303         addr=0;
 304         break;
 305     }
 306     u_int rom_addr=(u_int)rom;
 307     #ifdef ROM_COPY
 308     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 309     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 310     if((void *)rom>(void *)0xffffffff) {
 311       munmap(ROM_COPY, 67108864);
 312       if(mmap(ROM_COPY, 12582912,
 313               PROT_READ | PROT_WRITE,
 314               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 315               -1, 0) <= 0) {printf("mmap() failed\n");}
 316       memcpy(ROM_COPY,rom,12582912);
 317       rom_addr=(u_int)ROM_COPY;
 318     }
 319     #endif
 320     if(addr) {
 321       for(n=0x7F000;n<0x80000;n++) {
 322         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 323       }
 324     }
 325   }
 326 #endif
 327 }
 328
 329 static u_int get_page(u_int vaddr)
 330 {
 331 #ifndef PCSX
 332   u_int page=(vaddr^0x80000000)>>12;
 333 #else
 334   u_int page=vaddr&~0xe0000000;
 335   if (page < 0x1000000)
 336     page &= ~0x0e00000; // RAM mirrors
 337   page>>=12;
 338 #endif
 339 #ifndef DISABLE_TLB
 340   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 341 #endif
 342   if(page>2048) page=2048+(page&2047);
 343   return page;
 344 }
 345
 346 static u_int get_vpage(u_int vaddr)
 347 {
 348   u_int vpage=(vaddr^0x80000000)>>12;
 349 #ifndef DISABLE_TLB
 350   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 351 #endif
 352   if(vpage>2048) vpage=2048+(vpage&2047);
 353   return vpage;
 354 }
 355
 356 // Get address from virtual address
 357 // This is called from the recompiled JR/JALR instructions
 358 void *get_addr(u_int vaddr)
 359 {
 360   u_int page=get_page(vaddr);
 361   u_int vpage=get_vpage(vaddr);
 362   struct ll_entry *head;
 363   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 364   head=jump_in[page];
 365   while(head!=NULL) {
 366     if(head->vaddr==vaddr&&head->reg32==0) {
 367   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 368       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 369       ht_bin[3]=ht_bin[1];
 370       ht_bin[2]=ht_bin[0];
 371       ht_bin[1]=(int)head->addr;
 372       ht_bin[0]=vaddr;
 373       return head->addr;
 374     }
 375     head=head->next;
 376   }
 377   head=jump_dirty[vpage];
 378   while(head!=NULL) {
 379     if(head->vaddr==vaddr&&head->reg32==0) {
 380       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 381       // Don't restore blocks which are about to expire from the cache
 382       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 383       if(verify_dirty(head->addr)) {
 384         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 385         invalid_code[vaddr>>12]=0;
 386         inv_code_start=inv_code_end=~0;
 387 #ifndef DISABLE_TLB
 388         memory_map[vaddr>>12]|=0x40000000;
 389 #endif
 390         if(vpage<2048) {
 391 #ifndef DISABLE_TLB
 392           if(tlb_LUT_r[vaddr>>12]) {
 393             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 394             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 395           }
 396 #endif
 397           restore_candidate[vpage>>3]|=1<<(vpage&7);
 398         }
 399         else restore_candidate[page>>3]|=1<<(page&7);
 400         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 401         if(ht_bin[0]==vaddr) {
 402           ht_bin[1]=(int)head->addr; // Replace existing entry
 403         }
 404         else
 405         {
 406           ht_bin[3]=ht_bin[1];
 407           ht_bin[2]=ht_bin[0];
 408           ht_bin[1]=(int)head->addr;
 409           ht_bin[0]=vaddr;
 410         }
 411         return head->addr;
 412       }
 413     }
 414     head=head->next;
 415   }
 416   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 417   int r=new_recompile_block(vaddr);
 418   if(r==0) return get_addr(vaddr);
 419   // Execute in unmapped page, generate pagefault execption
 420   Status|=2;
 421   Cause=(vaddr<<31)|0x8;
 422   EPC=(vaddr&1)?vaddr-5:vaddr;
 423   BadVAddr=(vaddr&~1);
 424   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 425   EntryHi=BadVAddr&0xFFFFE000;
 426   return get_addr_ht(0x80000000);
 427 }
 428 // Look up address in hash table first
 429 void *get_addr_ht(u_int vaddr)
 430 {
 431   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 432   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 433   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 434   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 435   return get_addr(vaddr);
 436 }
 437
 438 void *get_addr_32(u_int vaddr,u_int flags)
 439 {
 440 #ifdef FORCE32
 441   return get_addr(vaddr);
 442 #else
 443   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 444   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 445   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 446   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 447   u_int page=get_page(vaddr);
 448   u_int vpage=get_vpage(vaddr);
 449   struct ll_entry *head;
 450   head=jump_in[page];
 451   while(head!=NULL) {
 452     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 453       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 454       if(head->reg32==0) {
 455         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 456         if(ht_bin[0]==-1) {
 457           ht_bin[1]=(int)head->addr;
 458           ht_bin[0]=vaddr;
 459         }else if(ht_bin[2]==-1) {
 460           ht_bin[3]=(int)head->addr;
 461           ht_bin[2]=vaddr;
 462         }
 463         //ht_bin[3]=ht_bin[1];
 464         //ht_bin[2]=ht_bin[0];
 465         //ht_bin[1]=(int)head->addr;
 466         //ht_bin[0]=vaddr;
 467       }
 468       return head->addr;
 469     }
 470     head=head->next;
 471   }
 472   head=jump_dirty[vpage];
 473   while(head!=NULL) {
 474     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 475       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 476       // Don't restore blocks which are about to expire from the cache
 477       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 478       if(verify_dirty(head->addr)) {
 479         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 480         invalid_code[vaddr>>12]=0;
 481         inv_code_start=inv_code_end=~0;
 482         memory_map[vaddr>>12]|=0x40000000;
 483         if(vpage<2048) {
 484 #ifndef DISABLE_TLB
 485           if(tlb_LUT_r[vaddr>>12]) {
 486             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 487             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 488           }
 489 #endif
 490           restore_candidate[vpage>>3]|=1<<(vpage&7);
 491         }
 492         else restore_candidate[page>>3]|=1<<(page&7);
 493         if(head->reg32==0) {
 494           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 495           if(ht_bin[0]==-1) {
 496             ht_bin[1]=(int)head->addr;
 497             ht_bin[0]=vaddr;
 498           }else if(ht_bin[2]==-1) {
 499             ht_bin[3]=(int)head->addr;
 500             ht_bin[2]=vaddr;
 501           }
 502           //ht_bin[3]=ht_bin[1];
 503           //ht_bin[2]=ht_bin[0];
 504           //ht_bin[1]=(int)head->addr;
 505           //ht_bin[0]=vaddr;
 506         }
 507         return head->addr;
 508       }
 509     }
 510     head=head->next;
 511   }
 512   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 513   int r=new_recompile_block(vaddr);
 514   if(r==0) return get_addr(vaddr);
 515   // Execute in unmapped page, generate pagefault execption
 516   Status|=2;
 517   Cause=(vaddr<<31)|0x8;
 518   EPC=(vaddr&1)?vaddr-5:vaddr;
 519   BadVAddr=(vaddr&~1);
 520   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 521   EntryHi=BadVAddr&0xFFFFE000;
 522   return get_addr_ht(0x80000000);
 523 #endif
 524 }
 525
 526 void clear_all_regs(signed char regmap[])
 527 {
 528   int hr;
 529   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 530 }
 531
 532 signed char get_reg(signed char regmap[],int r)
 533 {
 534   int hr;
 535   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 536   return -1;
 537 }
 538
 539 // Find a register that is available for two consecutive cycles
 540 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 541 {
 542   int hr;
 543   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 544   return -1;
 545 }
 546
 547 int count_free_regs(signed char regmap[])
 548 {
 549   int count=0;
 550   int hr;
 551   for(hr=0;hr<HOST_REGS;hr++)
 552   {
 553     if(hr!=EXCLUDE_REG) {
 554       if(regmap[hr]<0) count++;
 555     }
 556   }
 557   return count;
 558 }
 559
 560 void dirty_reg(struct regstat *cur,signed char reg)
 561 {
 562   int hr;
 563   if(!reg) return;
 564   for (hr=0;hr<HOST_REGS;hr++) {
 565     if((cur->regmap[hr]&63)==reg) {
 566       cur->dirty|=1<<hr;
 567     }
 568   }
 569 }
 570
 571 // If we dirty the lower half of a 64 bit register which is now being
 572 // sign-extended, we need to dump the upper half.
 573 // Note: Do this only after completion of the instruction, because
 574 // some instructions may need to read the full 64-bit value even if
 575 // overwriting it (eg SLTI, DSRA32).
 576 static void flush_dirty_uppers(struct regstat *cur)
 577 {
 578   int hr,reg;
 579   for (hr=0;hr<HOST_REGS;hr++) {
 580     if((cur->dirty>>hr)&1) {
 581       reg=cur->regmap[hr];
 582       if(reg>=64)
 583         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 584     }
 585   }
 586 }
 587
 588 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 589 {
 590   int hr;
 591   if(!reg) return;
 592   for (hr=0;hr<HOST_REGS;hr++) {
 593     if(cur->regmap[hr]==reg) {
 594       cur->isconst|=1<<hr;
 595       cur->constmap[hr]=value;
 596     }
 597     else if((cur->regmap[hr]^64)==reg) {
 598       cur->isconst|=1<<hr;
 599       cur->constmap[hr]=value>>32;
 600     }
 601   }
 602 }
 603
 604 void clear_const(struct regstat *cur,signed char reg)
 605 {
 606   int hr;
 607   if(!reg) return;
 608   for (hr=0;hr<HOST_REGS;hr++) {
 609     if((cur->regmap[hr]&63)==reg) {
 610       cur->isconst&=~(1<<hr);
 611     }
 612   }
 613 }
 614
 615 int is_const(struct regstat *cur,signed char reg)
 616 {
 617   int hr;
 618   if(reg<0) return 0;
 619   if(!reg) return 1;
 620   for (hr=0;hr<HOST_REGS;hr++) {
 621     if((cur->regmap[hr]&63)==reg) {
 622       return (cur->isconst>>hr)&1;
 623     }
 624   }
 625   return 0;
 626 }
 627 uint64_t get_const(struct regstat *cur,signed char reg)
 628 {
 629   int hr;
 630   if(!reg) return 0;
 631   for (hr=0;hr<HOST_REGS;hr++) {
 632     if(cur->regmap[hr]==reg) {
 633       return cur->constmap[hr];
 634     }
 635   }
 636   printf("Unknown constant in r%d\n",reg);
 637   exit(1);
 638 }
 639
 640 // Least soon needed registers
 641 // Look at the next ten instructions and see which registers
 642 // will be used.  Try not to reallocate these.
 643 void lsn(u_char hsn[], int i, int *preferred_reg)
 644 {
 645   int j;
 646   int b=-1;
 647   for(j=0;j<9;j++)
 648   {
 649     if(i+j>=slen) {
 650       j=slen-i-1;
 651       break;
 652     }
 653     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 654     {
 655       // Don't go past an unconditonal jump
 656       j++;
 657       break;
 658     }
 659   }
 660   for(;j>=0;j--)
 661   {
 662     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 663     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 664     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 665     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 666     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 667       // Stores can allocate zero
 668       hsn[rs1[i+j]]=j;
 669       hsn[rs2[i+j]]=j;
 670     }
 671     // On some architectures stores need invc_ptr
 672     #if defined(HOST_IMM8)
 673     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 674       hsn[INVCP]=j;
 675     }
 676     #endif
 677     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 678     {
 679       hsn[CCREG]=j;
 680       b=j;
 681     }
 682   }
 683   if(b>=0)
 684   {
 685     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 686     {
 687       // Follow first branch
 688       int t=(ba[i+b]-start)>>2;
 689       j=7-b;if(t+j>=slen) j=slen-t-1;
 690       for(;j>=0;j--)
 691       {
 692         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 693         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 694         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 695         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 696       }
 697     }
 698     // TODO: preferred register based on backward branch
 699   }
 700   // Delay slot should preferably not overwrite branch conditions or cycle count
 701   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 702     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 703     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 704     hsn[CCREG]=1;
 705     // ...or hash tables
 706     hsn[RHASH]=1;
 707     hsn[RHTBL]=1;
 708   }
 709   // Coprocessor load/store needs FTEMP, even if not declared
 710   if(itype[i]==C1LS||itype[i]==C2LS) {
 711     hsn[FTEMP]=0;
 712   }
 713   // Load L/R also uses FTEMP as a temporary register
 714   if(itype[i]==LOADLR) {
 715     hsn[FTEMP]=0;
 716   }
 717   // Also SWL/SWR/SDL/SDR
 718   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 719     hsn[FTEMP]=0;
 720   }
 721   // Don't remove the TLB registers either
 722   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 723     hsn[TLREG]=0;
 724   }
 725   // Don't remove the miniht registers
 726   if(itype[i]==UJUMP||itype[i]==RJUMP)
 727   {
 728     hsn[RHASH]=0;
 729     hsn[RHTBL]=0;
 730   }
 731 }
 732
 733 // We only want to allocate registers if we're going to use them again soon
 734 int needed_again(int r, int i)
 735 {
 736   int j;
 737   int b=-1;
 738   int rn=10;
 739
 740   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 741   {
 742     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 743       return 0; // Don't need any registers if exiting the block
 744   }
 745   for(j=0;j<9;j++)
 746   {
 747     if(i+j>=slen) {
 748       j=slen-i-1;
 749       break;
 750     }
 751     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 752     {
 753       // Don't go past an unconditonal jump
 754       j++;
 755       break;
 756     }
 757     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 758     {
 759       break;
 760     }
 761   }
 762   for(;j>=1;j--)
 763   {
 764     if(rs1[i+j]==r) rn=j;
 765     if(rs2[i+j]==r) rn=j;
 766     if((unneeded_reg[i+j]>>r)&1) rn=10;
 767     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 768     {
 769       b=j;
 770     }
 771   }
 772   /*
 773   if(b>=0)
 774   {
 775     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 776     {
 777       // Follow first branch
 778       int o=rn;
 779       int t=(ba[i+b]-start)>>2;
 780       j=7-b;if(t+j>=slen) j=slen-t-1;
 781       for(;j>=0;j--)
 782       {
 783         if(!((unneeded_reg[t+j]>>r)&1)) {
 784           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 785           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 786         }
 787         else rn=o;
 788       }
 789     }
 790   }*/
 791   if(rn<10) return 1;
 792   return 0;
 793 }
 794
 795 // Try to match register allocations at the end of a loop with those
 796 // at the beginning
 797 int loop_reg(int i, int r, int hr)
 798 {
 799   int j,k;
 800   for(j=0;j<9;j++)
 801   {
 802     if(i+j>=slen) {
 803       j=slen-i-1;
 804       break;
 805     }
 806     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 807     {
 808       // Don't go past an unconditonal jump
 809       j++;
 810       break;
 811     }
 812   }
 813   k=0;
 814   if(i>0){
 815     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 816       k--;
 817   }
 818   for(;k<j;k++)
 819   {
 820     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 821     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 822     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 823     {
 824       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 825       {
 826         int t=(ba[i+k]-start)>>2;
 827         int reg=get_reg(regs[t].regmap_entry,r);
 828         if(reg>=0) return reg;
 829         //reg=get_reg(regs[t+1].regmap_entry,r);
 830         //if(reg>=0) return reg;
 831       }
 832     }
 833   }
 834   return hr;
 835 }
 836
 837
 838 // Allocate every register, preserving source/target regs
 839 void alloc_all(struct regstat *cur,int i)
 840 {
 841   int hr;
 842
 843   for(hr=0;hr<HOST_REGS;hr++) {
 844     if(hr!=EXCLUDE_REG) {
 845       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 846          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 847       {
 848         cur->regmap[hr]=-1;
 849         cur->dirty&=~(1<<hr);
 850       }
 851       // Don't need zeros
 852       if((cur->regmap[hr]&63)==0)
 853       {
 854         cur->regmap[hr]=-1;
 855         cur->dirty&=~(1<<hr);
 856       }
 857     }
 858   }
 859 }
 860
 861 #ifndef FORCE32
 862 void div64(int64_t dividend,int64_t divisor)
 863 {
 864   lo=dividend/divisor;
 865   hi=dividend%divisor;
 866   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 867   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 868 }
 869 void divu64(uint64_t dividend,uint64_t divisor)
 870 {
 871   lo=dividend/divisor;
 872   hi=dividend%divisor;
 873   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 874   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 875 }
 876
 877 void mult64(uint64_t m1,uint64_t m2)
 878 {
 879    unsigned long long int op1, op2, op3, op4;
 880    unsigned long long int result1, result2, result3, result4;
 881    unsigned long long int temp1, temp2, temp3, temp4;
 882    int sign = 0;
 883
 884    if (m1 < 0)
 885      {
 886     op2 = -m1;
 887     sign = 1 - sign;
 888      }
 889    else op2 = m1;
 890    if (m2 < 0)
 891      {
 892     op4 = -m2;
 893     sign = 1 - sign;
 894      }
 895    else op4 = m2;
 896
 897    op1 = op2 & 0xFFFFFFFF;
 898    op2 = (op2 >> 32) & 0xFFFFFFFF;
 899    op3 = op4 & 0xFFFFFFFF;
 900    op4 = (op4 >> 32) & 0xFFFFFFFF;
 901
 902    temp1 = op1 * op3;
 903    temp2 = (temp1 >> 32) + op1 * op4;
 904    temp3 = op2 * op3;
 905    temp4 = (temp3 >> 32) + op2 * op4;
 906
 907    result1 = temp1 & 0xFFFFFFFF;
 908    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 909    result3 = (result2 >> 32) + temp4;
 910    result4 = (result3 >> 32);
 911
 912    lo = result1 | (result2 << 32);
 913    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 914    if (sign)
 915      {
 916     hi = ~hi;
 917     if (!lo) hi++;
 918     else lo = ~lo + 1;
 919      }
 920 }
 921
 922 void multu64(uint64_t m1,uint64_t m2)
 923 {
 924    unsigned long long int op1, op2, op3, op4;
 925    unsigned long long int result1, result2, result3, result4;
 926    unsigned long long int temp1, temp2, temp3, temp4;
 927
 928    op1 = m1 & 0xFFFFFFFF;
 929    op2 = (m1 >> 32) & 0xFFFFFFFF;
 930    op3 = m2 & 0xFFFFFFFF;
 931    op4 = (m2 >> 32) & 0xFFFFFFFF;
 932
 933    temp1 = op1 * op3;
 934    temp2 = (temp1 >> 32) + op1 * op4;
 935    temp3 = op2 * op3;
 936    temp4 = (temp3 >> 32) + op2 * op4;
 937
 938    result1 = temp1 & 0xFFFFFFFF;
 939    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 940    result3 = (result2 >> 32) + temp4;
 941    result4 = (result3 >> 32);
 942
 943    lo = result1 | (result2 << 32);
 944    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 945
 946   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 947   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 948 }
 949
 950 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 951 {
 952   if(bits) {
 953     original<<=64-bits;
 954     original>>=64-bits;
 955     loaded<<=bits;
 956     original|=loaded;
 957   }
 958   else original=loaded;
 959   return original;
 960 }
 961 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 962 {
 963   if(bits^56) {
 964     original>>=64-(bits^56);
 965     original<<=64-(bits^56);
 966     loaded>>=bits^56;
 967     original|=loaded;
 968   }
 969   else original=loaded;
 970   return original;
 971 }
 972 #endif
 973
 974 #ifdef __i386__
 975 #include "assem_x86.c"
 976 #endif
 977 #ifdef __x86_64__
 978 #include "assem_x64.c"
 979 #endif
 980 #ifdef __arm__
 981 #include "assem_arm.c"
 982 #endif
 983
 984 // Add virtual address mapping to linked list
 985 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 986 {
 987   struct ll_entry *new_entry;
 988   new_entry=malloc(sizeof(struct ll_entry));
 989   assert(new_entry!=NULL);
 990   new_entry->vaddr=vaddr;
 991   new_entry->reg32=0;
 992   new_entry->addr=addr;
 993   new_entry->next=*head;
 994   *head=new_entry;
 995 }
 996
 997 // Add virtual address mapping for 32-bit compiled block
 998 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 999 {
1000   ll_add(head,vaddr,addr);
1001 #ifndef FORCE32
1002   (*head)->reg32=reg32;
1003 #endif
1004 }
1005
1006 // Check if an address is already compiled
1007 // but don't return addresses which are about to expire from the cache
1008 void *check_addr(u_int vaddr)
1009 {
1010   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1011   if(ht_bin[0]==vaddr) {
1012     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1013       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1014   }
1015   if(ht_bin[2]==vaddr) {
1016     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1017       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1018   }
1019   u_int page=get_page(vaddr);
1020   struct ll_entry *head;
1021   head=jump_in[page];
1022   while(head!=NULL) {
1023     if(head->vaddr==vaddr&&head->reg32==0) {
1024       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1025         // Update existing entry with current address
1026         if(ht_bin[0]==vaddr) {
1027           ht_bin[1]=(int)head->addr;
1028           return head->addr;
1029         }
1030         if(ht_bin[2]==vaddr) {
1031           ht_bin[3]=(int)head->addr;
1032           return head->addr;
1033         }
1034         // Insert into hash table with low priority.
1035         // Don't evict existing entries, as they are probably
1036         // addresses that are being accessed frequently.
1037         if(ht_bin[0]==-1) {
1038           ht_bin[1]=(int)head->addr;
1039           ht_bin[0]=vaddr;
1040         }else if(ht_bin[2]==-1) {
1041           ht_bin[3]=(int)head->addr;
1042           ht_bin[2]=vaddr;
1043         }
1044         return head->addr;
1045       }
1046     }
1047     head=head->next;
1048   }
1049   return 0;
1050 }
1051
1052 void remove_hash(int vaddr)
1053 {
1054   //printf("remove hash: %x\n",vaddr);
1055   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1056   if(ht_bin[2]==vaddr) {
1057     ht_bin[2]=ht_bin[3]=-1;
1058   }
1059   if(ht_bin[0]==vaddr) {
1060     ht_bin[0]=ht_bin[2];
1061     ht_bin[1]=ht_bin[3];
1062     ht_bin[2]=ht_bin[3]=-1;
1063   }
1064 }
1065
1066 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1067 {
1068   struct ll_entry *next;
1069   while(*head) {
1070     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1071        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1072     {
1073       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1074       remove_hash((*head)->vaddr);
1075       next=(*head)->next;
1076       free(*head);
1077       *head=next;
1078     }
1079     else
1080     {
1081       head=&((*head)->next);
1082     }
1083   }
1084 }
1085
1086 // Remove all entries from linked list
1087 void ll_clear(struct ll_entry **head)
1088 {
1089   struct ll_entry *cur;
1090   struct ll_entry *next;
1091   if(cur=*head) {
1092     *head=0;
1093     while(cur) {
1094       next=cur->next;
1095       free(cur);
1096       cur=next;
1097     }
1098   }
1099 }
1100
1101 // Dereference the pointers and remove if it matches
1102 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1103 {
1104   while(head) {
1105     int ptr=get_pointer(head->addr);
1106     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1107     if(((ptr>>shift)==(addr>>shift)) ||
1108        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1109     {
1110       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1111       u_int host_addr=(u_int)kill_pointer(head->addr);
1112       #ifdef __arm__
1113         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1114       #endif
1115     }
1116     head=head->next;
1117   }
1118 }
1119
1120 // This is called when we write to a compiled block (see do_invstub)
1121 void invalidate_page(u_int page)
1122 {
1123   struct ll_entry *head;
1124   struct ll_entry *next;
1125   head=jump_in[page];
1126   jump_in[page]=0;
1127   while(head!=NULL) {
1128     inv_debug("INVALIDATE: %x\n",head->vaddr);
1129     remove_hash(head->vaddr);
1130     next=head->next;
1131     free(head);
1132     head=next;
1133   }
1134   head=jump_out[page];
1135   jump_out[page]=0;
1136   while(head!=NULL) {
1137     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1138     u_int host_addr=(u_int)kill_pointer(head->addr);
1139     #ifdef __arm__
1140       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1141     #endif
1142     next=head->next;
1143     free(head);
1144     head=next;
1145   }
1146 }
1147
1148 static void invalidate_block_range(u_int block, u_int first, u_int last)
1149 {
1150   u_int page=get_page(block<<12);
1151   //printf("first=%d last=%d\n",first,last);
1152   invalidate_page(page);
1153   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1154   assert(last<page+5);
1155   // Invalidate the adjacent pages if a block crosses a 4K boundary
1156   while(first<page) {
1157     invalidate_page(first);
1158     first++;
1159   }
1160   for(first=page+1;first<last;first++) {
1161     invalidate_page(first);
1162   }
1163   #ifdef __arm__
1164     do_clear_cache();
1165   #endif
1166
1167   // Don't trap writes
1168   invalid_code[block]=1;
1169 #ifndef DISABLE_TLB
1170   // If there is a valid TLB entry for this page, remove write protect
1171   if(tlb_LUT_w[block]) {
1172     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1173     // CHECK: Is this right?
1174     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1175     u_int real_block=tlb_LUT_w[block]>>12;
1176     invalid_code[real_block]=1;
1177     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1178   }
1179   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1180 #endif
1181
1182   #ifdef USE_MINI_HT
1183   memset(mini_ht,-1,sizeof(mini_ht));
1184   #endif
1185 }
1186
1187 void invalidate_block(u_int block)
1188 {
1189   u_int page=get_page(block<<12);
1190   u_int vpage=get_vpage(block<<12);
1191   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1192   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1193   u_int first,last;
1194   first=last=page;
1195   struct ll_entry *head;
1196   head=jump_dirty[vpage];
1197   //printf("page=%d vpage=%d\n",page,vpage);
1198   while(head!=NULL) {
1199     u_int start,end;
1200     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1201       get_bounds((int)head->addr,&start,&end);
1202       //printf("start: %x end: %x\n",start,end);
1203       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1204         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1205           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1206           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1207         }
1208       }
1209 #ifndef DISABLE_TLB
1210       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1211         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1212           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1213           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1214         }
1215       }
1216 #endif
1217     }
1218     head=head->next;
1219   }
1220   invalidate_block_range(block,first,last);
1221 }
1222
1223 void invalidate_addr(u_int addr)
1224 {
1225 #ifdef PCSX
1226   //static int rhits;
1227   // this check is done by the caller
1228   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1229   u_int page=get_page(addr);
1230   if(page<2048) { // RAM
1231     struct ll_entry *head;
1232     u_int addr_min=~0, addr_max=0;
1233     int mask=RAM_SIZE-1;
1234     int pg1;
1235     inv_code_start=addr&~0xfff;
1236     inv_code_end=addr|0xfff;
1237     pg1=page;
1238     if (pg1>0) {
1239       // must check previous page too because of spans..
1240       pg1--;
1241       inv_code_start-=0x1000;
1242     }
1243     for(;pg1<=page;pg1++) {
1244       for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1245         u_int start,end;
1246         get_bounds((int)head->addr,&start,&end);
1247         if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1248           if(start<addr_min) addr_min=start;
1249           if(end>addr_max) addr_max=end;
1250         }
1251         else if(addr<start) {
1252           if(start<inv_code_end)
1253             inv_code_end=start-1;
1254         }
1255         else {
1256           if(end>inv_code_start)
1257             inv_code_start=end;
1258         }
1259       }
1260     }
1261     if (addr_min!=~0) {
1262       inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1263       inv_code_start=inv_code_end=~0;
1264       invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1265       return;
1266     }
1267     else {
1268       inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1269     }
1270     //rhits=0;
1271     if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1272       return;
1273   }
1274 #endif
1275   invalidate_block(addr>>12);
1276 }
1277
1278 // This is called when loading a save state.
1279 // Anything could have changed, so invalidate everything.
1280 void invalidate_all_pages()
1281 {
1282   u_int page,n;
1283   for(page=0;page<4096;page++)
1284     invalidate_page(page);
1285   for(page=0;page<1048576;page++)
1286     if(!invalid_code[page]) {
1287       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1288       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1289     }
1290   #ifdef __arm__
1291   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1292   #endif
1293   #ifdef USE_MINI_HT
1294   memset(mini_ht,-1,sizeof(mini_ht));
1295   #endif
1296   #ifndef DISABLE_TLB
1297   // TLB
1298   for(page=0;page<0x100000;page++) {
1299     if(tlb_LUT_r[page]) {
1300       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1301       if(!tlb_LUT_w[page]||!invalid_code[page])
1302         memory_map[page]|=0x40000000; // Write protect
1303     }
1304     else memory_map[page]=-1;
1305     if(page==0x80000) page=0xC0000;
1306   }
1307   tlb_hacks();
1308   #endif
1309 }
1310
1311 // Add an entry to jump_out after making a link
1312 void add_link(u_int vaddr,void *src)
1313 {
1314   u_int page=get_page(vaddr);
1315   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1316   int *ptr=(int *)(src+4);
1317   assert((*ptr&0x0fff0000)==0x059f0000);
1318   ll_add(jump_out+page,vaddr,src);
1319   //int ptr=get_pointer(src);
1320   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1321 }
1322
1323 // If a code block was found to be unmodified (bit was set in
1324 // restore_candidate) and it remains unmodified (bit is clear
1325 // in invalid_code) then move the entries for that 4K page from
1326 // the dirty list to the clean list.
1327 void clean_blocks(u_int page)
1328 {
1329   struct ll_entry *head;
1330   inv_debug("INV: clean_blocks page=%d\n",page);
1331   head=jump_dirty[page];
1332   while(head!=NULL) {
1333     if(!invalid_code[head->vaddr>>12]) {
1334       // Don't restore blocks which are about to expire from the cache
1335       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1336         u_int start,end;
1337         if(verify_dirty((int)head->addr)) {
1338           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1339           u_int i;
1340           u_int inv=0;
1341           get_bounds((int)head->addr,&start,&end);
1342           if(start-(u_int)rdram<RAM_SIZE) {
1343             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1344               inv|=invalid_code[i];
1345             }
1346           }
1347 #ifndef DISABLE_TLB
1348           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1349             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1350             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1351             if(addr<start||addr>=end) inv=1;
1352           }
1353 #endif
1354           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1355             inv=1;
1356           }
1357           if(!inv) {
1358             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1359             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1360               u_int ppage=page;
1361 #ifndef DISABLE_TLB
1362               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1363 #endif
1364               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1365               //printf("page=%x, addr=%x\n",page,head->vaddr);
1366               //assert(head->vaddr>>12==(page|0x80000));
1367               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1368               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1369               if(!head->reg32) {
1370                 if(ht_bin[0]==head->vaddr) {
1371                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1372                 }
1373                 if(ht_bin[2]==head->vaddr) {
1374                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1375                 }
1376               }
1377             }
1378           }
1379         }
1380       }
1381     }
1382     head=head->next;
1383   }
1384 }
1385
1386
1387 void mov_alloc(struct regstat *current,int i)
1388 {
1389   // Note: Don't need to actually alloc the source registers
1390   if((~current->is32>>rs1[i])&1) {
1391     //alloc_reg64(current,i,rs1[i]);
1392     alloc_reg64(current,i,rt1[i]);
1393     current->is32&=~(1LL<<rt1[i]);
1394   } else {
1395     //alloc_reg(current,i,rs1[i]);
1396     alloc_reg(current,i,rt1[i]);
1397     current->is32|=(1LL<<rt1[i]);
1398   }
1399   clear_const(current,rs1[i]);
1400   clear_const(current,rt1[i]);
1401   dirty_reg(current,rt1[i]);
1402 }
1403
1404 void shiftimm_alloc(struct regstat *current,int i)
1405 {
1406   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1407   {
1408     if(rt1[i]) {
1409       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1410       else lt1[i]=rs1[i];
1411       alloc_reg(current,i,rt1[i]);
1412       current->is32|=1LL<<rt1[i];
1413       dirty_reg(current,rt1[i]);
1414       if(is_const(current,rs1[i])) {
1415         int v=get_const(current,rs1[i]);
1416         if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1417         if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1418         if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1419       }
1420       else clear_const(current,rt1[i]);
1421     }
1422   }
1423   else
1424   {
1425     clear_const(current,rs1[i]);
1426     clear_const(current,rt1[i]);
1427   }
1428
1429   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1430   {
1431     if(rt1[i]) {
1432       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1433       alloc_reg64(current,i,rt1[i]);
1434       current->is32&=~(1LL<<rt1[i]);
1435       dirty_reg(current,rt1[i]);
1436     }
1437   }
1438   if(opcode2[i]==0x3c) // DSLL32
1439   {
1440     if(rt1[i]) {
1441       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1442       alloc_reg64(current,i,rt1[i]);
1443       current->is32&=~(1LL<<rt1[i]);
1444       dirty_reg(current,rt1[i]);
1445     }
1446   }
1447   if(opcode2[i]==0x3e) // DSRL32
1448   {
1449     if(rt1[i]) {
1450       alloc_reg64(current,i,rs1[i]);
1451       if(imm[i]==32) {
1452         alloc_reg64(current,i,rt1[i]);
1453         current->is32&=~(1LL<<rt1[i]);
1454       } else {
1455         alloc_reg(current,i,rt1[i]);
1456         current->is32|=1LL<<rt1[i];
1457       }
1458       dirty_reg(current,rt1[i]);
1459     }
1460   }
1461   if(opcode2[i]==0x3f) // DSRA32
1462   {
1463     if(rt1[i]) {
1464       alloc_reg64(current,i,rs1[i]);
1465       alloc_reg(current,i,rt1[i]);
1466       current->is32|=1LL<<rt1[i];
1467       dirty_reg(current,rt1[i]);
1468     }
1469   }
1470 }
1471
1472 void shift_alloc(struct regstat *current,int i)
1473 {
1474   if(rt1[i]) {
1475     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1476     {
1477       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1478       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1479       alloc_reg(current,i,rt1[i]);
1480       if(rt1[i]==rs2[i]) {
1481         alloc_reg_temp(current,i,-1);
1482         minimum_free_regs[i]=1;
1483       }
1484       current->is32|=1LL<<rt1[i];
1485     } else { // DSLLV/DSRLV/DSRAV
1486       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1487       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1488       alloc_reg64(current,i,rt1[i]);
1489       current->is32&=~(1LL<<rt1[i]);
1490       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1491       {
1492         alloc_reg_temp(current,i,-1);
1493         minimum_free_regs[i]=1;
1494       }
1495     }
1496     clear_const(current,rs1[i]);
1497     clear_const(current,rs2[i]);
1498     clear_const(current,rt1[i]);
1499     dirty_reg(current,rt1[i]);
1500   }
1501 }
1502
1503 void alu_alloc(struct regstat *current,int i)
1504 {
1505   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1506     if(rt1[i]) {
1507       if(rs1[i]&&rs2[i]) {
1508         alloc_reg(current,i,rs1[i]);
1509         alloc_reg(current,i,rs2[i]);
1510       }
1511       else {
1512         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1513         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1514       }
1515       alloc_reg(current,i,rt1[i]);
1516     }
1517     current->is32|=1LL<<rt1[i];
1518   }
1519   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1520     if(rt1[i]) {
1521       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1522       {
1523         alloc_reg64(current,i,rs1[i]);
1524         alloc_reg64(current,i,rs2[i]);
1525         alloc_reg(current,i,rt1[i]);
1526       } else {
1527         alloc_reg(current,i,rs1[i]);
1528         alloc_reg(current,i,rs2[i]);
1529         alloc_reg(current,i,rt1[i]);
1530       }
1531     }
1532     current->is32|=1LL<<rt1[i];
1533   }
1534   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1535     if(rt1[i]) {
1536       if(rs1[i]&&rs2[i]) {
1537         alloc_reg(current,i,rs1[i]);
1538         alloc_reg(current,i,rs2[i]);
1539       }
1540       else
1541       {
1542         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1543         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1544       }
1545       alloc_reg(current,i,rt1[i]);
1546       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1547       {
1548         if(!((current->uu>>rt1[i])&1)) {
1549           alloc_reg64(current,i,rt1[i]);
1550         }
1551         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1552           if(rs1[i]&&rs2[i]) {
1553             alloc_reg64(current,i,rs1[i]);
1554             alloc_reg64(current,i,rs2[i]);
1555           }
1556           else
1557           {
1558             // Is is really worth it to keep 64-bit values in registers?
1559             #ifdef NATIVE_64BIT
1560             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1561             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1562             #endif
1563           }
1564         }
1565         current->is32&=~(1LL<<rt1[i]);
1566       } else {
1567         current->is32|=1LL<<rt1[i];
1568       }
1569     }
1570   }
1571   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1572     if(rt1[i]) {
1573       if(rs1[i]&&rs2[i]) {
1574         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1575           alloc_reg64(current,i,rs1[i]);
1576           alloc_reg64(current,i,rs2[i]);
1577           alloc_reg64(current,i,rt1[i]);
1578         } else {
1579           alloc_reg(current,i,rs1[i]);
1580           alloc_reg(current,i,rs2[i]);
1581           alloc_reg(current,i,rt1[i]);
1582         }
1583       }
1584       else {
1585         alloc_reg(current,i,rt1[i]);
1586         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1587           // DADD used as move, or zeroing
1588           // If we have a 64-bit source, then make the target 64 bits too
1589           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1590             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1591             alloc_reg64(current,i,rt1[i]);
1592           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1593             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1594             alloc_reg64(current,i,rt1[i]);
1595           }
1596           if(opcode2[i]>=0x2e&&rs2[i]) {
1597             // DSUB used as negation - 64-bit result
1598             // If we have a 32-bit register, extend it to 64 bits
1599             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1600             alloc_reg64(current,i,rt1[i]);
1601           }
1602         }
1603       }
1604       if(rs1[i]&&rs2[i]) {
1605         current->is32&=~(1LL<<rt1[i]);
1606       } else if(rs1[i]) {
1607         current->is32&=~(1LL<<rt1[i]);
1608         if((current->is32>>rs1[i])&1)
1609           current->is32|=1LL<<rt1[i];
1610       } else if(rs2[i]) {
1611         current->is32&=~(1LL<<rt1[i]);
1612         if((current->is32>>rs2[i])&1)
1613           current->is32|=1LL<<rt1[i];
1614       } else {
1615         current->is32|=1LL<<rt1[i];
1616       }
1617     }
1618   }
1619   clear_const(current,rs1[i]);
1620   clear_const(current,rs2[i]);
1621   clear_const(current,rt1[i]);
1622   dirty_reg(current,rt1[i]);
1623 }
1624
1625 void imm16_alloc(struct regstat *current,int i)
1626 {
1627   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1628   else lt1[i]=rs1[i];
1629   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1630   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1631     current->is32&=~(1LL<<rt1[i]);
1632     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1633       // TODO: Could preserve the 32-bit flag if the immediate is zero
1634       alloc_reg64(current,i,rt1[i]);
1635       alloc_reg64(current,i,rs1[i]);
1636     }
1637     clear_const(current,rs1[i]);
1638     clear_const(current,rt1[i]);
1639   }
1640   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1641     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1642     current->is32|=1LL<<rt1[i];
1643     clear_const(current,rs1[i]);
1644     clear_const(current,rt1[i]);
1645   }
1646   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1647     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1648       if(rs1[i]!=rt1[i]) {
1649         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1650         alloc_reg64(current,i,rt1[i]);
1651         current->is32&=~(1LL<<rt1[i]);
1652       }
1653     }
1654     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1655     if(is_const(current,rs1[i])) {
1656       int v=get_const(current,rs1[i]);
1657       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1658       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1659       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1660     }
1661     else clear_const(current,rt1[i]);
1662   }
1663   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1664     if(is_const(current,rs1[i])) {
1665       int v=get_const(current,rs1[i]);
1666       set_const(current,rt1[i],v+imm[i]);
1667     }
1668     else clear_const(current,rt1[i]);
1669     current->is32|=1LL<<rt1[i];
1670   }
1671   else {
1672     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1673     current->is32|=1LL<<rt1[i];
1674   }
1675   dirty_reg(current,rt1[i]);
1676 }
1677
1678 void load_alloc(struct regstat *current,int i)
1679 {
1680   clear_const(current,rt1[i]);
1681   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1682   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1683   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1684   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1685     alloc_reg(current,i,rt1[i]);
1686     assert(get_reg(current->regmap,rt1[i])>=0);
1687     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1688     {
1689       current->is32&=~(1LL<<rt1[i]);
1690       alloc_reg64(current,i,rt1[i]);
1691     }
1692     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1693     {
1694       current->is32&=~(1LL<<rt1[i]);
1695       alloc_reg64(current,i,rt1[i]);
1696       alloc_all(current,i);
1697       alloc_reg64(current,i,FTEMP);
1698       minimum_free_regs[i]=HOST_REGS;
1699     }
1700     else current->is32|=1LL<<rt1[i];
1701     dirty_reg(current,rt1[i]);
1702     // If using TLB, need a register for pointer to the mapping table
1703     if(using_tlb) alloc_reg(current,i,TLREG);
1704     // LWL/LWR need a temporary register for the old value
1705     if(opcode[i]==0x22||opcode[i]==0x26)
1706     {
1707       alloc_reg(current,i,FTEMP);
1708       alloc_reg_temp(current,i,-1);
1709       minimum_free_regs[i]=1;
1710     }
1711   }
1712   else
1713   {
1714     // Load to r0 or unneeded register (dummy load)
1715     // but we still need a register to calculate the address
1716     if(opcode[i]==0x22||opcode[i]==0x26)
1717     {
1718       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1719     }
1720     // If using TLB, need a register for pointer to the mapping table
1721     if(using_tlb) alloc_reg(current,i,TLREG);
1722     alloc_reg_temp(current,i,-1);
1723     minimum_free_regs[i]=1;
1724     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1725     {
1726       alloc_all(current,i);
1727       alloc_reg64(current,i,FTEMP);
1728       minimum_free_regs[i]=HOST_REGS;
1729     }
1730   }
1731 }
1732
1733 void store_alloc(struct regstat *current,int i)
1734 {
1735   clear_const(current,rs2[i]);
1736   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1737   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1738   alloc_reg(current,i,rs2[i]);
1739   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1740     alloc_reg64(current,i,rs2[i]);
1741     if(rs2[i]) alloc_reg(current,i,FTEMP);
1742   }
1743   // If using TLB, need a register for pointer to the mapping table
1744   if(using_tlb) alloc_reg(current,i,TLREG);
1745   #if defined(HOST_IMM8)
1746   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1747   else alloc_reg(current,i,INVCP);
1748   #endif
1749   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1750     alloc_reg(current,i,FTEMP);
1751   }
1752   // We need a temporary register for address generation
1753   alloc_reg_temp(current,i,-1);
1754   minimum_free_regs[i]=1;
1755 }
1756
1757 void c1ls_alloc(struct regstat *current,int i)
1758 {
1759   //clear_const(current,rs1[i]); // FIXME
1760   clear_const(current,rt1[i]);
1761   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1762   alloc_reg(current,i,CSREG); // Status
1763   alloc_reg(current,i,FTEMP);
1764   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1765     alloc_reg64(current,i,FTEMP);
1766   }
1767   // If using TLB, need a register for pointer to the mapping table
1768   if(using_tlb) alloc_reg(current,i,TLREG);
1769   #if defined(HOST_IMM8)
1770   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1771   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1772     alloc_reg(current,i,INVCP);
1773   #endif
1774   // We need a temporary register for address generation
1775   alloc_reg_temp(current,i,-1);
1776 }
1777
1778 void c2ls_alloc(struct regstat *current,int i)
1779 {
1780   clear_const(current,rt1[i]);
1781   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1782   alloc_reg(current,i,FTEMP);
1783   // If using TLB, need a register for pointer to the mapping table
1784   if(using_tlb) alloc_reg(current,i,TLREG);
1785   #if defined(HOST_IMM8)
1786   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1787   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1788     alloc_reg(current,i,INVCP);
1789   #endif
1790   // We need a temporary register for address generation
1791   alloc_reg_temp(current,i,-1);
1792   minimum_free_regs[i]=1;
1793 }
1794
1795 #ifndef multdiv_alloc
1796 void multdiv_alloc(struct regstat *current,int i)
1797 {
1798   //  case 0x18: MULT
1799   //  case 0x19: MULTU
1800   //  case 0x1A: DIV
1801   //  case 0x1B: DIVU
1802   //  case 0x1C: DMULT
1803   //  case 0x1D: DMULTU
1804   //  case 0x1E: DDIV
1805   //  case 0x1F: DDIVU
1806   clear_const(current,rs1[i]);
1807   clear_const(current,rs2[i]);
1808   if(rs1[i]&&rs2[i])
1809   {
1810     if((opcode2[i]&4)==0) // 32-bit
1811     {
1812       current->u&=~(1LL<<HIREG);
1813       current->u&=~(1LL<<LOREG);
1814       alloc_reg(current,i,HIREG);
1815       alloc_reg(current,i,LOREG);
1816       alloc_reg(current,i,rs1[i]);
1817       alloc_reg(current,i,rs2[i]);
1818       current->is32|=1LL<<HIREG;
1819       current->is32|=1LL<<LOREG;
1820       dirty_reg(current,HIREG);
1821       dirty_reg(current,LOREG);
1822     }
1823     else // 64-bit
1824     {
1825       current->u&=~(1LL<<HIREG);
1826       current->u&=~(1LL<<LOREG);
1827       current->uu&=~(1LL<<HIREG);
1828       current->uu&=~(1LL<<LOREG);
1829       alloc_reg64(current,i,HIREG);
1830       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1831       alloc_reg64(current,i,rs1[i]);
1832       alloc_reg64(current,i,rs2[i]);
1833       alloc_all(current,i);
1834       current->is32&=~(1LL<<HIREG);
1835       current->is32&=~(1LL<<LOREG);
1836       dirty_reg(current,HIREG);
1837       dirty_reg(current,LOREG);
1838       minimum_free_regs[i]=HOST_REGS;
1839     }
1840   }
1841   else
1842   {
1843     // Multiply by zero is zero.
1844     // MIPS does not have a divide by zero exception.
1845     // The result is undefined, we return zero.
1846     alloc_reg(current,i,HIREG);
1847     alloc_reg(current,i,LOREG);
1848     current->is32|=1LL<<HIREG;
1849     current->is32|=1LL<<LOREG;
1850     dirty_reg(current,HIREG);
1851     dirty_reg(current,LOREG);
1852   }
1853 }
1854 #endif
1855
1856 void cop0_alloc(struct regstat *current,int i)
1857 {
1858   if(opcode2[i]==0) // MFC0
1859   {
1860     if(rt1[i]) {
1861       clear_const(current,rt1[i]);
1862       alloc_all(current,i);
1863       alloc_reg(current,i,rt1[i]);
1864       current->is32|=1LL<<rt1[i];
1865       dirty_reg(current,rt1[i]);
1866     }
1867   }
1868   else if(opcode2[i]==4) // MTC0
1869   {
1870     if(rs1[i]){
1871       clear_const(current,rs1[i]);
1872       alloc_reg(current,i,rs1[i]);
1873       alloc_all(current,i);
1874     }
1875     else {
1876       alloc_all(current,i); // FIXME: Keep r0
1877       current->u&=~1LL;
1878       alloc_reg(current,i,0);
1879     }
1880   }
1881   else
1882   {
1883     // TLBR/TLBWI/TLBWR/TLBP/ERET
1884     assert(opcode2[i]==0x10);
1885     alloc_all(current,i);
1886   }
1887   minimum_free_regs[i]=HOST_REGS;
1888 }
1889
1890 void cop1_alloc(struct regstat *current,int i)
1891 {
1892   alloc_reg(current,i,CSREG); // Load status
1893   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1894   {
1895     if(rt1[i]){
1896       clear_const(current,rt1[i]);
1897       if(opcode2[i]==1) {
1898         alloc_reg64(current,i,rt1[i]); // DMFC1
1899         current->is32&=~(1LL<<rt1[i]);
1900       }else{
1901         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1902         current->is32|=1LL<<rt1[i];
1903       }
1904       dirty_reg(current,rt1[i]);
1905     }
1906     alloc_reg_temp(current,i,-1);
1907   }
1908   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1909   {
1910     if(rs1[i]){
1911       clear_const(current,rs1[i]);
1912       if(opcode2[i]==5)
1913         alloc_reg64(current,i,rs1[i]); // DMTC1
1914       else
1915         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1916       alloc_reg_temp(current,i,-1);
1917     }
1918     else {
1919       current->u&=~1LL;
1920       alloc_reg(current,i,0);
1921       alloc_reg_temp(current,i,-1);
1922     }
1923   }
1924   minimum_free_regs[i]=1;
1925 }
1926 void fconv_alloc(struct regstat *current,int i)
1927 {
1928   alloc_reg(current,i,CSREG); // Load status
1929   alloc_reg_temp(current,i,-1);
1930   minimum_free_regs[i]=1;
1931 }
1932 void float_alloc(struct regstat *current,int i)
1933 {
1934   alloc_reg(current,i,CSREG); // Load status
1935   alloc_reg_temp(current,i,-1);
1936   minimum_free_regs[i]=1;
1937 }
1938 void c2op_alloc(struct regstat *current,int i)
1939 {
1940   alloc_reg_temp(current,i,-1);
1941 }
1942 void fcomp_alloc(struct regstat *current,int i)
1943 {
1944   alloc_reg(current,i,CSREG); // Load status
1945   alloc_reg(current,i,FSREG); // Load flags
1946   dirty_reg(current,FSREG); // Flag will be modified
1947   alloc_reg_temp(current,i,-1);
1948   minimum_free_regs[i]=1;
1949 }
1950
1951 void syscall_alloc(struct regstat *current,int i)
1952 {
1953   alloc_cc(current,i);
1954   dirty_reg(current,CCREG);
1955   alloc_all(current,i);
1956   minimum_free_regs[i]=HOST_REGS;
1957   current->isconst=0;
1958 }
1959
1960 void delayslot_alloc(struct regstat *current,int i)
1961 {
1962   switch(itype[i]) {
1963     case UJUMP:
1964     case CJUMP:
1965     case SJUMP:
1966     case RJUMP:
1967     case FJUMP:
1968     case SYSCALL:
1969     case HLECALL:
1970     case SPAN:
1971       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1972       printf("Disabled speculative precompilation\n");
1973       stop_after_jal=1;
1974       break;
1975     case IMM16:
1976       imm16_alloc(current,i);
1977       break;
1978     case LOAD:
1979     case LOADLR:
1980       load_alloc(current,i);
1981       break;
1982     case STORE:
1983     case STORELR:
1984       store_alloc(current,i);
1985       break;
1986     case ALU:
1987       alu_alloc(current,i);
1988       break;
1989     case SHIFT:
1990       shift_alloc(current,i);
1991       break;
1992     case MULTDIV:
1993       multdiv_alloc(current,i);
1994       break;
1995     case SHIFTIMM:
1996       shiftimm_alloc(current,i);
1997       break;
1998     case MOV:
1999       mov_alloc(current,i);
2000       break;
2001     case COP0:
2002       cop0_alloc(current,i);
2003       break;
2004     case COP1:
2005     case COP2:
2006       cop1_alloc(current,i);
2007       break;
2008     case C1LS:
2009       c1ls_alloc(current,i);
2010       break;
2011     case C2LS:
2012       c2ls_alloc(current,i);
2013       break;
2014     case FCONV:
2015       fconv_alloc(current,i);
2016       break;
2017     case FLOAT:
2018       float_alloc(current,i);
2019       break;
2020     case FCOMP:
2021       fcomp_alloc(current,i);
2022       break;
2023     case C2OP:
2024       c2op_alloc(current,i);
2025       break;
2026   }
2027 }
2028
2029 // Special case where a branch and delay slot span two pages in virtual memory
2030 static void pagespan_alloc(struct regstat *current,int i)
2031 {
2032   current->isconst=0;
2033   current->wasconst=0;
2034   regs[i].wasconst=0;
2035   minimum_free_regs[i]=HOST_REGS;
2036   alloc_all(current,i);
2037   alloc_cc(current,i);
2038   dirty_reg(current,CCREG);
2039   if(opcode[i]==3) // JAL
2040   {
2041     alloc_reg(current,i,31);
2042     dirty_reg(current,31);
2043   }
2044   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2045   {
2046     alloc_reg(current,i,rs1[i]);
2047     if (rt1[i]!=0) {
2048       alloc_reg(current,i,rt1[i]);
2049       dirty_reg(current,rt1[i]);
2050     }
2051   }
2052   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2053   {
2054     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2055     if(rs2[i]) alloc_reg(current,i,rs2[i]);
2056     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2057     {
2058       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2059       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2060     }
2061   }
2062   else
2063   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2064   {
2065     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2066     if(!((current->is32>>rs1[i])&1))
2067     {
2068       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2069     }
2070   }
2071   else
2072   if(opcode[i]==0x11) // BC1
2073   {
2074     alloc_reg(current,i,FSREG);
2075     alloc_reg(current,i,CSREG);
2076   }
2077   //else ...
2078 }
2079
2080 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2081 {
2082   stubs[stubcount][0]=type;
2083   stubs[stubcount][1]=addr;
2084   stubs[stubcount][2]=retaddr;
2085   stubs[stubcount][3]=a;
2086   stubs[stubcount][4]=b;
2087   stubs[stubcount][5]=c;
2088   stubs[stubcount][6]=d;
2089   stubs[stubcount][7]=e;
2090   stubcount++;
2091 }
2092
2093 // Write out a single register
2094 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2095 {
2096   int hr;
2097   for(hr=0;hr<HOST_REGS;hr++) {
2098     if(hr!=EXCLUDE_REG) {
2099       if((regmap[hr]&63)==r) {
2100         if((dirty>>hr)&1) {
2101           if(regmap[hr]<64) {
2102             emit_storereg(r,hr);
2103 #ifndef FORCE32
2104             if((is32>>regmap[hr])&1) {
2105               emit_sarimm(hr,31,hr);
2106               emit_storereg(r|64,hr);
2107             }
2108 #endif
2109           }else{
2110             emit_storereg(r|64,hr);
2111           }
2112         }
2113       }
2114     }
2115   }
2116 }
2117
2118 int mchecksum()
2119 {
2120   //if(!tracedebug) return 0;
2121   int i;
2122   int sum=0;
2123   for(i=0;i<2097152;i++) {
2124     unsigned int temp=sum;
2125     sum<<=1;
2126     sum|=(~temp)>>31;
2127     sum^=((u_int *)rdram)[i];
2128   }
2129   return sum;
2130 }
2131 int rchecksum()
2132 {
2133   int i;
2134   int sum=0;
2135   for(i=0;i<64;i++)
2136     sum^=((u_int *)reg)[i];
2137   return sum;
2138 }
2139 void rlist()
2140 {
2141   int i;
2142   printf("TRACE: ");
2143   for(i=0;i<32;i++)
2144     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2145   printf("\n");
2146 #ifndef DISABLE_COP1
2147   printf("TRACE: ");
2148   for(i=0;i<32;i++)
2149     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2150   printf("\n");
2151 #endif
2152 }
2153
2154 void enabletrace()
2155 {
2156   tracedebug=1;
2157 }
2158
2159 void memdebug(int i)
2160 {
2161   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2162   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2163   //rlist();
2164   //if(tracedebug) {
2165   //if(Count>=-2084597794) {
2166   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2167   //if(0) {
2168     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2169     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2170     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2171     rlist();
2172     #ifdef __i386__
2173     printf("TRACE: %x\n",(&i)[-1]);
2174     #endif
2175     #ifdef __arm__
2176     int j;
2177     printf("TRACE: %x \n",(&j)[10]);
2178     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2179     #endif
2180     //fflush(stdout);
2181   }
2182   //printf("TRACE: %x\n",(&i)[-1]);
2183 }
2184
2185 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2186 {
2187   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2188 }
2189
2190 void alu_assemble(int i,struct regstat *i_regs)
2191 {
2192   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2193     if(rt1[i]) {
2194       signed char s1,s2,t;
2195       t=get_reg(i_regs->regmap,rt1[i]);
2196       if(t>=0) {
2197         s1=get_reg(i_regs->regmap,rs1[i]);
2198         s2=get_reg(i_regs->regmap,rs2[i]);
2199         if(rs1[i]&&rs2[i]) {
2200           assert(s1>=0);
2201           assert(s2>=0);
2202           if(opcode2[i]&2) emit_sub(s1,s2,t);
2203           else emit_add(s1,s2,t);
2204         }
2205         else if(rs1[i]) {
2206           if(s1>=0) emit_mov(s1,t);
2207           else emit_loadreg(rs1[i],t);
2208         }
2209         else if(rs2[i]) {
2210           if(s2>=0) {
2211             if(opcode2[i]&2) emit_neg(s2,t);
2212             else emit_mov(s2,t);
2213           }
2214           else {
2215             emit_loadreg(rs2[i],t);
2216             if(opcode2[i]&2) emit_neg(t,t);
2217           }
2218         }
2219         else emit_zeroreg(t);
2220       }
2221     }
2222   }
2223   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2224     if(rt1[i]) {
2225       signed char s1l,s2l,s1h,s2h,tl,th;
2226       tl=get_reg(i_regs->regmap,rt1[i]);
2227       th=get_reg(i_regs->regmap,rt1[i]|64);
2228       if(tl>=0) {
2229         s1l=get_reg(i_regs->regmap,rs1[i]);
2230         s2l=get_reg(i_regs->regmap,rs2[i]);
2231         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2232         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2233         if(rs1[i]&&rs2[i]) {
2234           assert(s1l>=0);
2235           assert(s2l>=0);
2236           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2237           else emit_adds(s1l,s2l,tl);
2238           if(th>=0) {
2239             #ifdef INVERTED_CARRY
2240             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2241             #else
2242             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2243             #endif
2244             else emit_add(s1h,s2h,th);
2245           }
2246         }
2247         else if(rs1[i]) {
2248           if(s1l>=0) emit_mov(s1l,tl);
2249           else emit_loadreg(rs1[i],tl);
2250           if(th>=0) {
2251             if(s1h>=0) emit_mov(s1h,th);
2252             else emit_loadreg(rs1[i]|64,th);
2253           }
2254         }
2255         else if(rs2[i]) {
2256           if(s2l>=0) {
2257             if(opcode2[i]&2) emit_negs(s2l,tl);
2258             else emit_mov(s2l,tl);
2259           }
2260           else {
2261             emit_loadreg(rs2[i],tl);
2262             if(opcode2[i]&2) emit_negs(tl,tl);
2263           }
2264           if(th>=0) {
2265             #ifdef INVERTED_CARRY
2266             if(s2h>=0) emit_mov(s2h,th);
2267             else emit_loadreg(rs2[i]|64,th);
2268             if(opcode2[i]&2) {
2269               emit_adcimm(-1,th); // x86 has inverted carry flag
2270               emit_not(th,th);
2271             }
2272             #else
2273             if(opcode2[i]&2) {
2274               if(s2h>=0) emit_rscimm(s2h,0,th);
2275               else {
2276                 emit_loadreg(rs2[i]|64,th);
2277                 emit_rscimm(th,0,th);
2278               }
2279             }else{
2280               if(s2h>=0) emit_mov(s2h,th);
2281               else emit_loadreg(rs2[i]|64,th);
2282             }
2283             #endif
2284           }
2285         }
2286         else {
2287           emit_zeroreg(tl);
2288           if(th>=0) emit_zeroreg(th);
2289         }
2290       }
2291     }
2292   }
2293   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2294     if(rt1[i]) {
2295       signed char s1l,s1h,s2l,s2h,t;
2296       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2297       {
2298         t=get_reg(i_regs->regmap,rt1[i]);
2299         //assert(t>=0);
2300         if(t>=0) {
2301           s1l=get_reg(i_regs->regmap,rs1[i]);
2302           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2303           s2l=get_reg(i_regs->regmap,rs2[i]);
2304           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2305           if(rs2[i]==0) // rx<r0
2306           {
2307             assert(s1h>=0);
2308             if(opcode2[i]==0x2a) // SLT
2309               emit_shrimm(s1h,31,t);
2310             else // SLTU (unsigned can not be less than zero)
2311               emit_zeroreg(t);
2312           }
2313           else if(rs1[i]==0) // r0<rx
2314           {
2315             assert(s2h>=0);
2316             if(opcode2[i]==0x2a) // SLT
2317               emit_set_gz64_32(s2h,s2l,t);
2318             else // SLTU (set if not zero)
2319               emit_set_nz64_32(s2h,s2l,t);
2320           }
2321           else {
2322             assert(s1l>=0);assert(s1h>=0);
2323             assert(s2l>=0);assert(s2h>=0);
2324             if(opcode2[i]==0x2a) // SLT
2325               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2326             else // SLTU
2327               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2328           }
2329         }
2330       } else {
2331         t=get_reg(i_regs->regmap,rt1[i]);
2332         //assert(t>=0);
2333         if(t>=0) {
2334           s1l=get_reg(i_regs->regmap,rs1[i]);
2335           s2l=get_reg(i_regs->regmap,rs2[i]);
2336           if(rs2[i]==0) // rx<r0
2337           {
2338             assert(s1l>=0);
2339             if(opcode2[i]==0x2a) // SLT
2340               emit_shrimm(s1l,31,t);
2341             else // SLTU (unsigned can not be less than zero)
2342               emit_zeroreg(t);
2343           }
2344           else if(rs1[i]==0) // r0<rx
2345           {
2346             assert(s2l>=0);
2347             if(opcode2[i]==0x2a) // SLT
2348               emit_set_gz32(s2l,t);
2349             else // SLTU (set if not zero)
2350               emit_set_nz32(s2l,t);
2351           }
2352           else{
2353             assert(s1l>=0);assert(s2l>=0);
2354             if(opcode2[i]==0x2a) // SLT
2355               emit_set_if_less32(s1l,s2l,t);
2356             else // SLTU
2357               emit_set_if_carry32(s1l,s2l,t);
2358           }
2359         }
2360       }
2361     }
2362   }
2363   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2364     if(rt1[i]) {
2365       signed char s1l,s1h,s2l,s2h,th,tl;
2366       tl=get_reg(i_regs->regmap,rt1[i]);
2367       th=get_reg(i_regs->regmap,rt1[i]|64);
2368       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2369       {
2370         assert(tl>=0);
2371         if(tl>=0) {
2372           s1l=get_reg(i_regs->regmap,rs1[i]);
2373           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2374           s2l=get_reg(i_regs->regmap,rs2[i]);
2375           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2376           if(rs1[i]&&rs2[i]) {
2377             assert(s1l>=0);assert(s1h>=0);
2378             assert(s2l>=0);assert(s2h>=0);
2379             if(opcode2[i]==0x24) { // AND
2380               emit_and(s1l,s2l,tl);
2381               emit_and(s1h,s2h,th);
2382             } else
2383             if(opcode2[i]==0x25) { // OR
2384               emit_or(s1l,s2l,tl);
2385               emit_or(s1h,s2h,th);
2386             } else
2387             if(opcode2[i]==0x26) { // XOR
2388               emit_xor(s1l,s2l,tl);
2389               emit_xor(s1h,s2h,th);
2390             } else
2391             if(opcode2[i]==0x27) { // NOR
2392               emit_or(s1l,s2l,tl);
2393               emit_or(s1h,s2h,th);
2394               emit_not(tl,tl);
2395               emit_not(th,th);
2396             }
2397           }
2398           else
2399           {
2400             if(opcode2[i]==0x24) { // AND
2401               emit_zeroreg(tl);
2402               emit_zeroreg(th);
2403             } else
2404             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2405               if(rs1[i]){
2406                 if(s1l>=0) emit_mov(s1l,tl);
2407                 else emit_loadreg(rs1[i],tl);
2408                 if(s1h>=0) emit_mov(s1h,th);
2409                 else emit_loadreg(rs1[i]|64,th);
2410               }
2411               else
2412               if(rs2[i]){
2413                 if(s2l>=0) emit_mov(s2l,tl);
2414                 else emit_loadreg(rs2[i],tl);
2415                 if(s2h>=0) emit_mov(s2h,th);
2416                 else emit_loadreg(rs2[i]|64,th);
2417               }
2418               else{
2419                 emit_zeroreg(tl);
2420                 emit_zeroreg(th);
2421               }
2422             } else
2423             if(opcode2[i]==0x27) { // NOR
2424               if(rs1[i]){
2425                 if(s1l>=0) emit_not(s1l,tl);
2426                 else{
2427                   emit_loadreg(rs1[i],tl);
2428                   emit_not(tl,tl);
2429                 }
2430                 if(s1h>=0) emit_not(s1h,th);
2431                 else{
2432                   emit_loadreg(rs1[i]|64,th);
2433                   emit_not(th,th);
2434                 }
2435               }
2436               else
2437               if(rs2[i]){
2438                 if(s2l>=0) emit_not(s2l,tl);
2439                 else{
2440                   emit_loadreg(rs2[i],tl);
2441                   emit_not(tl,tl);
2442                 }
2443                 if(s2h>=0) emit_not(s2h,th);
2444                 else{
2445                   emit_loadreg(rs2[i]|64,th);
2446                   emit_not(th,th);
2447                 }
2448               }
2449               else {
2450                 emit_movimm(-1,tl);
2451                 emit_movimm(-1,th);
2452               }
2453             }
2454           }
2455         }
2456       }
2457       else
2458       {
2459         // 32 bit
2460         if(tl>=0) {
2461           s1l=get_reg(i_regs->regmap,rs1[i]);
2462           s2l=get_reg(i_regs->regmap,rs2[i]);
2463           if(rs1[i]&&rs2[i]) {
2464             assert(s1l>=0);
2465             assert(s2l>=0);
2466             if(opcode2[i]==0x24) { // AND
2467               emit_and(s1l,s2l,tl);
2468             } else
2469             if(opcode2[i]==0x25) { // OR
2470               emit_or(s1l,s2l,tl);
2471             } else
2472             if(opcode2[i]==0x26) { // XOR
2473               emit_xor(s1l,s2l,tl);
2474             } else
2475             if(opcode2[i]==0x27) { // NOR
2476               emit_or(s1l,s2l,tl);
2477               emit_not(tl,tl);
2478             }
2479           }
2480           else
2481           {
2482             if(opcode2[i]==0x24) { // AND
2483               emit_zeroreg(tl);
2484             } else
2485             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2486               if(rs1[i]){
2487                 if(s1l>=0) emit_mov(s1l,tl);
2488                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2489               }
2490               else
2491               if(rs2[i]){
2492                 if(s2l>=0) emit_mov(s2l,tl);
2493                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2494               }
2495               else emit_zeroreg(tl);
2496             } else
2497             if(opcode2[i]==0x27) { // NOR
2498               if(rs1[i]){
2499                 if(s1l>=0) emit_not(s1l,tl);
2500                 else {
2501                   emit_loadreg(rs1[i],tl);
2502                   emit_not(tl,tl);
2503                 }
2504               }
2505               else
2506               if(rs2[i]){
2507                 if(s2l>=0) emit_not(s2l,tl);
2508                 else {
2509                   emit_loadreg(rs2[i],tl);
2510                   emit_not(tl,tl);
2511                 }
2512               }
2513               else emit_movimm(-1,tl);
2514             }
2515           }
2516         }
2517       }
2518     }
2519   }
2520 }
2521
2522 void imm16_assemble(int i,struct regstat *i_regs)
2523 {
2524   if (opcode[i]==0x0f) { // LUI
2525     if(rt1[i]) {
2526       signed char t;
2527       t=get_reg(i_regs->regmap,rt1[i]);
2528       //assert(t>=0);
2529       if(t>=0) {
2530         if(!((i_regs->isconst>>t)&1))
2531           emit_movimm(imm[i]<<16,t);
2532       }
2533     }
2534   }
2535   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2536     if(rt1[i]) {
2537       signed char s,t;
2538       t=get_reg(i_regs->regmap,rt1[i]);
2539       s=get_reg(i_regs->regmap,rs1[i]);
2540       if(rs1[i]) {
2541         //assert(t>=0);
2542         //assert(s>=0);
2543         if(t>=0) {
2544           if(!((i_regs->isconst>>t)&1)) {
2545             if(s<0) {
2546               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2547               emit_addimm(t,imm[i],t);
2548             }else{
2549               if(!((i_regs->wasconst>>s)&1))
2550                 emit_addimm(s,imm[i],t);
2551               else
2552                 emit_movimm(constmap[i][s]+imm[i],t);
2553             }
2554           }
2555         }
2556       } else {
2557         if(t>=0) {
2558           if(!((i_regs->isconst>>t)&1))
2559             emit_movimm(imm[i],t);
2560         }
2561       }
2562     }
2563   }
2564   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2565     if(rt1[i]) {
2566       signed char sh,sl,th,tl;
2567       th=get_reg(i_regs->regmap,rt1[i]|64);
2568       tl=get_reg(i_regs->regmap,rt1[i]);
2569       sh=get_reg(i_regs->regmap,rs1[i]|64);
2570       sl=get_reg(i_regs->regmap,rs1[i]);
2571       if(tl>=0) {
2572         if(rs1[i]) {
2573           assert(sh>=0);
2574           assert(sl>=0);
2575           if(th>=0) {
2576             emit_addimm64_32(sh,sl,imm[i],th,tl);
2577           }
2578           else {
2579             emit_addimm(sl,imm[i],tl);
2580           }
2581         } else {
2582           emit_movimm(imm[i],tl);
2583           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2584         }
2585       }
2586     }
2587   }
2588   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2589     if(rt1[i]) {
2590       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2591       signed char sh,sl,t;
2592       t=get_reg(i_regs->regmap,rt1[i]);
2593       sh=get_reg(i_regs->regmap,rs1[i]|64);
2594       sl=get_reg(i_regs->regmap,rs1[i]);
2595       //assert(t>=0);
2596       if(t>=0) {
2597         if(rs1[i]>0) {
2598           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2599           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2600             if(opcode[i]==0x0a) { // SLTI
2601               if(sl<0) {
2602                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2603                 emit_slti32(t,imm[i],t);
2604               }else{
2605                 emit_slti32(sl,imm[i],t);
2606               }
2607             }
2608             else { // SLTIU
2609               if(sl<0) {
2610                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2611                 emit_sltiu32(t,imm[i],t);
2612               }else{
2613                 emit_sltiu32(sl,imm[i],t);
2614               }
2615             }
2616           }else{ // 64-bit
2617             assert(sl>=0);
2618             if(opcode[i]==0x0a) // SLTI
2619               emit_slti64_32(sh,sl,imm[i],t);
2620             else // SLTIU
2621               emit_sltiu64_32(sh,sl,imm[i],t);
2622           }
2623         }else{
2624           // SLTI(U) with r0 is just stupid,
2625           // nonetheless examples can be found
2626           if(opcode[i]==0x0a) // SLTI
2627             if(0<imm[i]) emit_movimm(1,t);
2628             else emit_zeroreg(t);
2629           else // SLTIU
2630           {
2631             if(imm[i]) emit_movimm(1,t);
2632             else emit_zeroreg(t);
2633           }
2634         }
2635       }
2636     }
2637   }
2638   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2639     if(rt1[i]) {
2640       signed char sh,sl,th,tl;
2641       th=get_reg(i_regs->regmap,rt1[i]|64);
2642       tl=get_reg(i_regs->regmap,rt1[i]);
2643       sh=get_reg(i_regs->regmap,rs1[i]|64);
2644       sl=get_reg(i_regs->regmap,rs1[i]);
2645       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2646         if(opcode[i]==0x0c) //ANDI
2647         {
2648           if(rs1[i]) {
2649             if(sl<0) {
2650               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2651               emit_andimm(tl,imm[i],tl);
2652             }else{
2653               if(!((i_regs->wasconst>>sl)&1))
2654                 emit_andimm(sl,imm[i],tl);
2655               else
2656                 emit_movimm(constmap[i][sl]&imm[i],tl);
2657             }
2658           }
2659           else
2660             emit_zeroreg(tl);
2661           if(th>=0) emit_zeroreg(th);
2662         }
2663         else
2664         {
2665           if(rs1[i]) {
2666             if(sl<0) {
2667               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2668             }
2669             if(th>=0) {
2670               if(sh<0) {
2671                 emit_loadreg(rs1[i]|64,th);
2672               }else{
2673                 emit_mov(sh,th);
2674               }
2675             }
2676             if(opcode[i]==0x0d) //ORI
2677             if(sl<0) {
2678               emit_orimm(tl,imm[i],tl);
2679             }else{
2680               if(!((i_regs->wasconst>>sl)&1))
2681                 emit_orimm(sl,imm[i],tl);
2682               else
2683                 emit_movimm(constmap[i][sl]|imm[i],tl);
2684             }
2685             if(opcode[i]==0x0e) //XORI
2686             if(sl<0) {
2687               emit_xorimm(tl,imm[i],tl);
2688             }else{
2689               if(!((i_regs->wasconst>>sl)&1))
2690                 emit_xorimm(sl,imm[i],tl);
2691               else
2692                 emit_movimm(constmap[i][sl]^imm[i],tl);
2693             }
2694           }
2695           else {
2696             emit_movimm(imm[i],tl);
2697             if(th>=0) emit_zeroreg(th);
2698           }
2699         }
2700       }
2701     }
2702   }
2703 }
2704
2705 void shiftimm_assemble(int i,struct regstat *i_regs)
2706 {
2707   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2708   {
2709     if(rt1[i]) {
2710       signed char s,t;
2711       t=get_reg(i_regs->regmap,rt1[i]);
2712       s=get_reg(i_regs->regmap,rs1[i]);
2713       //assert(t>=0);
2714       if(t>=0&&!((i_regs->isconst>>t)&1)){
2715         if(rs1[i]==0)
2716         {
2717           emit_zeroreg(t);
2718         }
2719         else
2720         {
2721           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2722           if(imm[i]) {
2723             if(opcode2[i]==0) // SLL
2724             {
2725               emit_shlimm(s<0?t:s,imm[i],t);
2726             }
2727             if(opcode2[i]==2) // SRL
2728             {
2729               emit_shrimm(s<0?t:s,imm[i],t);
2730             }
2731             if(opcode2[i]==3) // SRA
2732             {
2733               emit_sarimm(s<0?t:s,imm[i],t);
2734             }
2735           }else{
2736             // Shift by zero
2737             if(s>=0 && s!=t) emit_mov(s,t);
2738           }
2739         }
2740       }
2741       //emit_storereg(rt1[i],t); //DEBUG
2742     }
2743   }
2744   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2745   {
2746     if(rt1[i]) {
2747       signed char sh,sl,th,tl;
2748       th=get_reg(i_regs->regmap,rt1[i]|64);
2749       tl=get_reg(i_regs->regmap,rt1[i]);
2750       sh=get_reg(i_regs->regmap,rs1[i]|64);
2751       sl=get_reg(i_regs->regmap,rs1[i]);
2752       if(tl>=0) {
2753         if(rs1[i]==0)
2754         {
2755           emit_zeroreg(tl);
2756           if(th>=0) emit_zeroreg(th);
2757         }
2758         else
2759         {
2760           assert(sl>=0);
2761           assert(sh>=0);
2762           if(imm[i]) {
2763             if(opcode2[i]==0x38) // DSLL
2764             {
2765               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2766               emit_shlimm(sl,imm[i],tl);
2767             }
2768             if(opcode2[i]==0x3a) // DSRL
2769             {
2770               emit_shrdimm(sl,sh,imm[i],tl);
2771               if(th>=0) emit_shrimm(sh,imm[i],th);
2772             }
2773             if(opcode2[i]==0x3b) // DSRA
2774             {
2775               emit_shrdimm(sl,sh,imm[i],tl);
2776               if(th>=0) emit_sarimm(sh,imm[i],th);
2777             }
2778           }else{
2779             // Shift by zero
2780             if(sl!=tl) emit_mov(sl,tl);
2781             if(th>=0&&sh!=th) emit_mov(sh,th);
2782           }
2783         }
2784       }
2785     }
2786   }
2787   if(opcode2[i]==0x3c) // DSLL32
2788   {
2789     if(rt1[i]) {
2790       signed char sl,tl,th;
2791       tl=get_reg(i_regs->regmap,rt1[i]);
2792       th=get_reg(i_regs->regmap,rt1[i]|64);
2793       sl=get_reg(i_regs->regmap,rs1[i]);
2794       if(th>=0||tl>=0){
2795         assert(tl>=0);
2796         assert(th>=0);
2797         assert(sl>=0);
2798         emit_mov(sl,th);
2799         emit_zeroreg(tl);
2800         if(imm[i]>32)
2801         {
2802           emit_shlimm(th,imm[i]&31,th);
2803         }
2804       }
2805     }
2806   }
2807   if(opcode2[i]==0x3e) // DSRL32
2808   {
2809     if(rt1[i]) {
2810       signed char sh,tl,th;
2811       tl=get_reg(i_regs->regmap,rt1[i]);
2812       th=get_reg(i_regs->regmap,rt1[i]|64);
2813       sh=get_reg(i_regs->regmap,rs1[i]|64);
2814       if(tl>=0){
2815         assert(sh>=0);
2816         emit_mov(sh,tl);
2817         if(th>=0) emit_zeroreg(th);
2818         if(imm[i]>32)
2819         {
2820           emit_shrimm(tl,imm[i]&31,tl);
2821         }
2822       }
2823     }
2824   }
2825   if(opcode2[i]==0x3f) // DSRA32
2826   {
2827     if(rt1[i]) {
2828       signed char sh,tl;
2829       tl=get_reg(i_regs->regmap,rt1[i]);
2830       sh=get_reg(i_regs->regmap,rs1[i]|64);
2831       if(tl>=0){
2832         assert(sh>=0);
2833         emit_mov(sh,tl);
2834         if(imm[i]>32)
2835         {
2836           emit_sarimm(tl,imm[i]&31,tl);
2837         }
2838       }
2839     }
2840   }
2841 }
2842
2843 #ifndef shift_assemble
2844 void shift_assemble(int i,struct regstat *i_regs)
2845 {
2846   printf("Need shift_assemble for this architecture.\n");
2847   exit(1);
2848 }
2849 #endif
2850
2851 void load_assemble(int i,struct regstat *i_regs)
2852 {
2853   int s,th,tl,addr,map=-1;
2854   int offset;
2855   int jaddr=0;
2856   int memtarget=0,c=0;
2857   int fastload_reg_override=0;
2858   u_int hr,reglist=0;
2859   th=get_reg(i_regs->regmap,rt1[i]|64);
2860   tl=get_reg(i_regs->regmap,rt1[i]);
2861   s=get_reg(i_regs->regmap,rs1[i]);
2862   offset=imm[i];
2863   for(hr=0;hr<HOST_REGS;hr++) {
2864     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2865   }
2866   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2867   if(s>=0) {
2868     c=(i_regs->wasconst>>s)&1;
2869     if (c) {
2870       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2871       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2872     }
2873   }
2874   //printf("load_assemble: c=%d\n",c);
2875   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2876   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2877 #ifdef PCSX
2878   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2879     ||rt1[i]==0) {
2880       // could be FIFO, must perform the read
2881       // ||dummy read
2882       assem_debug("(forced read)\n");
2883       tl=get_reg(i_regs->regmap,-1);
2884       assert(tl>=0);
2885   }
2886 #endif
2887   if(offset||s<0||c) addr=tl;
2888   else addr=s;
2889   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2890  if(tl>=0) {
2891   //printf("load_assemble: c=%d\n",c);
2892   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2893   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2894   reglist&=~(1<<tl);
2895   if(th>=0) reglist&=~(1<<th);
2896   if(!using_tlb) {
2897     if(!c) {
2898       #ifdef RAM_OFFSET
2899       map=get_reg(i_regs->regmap,ROREG);
2900       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2901       #endif
2902 //#define R29_HACK 1
2903       #ifdef R29_HACK
2904       // Strmnnrmn's speed hack
2905       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2906       #endif
2907       {
2908         jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2909       }
2910     }
2911   }else{ // using tlb
2912     int x=0;
2913     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2914     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2915     map=get_reg(i_regs->regmap,TLREG);
2916     assert(map>=0);
2917     reglist&=~(1<<map);
2918     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2919     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2920   }
2921   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2922   if (opcode[i]==0x20) { // LB
2923     if(!c||memtarget) {
2924       if(!dummy) {
2925         #ifdef HOST_IMM_ADDR32
2926         if(c)
2927           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2928         else
2929         #endif
2930         {
2931           //emit_xorimm(addr,3,tl);
2932           //gen_tlb_addr_r(tl,map);
2933           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2934           int x=0,a=tl;
2935 #ifdef BIG_ENDIAN_MIPS
2936           if(!c) emit_xorimm(addr,3,tl);
2937           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2938 #else
2939           if(!c) a=addr;
2940 #endif
2941           if(fastload_reg_override) a=fastload_reg_override;
2942
2943           emit_movsbl_indexed_tlb(x,a,map,tl);
2944         }
2945       }
2946       if(jaddr)
2947         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2948     }
2949     else
2950       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2951   }
2952   if (opcode[i]==0x21) { // LH
2953     if(!c||memtarget) {
2954       if(!dummy) {
2955         #ifdef HOST_IMM_ADDR32
2956         if(c)
2957           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2958         else
2959         #endif
2960         {
2961           int x=0,a=tl;
2962 #ifdef BIG_ENDIAN_MIPS
2963           if(!c) emit_xorimm(addr,2,tl);
2964           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2965 #else
2966           if(!c) a=addr;
2967 #endif
2968           if(fastload_reg_override) a=fastload_reg_override;
2969           //#ifdef
2970           //emit_movswl_indexed_tlb(x,tl,map,tl);
2971           //else
2972           if(map>=0) {
2973             gen_tlb_addr_r(a,map);
2974             emit_movswl_indexed(x,a,tl);
2975           }else{
2976             #ifdef RAM_OFFSET
2977             emit_movswl_indexed(x,a,tl);
2978             #else
2979             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2980             #endif
2981           }
2982         }
2983       }
2984       if(jaddr)
2985         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2986     }
2987     else
2988       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2989   }
2990   if (opcode[i]==0x23) { // LW
2991     if(!c||memtarget) {
2992       if(!dummy) {
2993         int a=addr;
2994         if(fastload_reg_override) a=fastload_reg_override;
2995         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2996         #ifdef HOST_IMM_ADDR32
2997         if(c)
2998           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2999         else
3000         #endif
3001         emit_readword_indexed_tlb(0,a,map,tl);
3002       }
3003       if(jaddr)
3004         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3005     }
3006     else
3007       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3008   }
3009   if (opcode[i]==0x24) { // LBU
3010     if(!c||memtarget) {
3011       if(!dummy) {
3012         #ifdef HOST_IMM_ADDR32
3013         if(c)
3014           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3015         else
3016         #endif
3017         {
3018           //emit_xorimm(addr,3,tl);
3019           //gen_tlb_addr_r(tl,map);
3020           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3021           int x=0,a=tl;
3022 #ifdef BIG_ENDIAN_MIPS
3023           if(!c) emit_xorimm(addr,3,tl);
3024           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3025 #else
3026           if(!c) a=addr;
3027 #endif
3028           if(fastload_reg_override) a=fastload_reg_override;
3029
3030           emit_movzbl_indexed_tlb(x,a,map,tl);
3031         }
3032       }
3033       if(jaddr)
3034         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3035     }
3036     else
3037       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3038   }
3039   if (opcode[i]==0x25) { // LHU
3040     if(!c||memtarget) {
3041       if(!dummy) {
3042         #ifdef HOST_IMM_ADDR32
3043         if(c)
3044           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3045         else
3046         #endif
3047         {
3048           int x=0,a=tl;
3049 #ifdef BIG_ENDIAN_MIPS
3050           if(!c) emit_xorimm(addr,2,tl);
3051           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3052 #else
3053           if(!c) a=addr;
3054 #endif
3055           if(fastload_reg_override) a=fastload_reg_override;
3056           //#ifdef
3057           //emit_movzwl_indexed_tlb(x,tl,map,tl);
3058           //#else
3059           if(map>=0) {
3060             gen_tlb_addr_r(a,map);
3061             emit_movzwl_indexed(x,a,tl);
3062           }else{
3063             #ifdef RAM_OFFSET
3064             emit_movzwl_indexed(x,a,tl);
3065             #else
3066             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3067             #endif
3068           }
3069         }
3070       }
3071       if(jaddr)
3072         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3073     }
3074     else
3075       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3076   }
3077   if (opcode[i]==0x27) { // LWU
3078     assert(th>=0);
3079     if(!c||memtarget) {
3080       if(!dummy) {
3081         int a=addr;
3082         if(fastload_reg_override) a=fastload_reg_override;
3083         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3084         #ifdef HOST_IMM_ADDR32
3085         if(c)
3086           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3087         else
3088         #endif
3089         emit_readword_indexed_tlb(0,a,map,tl);
3090       }
3091       if(jaddr)
3092         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3093     }
3094     else {
3095       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3096     }
3097     emit_zeroreg(th);
3098   }
3099   if (opcode[i]==0x37) { // LD
3100     if(!c||memtarget) {
3101       if(!dummy) {
3102         int a=addr;
3103         if(fastload_reg_override) a=fastload_reg_override;
3104         //gen_tlb_addr_r(tl,map);
3105         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3106         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3107         #ifdef HOST_IMM_ADDR32
3108         if(c)
3109           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3110         else
3111         #endif
3112         emit_readdword_indexed_tlb(0,a,map,th,tl);
3113       }
3114       if(jaddr)
3115         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3116     }
3117     else
3118       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3119   }
3120  }
3121   //emit_storereg(rt1[i],tl); // DEBUG
3122   //if(opcode[i]==0x23)
3123   //if(opcode[i]==0x24)
3124   //if(opcode[i]==0x23||opcode[i]==0x24)
3125   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3126   {
3127     //emit_pusha();
3128     save_regs(0x100f);
3129         emit_readword((int)&last_count,ECX);
3130         #ifdef __i386__
3131         if(get_reg(i_regs->regmap,CCREG)<0)
3132           emit_loadreg(CCREG,HOST_CCREG);
3133         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3134         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3135         emit_writeword(HOST_CCREG,(int)&Count);
3136         #endif
3137         #ifdef __arm__
3138         if(get_reg(i_regs->regmap,CCREG)<0)
3139           emit_loadreg(CCREG,0);
3140         else
3141           emit_mov(HOST_CCREG,0);
3142         emit_add(0,ECX,0);
3143         emit_addimm(0,2*ccadj[i],0);
3144         emit_writeword(0,(int)&Count);
3145         #endif
3146     emit_call((int)memdebug);
3147     //emit_popa();
3148     restore_regs(0x100f);
3149   }/**/
3150 }
3151
3152 #ifndef loadlr_assemble
3153 void loadlr_assemble(int i,struct regstat *i_regs)
3154 {
3155   printf("Need loadlr_assemble for this architecture.\n");
3156   exit(1);
3157 }
3158 #endif
3159
3160 void store_assemble(int i,struct regstat *i_regs)
3161 {
3162   int s,th,tl,map=-1;
3163   int addr,temp;
3164   int offset;
3165   int jaddr=0,jaddr2,type;
3166   int memtarget=0,c=0;
3167   int agr=AGEN1+(i&1);
3168   int faststore_reg_override=0;
3169   u_int hr,reglist=0;
3170   th=get_reg(i_regs->regmap,rs2[i]|64);
3171   tl=get_reg(i_regs->regmap,rs2[i]);
3172   s=get_reg(i_regs->regmap,rs1[i]);
3173   temp=get_reg(i_regs->regmap,agr);
3174   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3175   offset=imm[i];
3176   if(s>=0) {
3177     c=(i_regs->wasconst>>s)&1;
3178     if(c) {
3179       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3180       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3181     }
3182   }
3183   assert(tl>=0);
3184   assert(temp>=0);
3185   for(hr=0;hr<HOST_REGS;hr++) {
3186     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3187   }
3188   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3189   if(offset||s<0||c) addr=temp;
3190   else addr=s;
3191   if(!using_tlb) {
3192     if(!c) {
3193       #ifndef PCSX
3194       #ifdef R29_HACK
3195       // Strmnnrmn's speed hack
3196       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3197       #endif
3198       emit_cmpimm(addr,RAM_SIZE);
3199       #ifdef DESTRUCTIVE_SHIFT
3200       if(s==addr) emit_mov(s,temp);
3201       #endif
3202       #ifdef R29_HACK
3203       memtarget=1;
3204       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3205       #endif
3206       {
3207         jaddr=(int)out;
3208         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3209         // Hint to branch predictor that the branch is unlikely to be taken
3210         if(rs1[i]>=28)
3211           emit_jno_unlikely(0);
3212         else
3213         #endif
3214         emit_jno(0);
3215       }
3216       #else
3217         jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3218       #endif
3219     }
3220   }else{ // using tlb
3221     int x=0;
3222     if (opcode[i]==0x28) x=3; // SB
3223     if (opcode[i]==0x29) x=2; // SH
3224     map=get_reg(i_regs->regmap,TLREG);
3225     assert(map>=0);
3226     reglist&=~(1<<map);
3227     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3228     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3229   }
3230
3231   if (opcode[i]==0x28) { // SB
3232     if(!c||memtarget) {
3233       int x=0,a=temp;
3234 #ifdef BIG_ENDIAN_MIPS
3235       if(!c) emit_xorimm(addr,3,temp);
3236       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3237 #else
3238       if(!c) a=addr;
3239 #endif
3240       if(faststore_reg_override) a=faststore_reg_override;
3241       //gen_tlb_addr_w(temp,map);
3242       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3243       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3244     }
3245     type=STOREB_STUB;
3246   }
3247   if (opcode[i]==0x29) { // SH
3248     if(!c||memtarget) {
3249       int x=0,a=temp;
3250 #ifdef BIG_ENDIAN_MIPS
3251       if(!c) emit_xorimm(addr,2,temp);
3252       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3253 #else
3254       if(!c) a=addr;
3255 #endif
3256       if(faststore_reg_override) a=faststore_reg_override;
3257       //#ifdef
3258       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3259       //#else
3260       if(map>=0) {
3261         gen_tlb_addr_w(a,map);
3262         emit_writehword_indexed(tl,x,a);
3263       }else
3264         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3265     }
3266     type=STOREH_STUB;
3267   }
3268   if (opcode[i]==0x2B) { // SW
3269     if(!c||memtarget) {
3270       int a=addr;
3271       if(faststore_reg_override) a=faststore_reg_override;
3272       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3273       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3274     }
3275     type=STOREW_STUB;
3276   }
3277   if (opcode[i]==0x3F) { // SD
3278     if(!c||memtarget) {
3279       int a=addr;
3280       if(faststore_reg_override) a=faststore_reg_override;
3281       if(rs2[i]) {
3282         assert(th>=0);
3283         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3284         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3285         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3286       }else{
3287         // Store zero
3288         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3289         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3290         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3291       }
3292     }
3293     type=STORED_STUB;
3294   }
3295 #ifdef PCSX
3296   if(jaddr) {
3297     // PCSX store handlers don't check invcode again
3298     reglist|=1<<addr;
3299     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3300     jaddr=0;
3301   }
3302 #endif
3303   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))) {
3304     if(!c||memtarget) {
3305       #ifdef DESTRUCTIVE_SHIFT
3306       // The x86 shift operation is 'destructive'; it overwrites the
3307       // source register, so we need to make a copy first and use that.
3308       addr=temp;
3309       #endif
3310       #if defined(HOST_IMM8)
3311       int ir=get_reg(i_regs->regmap,INVCP);
3312       assert(ir>=0);
3313       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3314       #else
3315       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3316       #endif
3317       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3318       emit_callne(invalidate_addr_reg[addr]);
3319       #else
3320       jaddr2=(int)out;
3321       emit_jne(0);
3322       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3323       #endif
3324     }
3325   }
3326   if(jaddr) {
3327     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3328   } else if(c&&!memtarget) {
3329     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3330   }
3331   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3332   //if(opcode[i]==0x2B || opcode[i]==0x28)
3333   //if(opcode[i]==0x2B || opcode[i]==0x29)
3334   //if(opcode[i]==0x2B)
3335   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3336   {
3337     #ifdef __i386__
3338     emit_pusha();
3339     #endif
3340     #ifdef __arm__
3341     save_regs(0x100f);
3342     #endif
3343         emit_readword((int)&last_count,ECX);
3344         #ifdef __i386__
3345         if(get_reg(i_regs->regmap,CCREG)<0)
3346           emit_loadreg(CCREG,HOST_CCREG);
3347         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3348         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3349         emit_writeword(HOST_CCREG,(int)&Count);
3350         #endif
3351         #ifdef __arm__
3352         if(get_reg(i_regs->regmap,CCREG)<0)
3353           emit_loadreg(CCREG,0);
3354         else
3355           emit_mov(HOST_CCREG,0);
3356         emit_add(0,ECX,0);
3357         emit_addimm(0,2*ccadj[i],0);
3358         emit_writeword(0,(int)&Count);
3359         #endif
3360     emit_call((int)memdebug);
3361     #ifdef __i386__
3362     emit_popa();
3363     #endif
3364     #ifdef __arm__
3365     restore_regs(0x100f);
3366     #endif
3367   }/**/
3368 }
3369
3370 void storelr_assemble(int i,struct regstat *i_regs)
3371 {
3372   int s,th,tl;
3373   int temp;
3374   int temp2;
3375   int offset;
3376   int jaddr=0,jaddr2;
3377   int case1,case2,case3;
3378   int done0,done1,done2;
3379   int memtarget=0,c=0;
3380   int agr=AGEN1+(i&1);
3381   u_int hr,reglist=0;
3382   th=get_reg(i_regs->regmap,rs2[i]|64);
3383   tl=get_reg(i_regs->regmap,rs2[i]);
3384   s=get_reg(i_regs->regmap,rs1[i]);
3385   temp=get_reg(i_regs->regmap,agr);
3386   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3387   offset=imm[i];
3388   if(s>=0) {
3389     c=(i_regs->isconst>>s)&1;
3390     if(c) {
3391       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3392       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3393     }
3394   }
3395   assert(tl>=0);
3396   for(hr=0;hr<HOST_REGS;hr++) {
3397     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3398   }
3399   assert(temp>=0);
3400   if(!using_tlb) {
3401     if(!c) {
3402       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3403       if(!offset&&s!=temp) emit_mov(s,temp);
3404       jaddr=(int)out;
3405       emit_jno(0);
3406     }
3407     else
3408     {
3409       if(!memtarget||!rs1[i]) {
3410         jaddr=(int)out;
3411         emit_jmp(0);
3412       }
3413     }
3414     #ifdef RAM_OFFSET
3415     int map=get_reg(i_regs->regmap,ROREG);
3416     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3417     gen_tlb_addr_w(temp,map);
3418     #else
3419     if((u_int)rdram!=0x80000000)
3420       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3421     #endif
3422   }else{ // using tlb
3423     int map=get_reg(i_regs->regmap,TLREG);
3424     assert(map>=0);
3425     reglist&=~(1<<map);
3426     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3427     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3428     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3429     if(!jaddr&&!memtarget) {
3430       jaddr=(int)out;
3431       emit_jmp(0);
3432     }
3433     gen_tlb_addr_w(temp,map);
3434   }
3435
3436   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3437     temp2=get_reg(i_regs->regmap,FTEMP);
3438     if(!rs2[i]) temp2=th=tl;
3439   }
3440
3441 #ifndef BIG_ENDIAN_MIPS
3442     emit_xorimm(temp,3,temp);
3443 #endif
3444   emit_testimm(temp,2);
3445   case2=(int)out;
3446   emit_jne(0);
3447   emit_testimm(temp,1);
3448   case1=(int)out;
3449   emit_jne(0);
3450   // 0
3451   if (opcode[i]==0x2A) { // SWL
3452     emit_writeword_indexed(tl,0,temp);
3453   }
3454   if (opcode[i]==0x2E) { // SWR
3455     emit_writebyte_indexed(tl,3,temp);
3456   }
3457   if (opcode[i]==0x2C) { // SDL
3458     emit_writeword_indexed(th,0,temp);
3459     if(rs2[i]) emit_mov(tl,temp2);
3460   }
3461   if (opcode[i]==0x2D) { // SDR
3462     emit_writebyte_indexed(tl,3,temp);
3463     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3464   }
3465   done0=(int)out;
3466   emit_jmp(0);
3467   // 1
3468   set_jump_target(case1,(int)out);
3469   if (opcode[i]==0x2A) { // SWL
3470     // Write 3 msb into three least significant bytes
3471     if(rs2[i]) emit_rorimm(tl,8,tl);
3472     emit_writehword_indexed(tl,-1,temp);
3473     if(rs2[i]) emit_rorimm(tl,16,tl);
3474     emit_writebyte_indexed(tl,1,temp);
3475     if(rs2[i]) emit_rorimm(tl,8,tl);
3476   }
3477   if (opcode[i]==0x2E) { // SWR
3478     // Write two lsb into two most significant bytes
3479     emit_writehword_indexed(tl,1,temp);
3480   }
3481   if (opcode[i]==0x2C) { // SDL
3482     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3483     // Write 3 msb into three least significant bytes
3484     if(rs2[i]) emit_rorimm(th,8,th);
3485     emit_writehword_indexed(th,-1,temp);
3486     if(rs2[i]) emit_rorimm(th,16,th);
3487     emit_writebyte_indexed(th,1,temp);
3488     if(rs2[i]) emit_rorimm(th,8,th);
3489   }
3490   if (opcode[i]==0x2D) { // SDR
3491     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3492     // Write two lsb into two most significant bytes
3493     emit_writehword_indexed(tl,1,temp);
3494   }
3495   done1=(int)out;
3496   emit_jmp(0);
3497   // 2
3498   set_jump_target(case2,(int)out);
3499   emit_testimm(temp,1);
3500   case3=(int)out;
3501   emit_jne(0);
3502   if (opcode[i]==0x2A) { // SWL
3503     // Write two msb into two least significant bytes
3504     if(rs2[i]) emit_rorimm(tl,16,tl);
3505     emit_writehword_indexed(tl,-2,temp);
3506     if(rs2[i]) emit_rorimm(tl,16,tl);
3507   }
3508   if (opcode[i]==0x2E) { // SWR
3509     // Write 3 lsb into three most significant bytes
3510     emit_writebyte_indexed(tl,-1,temp);
3511     if(rs2[i]) emit_rorimm(tl,8,tl);
3512     emit_writehword_indexed(tl,0,temp);
3513     if(rs2[i]) emit_rorimm(tl,24,tl);
3514   }
3515   if (opcode[i]==0x2C) { // SDL
3516     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3517     // Write two msb into two least significant bytes
3518     if(rs2[i]) emit_rorimm(th,16,th);
3519     emit_writehword_indexed(th,-2,temp);
3520     if(rs2[i]) emit_rorimm(th,16,th);
3521   }
3522   if (opcode[i]==0x2D) { // SDR
3523     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3524     // Write 3 lsb into three most significant bytes
3525     emit_writebyte_indexed(tl,-1,temp);
3526     if(rs2[i]) emit_rorimm(tl,8,tl);
3527     emit_writehword_indexed(tl,0,temp);
3528     if(rs2[i]) emit_rorimm(tl,24,tl);
3529   }
3530   done2=(int)out;
3531   emit_jmp(0);
3532   // 3
3533   set_jump_target(case3,(int)out);
3534   if (opcode[i]==0x2A) { // SWL
3535     // Write msb into least significant byte
3536     if(rs2[i]) emit_rorimm(tl,24,tl);
3537     emit_writebyte_indexed(tl,-3,temp);
3538     if(rs2[i]) emit_rorimm(tl,8,tl);
3539   }
3540   if (opcode[i]==0x2E) { // SWR
3541     // Write entire word
3542     emit_writeword_indexed(tl,-3,temp);
3543   }
3544   if (opcode[i]==0x2C) { // SDL
3545     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3546     // Write msb into least significant byte
3547     if(rs2[i]) emit_rorimm(th,24,th);
3548     emit_writebyte_indexed(th,-3,temp);
3549     if(rs2[i]) emit_rorimm(th,8,th);
3550   }
3551   if (opcode[i]==0x2D) { // SDR
3552     if(rs2[i]) emit_mov(th,temp2);
3553     // Write entire word
3554     emit_writeword_indexed(tl,-3,temp);
3555   }
3556   set_jump_target(done0,(int)out);
3557   set_jump_target(done1,(int)out);
3558   set_jump_target(done2,(int)out);
3559   if (opcode[i]==0x2C) { // SDL
3560     emit_testimm(temp,4);
3561     done0=(int)out;
3562     emit_jne(0);
3563     emit_andimm(temp,~3,temp);
3564     emit_writeword_indexed(temp2,4,temp);
3565     set_jump_target(done0,(int)out);
3566   }
3567   if (opcode[i]==0x2D) { // SDR
3568     emit_testimm(temp,4);
3569     done0=(int)out;
3570     emit_jeq(0);
3571     emit_andimm(temp,~3,temp);
3572     emit_writeword_indexed(temp2,-4,temp);
3573     set_jump_target(done0,(int)out);
3574   }
3575   if(!c||!memtarget)
3576     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3577   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))) {
3578     #ifdef RAM_OFFSET
3579     int map=get_reg(i_regs->regmap,ROREG);
3580     if(map<0) map=HOST_TEMPREG;
3581     gen_orig_addr_w(temp,map);
3582     #else
3583     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3584     #endif
3585     #if defined(HOST_IMM8)
3586     int ir=get_reg(i_regs->regmap,INVCP);
3587     assert(ir>=0);
3588     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3589     #else
3590     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3591     #endif
3592     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3593     emit_callne(invalidate_addr_reg[temp]);
3594     #else
3595     jaddr2=(int)out;
3596     emit_jne(0);
3597     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3598     #endif
3599   }
3600   /*
3601     emit_pusha();
3602     //save_regs(0x100f);
3603         emit_readword((int)&last_count,ECX);
3604         if(get_reg(i_regs->regmap,CCREG)<0)
3605           emit_loadreg(CCREG,HOST_CCREG);
3606         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3607         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3608         emit_writeword(HOST_CCREG,(int)&Count);
3609     emit_call((int)memdebug);
3610     emit_popa();
3611     //restore_regs(0x100f);
3612   /**/
3613 }
3614
3615 void c1ls_assemble(int i,struct regstat *i_regs)
3616 {
3617 #ifndef DISABLE_COP1
3618   int s,th,tl;
3619   int temp,ar;
3620   int map=-1;
3621   int offset;
3622   int c=0;
3623   int jaddr,jaddr2=0,jaddr3,type;
3624   int agr=AGEN1+(i&1);
3625   u_int hr,reglist=0;
3626   th=get_reg(i_regs->regmap,FTEMP|64);
3627   tl=get_reg(i_regs->regmap,FTEMP);
3628   s=get_reg(i_regs->regmap,rs1[i]);
3629   temp=get_reg(i_regs->regmap,agr);
3630   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3631   offset=imm[i];
3632   assert(tl>=0);
3633   assert(rs1[i]>0);
3634   assert(temp>=0);
3635   for(hr=0;hr<HOST_REGS;hr++) {
3636     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3637   }
3638   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3639   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3640   {
3641     // Loads use a temporary register which we need to save
3642     reglist|=1<<temp;
3643   }
3644   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3645     ar=temp;
3646   else // LWC1/LDC1
3647     ar=tl;
3648   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3649   //else c=(i_regs->wasconst>>s)&1;
3650   if(s>=0) c=(i_regs->wasconst>>s)&1;
3651   // Check cop1 unusable
3652   if(!cop1_usable) {
3653     signed char rs=get_reg(i_regs->regmap,CSREG);
3654     assert(rs>=0);
3655     emit_testimm(rs,0x20000000);
3656     jaddr=(int)out;
3657     emit_jeq(0);
3658     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3659     cop1_usable=1;
3660   }
3661   if (opcode[i]==0x39) { // SWC1 (get float address)
3662     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3663   }
3664   if (opcode[i]==0x3D) { // SDC1 (get double address)
3665     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3666   }
3667   // Generate address + offset
3668   if(!using_tlb) {
3669     if(!c)
3670       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3671   }
3672   else
3673   {
3674     map=get_reg(i_regs->regmap,TLREG);
3675     assert(map>=0);
3676     reglist&=~(1<<map);
3677     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3678       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3679     }
3680     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3681       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3682     }
3683   }
3684   if (opcode[i]==0x39) { // SWC1 (read float)
3685     emit_readword_indexed(0,tl,tl);
3686   }
3687   if (opcode[i]==0x3D) { // SDC1 (read double)
3688     emit_readword_indexed(4,tl,th);
3689     emit_readword_indexed(0,tl,tl);
3690   }
3691   if (opcode[i]==0x31) { // LWC1 (get target address)
3692     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3693   }
3694   if (opcode[i]==0x35) { // LDC1 (get target address)
3695     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3696   }
3697   if(!using_tlb) {
3698     if(!c) {
3699       jaddr2=(int)out;
3700       emit_jno(0);
3701     }
3702     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3703       jaddr2=(int)out;
3704       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3705     }
3706     #ifdef DESTRUCTIVE_SHIFT
3707     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3708       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3709     }
3710     #endif
3711   }else{
3712     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3713       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3714     }
3715     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3716       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3717     }
3718   }
3719   if (opcode[i]==0x31) { // LWC1
3720     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3721     //gen_tlb_addr_r(ar,map);
3722     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3723     #ifdef HOST_IMM_ADDR32
3724     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3725     else
3726     #endif
3727     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3728     type=LOADW_STUB;
3729   }
3730   if (opcode[i]==0x35) { // LDC1
3731     assert(th>=0);
3732     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3733     //gen_tlb_addr_r(ar,map);
3734     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3735     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3736     #ifdef HOST_IMM_ADDR32
3737     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3738     else
3739     #endif
3740     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3741     type=LOADD_STUB;
3742   }
3743   if (opcode[i]==0x39) { // SWC1
3744     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3745     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3746     type=STOREW_STUB;
3747   }
3748   if (opcode[i]==0x3D) { // SDC1
3749     assert(th>=0);
3750     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3751     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3752     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3753     type=STORED_STUB;
3754   }
3755   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))) {
3756     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3757       #ifndef DESTRUCTIVE_SHIFT
3758       temp=offset||c||s<0?ar:s;
3759       #endif
3760       #if defined(HOST_IMM8)
3761       int ir=get_reg(i_regs->regmap,INVCP);
3762       assert(ir>=0);
3763       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3764       #else
3765       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3766       #endif
3767       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3768       emit_callne(invalidate_addr_reg[temp]);
3769       #else
3770       jaddr3=(int)out;
3771       emit_jne(0);
3772       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3773       #endif
3774     }
3775   }
3776   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3777   if (opcode[i]==0x31) { // LWC1 (write float)
3778     emit_writeword_indexed(tl,0,temp);
3779   }
3780   if (opcode[i]==0x35) { // LDC1 (write double)
3781     emit_writeword_indexed(th,4,temp);
3782     emit_writeword_indexed(tl,0,temp);
3783   }
3784   //if(opcode[i]==0x39)
3785   /*if(opcode[i]==0x39||opcode[i]==0x31)
3786   {
3787     emit_pusha();
3788         emit_readword((int)&last_count,ECX);
3789         if(get_reg(i_regs->regmap,CCREG)<0)
3790           emit_loadreg(CCREG,HOST_CCREG);
3791         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3792         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3793         emit_writeword(HOST_CCREG,(int)&Count);
3794     emit_call((int)memdebug);
3795     emit_popa();
3796   }/**/
3797 #else
3798   cop1_unusable(i, i_regs);
3799 #endif
3800 }
3801
3802 void c2ls_assemble(int i,struct regstat *i_regs)
3803 {
3804   int s,tl;
3805   int ar;
3806   int offset;
3807   int memtarget=0,c=0;
3808   int jaddr2=0,jaddr3,type;
3809   int agr=AGEN1+(i&1);
3810   int fastio_reg_override=0;
3811   u_int hr,reglist=0;
3812   u_int copr=(source[i]>>16)&0x1f;
3813   s=get_reg(i_regs->regmap,rs1[i]);
3814   tl=get_reg(i_regs->regmap,FTEMP);
3815   offset=imm[i];
3816   assert(rs1[i]>0);
3817   assert(tl>=0);
3818   assert(!using_tlb);
3819
3820   for(hr=0;hr<HOST_REGS;hr++) {
3821     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3822   }
3823   if(i_regs->regmap[HOST_CCREG]==CCREG)
3824     reglist&=~(1<<HOST_CCREG);
3825
3826   // get the address
3827   if (opcode[i]==0x3a) { // SWC2
3828     ar=get_reg(i_regs->regmap,agr);
3829     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3830     reglist|=1<<ar;
3831   } else { // LWC2
3832     ar=tl;
3833   }
3834   if(s>=0) c=(i_regs->wasconst>>s)&1;
3835   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3836   if (!offset&&!c&&s>=0) ar=s;
3837   assert(ar>=0);
3838
3839   if (opcode[i]==0x3a) { // SWC2
3840     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3841     type=STOREW_STUB;
3842   }
3843   else
3844     type=LOADW_STUB;
3845
3846   if(c&&!memtarget) {
3847     jaddr2=(int)out;
3848     emit_jmp(0); // inline_readstub/inline_writestub?
3849   }
3850   else {
3851     if(!c) {
3852       jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3853     }
3854     if (opcode[i]==0x32) { // LWC2
3855       #ifdef HOST_IMM_ADDR32
3856       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3857       else
3858       #endif
3859       int a=ar;
3860       if(fastio_reg_override) a=fastio_reg_override;
3861       emit_readword_indexed(0,a,tl);
3862     }
3863     if (opcode[i]==0x3a) { // SWC2
3864       #ifdef DESTRUCTIVE_SHIFT
3865       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3866       #endif
3867       int a=ar;
3868       if(fastio_reg_override) a=fastio_reg_override;
3869       emit_writeword_indexed(tl,0,a);
3870     }
3871   }
3872   if(jaddr2)
3873     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3874   if (!(i_regs->waswritten&(1<<rs1[i]))&&opcode[i]==0x3a) { // SWC2
3875 #if defined(HOST_IMM8)
3876     int ir=get_reg(i_regs->regmap,INVCP);
3877     assert(ir>=0);
3878     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3879 #else
3880     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3881 #endif
3882     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3883     emit_callne(invalidate_addr_reg[ar]);
3884     #else
3885     jaddr3=(int)out;
3886     emit_jne(0);
3887     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3888     #endif
3889   }
3890   if (opcode[i]==0x32) { // LWC2
3891     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3892   }
3893 }
3894
3895 #ifndef multdiv_assemble
3896 void multdiv_assemble(int i,struct regstat *i_regs)
3897 {
3898   printf("Need multdiv_assemble for this architecture.\n");
3899   exit(1);
3900 }
3901 #endif
3902
3903 void mov_assemble(int i,struct regstat *i_regs)
3904 {
3905   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3906   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3907   if(rt1[i]) {
3908     signed char sh,sl,th,tl;
3909     th=get_reg(i_regs->regmap,rt1[i]|64);
3910     tl=get_reg(i_regs->regmap,rt1[i]);
3911     //assert(tl>=0);
3912     if(tl>=0) {
3913       sh=get_reg(i_regs->regmap,rs1[i]|64);
3914       sl=get_reg(i_regs->regmap,rs1[i]);
3915       if(sl>=0) emit_mov(sl,tl);
3916       else emit_loadreg(rs1[i],tl);
3917       if(th>=0) {
3918         if(sh>=0) emit_mov(sh,th);
3919         else emit_loadreg(rs1[i]|64,th);
3920       }
3921     }
3922   }
3923 }
3924
3925 #ifndef fconv_assemble
3926 void fconv_assemble(int i,struct regstat *i_regs)
3927 {
3928   printf("Need fconv_assemble for this architecture.\n");
3929   exit(1);
3930 }
3931 #endif
3932
3933 #if 0
3934 void float_assemble(int i,struct regstat *i_regs)
3935 {
3936   printf("Need float_assemble for this architecture.\n");
3937   exit(1);
3938 }
3939 #endif
3940
3941 void syscall_assemble(int i,struct regstat *i_regs)
3942 {
3943   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3944   assert(ccreg==HOST_CCREG);
3945   assert(!is_delayslot);
3946   emit_movimm(start+i*4,EAX); // Get PC
3947   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3948   emit_jmp((int)jump_syscall_hle); // XXX
3949 }
3950
3951 void hlecall_assemble(int i,struct regstat *i_regs)
3952 {
3953   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3954   assert(ccreg==HOST_CCREG);
3955   assert(!is_delayslot);
3956   emit_movimm(start+i*4+4,0); // Get PC
3957   emit_movimm((int)psxHLEt[source[i]&7],1);
3958   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3959   emit_jmp((int)jump_hlecall);
3960 }
3961
3962 void intcall_assemble(int i,struct regstat *i_regs)
3963 {
3964   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3965   assert(ccreg==HOST_CCREG);
3966   assert(!is_delayslot);
3967   emit_movimm(start+i*4,0); // Get PC
3968   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3969   emit_jmp((int)jump_intcall);
3970 }
3971
3972 void ds_assemble(int i,struct regstat *i_regs)
3973 {
3974   speculate_register_values(i);
3975   is_delayslot=1;
3976   switch(itype[i]) {
3977     case ALU:
3978       alu_assemble(i,i_regs);break;
3979     case IMM16:
3980       imm16_assemble(i,i_regs);break;
3981     case SHIFT:
3982       shift_assemble(i,i_regs);break;
3983     case SHIFTIMM:
3984       shiftimm_assemble(i,i_regs);break;
3985     case LOAD:
3986       load_assemble(i,i_regs);break;
3987     case LOADLR:
3988       loadlr_assemble(i,i_regs);break;
3989     case STORE:
3990       store_assemble(i,i_regs);break;
3991     case STORELR:
3992       storelr_assemble(i,i_regs);break;
3993     case COP0:
3994       cop0_assemble(i,i_regs);break;
3995     case COP1:
3996       cop1_assemble(i,i_regs);break;
3997     case C1LS:
3998       c1ls_assemble(i,i_regs);break;
3999     case COP2:
4000       cop2_assemble(i,i_regs);break;
4001     case C2LS:
4002       c2ls_assemble(i,i_regs);break;
4003     case C2OP:
4004       c2op_assemble(i,i_regs);break;
4005     case FCONV:
4006       fconv_assemble(i,i_regs);break;
4007     case FLOAT:
4008       float_assemble(i,i_regs);break;
4009     case FCOMP:
4010       fcomp_assemble(i,i_regs);break;
4011     case MULTDIV:
4012       multdiv_assemble(i,i_regs);break;
4013     case MOV:
4014       mov_assemble(i,i_regs);break;
4015     case SYSCALL:
4016     case HLECALL:
4017     case INTCALL:
4018     case SPAN:
4019     case UJUMP:
4020     case RJUMP:
4021     case CJUMP:
4022     case SJUMP:
4023     case FJUMP:
4024       printf("Jump in the delay slot.  This is probably a bug.\n");
4025   }
4026   is_delayslot=0;
4027 }
4028
4029 // Is the branch target a valid internal jump?
4030 int internal_branch(uint64_t i_is32,int addr)
4031 {
4032   if(addr&1) return 0; // Indirect (register) jump
4033   if(addr>=start && addr<start+slen*4-4)
4034   {
4035     int t=(addr-start)>>2;
4036     // Delay slots are not valid branch targets
4037     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4038     // 64 -> 32 bit transition requires a recompile
4039     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4040     {
4041       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4042       else printf("optimizable: yes\n");
4043     }*/
4044     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4045 #ifndef FORCE32
4046     if(requires_32bit[t]&~i_is32) return 0;
4047     else
4048 #endif
4049       return 1;
4050   }
4051   return 0;
4052 }
4053
4054 #ifndef wb_invalidate
4055 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4056   uint64_t u,uint64_t uu)
4057 {
4058   int hr;
4059   for(hr=0;hr<HOST_REGS;hr++) {
4060     if(hr!=EXCLUDE_REG) {
4061       if(pre[hr]!=entry[hr]) {
4062         if(pre[hr]>=0) {
4063           if((dirty>>hr)&1) {
4064             if(get_reg(entry,pre[hr])<0) {
4065               if(pre[hr]<64) {
4066                 if(!((u>>pre[hr])&1)) {
4067                   emit_storereg(pre[hr],hr);
4068                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4069                     emit_sarimm(hr,31,hr);
4070                     emit_storereg(pre[hr]|64,hr);
4071                   }
4072                 }
4073               }else{
4074                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4075                   emit_storereg(pre[hr],hr);
4076                 }
4077               }
4078             }
4079           }
4080         }
4081       }
4082     }
4083   }
4084   // Move from one register to another (no writeback)
4085   for(hr=0;hr<HOST_REGS;hr++) {
4086     if(hr!=EXCLUDE_REG) {
4087       if(pre[hr]!=entry[hr]) {
4088         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4089           int nr;
4090           if((nr=get_reg(entry,pre[hr]))>=0) {
4091             emit_mov(hr,nr);
4092           }
4093         }
4094       }
4095     }
4096   }
4097 }
4098 #endif
4099
4100 // Load the specified registers
4101 // This only loads the registers given as arguments because
4102 // we don't want to load things that will be overwritten
4103 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4104 {
4105   int hr;
4106   // Load 32-bit regs
4107   for(hr=0;hr<HOST_REGS;hr++) {
4108     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4109       if(entry[hr]!=regmap[hr]) {
4110         if(regmap[hr]==rs1||regmap[hr]==rs2)
4111         {
4112           if(regmap[hr]==0) {
4113             emit_zeroreg(hr);
4114           }
4115           else
4116           {
4117             emit_loadreg(regmap[hr],hr);
4118           }
4119         }
4120       }
4121     }
4122   }
4123   //Load 64-bit regs
4124   for(hr=0;hr<HOST_REGS;hr++) {
4125     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4126       if(entry[hr]!=regmap[hr]) {
4127         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4128         {
4129           assert(regmap[hr]!=64);
4130           if((is32>>(regmap[hr]&63))&1) {
4131             int lr=get_reg(regmap,regmap[hr]-64);
4132             if(lr>=0)
4133               emit_sarimm(lr,31,hr);
4134             else
4135               emit_loadreg(regmap[hr],hr);
4136           }
4137           else
4138           {
4139             emit_loadreg(regmap[hr],hr);
4140           }
4141         }
4142       }
4143     }
4144   }
4145 }
4146
4147 // Load registers prior to the start of a loop
4148 // so that they are not loaded within the loop
4149 static void loop_preload(signed char pre[],signed char entry[])
4150 {
4151   int hr;
4152   for(hr=0;hr<HOST_REGS;hr++) {
4153     if(hr!=EXCLUDE_REG) {
4154       if(pre[hr]!=entry[hr]) {
4155         if(entry[hr]>=0) {
4156           if(get_reg(pre,entry[hr])<0) {
4157             assem_debug("loop preload:\n");
4158             //printf("loop preload: %d\n",hr);
4159             if(entry[hr]==0) {
4160               emit_zeroreg(hr);
4161             }
4162             else if(entry[hr]<TEMPREG)
4163             {
4164               emit_loadreg(entry[hr],hr);
4165             }
4166             else if(entry[hr]-64<TEMPREG)
4167             {
4168               emit_loadreg(entry[hr],hr);
4169             }
4170           }
4171         }
4172       }
4173     }
4174   }
4175 }
4176
4177 // Generate address for load/store instruction
4178 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4179 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4180 {
4181   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4182     int ra=-1;
4183     int agr=AGEN1+(i&1);
4184     int mgr=MGEN1+(i&1);
4185     if(itype[i]==LOAD) {
4186       ra=get_reg(i_regs->regmap,rt1[i]);
4187       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4188       assert(ra>=0);
4189     }
4190     if(itype[i]==LOADLR) {
4191       ra=get_reg(i_regs->regmap,FTEMP);
4192     }
4193     if(itype[i]==STORE||itype[i]==STORELR) {
4194       ra=get_reg(i_regs->regmap,agr);
4195       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4196     }
4197     if(itype[i]==C1LS||itype[i]==C2LS) {
4198       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4199         ra=get_reg(i_regs->regmap,FTEMP);
4200       else { // SWC1/SDC1/SWC2/SDC2
4201         ra=get_reg(i_regs->regmap,agr);
4202         if(ra<0) ra=get_reg(i_regs->regmap,-1);
4203       }
4204     }
4205     int rs=get_reg(i_regs->regmap,rs1[i]);
4206     int rm=get_reg(i_regs->regmap,TLREG);
4207     if(ra>=0) {
4208       int offset=imm[i];
4209       int c=(i_regs->wasconst>>rs)&1;
4210       if(rs1[i]==0) {
4211         // Using r0 as a base address
4212         /*if(rm>=0) {
4213           if(!entry||entry[rm]!=mgr) {
4214             generate_map_const(offset,rm);
4215           } // else did it in the previous cycle
4216         }*/
4217         if(!entry||entry[ra]!=agr) {
4218           if (opcode[i]==0x22||opcode[i]==0x26) {
4219             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4220           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4221             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4222           }else{
4223             emit_movimm(offset,ra);
4224           }
4225         } // else did it in the previous cycle
4226       }
4227       else if(rs<0) {
4228         if(!entry||entry[ra]!=rs1[i])
4229           emit_loadreg(rs1[i],ra);
4230         //if(!entry||entry[ra]!=rs1[i])
4231         //  printf("poor load scheduling!\n");
4232       }
4233       else if(c) {
4234 #ifndef DISABLE_TLB
4235         if(rm>=0) {
4236           if(!entry||entry[rm]!=mgr) {
4237             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4238               // Stores to memory go thru the mapper to detect self-modifying
4239               // code, loads don't.
4240               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4241                  (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4242                 generate_map_const(constmap[i][rs]+offset,rm);
4243             }else{
4244               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4245                 generate_map_const(constmap[i][rs]+offset,rm);
4246             }
4247           }
4248         }
4249 #endif
4250         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4251           if(!entry||entry[ra]!=agr) {
4252             if (opcode[i]==0x22||opcode[i]==0x26) {
4253               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4254             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4255               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4256             }else{
4257               #ifdef HOST_IMM_ADDR32
4258               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4259                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4260               #endif
4261               emit_movimm(constmap[i][rs]+offset,ra);
4262               regs[i].loadedconst|=1<<ra;
4263             }
4264           } // else did it in the previous cycle
4265         } // else load_consts already did it
4266       }
4267       if(offset&&!c&&rs1[i]) {
4268         if(rs>=0) {
4269           emit_addimm(rs,offset,ra);
4270         }else{
4271           emit_addimm(ra,offset,ra);
4272         }
4273       }
4274     }
4275   }
4276   // Preload constants for next instruction
4277   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4278     int agr,ra;
4279     #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4280     // Mapper entry
4281     agr=MGEN1+((i+1)&1);
4282     ra=get_reg(i_regs->regmap,agr);
4283     if(ra>=0) {
4284       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4285       int offset=imm[i+1];
4286       int c=(regs[i+1].wasconst>>rs)&1;
4287       if(c) {
4288         if(itype[i+1]==STORE||itype[i+1]==STORELR
4289            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4290           // Stores to memory go thru the mapper to detect self-modifying
4291           // code, loads don't.
4292           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4293              (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4294             generate_map_const(constmap[i+1][rs]+offset,ra);
4295         }else{
4296           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4297             generate_map_const(constmap[i+1][rs]+offset,ra);
4298         }
4299       }
4300       /*else if(rs1[i]==0) {
4301         generate_map_const(offset,ra);
4302       }*/
4303     }
4304     #endif
4305     // Actual address
4306     agr=AGEN1+((i+1)&1);
4307     ra=get_reg(i_regs->regmap,agr);
4308     if(ra>=0) {
4309       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4310       int offset=imm[i+1];
4311       int c=(regs[i+1].wasconst>>rs)&1;
4312       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4313         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4314           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4315         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4316           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4317         }else{
4318           #ifdef HOST_IMM_ADDR32
4319           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4320              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4321           #endif
4322           emit_movimm(constmap[i+1][rs]+offset,ra);
4323           regs[i+1].loadedconst|=1<<ra;
4324         }
4325       }
4326       else if(rs1[i+1]==0) {
4327         // Using r0 as a base address
4328         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4329           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4330         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4331           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4332         }else{
4333           emit_movimm(offset,ra);
4334         }
4335       }
4336     }
4337   }
4338 }
4339
4340 int get_final_value(int hr, int i, int *value)
4341 {
4342   int reg=regs[i].regmap[hr];
4343   while(i<slen-1) {
4344     if(regs[i+1].regmap[hr]!=reg) break;
4345     if(!((regs[i+1].isconst>>hr)&1)) break;
4346     if(bt[i+1]) break;
4347     i++;
4348   }
4349   if(i<slen-1) {
4350     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4351       *value=constmap[i][hr];
4352       return 1;
4353     }
4354     if(!bt[i+1]) {
4355       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4356         // Load in delay slot, out-of-order execution
4357         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4358         {
4359           #ifdef HOST_IMM_ADDR32
4360           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4361           #endif
4362           // Precompute load address
4363           *value=constmap[i][hr]+imm[i+2];
4364           return 1;
4365         }
4366       }
4367       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4368       {
4369         #ifdef HOST_IMM_ADDR32
4370         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4371         #endif
4372         // Precompute load address
4373         *value=constmap[i][hr]+imm[i+1];
4374         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4375         return 1;
4376       }
4377     }
4378   }
4379   *value=constmap[i][hr];
4380   //printf("c=%x\n",(int)constmap[i][hr]);
4381   if(i==slen-1) return 1;
4382   if(reg<64) {
4383     return !((unneeded_reg[i+1]>>reg)&1);
4384   }else{
4385     return !((unneeded_reg_upper[i+1]>>reg)&1);
4386   }
4387 }
4388
4389 // Load registers with known constants
4390 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4391 {
4392   int hr,hr2;
4393   // propagate loaded constant flags
4394   if(i==0||bt[i])
4395     regs[i].loadedconst=0;
4396   else {
4397     for(hr=0;hr<HOST_REGS;hr++) {
4398       if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4399          &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4400       {
4401         regs[i].loadedconst|=1<<hr;
4402       }
4403     }
4404   }
4405   // Load 32-bit regs
4406   for(hr=0;hr<HOST_REGS;hr++) {
4407     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4408       //if(entry[hr]!=regmap[hr]) {
4409       if(!((regs[i].loadedconst>>hr)&1)) {
4410         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4411           int value,similar=0;
4412           if(get_final_value(hr,i,&value)) {
4413             // see if some other register has similar value
4414             for(hr2=0;hr2<HOST_REGS;hr2++) {
4415               if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4416                 if(is_similar_value(value,constmap[i][hr2])) {
4417                   similar=1;
4418                   break;
4419                 }
4420               }
4421             }
4422             if(similar) {
4423               int value2;
4424               if(get_final_value(hr2,i,&value2)) // is this needed?
4425                 emit_movimm_from(value2,hr2,value,hr);
4426               else
4427                 emit_movimm(value,hr);
4428             }
4429             else if(value==0) {
4430               emit_zeroreg(hr);
4431             }
4432             else {
4433               emit_movimm(value,hr);
4434             }
4435           }
4436           regs[i].loadedconst|=1<<hr;
4437         }
4438       }
4439     }
4440   }
4441   // Load 64-bit regs
4442   for(hr=0;hr<HOST_REGS;hr++) {
4443     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4444       //if(entry[hr]!=regmap[hr]) {
4445       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4446         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4447           if((is32>>(regmap[hr]&63))&1) {
4448             int lr=get_reg(regmap,regmap[hr]-64);
4449             assert(lr>=0);
4450             emit_sarimm(lr,31,hr);
4451           }
4452           else
4453           {
4454             int value;
4455             if(get_final_value(hr,i,&value)) {
4456               if(value==0) {
4457                 emit_zeroreg(hr);
4458               }
4459               else {
4460                 emit_movimm(value,hr);
4461               }
4462             }
4463           }
4464         }
4465       }
4466     }
4467   }
4468 }
4469 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4470 {
4471   int hr;
4472   // Load 32-bit regs
4473   for(hr=0;hr<HOST_REGS;hr++) {
4474     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4475       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4476         int value=constmap[i][hr];
4477         if(value==0) {
4478           emit_zeroreg(hr);
4479         }
4480         else {
4481           emit_movimm(value,hr);
4482         }
4483       }
4484     }
4485   }
4486   // Load 64-bit regs
4487   for(hr=0;hr<HOST_REGS;hr++) {
4488     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4489       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4490         if((is32>>(regmap[hr]&63))&1) {
4491           int lr=get_reg(regmap,regmap[hr]-64);
4492           assert(lr>=0);
4493           emit_sarimm(lr,31,hr);
4494         }
4495         else
4496         {
4497           int value=constmap[i][hr];
4498           if(value==0) {
4499             emit_zeroreg(hr);
4500           }
4501           else {
4502             emit_movimm(value,hr);
4503           }
4504         }
4505       }
4506     }
4507   }
4508 }
4509
4510 // Write out all dirty registers (except cycle count)
4511 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4512 {
4513   int hr;
4514   for(hr=0;hr<HOST_REGS;hr++) {
4515     if(hr!=EXCLUDE_REG) {
4516       if(i_regmap[hr]>0) {
4517         if(i_regmap[hr]!=CCREG) {
4518           if((i_dirty>>hr)&1) {
4519             if(i_regmap[hr]<64) {
4520               emit_storereg(i_regmap[hr],hr);
4521 #ifndef FORCE32
4522               if( ((i_is32>>i_regmap[hr])&1) ) {
4523                 #ifdef DESTRUCTIVE_WRITEBACK
4524                 emit_sarimm(hr,31,hr);
4525                 emit_storereg(i_regmap[hr]|64,hr);
4526                 #else
4527                 emit_sarimm(hr,31,HOST_TEMPREG);
4528                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4529                 #endif
4530               }
4531 #endif
4532             }else{
4533               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4534                 emit_storereg(i_regmap[hr],hr);
4535               }
4536             }
4537           }
4538         }
4539       }
4540     }
4541   }
4542 }
4543 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4544 // This writes the registers not written by store_regs_bt
4545 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4546 {
4547   int hr;
4548   int t=(addr-start)>>2;
4549   for(hr=0;hr<HOST_REGS;hr++) {
4550     if(hr!=EXCLUDE_REG) {
4551       if(i_regmap[hr]>0) {
4552         if(i_regmap[hr]!=CCREG) {
4553           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4554             if((i_dirty>>hr)&1) {
4555               if(i_regmap[hr]<64) {
4556                 emit_storereg(i_regmap[hr],hr);
4557 #ifndef FORCE32
4558                 if( ((i_is32>>i_regmap[hr])&1) ) {
4559                   #ifdef DESTRUCTIVE_WRITEBACK
4560                   emit_sarimm(hr,31,hr);
4561                   emit_storereg(i_regmap[hr]|64,hr);
4562                   #else
4563                   emit_sarimm(hr,31,HOST_TEMPREG);
4564                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4565                   #endif
4566                 }
4567 #endif
4568               }else{
4569                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4570                   emit_storereg(i_regmap[hr],hr);
4571                 }
4572               }
4573             }
4574           }
4575         }
4576       }
4577     }
4578   }
4579 }
4580
4581 // Load all registers (except cycle count)
4582 void load_all_regs(signed char i_regmap[])
4583 {
4584   int hr;
4585   for(hr=0;hr<HOST_REGS;hr++) {
4586     if(hr!=EXCLUDE_REG) {
4587       if(i_regmap[hr]==0) {
4588         emit_zeroreg(hr);
4589       }
4590       else
4591       if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4592       {
4593         emit_loadreg(i_regmap[hr],hr);
4594       }
4595     }
4596   }
4597 }
4598
4599 // Load all current registers also needed by next instruction
4600 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4601 {
4602   int hr;
4603   for(hr=0;hr<HOST_REGS;hr++) {
4604     if(hr!=EXCLUDE_REG) {
4605       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4606         if(i_regmap[hr]==0) {
4607           emit_zeroreg(hr);
4608         }
4609         else
4610         if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4611         {
4612           emit_loadreg(i_regmap[hr],hr);
4613         }
4614       }
4615     }
4616   }
4617 }
4618
4619 // Load all regs, storing cycle count if necessary
4620 void load_regs_entry(int t)
4621 {
4622   int hr;
4623   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4624   else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4625   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4626     emit_storereg(CCREG,HOST_CCREG);
4627   }
4628   // Load 32-bit regs
4629   for(hr=0;hr<HOST_REGS;hr++) {
4630     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4631       if(regs[t].regmap_entry[hr]==0) {
4632         emit_zeroreg(hr);
4633       }
4634       else if(regs[t].regmap_entry[hr]!=CCREG)
4635       {
4636         emit_loadreg(regs[t].regmap_entry[hr],hr);
4637       }
4638     }
4639   }
4640   // Load 64-bit regs
4641   for(hr=0;hr<HOST_REGS;hr++) {
4642     if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4643       assert(regs[t].regmap_entry[hr]!=64);
4644       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4645         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4646         if(lr<0) {
4647           emit_loadreg(regs[t].regmap_entry[hr],hr);
4648         }
4649         else
4650         {
4651           emit_sarimm(lr,31,hr);
4652         }
4653       }
4654       else
4655       {
4656         emit_loadreg(regs[t].regmap_entry[hr],hr);
4657       }
4658     }
4659   }
4660 }
4661
4662 // Store dirty registers prior to branch
4663 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4664 {
4665   if(internal_branch(i_is32,addr))
4666   {
4667     int t=(addr-start)>>2;
4668     int hr;
4669     for(hr=0;hr<HOST_REGS;hr++) {
4670       if(hr!=EXCLUDE_REG) {
4671         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4672           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4673             if((i_dirty>>hr)&1) {
4674               if(i_regmap[hr]<64) {
4675                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4676                   emit_storereg(i_regmap[hr],hr);
4677                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4678                     #ifdef DESTRUCTIVE_WRITEBACK
4679                     emit_sarimm(hr,31,hr);
4680                     emit_storereg(i_regmap[hr]|64,hr);
4681                     #else
4682                     emit_sarimm(hr,31,HOST_TEMPREG);
4683                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4684                     #endif
4685                   }
4686                 }
4687               }else{
4688                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4689                   emit_storereg(i_regmap[hr],hr);
4690                 }
4691               }
4692             }
4693           }
4694         }
4695       }
4696     }
4697   }
4698   else
4699   {
4700     // Branch out of this block, write out all dirty regs
4701     wb_dirtys(i_regmap,i_is32,i_dirty);
4702   }
4703 }
4704
4705 // Load all needed registers for branch target
4706 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4707 {
4708   //if(addr>=start && addr<(start+slen*4))
4709   if(internal_branch(i_is32,addr))
4710   {
4711     int t=(addr-start)>>2;
4712     int hr;
4713     // Store the cycle count before loading something else
4714     if(i_regmap[HOST_CCREG]!=CCREG) {
4715       assert(i_regmap[HOST_CCREG]==-1);
4716     }
4717     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4718       emit_storereg(CCREG,HOST_CCREG);
4719     }
4720     // Load 32-bit regs
4721     for(hr=0;hr<HOST_REGS;hr++) {
4722       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4723         #ifdef DESTRUCTIVE_WRITEBACK
4724         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4725         #else
4726         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4727         #endif
4728           if(regs[t].regmap_entry[hr]==0) {
4729             emit_zeroreg(hr);
4730           }
4731           else if(regs[t].regmap_entry[hr]!=CCREG)
4732           {
4733             emit_loadreg(regs[t].regmap_entry[hr],hr);
4734           }
4735         }
4736       }
4737     }
4738     //Load 64-bit regs
4739     for(hr=0;hr<HOST_REGS;hr++) {
4740       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4741         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4742           assert(regs[t].regmap_entry[hr]!=64);
4743           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4744             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4745             if(lr<0) {
4746               emit_loadreg(regs[t].regmap_entry[hr],hr);
4747             }
4748             else
4749             {
4750               emit_sarimm(lr,31,hr);
4751             }
4752           }
4753           else
4754           {
4755             emit_loadreg(regs[t].regmap_entry[hr],hr);
4756           }
4757         }
4758         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4759           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4760           assert(lr>=0);
4761           emit_sarimm(lr,31,hr);
4762         }
4763       }
4764     }
4765   }
4766 }
4767
4768 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4769 {
4770   if(addr>=start && addr<start+slen*4-4)
4771   {
4772     int t=(addr-start)>>2;
4773     int hr;
4774     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4775     for(hr=0;hr<HOST_REGS;hr++)
4776     {
4777       if(hr!=EXCLUDE_REG)
4778       {
4779         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4780         {
4781           if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4782           {
4783             return 0;
4784           }
4785           else
4786           if((i_dirty>>hr)&1)
4787           {
4788             if(i_regmap[hr]<TEMPREG)
4789             {
4790               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4791                 return 0;
4792             }
4793             else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4794             {
4795               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4796                 return 0;
4797             }
4798           }
4799         }
4800         else // Same register but is it 32-bit or dirty?
4801         if(i_regmap[hr]>=0)
4802         {
4803           if(!((regs[t].dirty>>hr)&1))
4804           {
4805             if((i_dirty>>hr)&1)
4806             {
4807               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4808               {
4809                 //printf("%x: dirty no match\n",addr);
4810                 return 0;
4811               }
4812             }
4813           }
4814           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4815           {
4816             //printf("%x: is32 no match\n",addr);
4817             return 0;
4818           }
4819         }
4820       }
4821     }
4822     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4823 #ifndef FORCE32
4824     if(requires_32bit[t]&~i_is32) return 0;
4825 #endif
4826     // Delay slots are not valid branch targets
4827     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4828     // Delay slots require additional processing, so do not match
4829     if(is_ds[t]) return 0;
4830   }
4831   else
4832   {
4833     int hr;
4834     for(hr=0;hr<HOST_REGS;hr++)
4835     {
4836       if(hr!=EXCLUDE_REG)
4837       {
4838         if(i_regmap[hr]>=0)
4839         {
4840           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4841           {
4842             if((i_dirty>>hr)&1)
4843             {
4844               return 0;
4845             }
4846           }
4847         }
4848       }
4849     }
4850   }
4851   return 1;
4852 }
4853
4854 // Used when a branch jumps into the delay slot of another branch
4855 void ds_assemble_entry(int i)
4856 {
4857   int t=(ba[i]-start)>>2;
4858   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4859   assem_debug("Assemble delay slot at %x\n",ba[i]);
4860   assem_debug("<->\n");
4861   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4862     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4863   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4864   address_generation(t,&regs[t],regs[t].regmap_entry);
4865   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4866     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4867   cop1_usable=0;
4868   is_delayslot=0;
4869   switch(itype[t]) {
4870     case ALU:
4871       alu_assemble(t,&regs[t]);break;
4872     case IMM16:
4873       imm16_assemble(t,&regs[t]);break;
4874     case SHIFT:
4875       shift_assemble(t,&regs[t]);break;
4876     case SHIFTIMM:
4877       shiftimm_assemble(t,&regs[t]);break;
4878     case LOAD:
4879       load_assemble(t,&regs[t]);break;
4880     case LOADLR:
4881       loadlr_assemble(t,&regs[t]);break;
4882     case STORE:
4883       store_assemble(t,&regs[t]);break;
4884     case STORELR:
4885       storelr_assemble(t,&regs[t]);break;
4886     case COP0:
4887       cop0_assemble(t,&regs[t]);break;
4888     case COP1:
4889       cop1_assemble(t,&regs[t]);break;
4890     case C1LS:
4891       c1ls_assemble(t,&regs[t]);break;
4892     case COP2:
4893       cop2_assemble(t,&regs[t]);break;
4894     case C2LS:
4895       c2ls_assemble(t,&regs[t]);break;
4896     case C2OP:
4897       c2op_assemble(t,&regs[t]);break;
4898     case FCONV:
4899       fconv_assemble(t,&regs[t]);break;
4900     case FLOAT:
4901       float_assemble(t,&regs[t]);break;
4902     case FCOMP:
4903       fcomp_assemble(t,&regs[t]);break;
4904     case MULTDIV:
4905       multdiv_assemble(t,&regs[t]);break;
4906     case MOV:
4907       mov_assemble(t,&regs[t]);break;
4908     case SYSCALL:
4909     case HLECALL:
4910     case INTCALL:
4911     case SPAN:
4912     case UJUMP:
4913     case RJUMP:
4914     case CJUMP:
4915     case SJUMP:
4916     case FJUMP:
4917       printf("Jump in the delay slot.  This is probably a bug.\n");
4918   }
4919   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4920   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4921   if(internal_branch(regs[t].is32,ba[i]+4))
4922     assem_debug("branch: internal\n");
4923   else
4924     assem_debug("branch: external\n");
4925   assert(internal_branch(regs[t].is32,ba[i]+4));
4926   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4927   emit_jmp(0);
4928 }
4929
4930 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4931 {
4932   int count;
4933   int jaddr;
4934   int idle=0;
4935   if(itype[i]==RJUMP)
4936   {
4937     *adj=0;
4938   }
4939   //if(ba[i]>=start && ba[i]<(start+slen*4))
4940   if(internal_branch(branch_regs[i].is32,ba[i]))
4941   {
4942     int t=(ba[i]-start)>>2;
4943     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4944     else *adj=ccadj[t];
4945   }
4946   else
4947   {
4948     *adj=0;
4949   }
4950   count=ccadj[i];
4951   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4952     // Idle loop
4953     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4954     idle=(int)out;
4955     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4956     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4957     jaddr=(int)out;
4958     emit_jmp(0);
4959   }
4960   else if(*adj==0||invert) {
4961     emit_addimm_and_set_flags(CLOCK_ADJUST(count+2),HOST_CCREG);
4962     jaddr=(int)out;
4963     emit_jns(0);
4964   }
4965   else
4966   {
4967     emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4968     jaddr=(int)out;
4969     emit_jns(0);
4970   }
4971   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4972 }
4973
4974 void do_ccstub(int n)
4975 {
4976   literal_pool(256);
4977   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4978   set_jump_target(stubs[n][1],(int)out);
4979   int i=stubs[n][4];
4980   if(stubs[n][6]==NULLDS) {
4981     // Delay slot instruction is nullified ("likely" branch)
4982     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4983   }
4984   else if(stubs[n][6]!=TAKEN) {
4985     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4986   }
4987   else {
4988     if(internal_branch(branch_regs[i].is32,ba[i]))
4989       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4990   }
4991   if(stubs[n][5]!=-1)
4992   {
4993     // Save PC as return address
4994     emit_movimm(stubs[n][5],EAX);
4995     emit_writeword(EAX,(int)&pcaddr);
4996   }
4997   else
4998   {
4999     // Return address depends on which way the branch goes
5000     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
5001     {
5002       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5003       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5004       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5005       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5006       if(rs1[i]==0)
5007       {
5008         s1l=s2l;s1h=s2h;
5009         s2l=s2h=-1;
5010       }
5011       else if(rs2[i]==0)
5012       {
5013         s2l=s2h=-1;
5014       }
5015       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
5016         s1h=s2h=-1;
5017       }
5018       assert(s1l>=0);
5019       #ifdef DESTRUCTIVE_WRITEBACK
5020       if(rs1[i]) {
5021         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
5022           emit_loadreg(rs1[i],s1l);
5023       }
5024       else {
5025         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
5026           emit_loadreg(rs2[i],s1l);
5027       }
5028       if(s2l>=0)
5029         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
5030           emit_loadreg(rs2[i],s2l);
5031       #endif
5032       int hr=0;
5033       int addr=-1,alt=-1,ntaddr=-1;
5034       while(hr<HOST_REGS)
5035       {
5036         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5037            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5038            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5039         {
5040           addr=hr++;break;
5041         }
5042         hr++;
5043       }
5044       while(hr<HOST_REGS)
5045       {
5046         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5047            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5048            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5049         {
5050           alt=hr++;break;
5051         }
5052         hr++;
5053       }
5054       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5055       {
5056         while(hr<HOST_REGS)
5057         {
5058           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5059              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5060              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5061           {
5062             ntaddr=hr;break;
5063           }
5064           hr++;
5065         }
5066         assert(hr<HOST_REGS);
5067       }
5068       if((opcode[i]&0x2f)==4) // BEQ
5069       {
5070         #ifdef HAVE_CMOV_IMM
5071         if(s1h<0) {
5072           if(s2l>=0) emit_cmp(s1l,s2l);
5073           else emit_test(s1l,s1l);
5074           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5075         }
5076         else
5077         #endif
5078         {
5079           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5080           if(s1h>=0) {
5081             if(s2h>=0) emit_cmp(s1h,s2h);
5082             else emit_test(s1h,s1h);
5083             emit_cmovne_reg(alt,addr);
5084           }
5085           if(s2l>=0) emit_cmp(s1l,s2l);
5086           else emit_test(s1l,s1l);
5087           emit_cmovne_reg(alt,addr);
5088         }
5089       }
5090       if((opcode[i]&0x2f)==5) // BNE
5091       {
5092         #ifdef HAVE_CMOV_IMM
5093         if(s1h<0) {
5094           if(s2l>=0) emit_cmp(s1l,s2l);
5095           else emit_test(s1l,s1l);
5096           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5097         }
5098         else
5099         #endif
5100         {
5101           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5102           if(s1h>=0) {
5103             if(s2h>=0) emit_cmp(s1h,s2h);
5104             else emit_test(s1h,s1h);
5105             emit_cmovne_reg(alt,addr);
5106           }
5107           if(s2l>=0) emit_cmp(s1l,s2l);
5108           else emit_test(s1l,s1l);
5109           emit_cmovne_reg(alt,addr);
5110         }
5111       }
5112       if((opcode[i]&0x2f)==6) // BLEZ
5113       {
5114         //emit_movimm(ba[i],alt);
5115         //emit_movimm(start+i*4+8,addr);
5116         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5117         emit_cmpimm(s1l,1);
5118         if(s1h>=0) emit_mov(addr,ntaddr);
5119         emit_cmovl_reg(alt,addr);
5120         if(s1h>=0) {
5121           emit_test(s1h,s1h);
5122           emit_cmovne_reg(ntaddr,addr);
5123           emit_cmovs_reg(alt,addr);
5124         }
5125       }
5126       if((opcode[i]&0x2f)==7) // BGTZ
5127       {
5128         //emit_movimm(ba[i],addr);
5129         //emit_movimm(start+i*4+8,ntaddr);
5130         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5131         emit_cmpimm(s1l,1);
5132         if(s1h>=0) emit_mov(addr,alt);
5133         emit_cmovl_reg(ntaddr,addr);
5134         if(s1h>=0) {
5135           emit_test(s1h,s1h);
5136           emit_cmovne_reg(alt,addr);
5137           emit_cmovs_reg(ntaddr,addr);
5138         }
5139       }
5140       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5141       {
5142         //emit_movimm(ba[i],alt);
5143         //emit_movimm(start+i*4+8,addr);
5144         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5145         if(s1h>=0) emit_test(s1h,s1h);
5146         else emit_test(s1l,s1l);
5147         emit_cmovs_reg(alt,addr);
5148       }
5149       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5150       {
5151         //emit_movimm(ba[i],addr);
5152         //emit_movimm(start+i*4+8,alt);
5153         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5154         if(s1h>=0) emit_test(s1h,s1h);
5155         else emit_test(s1l,s1l);
5156         emit_cmovs_reg(alt,addr);
5157       }
5158       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5159         if(source[i]&0x10000) // BC1T
5160         {
5161           //emit_movimm(ba[i],alt);
5162           //emit_movimm(start+i*4+8,addr);
5163           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5164           emit_testimm(s1l,0x800000);
5165           emit_cmovne_reg(alt,addr);
5166         }
5167         else // BC1F
5168         {
5169           //emit_movimm(ba[i],addr);
5170           //emit_movimm(start+i*4+8,alt);
5171           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5172           emit_testimm(s1l,0x800000);
5173           emit_cmovne_reg(alt,addr);
5174         }
5175       }
5176       emit_writeword(addr,(int)&pcaddr);
5177     }
5178     else
5179     if(itype[i]==RJUMP)
5180     {
5181       int r=get_reg(branch_regs[i].regmap,rs1[i]);
5182       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5183         r=get_reg(branch_regs[i].regmap,RTEMP);
5184       }
5185       emit_writeword(r,(int)&pcaddr);
5186     }
5187     else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5188   }
5189   // Update cycle count
5190   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5191   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5192   emit_call((int)cc_interrupt);
5193   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5194   if(stubs[n][6]==TAKEN) {
5195     if(internal_branch(branch_regs[i].is32,ba[i]))
5196       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5197     else if(itype[i]==RJUMP) {
5198       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5199         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5200       else
5201         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5202     }
5203   }else if(stubs[n][6]==NOTTAKEN) {
5204     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5205     else load_all_regs(branch_regs[i].regmap);
5206   }else if(stubs[n][6]==NULLDS) {
5207     // Delay slot instruction is nullified ("likely" branch)
5208     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5209     else load_all_regs(regs[i].regmap);
5210   }else{
5211     load_all_regs(branch_regs[i].regmap);
5212   }
5213   emit_jmp(stubs[n][2]); // return address
5214
5215   /* This works but uses a lot of memory...
5216   emit_readword((int)&last_count,ECX);
5217   emit_add(HOST_CCREG,ECX,EAX);
5218   emit_writeword(EAX,(int)&Count);
5219   emit_call((int)gen_interupt);
5220   emit_readword((int)&Count,HOST_CCREG);
5221   emit_readword((int)&next_interupt,EAX);
5222   emit_readword((int)&pending_exception,EBX);
5223   emit_writeword(EAX,(int)&last_count);
5224   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5225   emit_test(EBX,EBX);
5226   int jne_instr=(int)out;
5227   emit_jne(0);
5228   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5229   load_all_regs(branch_regs[i].regmap);
5230   emit_jmp(stubs[n][2]); // return address
5231   set_jump_target(jne_instr,(int)out);
5232   emit_readword((int)&pcaddr,EAX);
5233   // Call get_addr_ht instead of doing the hash table here.
5234   // This code is executed infrequently and takes up a lot of space
5235   // so smaller is better.
5236   emit_storereg(CCREG,HOST_CCREG);
5237   emit_pushreg(EAX);
5238   emit_call((int)get_addr_ht);
5239   emit_loadreg(CCREG,HOST_CCREG);
5240   emit_addimm(ESP,4,ESP);
5241   emit_jmpreg(EAX);*/
5242 }
5243
5244 add_to_linker(int addr,int target,int ext)
5245 {
5246   link_addr[linkcount][0]=addr;
5247   link_addr[linkcount][1]=target;
5248   link_addr[linkcount][2]=ext;
5249   linkcount++;
5250 }
5251
5252 static void ujump_assemble_write_ra(int i)
5253 {
5254   int rt;
5255   unsigned int return_address;
5256   rt=get_reg(branch_regs[i].regmap,31);
5257   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5258   //assert(rt>=0);
5259   return_address=start+i*4+8;
5260   if(rt>=0) {
5261     #ifdef USE_MINI_HT
5262     if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5263       int temp=-1; // note: must be ds-safe
5264       #ifdef HOST_TEMPREG
5265       temp=HOST_TEMPREG;
5266       #endif
5267       if(temp>=0) do_miniht_insert(return_address,rt,temp);
5268       else emit_movimm(return_address,rt);
5269     }
5270     else
5271     #endif
5272     {
5273       #ifdef REG_PREFETCH
5274       if(temp>=0)
5275       {
5276         if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5277       }
5278       #endif
5279       emit_movimm(return_address,rt); // PC into link register
5280       #ifdef IMM_PREFETCH
5281       emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5282       #endif
5283     }
5284   }
5285 }
5286
5287 void ujump_assemble(int i,struct regstat *i_regs)
5288 {
5289   signed char *i_regmap=i_regs->regmap;
5290   int ra_done=0;
5291   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5292   address_generation(i+1,i_regs,regs[i].regmap_entry);
5293   #ifdef REG_PREFETCH
5294   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5295   if(rt1[i]==31&&temp>=0)
5296   {
5297     int return_address=start+i*4+8;
5298     if(get_reg(branch_regs[i].regmap,31)>0)
5299     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5300   }
5301   #endif
5302   if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5303     ujump_assemble_write_ra(i); // writeback ra for DS
5304     ra_done=1;
5305   }
5306   ds_assemble(i+1,i_regs);
5307   uint64_t bc_unneeded=branch_regs[i].u;
5308   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5309   bc_unneeded|=1|(1LL<<rt1[i]);
5310   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5311   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5312                 bc_unneeded,bc_unneeded_upper);
5313   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5314   if(!ra_done&&rt1[i]==31)
5315     ujump_assemble_write_ra(i);
5316   int cc,adj;
5317   cc=get_reg(branch_regs[i].regmap,CCREG);
5318   assert(cc==HOST_CCREG);
5319   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5320   #ifdef REG_PREFETCH
5321   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5322   #endif
5323   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5324   if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5325   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5326   if(internal_branch(branch_regs[i].is32,ba[i]))
5327     assem_debug("branch: internal\n");
5328   else
5329     assem_debug("branch: external\n");
5330   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5331     ds_assemble_entry(i);
5332   }
5333   else {
5334     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5335     emit_jmp(0);
5336   }
5337 }
5338
5339 static void rjump_assemble_write_ra(int i)
5340 {
5341   int rt,return_address;
5342   assert(rt1[i+1]!=rt1[i]);
5343   assert(rt2[i+1]!=rt1[i]);
5344   rt=get_reg(branch_regs[i].regmap,rt1[i]);
5345   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5346   assert(rt>=0);
5347   return_address=start+i*4+8;
5348   #ifdef REG_PREFETCH
5349   if(temp>=0)
5350   {
5351     if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5352   }
5353   #endif
5354   emit_movimm(return_address,rt); // PC into link register
5355   #ifdef IMM_PREFETCH
5356   emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5357   #endif
5358 }
5359
5360 void rjump_assemble(int i,struct regstat *i_regs)
5361 {
5362   signed char *i_regmap=i_regs->regmap;
5363   int temp;
5364   int rs,cc,adj;
5365   int ra_done=0;
5366   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5367   assert(rs>=0);
5368   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5369     // Delay slot abuse, make a copy of the branch address register
5370     temp=get_reg(branch_regs[i].regmap,RTEMP);
5371     assert(temp>=0);
5372     assert(regs[i].regmap[temp]==RTEMP);
5373     emit_mov(rs,temp);
5374     rs=temp;
5375   }
5376   address_generation(i+1,i_regs,regs[i].regmap_entry);
5377   #ifdef REG_PREFETCH
5378   if(rt1[i]==31)
5379   {
5380     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5381       int return_address=start+i*4+8;
5382       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5383     }
5384   }
5385   #endif
5386   #ifdef USE_MINI_HT
5387   if(rs1[i]==31) {
5388     int rh=get_reg(regs[i].regmap,RHASH);
5389     if(rh>=0) do_preload_rhash(rh);
5390   }
5391   #endif
5392   if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5393     rjump_assemble_write_ra(i);
5394     ra_done=1;
5395   }
5396   ds_assemble(i+1,i_regs);
5397   uint64_t bc_unneeded=branch_regs[i].u;
5398   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5399   bc_unneeded|=1|(1LL<<rt1[i]);
5400   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5401   bc_unneeded&=~(1LL<<rs1[i]);
5402   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5403                 bc_unneeded,bc_unneeded_upper);
5404   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5405   if(!ra_done&&rt1[i]!=0)
5406     rjump_assemble_write_ra(i);
5407   cc=get_reg(branch_regs[i].regmap,CCREG);
5408   assert(cc==HOST_CCREG);
5409   #ifdef USE_MINI_HT
5410   int rh=get_reg(branch_regs[i].regmap,RHASH);
5411   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5412   if(rs1[i]==31) {
5413     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5414     do_preload_rhtbl(ht);
5415     do_rhash(rs,rh);
5416   }
5417   #endif
5418   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5419   #ifdef DESTRUCTIVE_WRITEBACK
5420   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5421     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5422       emit_loadreg(rs1[i],rs);
5423     }
5424   }
5425   #endif
5426   #ifdef REG_PREFETCH
5427   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5428   #endif
5429   #ifdef USE_MINI_HT
5430   if(rs1[i]==31) {
5431     do_miniht_load(ht,rh);
5432   }
5433   #endif
5434   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5435   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5436   //assert(adj==0);
5437   emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5438   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5439 #ifdef PCSX
5440   if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5441     // special case for RFE
5442     emit_jmp(0);
5443   else
5444 #endif
5445   emit_jns(0);
5446   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5447   #ifdef USE_MINI_HT
5448   if(rs1[i]==31) {
5449     do_miniht_jump(rs,rh,ht);
5450   }
5451   else
5452   #endif
5453   {
5454     //if(rs!=EAX) emit_mov(rs,EAX);
5455     //emit_jmp((int)jump_vaddr_eax);
5456     emit_jmp(jump_vaddr_reg[rs]);
5457   }
5458   /* Check hash table
5459   temp=!rs;
5460   emit_mov(rs,temp);
5461   emit_shrimm(rs,16,rs);
5462   emit_xor(temp,rs,rs);
5463   emit_movzwl_reg(rs,rs);
5464   emit_shlimm(rs,4,rs);
5465   emit_cmpmem_indexed((int)hash_table,rs,temp);
5466   emit_jne((int)out+14);
5467   emit_readword_indexed((int)hash_table+4,rs,rs);
5468   emit_jmpreg(rs);
5469   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5470   emit_addimm_no_flags(8,rs);
5471   emit_jeq((int)out-17);
5472   // No hit on hash table, call compiler
5473   emit_pushreg(temp);
5474 //DEBUG >
5475 #ifdef DEBUG_CYCLE_COUNT
5476   emit_readword((int)&last_count,ECX);
5477   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5478   emit_readword((int)&next_interupt,ECX);
5479   emit_writeword(HOST_CCREG,(int)&Count);
5480   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5481   emit_writeword(ECX,(int)&last_count);
5482 #endif
5483 //DEBUG <
5484   emit_storereg(CCREG,HOST_CCREG);
5485   emit_call((int)get_addr);
5486   emit_loadreg(CCREG,HOST_CCREG);
5487   emit_addimm(ESP,4,ESP);
5488   emit_jmpreg(EAX);*/
5489   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5490   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5491   #endif
5492 }
5493
5494 void cjump_assemble(int i,struct regstat *i_regs)
5495 {
5496   signed char *i_regmap=i_regs->regmap;
5497   int cc;
5498   int match;
5499   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5500   assem_debug("match=%d\n",match);
5501   int s1h,s1l,s2h,s2l;
5502   int prev_cop1_usable=cop1_usable;
5503   int unconditional=0,nop=0;
5504   int only32=0;
5505   int invert=0;
5506   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5507   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5508   if(!match) invert=1;
5509   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5510   if(i>(ba[i]-start)>>2) invert=1;
5511   #endif
5512
5513   if(ooo[i]) {
5514     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5515     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5516     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5517     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5518   }
5519   else {
5520     s1l=get_reg(i_regmap,rs1[i]);
5521     s1h=get_reg(i_regmap,rs1[i]|64);
5522     s2l=get_reg(i_regmap,rs2[i]);
5523     s2h=get_reg(i_regmap,rs2[i]|64);
5524   }
5525   if(rs1[i]==0&&rs2[i]==0)
5526   {
5527     if(opcode[i]&1) nop=1;
5528     else unconditional=1;
5529     //assert(opcode[i]!=5);
5530     //assert(opcode[i]!=7);
5531     //assert(opcode[i]!=0x15);
5532     //assert(opcode[i]!=0x17);
5533   }
5534   else if(rs1[i]==0)
5535   {
5536     s1l=s2l;s1h=s2h;
5537     s2l=s2h=-1;
5538     only32=(regs[i].was32>>rs2[i])&1;
5539   }
5540   else if(rs2[i]==0)
5541   {
5542     s2l=s2h=-1;
5543     only32=(regs[i].was32>>rs1[i])&1;
5544   }
5545   else {
5546     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5547   }
5548
5549   if(ooo[i]) {
5550     // Out of order execution (delay slot first)
5551     //printf("OOOE\n");
5552     address_generation(i+1,i_regs,regs[i].regmap_entry);
5553     ds_assemble(i+1,i_regs);
5554     int adj;
5555     uint64_t bc_unneeded=branch_regs[i].u;
5556     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5557     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5558     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5559     bc_unneeded|=1;
5560     bc_unneeded_upper|=1;
5561     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5562                   bc_unneeded,bc_unneeded_upper);
5563     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5564     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5565     cc=get_reg(branch_regs[i].regmap,CCREG);
5566     assert(cc==HOST_CCREG);
5567     if(unconditional)
5568       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5569     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5570     //assem_debug("cycle count (adj)\n");
5571     if(unconditional) {
5572       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5573       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5574         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5575         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5576         if(internal)
5577           assem_debug("branch: internal\n");
5578         else
5579           assem_debug("branch: external\n");
5580         if(internal&&is_ds[(ba[i]-start)>>2]) {
5581           ds_assemble_entry(i);
5582         }
5583         else {
5584           add_to_linker((int)out,ba[i],internal);
5585           emit_jmp(0);
5586         }
5587         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5588         if(((u_int)out)&7) emit_addnop(0);
5589         #endif
5590       }
5591     }
5592     else if(nop) {
5593       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5594       int jaddr=(int)out;
5595       emit_jns(0);
5596       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5597     }
5598     else {
5599       int taken=0,nottaken=0,nottaken1=0;
5600       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5601       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5602       if(!only32)
5603       {
5604         assert(s1h>=0);
5605         if(opcode[i]==4) // BEQ
5606         {
5607           if(s2h>=0) emit_cmp(s1h,s2h);
5608           else emit_test(s1h,s1h);
5609           nottaken1=(int)out;
5610           emit_jne(1);
5611         }
5612         if(opcode[i]==5) // BNE
5613         {
5614           if(s2h>=0) emit_cmp(s1h,s2h);
5615           else emit_test(s1h,s1h);
5616           if(invert) taken=(int)out;
5617           else add_to_linker((int)out,ba[i],internal);
5618           emit_jne(0);
5619         }
5620         if(opcode[i]==6) // BLEZ
5621         {
5622           emit_test(s1h,s1h);
5623           if(invert) taken=(int)out;
5624           else add_to_linker((int)out,ba[i],internal);
5625           emit_js(0);
5626           nottaken1=(int)out;
5627           emit_jne(1);
5628         }
5629         if(opcode[i]==7) // BGTZ
5630         {
5631           emit_test(s1h,s1h);
5632           nottaken1=(int)out;
5633           emit_js(1);
5634           if(invert) taken=(int)out;
5635           else add_to_linker((int)out,ba[i],internal);
5636           emit_jne(0);
5637         }
5638       } // if(!only32)
5639
5640       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5641       assert(s1l>=0);
5642       if(opcode[i]==4) // BEQ
5643       {
5644         if(s2l>=0) emit_cmp(s1l,s2l);
5645         else emit_test(s1l,s1l);
5646         if(invert){
5647           nottaken=(int)out;
5648           emit_jne(1);
5649         }else{
5650           add_to_linker((int)out,ba[i],internal);
5651           emit_jeq(0);
5652         }
5653       }
5654       if(opcode[i]==5) // BNE
5655       {
5656         if(s2l>=0) emit_cmp(s1l,s2l);
5657         else emit_test(s1l,s1l);
5658         if(invert){
5659           nottaken=(int)out;
5660           emit_jeq(1);
5661         }else{
5662           add_to_linker((int)out,ba[i],internal);
5663           emit_jne(0);
5664         }
5665       }
5666       if(opcode[i]==6) // BLEZ
5667       {
5668         emit_cmpimm(s1l,1);
5669         if(invert){
5670           nottaken=(int)out;
5671           emit_jge(1);
5672         }else{
5673           add_to_linker((int)out,ba[i],internal);
5674           emit_jl(0);
5675         }
5676       }
5677       if(opcode[i]==7) // BGTZ
5678       {
5679         emit_cmpimm(s1l,1);
5680         if(invert){
5681           nottaken=(int)out;
5682           emit_jl(1);
5683         }else{
5684           add_to_linker((int)out,ba[i],internal);
5685           emit_jge(0);
5686         }
5687       }
5688       if(invert) {
5689         if(taken) set_jump_target(taken,(int)out);
5690         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5691         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5692           if(adj) {
5693             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5694             add_to_linker((int)out,ba[i],internal);
5695           }else{
5696             emit_addnop(13);
5697             add_to_linker((int)out,ba[i],internal*2);
5698           }
5699           emit_jmp(0);
5700         }else
5701         #endif
5702         {
5703           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5704           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5705           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5706           if(internal)
5707             assem_debug("branch: internal\n");
5708           else
5709             assem_debug("branch: external\n");
5710           if(internal&&is_ds[(ba[i]-start)>>2]) {
5711             ds_assemble_entry(i);
5712           }
5713           else {
5714             add_to_linker((int)out,ba[i],internal);
5715             emit_jmp(0);
5716           }
5717         }
5718         set_jump_target(nottaken,(int)out);
5719       }
5720
5721       if(nottaken1) set_jump_target(nottaken1,(int)out);
5722       if(adj) {
5723         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5724       }
5725     } // (!unconditional)
5726   } // if(ooo)
5727   else
5728   {
5729     // In-order execution (branch first)
5730     //if(likely[i]) printf("IOL\n");
5731     //else
5732     //printf("IOE\n");
5733     int taken=0,nottaken=0,nottaken1=0;
5734     if(!unconditional&&!nop) {
5735       if(!only32)
5736       {
5737         assert(s1h>=0);
5738         if((opcode[i]&0x2f)==4) // BEQ
5739         {
5740           if(s2h>=0) emit_cmp(s1h,s2h);
5741           else emit_test(s1h,s1h);
5742           nottaken1=(int)out;
5743           emit_jne(2);
5744         }
5745         if((opcode[i]&0x2f)==5) // BNE
5746         {
5747           if(s2h>=0) emit_cmp(s1h,s2h);
5748           else emit_test(s1h,s1h);
5749           taken=(int)out;
5750           emit_jne(1);
5751         }
5752         if((opcode[i]&0x2f)==6) // BLEZ
5753         {
5754           emit_test(s1h,s1h);
5755           taken=(int)out;
5756           emit_js(1);
5757           nottaken1=(int)out;
5758           emit_jne(2);
5759         }
5760         if((opcode[i]&0x2f)==7) // BGTZ
5761         {
5762           emit_test(s1h,s1h);
5763           nottaken1=(int)out;
5764           emit_js(2);
5765           taken=(int)out;
5766           emit_jne(1);
5767         }
5768       } // if(!only32)
5769
5770       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5771       assert(s1l>=0);
5772       if((opcode[i]&0x2f)==4) // BEQ
5773       {
5774         if(s2l>=0) emit_cmp(s1l,s2l);
5775         else emit_test(s1l,s1l);
5776         nottaken=(int)out;
5777         emit_jne(2);
5778       }
5779       if((opcode[i]&0x2f)==5) // BNE
5780       {
5781         if(s2l>=0) emit_cmp(s1l,s2l);
5782         else emit_test(s1l,s1l);
5783         nottaken=(int)out;
5784         emit_jeq(2);
5785       }
5786       if((opcode[i]&0x2f)==6) // BLEZ
5787       {
5788         emit_cmpimm(s1l,1);
5789         nottaken=(int)out;
5790         emit_jge(2);
5791       }
5792       if((opcode[i]&0x2f)==7) // BGTZ
5793       {
5794         emit_cmpimm(s1l,1);
5795         nottaken=(int)out;
5796         emit_jl(2);
5797       }
5798     } // if(!unconditional)
5799     int adj;
5800     uint64_t ds_unneeded=branch_regs[i].u;
5801     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5802     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5803     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5804     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5805     ds_unneeded|=1;
5806     ds_unneeded_upper|=1;
5807     // branch taken
5808     if(!nop) {
5809       if(taken) set_jump_target(taken,(int)out);
5810       assem_debug("1:\n");
5811       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5812                     ds_unneeded,ds_unneeded_upper);
5813       // load regs
5814       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5815       address_generation(i+1,&branch_regs[i],0);
5816       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5817       ds_assemble(i+1,&branch_regs[i]);
5818       cc=get_reg(branch_regs[i].regmap,CCREG);
5819       if(cc==-1) {
5820         emit_loadreg(CCREG,cc=HOST_CCREG);
5821         // CHECK: Is the following instruction (fall thru) allocated ok?
5822       }
5823       assert(cc==HOST_CCREG);
5824       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5825       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5826       assem_debug("cycle count (adj)\n");
5827       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5828       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5829       if(internal)
5830         assem_debug("branch: internal\n");
5831       else
5832         assem_debug("branch: external\n");
5833       if(internal&&is_ds[(ba[i]-start)>>2]) {
5834         ds_assemble_entry(i);
5835       }
5836       else {
5837         add_to_linker((int)out,ba[i],internal);
5838         emit_jmp(0);
5839       }
5840     }
5841     // branch not taken
5842     cop1_usable=prev_cop1_usable;
5843     if(!unconditional) {
5844       if(nottaken1) set_jump_target(nottaken1,(int)out);
5845       set_jump_target(nottaken,(int)out);
5846       assem_debug("2:\n");
5847       if(!likely[i]) {
5848         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5849                       ds_unneeded,ds_unneeded_upper);
5850         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5851         address_generation(i+1,&branch_regs[i],0);
5852         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5853         ds_assemble(i+1,&branch_regs[i]);
5854       }
5855       cc=get_reg(branch_regs[i].regmap,CCREG);
5856       if(cc==-1&&!likely[i]) {
5857         // Cycle count isn't in a register, temporarily load it then write it out
5858         emit_loadreg(CCREG,HOST_CCREG);
5859         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5860         int jaddr=(int)out;
5861         emit_jns(0);
5862         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5863         emit_storereg(CCREG,HOST_CCREG);
5864       }
5865       else{
5866         cc=get_reg(i_regmap,CCREG);
5867         assert(cc==HOST_CCREG);
5868         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5869         int jaddr=(int)out;
5870         emit_jns(0);
5871         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5872       }
5873     }
5874   }
5875 }
5876
5877 void sjump_assemble(int i,struct regstat *i_regs)
5878 {
5879   signed char *i_regmap=i_regs->regmap;
5880   int cc;
5881   int match;
5882   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5883   assem_debug("smatch=%d\n",match);
5884   int s1h,s1l;
5885   int prev_cop1_usable=cop1_usable;
5886   int unconditional=0,nevertaken=0;
5887   int only32=0;
5888   int invert=0;
5889   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5890   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5891   if(!match) invert=1;
5892   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5893   if(i>(ba[i]-start)>>2) invert=1;
5894   #endif
5895
5896   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5897   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5898
5899   if(ooo[i]) {
5900     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5901     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5902   }
5903   else {
5904     s1l=get_reg(i_regmap,rs1[i]);
5905     s1h=get_reg(i_regmap,rs1[i]|64);
5906   }
5907   if(rs1[i]==0)
5908   {
5909     if(opcode2[i]&1) unconditional=1;
5910     else nevertaken=1;
5911     // These are never taken (r0 is never less than zero)
5912     //assert(opcode2[i]!=0);
5913     //assert(opcode2[i]!=2);
5914     //assert(opcode2[i]!=0x10);
5915     //assert(opcode2[i]!=0x12);
5916   }
5917   else {
5918     only32=(regs[i].was32>>rs1[i])&1;
5919   }
5920
5921   if(ooo[i]) {
5922     // Out of order execution (delay slot first)
5923     //printf("OOOE\n");
5924     address_generation(i+1,i_regs,regs[i].regmap_entry);
5925     ds_assemble(i+1,i_regs);
5926     int adj;
5927     uint64_t bc_unneeded=branch_regs[i].u;
5928     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5929     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5930     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5931     bc_unneeded|=1;
5932     bc_unneeded_upper|=1;
5933     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5934                   bc_unneeded,bc_unneeded_upper);
5935     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5936     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5937     if(rt1[i]==31) {
5938       int rt,return_address;
5939       rt=get_reg(branch_regs[i].regmap,31);
5940       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5941       if(rt>=0) {
5942         // Save the PC even if the branch is not taken
5943         return_address=start+i*4+8;
5944         emit_movimm(return_address,rt); // PC into link register
5945         #ifdef IMM_PREFETCH
5946         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5947         #endif
5948       }
5949     }
5950     cc=get_reg(branch_regs[i].regmap,CCREG);
5951     assert(cc==HOST_CCREG);
5952     if(unconditional)
5953       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5954     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5955     assem_debug("cycle count (adj)\n");
5956     if(unconditional) {
5957       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5958       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5959         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5960         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5961         if(internal)
5962           assem_debug("branch: internal\n");
5963         else
5964           assem_debug("branch: external\n");
5965         if(internal&&is_ds[(ba[i]-start)>>2]) {
5966           ds_assemble_entry(i);
5967         }
5968         else {
5969           add_to_linker((int)out,ba[i],internal);
5970           emit_jmp(0);
5971         }
5972         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5973         if(((u_int)out)&7) emit_addnop(0);
5974         #endif
5975       }
5976     }
5977     else if(nevertaken) {
5978       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5979       int jaddr=(int)out;
5980       emit_jns(0);
5981       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5982     }
5983     else {
5984       int nottaken=0;
5985       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5986       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5987       if(!only32)
5988       {
5989         assert(s1h>=0);
5990         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5991         {
5992           emit_test(s1h,s1h);
5993           if(invert){
5994             nottaken=(int)out;
5995             emit_jns(1);
5996           }else{
5997             add_to_linker((int)out,ba[i],internal);
5998             emit_js(0);
5999           }
6000         }
6001         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6002         {
6003           emit_test(s1h,s1h);
6004           if(invert){
6005             nottaken=(int)out;
6006             emit_js(1);
6007           }else{
6008             add_to_linker((int)out,ba[i],internal);
6009             emit_jns(0);
6010           }
6011         }
6012       } // if(!only32)
6013       else
6014       {
6015         assert(s1l>=0);
6016         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6017         {
6018           emit_test(s1l,s1l);
6019           if(invert){
6020             nottaken=(int)out;
6021             emit_jns(1);
6022           }else{
6023             add_to_linker((int)out,ba[i],internal);
6024             emit_js(0);
6025           }
6026         }
6027         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6028         {
6029           emit_test(s1l,s1l);
6030           if(invert){
6031             nottaken=(int)out;
6032             emit_js(1);
6033           }else{
6034             add_to_linker((int)out,ba[i],internal);
6035             emit_jns(0);
6036           }
6037         }
6038       } // if(!only32)
6039
6040       if(invert) {
6041         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6042         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6043           if(adj) {
6044             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6045             add_to_linker((int)out,ba[i],internal);
6046           }else{
6047             emit_addnop(13);
6048             add_to_linker((int)out,ba[i],internal*2);
6049           }
6050           emit_jmp(0);
6051         }else
6052         #endif
6053         {
6054           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6055           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6056           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6057           if(internal)
6058             assem_debug("branch: internal\n");
6059           else
6060             assem_debug("branch: external\n");
6061           if(internal&&is_ds[(ba[i]-start)>>2]) {
6062             ds_assemble_entry(i);
6063           }
6064           else {
6065             add_to_linker((int)out,ba[i],internal);
6066             emit_jmp(0);
6067           }
6068         }
6069         set_jump_target(nottaken,(int)out);
6070       }
6071
6072       if(adj) {
6073         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6074       }
6075     } // (!unconditional)
6076   } // if(ooo)
6077   else
6078   {
6079     // In-order execution (branch first)
6080     //printf("IOE\n");
6081     int nottaken=0;
6082     if(rt1[i]==31) {
6083       int rt,return_address;
6084       rt=get_reg(branch_regs[i].regmap,31);
6085       if(rt>=0) {
6086         // Save the PC even if the branch is not taken
6087         return_address=start+i*4+8;
6088         emit_movimm(return_address,rt); // PC into link register
6089         #ifdef IMM_PREFETCH
6090         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6091         #endif
6092       }
6093     }
6094     if(!unconditional) {
6095       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6096       if(!only32)
6097       {
6098         assert(s1h>=0);
6099         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6100         {
6101           emit_test(s1h,s1h);
6102           nottaken=(int)out;
6103           emit_jns(1);
6104         }
6105         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6106         {
6107           emit_test(s1h,s1h);
6108           nottaken=(int)out;
6109           emit_js(1);
6110         }
6111       } // if(!only32)
6112       else
6113       {
6114         assert(s1l>=0);
6115         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6116         {
6117           emit_test(s1l,s1l);
6118           nottaken=(int)out;
6119           emit_jns(1);
6120         }
6121         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6122         {
6123           emit_test(s1l,s1l);
6124           nottaken=(int)out;
6125           emit_js(1);
6126         }
6127       }
6128     } // if(!unconditional)
6129     int adj;
6130     uint64_t ds_unneeded=branch_regs[i].u;
6131     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6132     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6133     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6134     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6135     ds_unneeded|=1;
6136     ds_unneeded_upper|=1;
6137     // branch taken
6138     if(!nevertaken) {
6139       //assem_debug("1:\n");
6140       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6141                     ds_unneeded,ds_unneeded_upper);
6142       // load regs
6143       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6144       address_generation(i+1,&branch_regs[i],0);
6145       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6146       ds_assemble(i+1,&branch_regs[i]);
6147       cc=get_reg(branch_regs[i].regmap,CCREG);
6148       if(cc==-1) {
6149         emit_loadreg(CCREG,cc=HOST_CCREG);
6150         // CHECK: Is the following instruction (fall thru) allocated ok?
6151       }
6152       assert(cc==HOST_CCREG);
6153       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6154       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6155       assem_debug("cycle count (adj)\n");
6156       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6157       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6158       if(internal)
6159         assem_debug("branch: internal\n");
6160       else
6161         assem_debug("branch: external\n");
6162       if(internal&&is_ds[(ba[i]-start)>>2]) {
6163         ds_assemble_entry(i);
6164       }
6165       else {
6166         add_to_linker((int)out,ba[i],internal);
6167         emit_jmp(0);
6168       }
6169     }
6170     // branch not taken
6171     cop1_usable=prev_cop1_usable;
6172     if(!unconditional) {
6173       set_jump_target(nottaken,(int)out);
6174       assem_debug("1:\n");
6175       if(!likely[i]) {
6176         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6177                       ds_unneeded,ds_unneeded_upper);
6178         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6179         address_generation(i+1,&branch_regs[i],0);
6180         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6181         ds_assemble(i+1,&branch_regs[i]);
6182       }
6183       cc=get_reg(branch_regs[i].regmap,CCREG);
6184       if(cc==-1&&!likely[i]) {
6185         // Cycle count isn't in a register, temporarily load it then write it out
6186         emit_loadreg(CCREG,HOST_CCREG);
6187         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6188         int jaddr=(int)out;
6189         emit_jns(0);
6190         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6191         emit_storereg(CCREG,HOST_CCREG);
6192       }
6193       else{
6194         cc=get_reg(i_regmap,CCREG);
6195         assert(cc==HOST_CCREG);
6196         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6197         int jaddr=(int)out;
6198         emit_jns(0);
6199         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6200       }
6201     }
6202   }
6203 }
6204
6205 void fjump_assemble(int i,struct regstat *i_regs)
6206 {
6207   signed char *i_regmap=i_regs->regmap;
6208   int cc;
6209   int match;
6210   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6211   assem_debug("fmatch=%d\n",match);
6212   int fs,cs;
6213   int eaddr;
6214   int invert=0;
6215   int internal=internal_branch(branch_regs[i].is32,ba[i]);
6216   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6217   if(!match) invert=1;
6218   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6219   if(i>(ba[i]-start)>>2) invert=1;
6220   #endif
6221
6222   if(ooo[i]) {
6223     fs=get_reg(branch_regs[i].regmap,FSREG);
6224     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6225   }
6226   else {
6227     fs=get_reg(i_regmap,FSREG);
6228   }
6229
6230   // Check cop1 unusable
6231   if(!cop1_usable) {
6232     cs=get_reg(i_regmap,CSREG);
6233     assert(cs>=0);
6234     emit_testimm(cs,0x20000000);
6235     eaddr=(int)out;
6236     emit_jeq(0);
6237     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6238     cop1_usable=1;
6239   }
6240
6241   if(ooo[i]) {
6242     // Out of order execution (delay slot first)
6243     //printf("OOOE\n");
6244     ds_assemble(i+1,i_regs);
6245     int adj;
6246     uint64_t bc_unneeded=branch_regs[i].u;
6247     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6248     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6249     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6250     bc_unneeded|=1;
6251     bc_unneeded_upper|=1;
6252     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6253                   bc_unneeded,bc_unneeded_upper);
6254     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6255     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6256     cc=get_reg(branch_regs[i].regmap,CCREG);
6257     assert(cc==HOST_CCREG);
6258     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6259     assem_debug("cycle count (adj)\n");
6260     if(1) {
6261       int nottaken=0;
6262       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6263       if(1) {
6264         assert(fs>=0);
6265         emit_testimm(fs,0x800000);
6266         if(source[i]&0x10000) // BC1T
6267         {
6268           if(invert){
6269             nottaken=(int)out;
6270             emit_jeq(1);
6271           }else{
6272             add_to_linker((int)out,ba[i],internal);
6273             emit_jne(0);
6274           }
6275         }
6276         else // BC1F
6277           if(invert){
6278             nottaken=(int)out;
6279             emit_jne(1);
6280           }else{
6281             add_to_linker((int)out,ba[i],internal);
6282             emit_jeq(0);
6283           }
6284         {
6285         }
6286       } // if(!only32)
6287
6288       if(invert) {
6289         if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6290         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6291         else if(match) emit_addnop(13);
6292         #endif
6293         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6294         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6295         if(internal)
6296           assem_debug("branch: internal\n");
6297         else
6298           assem_debug("branch: external\n");
6299         if(internal&&is_ds[(ba[i]-start)>>2]) {
6300           ds_assemble_entry(i);
6301         }
6302         else {
6303           add_to_linker((int)out,ba[i],internal);
6304           emit_jmp(0);
6305         }
6306         set_jump_target(nottaken,(int)out);
6307       }
6308
6309       if(adj) {
6310         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6311       }
6312     } // (!unconditional)
6313   } // if(ooo)
6314   else
6315   {
6316     // In-order execution (branch first)
6317     //printf("IOE\n");
6318     int nottaken=0;
6319     if(1) {
6320       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6321       if(1) {
6322         assert(fs>=0);
6323         emit_testimm(fs,0x800000);
6324         if(source[i]&0x10000) // BC1T
6325         {
6326           nottaken=(int)out;
6327           emit_jeq(1);
6328         }
6329         else // BC1F
6330         {
6331           nottaken=(int)out;
6332           emit_jne(1);
6333         }
6334       }
6335     } // if(!unconditional)
6336     int adj;
6337     uint64_t ds_unneeded=branch_regs[i].u;
6338     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6339     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6340     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6341     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6342     ds_unneeded|=1;
6343     ds_unneeded_upper|=1;
6344     // branch taken
6345     //assem_debug("1:\n");
6346     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6347                   ds_unneeded,ds_unneeded_upper);
6348     // load regs
6349     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6350     address_generation(i+1,&branch_regs[i],0);
6351     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6352     ds_assemble(i+1,&branch_regs[i]);
6353     cc=get_reg(branch_regs[i].regmap,CCREG);
6354     if(cc==-1) {
6355       emit_loadreg(CCREG,cc=HOST_CCREG);
6356       // CHECK: Is the following instruction (fall thru) allocated ok?
6357     }
6358     assert(cc==HOST_CCREG);
6359     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6360     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6361     assem_debug("cycle count (adj)\n");
6362     if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6363     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6364     if(internal)
6365       assem_debug("branch: internal\n");
6366     else
6367       assem_debug("branch: external\n");
6368     if(internal&&is_ds[(ba[i]-start)>>2]) {
6369       ds_assemble_entry(i);
6370     }
6371     else {
6372       add_to_linker((int)out,ba[i],internal);
6373       emit_jmp(0);
6374     }
6375
6376     // branch not taken
6377     if(1) { // <- FIXME (don't need this)
6378       set_jump_target(nottaken,(int)out);
6379       assem_debug("1:\n");
6380       if(!likely[i]) {
6381         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6382                       ds_unneeded,ds_unneeded_upper);
6383         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6384         address_generation(i+1,&branch_regs[i],0);
6385         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6386         ds_assemble(i+1,&branch_regs[i]);
6387       }
6388       cc=get_reg(branch_regs[i].regmap,CCREG);
6389       if(cc==-1&&!likely[i]) {
6390         // Cycle count isn't in a register, temporarily load it then write it out
6391         emit_loadreg(CCREG,HOST_CCREG);
6392         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6393         int jaddr=(int)out;
6394         emit_jns(0);
6395         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6396         emit_storereg(CCREG,HOST_CCREG);
6397       }
6398       else{
6399         cc=get_reg(i_regmap,CCREG);
6400         assert(cc==HOST_CCREG);
6401         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6402         int jaddr=(int)out;
6403         emit_jns(0);
6404         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6405       }
6406     }
6407   }
6408 }
6409
6410 static void pagespan_assemble(int i,struct regstat *i_regs)
6411 {
6412   int s1l=get_reg(i_regs->regmap,rs1[i]);
6413   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6414   int s2l=get_reg(i_regs->regmap,rs2[i]);
6415   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6416   void *nt_branch=NULL;
6417   int taken=0;
6418   int nottaken=0;
6419   int unconditional=0;
6420   if(rs1[i]==0)
6421   {
6422     s1l=s2l;s1h=s2h;
6423     s2l=s2h=-1;
6424   }
6425   else if(rs2[i]==0)
6426   {
6427     s2l=s2h=-1;
6428   }
6429   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6430     s1h=s2h=-1;
6431   }
6432   int hr=0;
6433   int addr,alt,ntaddr;
6434   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6435   else {
6436     while(hr<HOST_REGS)
6437     {
6438       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6439          (i_regs->regmap[hr]&63)!=rs1[i] &&
6440          (i_regs->regmap[hr]&63)!=rs2[i] )
6441       {
6442         addr=hr++;break;
6443       }
6444       hr++;
6445     }
6446   }
6447   while(hr<HOST_REGS)
6448   {
6449     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6450        (i_regs->regmap[hr]&63)!=rs1[i] &&
6451        (i_regs->regmap[hr]&63)!=rs2[i] )
6452     {
6453       alt=hr++;break;
6454     }
6455     hr++;
6456   }
6457   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6458   {
6459     while(hr<HOST_REGS)
6460     {
6461       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6462          (i_regs->regmap[hr]&63)!=rs1[i] &&
6463          (i_regs->regmap[hr]&63)!=rs2[i] )
6464       {
6465         ntaddr=hr;break;
6466       }
6467       hr++;
6468     }
6469   }
6470   assert(hr<HOST_REGS);
6471   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6472     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6473   }
6474   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6475   if(opcode[i]==2) // J
6476   {
6477     unconditional=1;
6478   }
6479   if(opcode[i]==3) // JAL
6480   {
6481     // TODO: mini_ht
6482     int rt=get_reg(i_regs->regmap,31);
6483     emit_movimm(start+i*4+8,rt);
6484     unconditional=1;
6485   }
6486   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6487   {
6488     emit_mov(s1l,addr);
6489     if(opcode2[i]==9) // JALR
6490     {
6491       int rt=get_reg(i_regs->regmap,rt1[i]);
6492       emit_movimm(start+i*4+8,rt);
6493     }
6494   }
6495   if((opcode[i]&0x3f)==4) // BEQ
6496   {
6497     if(rs1[i]==rs2[i])
6498     {
6499       unconditional=1;
6500     }
6501     else
6502     #ifdef HAVE_CMOV_IMM
6503     if(s1h<0) {
6504       if(s2l>=0) emit_cmp(s1l,s2l);
6505       else emit_test(s1l,s1l);
6506       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6507     }
6508     else
6509     #endif
6510     {
6511       assert(s1l>=0);
6512       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6513       if(s1h>=0) {
6514         if(s2h>=0) emit_cmp(s1h,s2h);
6515         else emit_test(s1h,s1h);
6516         emit_cmovne_reg(alt,addr);
6517       }
6518       if(s2l>=0) emit_cmp(s1l,s2l);
6519       else emit_test(s1l,s1l);
6520       emit_cmovne_reg(alt,addr);
6521     }
6522   }
6523   if((opcode[i]&0x3f)==5) // BNE
6524   {
6525     #ifdef HAVE_CMOV_IMM
6526     if(s1h<0) {
6527       if(s2l>=0) emit_cmp(s1l,s2l);
6528       else emit_test(s1l,s1l);
6529       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6530     }
6531     else
6532     #endif
6533     {
6534       assert(s1l>=0);
6535       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6536       if(s1h>=0) {
6537         if(s2h>=0) emit_cmp(s1h,s2h);
6538         else emit_test(s1h,s1h);
6539         emit_cmovne_reg(alt,addr);
6540       }
6541       if(s2l>=0) emit_cmp(s1l,s2l);
6542       else emit_test(s1l,s1l);
6543       emit_cmovne_reg(alt,addr);
6544     }
6545   }
6546   if((opcode[i]&0x3f)==0x14) // BEQL
6547   {
6548     if(s1h>=0) {
6549       if(s2h>=0) emit_cmp(s1h,s2h);
6550       else emit_test(s1h,s1h);
6551       nottaken=(int)out;
6552       emit_jne(0);
6553     }
6554     if(s2l>=0) emit_cmp(s1l,s2l);
6555     else emit_test(s1l,s1l);
6556     if(nottaken) set_jump_target(nottaken,(int)out);
6557     nottaken=(int)out;
6558     emit_jne(0);
6559   }
6560   if((opcode[i]&0x3f)==0x15) // BNEL
6561   {
6562     if(s1h>=0) {
6563       if(s2h>=0) emit_cmp(s1h,s2h);
6564       else emit_test(s1h,s1h);
6565       taken=(int)out;
6566       emit_jne(0);
6567     }
6568     if(s2l>=0) emit_cmp(s1l,s2l);
6569     else emit_test(s1l,s1l);
6570     nottaken=(int)out;
6571     emit_jeq(0);
6572     if(taken) set_jump_target(taken,(int)out);
6573   }
6574   if((opcode[i]&0x3f)==6) // BLEZ
6575   {
6576     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6577     emit_cmpimm(s1l,1);
6578     if(s1h>=0) emit_mov(addr,ntaddr);
6579     emit_cmovl_reg(alt,addr);
6580     if(s1h>=0) {
6581       emit_test(s1h,s1h);
6582       emit_cmovne_reg(ntaddr,addr);
6583       emit_cmovs_reg(alt,addr);
6584     }
6585   }
6586   if((opcode[i]&0x3f)==7) // BGTZ
6587   {
6588     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6589     emit_cmpimm(s1l,1);
6590     if(s1h>=0) emit_mov(addr,alt);
6591     emit_cmovl_reg(ntaddr,addr);
6592     if(s1h>=0) {
6593       emit_test(s1h,s1h);
6594       emit_cmovne_reg(alt,addr);
6595       emit_cmovs_reg(ntaddr,addr);
6596     }
6597   }
6598   if((opcode[i]&0x3f)==0x16) // BLEZL
6599   {
6600     assert((opcode[i]&0x3f)!=0x16);
6601   }
6602   if((opcode[i]&0x3f)==0x17) // BGTZL
6603   {
6604     assert((opcode[i]&0x3f)!=0x17);
6605   }
6606   assert(opcode[i]!=1); // BLTZ/BGEZ
6607
6608   //FIXME: Check CSREG
6609   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6610     if((source[i]&0x30000)==0) // BC1F
6611     {
6612       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6613       emit_testimm(s1l,0x800000);
6614       emit_cmovne_reg(alt,addr);
6615     }
6616     if((source[i]&0x30000)==0x10000) // BC1T
6617     {
6618       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6619       emit_testimm(s1l,0x800000);
6620       emit_cmovne_reg(alt,addr);
6621     }
6622     if((source[i]&0x30000)==0x20000) // BC1FL
6623     {
6624       emit_testimm(s1l,0x800000);
6625       nottaken=(int)out;
6626       emit_jne(0);
6627     }
6628     if((source[i]&0x30000)==0x30000) // BC1TL
6629     {
6630       emit_testimm(s1l,0x800000);
6631       nottaken=(int)out;
6632       emit_jeq(0);
6633     }
6634   }
6635
6636   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6637   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6638   if(likely[i]||unconditional)
6639   {
6640     emit_movimm(ba[i],HOST_BTREG);
6641   }
6642   else if(addr!=HOST_BTREG)
6643   {
6644     emit_mov(addr,HOST_BTREG);
6645   }
6646   void *branch_addr=out;
6647   emit_jmp(0);
6648   int target_addr=start+i*4+5;
6649   void *stub=out;
6650   void *compiled_target_addr=check_addr(target_addr);
6651   emit_extjump_ds((int)branch_addr,target_addr);
6652   if(compiled_target_addr) {
6653     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6654     add_link(target_addr,stub);
6655   }
6656   else set_jump_target((int)branch_addr,(int)stub);
6657   if(likely[i]) {
6658     // Not-taken path
6659     set_jump_target((int)nottaken,(int)out);
6660     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6661     void *branch_addr=out;
6662     emit_jmp(0);
6663     int target_addr=start+i*4+8;
6664     void *stub=out;
6665     void *compiled_target_addr=check_addr(target_addr);
6666     emit_extjump_ds((int)branch_addr,target_addr);
6667     if(compiled_target_addr) {
6668       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6669       add_link(target_addr,stub);
6670     }
6671     else set_jump_target((int)branch_addr,(int)stub);
6672   }
6673 }
6674
6675 // Assemble the delay slot for the above
6676 static void pagespan_ds()
6677 {
6678   assem_debug("initial delay slot:\n");
6679   u_int vaddr=start+1;
6680   u_int page=get_page(vaddr);
6681   u_int vpage=get_vpage(vaddr);
6682   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6683   do_dirty_stub_ds();
6684   ll_add(jump_in+page,vaddr,(void *)out);
6685   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6686   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6687     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6688   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6689     emit_writeword(HOST_BTREG,(int)&branch_target);
6690   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6691   address_generation(0,&regs[0],regs[0].regmap_entry);
6692   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6693     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6694   cop1_usable=0;
6695   is_delayslot=0;
6696   switch(itype[0]) {
6697     case ALU:
6698       alu_assemble(0,&regs[0]);break;
6699     case IMM16:
6700       imm16_assemble(0,&regs[0]);break;
6701     case SHIFT:
6702       shift_assemble(0,&regs[0]);break;
6703     case SHIFTIMM:
6704       shiftimm_assemble(0,&regs[0]);break;
6705     case LOAD:
6706       load_assemble(0,&regs[0]);break;
6707     case LOADLR:
6708       loadlr_assemble(0,&regs[0]);break;
6709     case STORE:
6710       store_assemble(0,&regs[0]);break;
6711     case STORELR:
6712       storelr_assemble(0,&regs[0]);break;
6713     case COP0:
6714       cop0_assemble(0,&regs[0]);break;
6715     case COP1:
6716       cop1_assemble(0,&regs[0]);break;
6717     case C1LS:
6718       c1ls_assemble(0,&regs[0]);break;
6719     case COP2:
6720       cop2_assemble(0,&regs[0]);break;
6721     case C2LS:
6722       c2ls_assemble(0,&regs[0]);break;
6723     case C2OP:
6724       c2op_assemble(0,&regs[0]);break;
6725     case FCONV:
6726       fconv_assemble(0,&regs[0]);break;
6727     case FLOAT:
6728       float_assemble(0,&regs[0]);break;
6729     case FCOMP:
6730       fcomp_assemble(0,&regs[0]);break;
6731     case MULTDIV:
6732       multdiv_assemble(0,&regs[0]);break;
6733     case MOV:
6734       mov_assemble(0,&regs[0]);break;
6735     case SYSCALL:
6736     case HLECALL:
6737     case INTCALL:
6738     case SPAN:
6739     case UJUMP:
6740     case RJUMP:
6741     case CJUMP:
6742     case SJUMP:
6743     case FJUMP:
6744       printf("Jump in the delay slot.  This is probably a bug.\n");
6745   }
6746   int btaddr=get_reg(regs[0].regmap,BTREG);
6747   if(btaddr<0) {
6748     btaddr=get_reg(regs[0].regmap,-1);
6749     emit_readword((int)&branch_target,btaddr);
6750   }
6751   assert(btaddr!=HOST_CCREG);
6752   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6753 #ifdef HOST_IMM8
6754   emit_movimm(start+4,HOST_TEMPREG);
6755   emit_cmp(btaddr,HOST_TEMPREG);
6756 #else
6757   emit_cmpimm(btaddr,start+4);
6758 #endif
6759   int branch=(int)out;
6760   emit_jeq(0);
6761   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6762   emit_jmp(jump_vaddr_reg[btaddr]);
6763   set_jump_target(branch,(int)out);
6764   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6765   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6766 }
6767
6768 // Basic liveness analysis for MIPS registers
6769 void unneeded_registers(int istart,int iend,int r)
6770 {
6771   int i;
6772   uint64_t u,uu,gte_u,b,bu,gte_bu;
6773   uint64_t temp_u,temp_uu,temp_gte_u;
6774   uint64_t tdep;
6775   if(iend==slen-1) {
6776     u=1;uu=1;
6777   }else{
6778     u=unneeded_reg[iend+1];
6779     uu=unneeded_reg_upper[iend+1];
6780     u=1;uu=1;
6781   }
6782   gte_u=temp_gte_u=0;
6783
6784   for (i=iend;i>=istart;i--)
6785   {
6786     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6787     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6788     {
6789       // If subroutine call, flag return address as a possible branch target
6790       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6791
6792       if(ba[i]<start || ba[i]>=(start+slen*4))
6793       {
6794         // Branch out of this block, flush all regs
6795         u=1;
6796         uu=1;
6797         gte_u=0;
6798         /* Hexagon hack
6799         if(itype[i]==UJUMP&&rt1[i]==31)
6800         {
6801           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6802         }
6803         if(itype[i]==RJUMP&&rs1[i]==31)
6804         {
6805           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6806         }
6807         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6808           if(itype[i]==UJUMP&&rt1[i]==31)
6809           {
6810             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6811             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6812           }
6813           if(itype[i]==RJUMP&&rs1[i]==31)
6814           {
6815             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6816             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6817           }
6818         }*/
6819         branch_unneeded_reg[i]=u;
6820         branch_unneeded_reg_upper[i]=uu;
6821         // Merge in delay slot
6822         tdep=(~uu>>rt1[i+1])&1;
6823         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6824         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6825         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6826         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6827         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6828         u|=1;uu|=1;
6829         gte_u|=gte_rt[i+1];
6830         gte_u&=~gte_rs[i+1];
6831         // If branch is "likely" (and conditional)
6832         // then we skip the delay slot on the fall-thru path
6833         if(likely[i]) {
6834           if(i<slen-1) {
6835             u&=unneeded_reg[i+2];
6836             uu&=unneeded_reg_upper[i+2];
6837             gte_u&=gte_unneeded[i+2];
6838           }
6839           else
6840           {
6841             u=1;
6842             uu=1;
6843             gte_u=0;
6844           }
6845         }
6846       }
6847       else
6848       {
6849         // Internal branch, flag target
6850         bt[(ba[i]-start)>>2]=1;
6851         if(ba[i]<=start+i*4) {
6852           // Backward branch
6853           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6854           {
6855             // Unconditional branch
6856             temp_u=1;temp_uu=1;
6857             temp_gte_u=0;
6858           } else {
6859             // Conditional branch (not taken case)
6860             temp_u=unneeded_reg[i+2];
6861             temp_uu=unneeded_reg_upper[i+2];
6862             temp_gte_u&=gte_unneeded[i+2];
6863           }
6864           // Merge in delay slot
6865           tdep=(~temp_uu>>rt1[i+1])&1;
6866           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6867           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6868           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6869           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6870           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6871           temp_u|=1;temp_uu|=1;
6872           temp_gte_u|=gte_rt[i+1];
6873           temp_gte_u&=~gte_rs[i+1];
6874           // If branch is "likely" (and conditional)
6875           // then we skip the delay slot on the fall-thru path
6876           if(likely[i]) {
6877             if(i<slen-1) {
6878               temp_u&=unneeded_reg[i+2];
6879               temp_uu&=unneeded_reg_upper[i+2];
6880               temp_gte_u&=gte_unneeded[i+2];
6881             }
6882             else
6883             {
6884               temp_u=1;
6885               temp_uu=1;
6886               temp_gte_u=0;
6887             }
6888           }
6889           tdep=(~temp_uu>>rt1[i])&1;
6890           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6891           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6892           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6893           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6894           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6895           temp_u|=1;temp_uu|=1;
6896           temp_gte_u|=gte_rt[i];
6897           temp_gte_u&=~gte_rs[i];
6898           unneeded_reg[i]=temp_u;
6899           unneeded_reg_upper[i]=temp_uu;
6900           gte_unneeded[i]=temp_gte_u;
6901           // Only go three levels deep.  This recursion can take an
6902           // excessive amount of time if there are a lot of nested loops.
6903           if(r<2) {
6904             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6905           }else{
6906             unneeded_reg[(ba[i]-start)>>2]=1;
6907             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6908             gte_unneeded[(ba[i]-start)>>2]=0;
6909           }
6910         } /*else*/ if(1) {
6911           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6912           {
6913             // Unconditional branch
6914             u=unneeded_reg[(ba[i]-start)>>2];
6915             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6916             gte_u=gte_unneeded[(ba[i]-start)>>2];
6917             branch_unneeded_reg[i]=u;
6918             branch_unneeded_reg_upper[i]=uu;
6919         //u=1;
6920         //uu=1;
6921         //branch_unneeded_reg[i]=u;
6922         //branch_unneeded_reg_upper[i]=uu;
6923             // Merge in delay slot
6924             tdep=(~uu>>rt1[i+1])&1;
6925             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6926             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6927             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6928             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6929             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6930             u|=1;uu|=1;
6931             gte_u|=gte_rt[i+1];
6932             gte_u&=~gte_rs[i+1];
6933           } else {
6934             // Conditional branch
6935             b=unneeded_reg[(ba[i]-start)>>2];
6936             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6937             gte_bu=gte_unneeded[(ba[i]-start)>>2];
6938             branch_unneeded_reg[i]=b;
6939             branch_unneeded_reg_upper[i]=bu;
6940         //b=1;
6941         //bu=1;
6942         //branch_unneeded_reg[i]=b;
6943         //branch_unneeded_reg_upper[i]=bu;
6944             // Branch delay slot
6945             tdep=(~uu>>rt1[i+1])&1;
6946             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6947             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6948             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6949             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6950             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6951             b|=1;bu|=1;
6952             gte_bu|=gte_rt[i+1];
6953             gte_bu&=~gte_rs[i+1];
6954             // If branch is "likely" then we skip the
6955             // delay slot on the fall-thru path
6956             if(likely[i]) {
6957               u=b;
6958               uu=bu;
6959               gte_u=gte_bu;
6960               if(i<slen-1) {
6961                 u&=unneeded_reg[i+2];
6962                 uu&=unneeded_reg_upper[i+2];
6963                 gte_u&=gte_unneeded[i+2];
6964         //u=1;
6965         //uu=1;
6966               }
6967             } else {
6968               u&=b;
6969               uu&=bu;
6970               gte_u&=gte_bu;
6971         //u=1;
6972         //uu=1;
6973             }
6974             if(i<slen-1) {
6975               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6976               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6977         //branch_unneeded_reg[i]=1;
6978         //branch_unneeded_reg_upper[i]=1;
6979             } else {
6980               branch_unneeded_reg[i]=1;
6981               branch_unneeded_reg_upper[i]=1;
6982             }
6983           }
6984         }
6985       }
6986     }
6987     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6988     {
6989       // SYSCALL instruction (software interrupt)
6990       u=1;
6991       uu=1;
6992     }
6993     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6994     {
6995       // ERET instruction (return from interrupt)
6996       u=1;
6997       uu=1;
6998     }
6999     //u=uu=1; // DEBUG
7000     tdep=(~uu>>rt1[i])&1;
7001     // Written registers are unneeded
7002     u|=1LL<<rt1[i];
7003     u|=1LL<<rt2[i];
7004     uu|=1LL<<rt1[i];
7005     uu|=1LL<<rt2[i];
7006     gte_u|=gte_rt[i];
7007     // Accessed registers are needed
7008     u&=~(1LL<<rs1[i]);
7009     u&=~(1LL<<rs2[i]);
7010     uu&=~(1LL<<us1[i]);
7011     uu&=~(1LL<<us2[i]);
7012     gte_u&=~gte_rs[i];
7013     // Source-target dependencies
7014     uu&=~(tdep<<dep1[i]);
7015     uu&=~(tdep<<dep2[i]);
7016     // R0 is always unneeded
7017     u|=1;uu|=1;
7018     // Save it
7019     unneeded_reg[i]=u;
7020     unneeded_reg_upper[i]=uu;
7021     gte_unneeded[i]=gte_u;
7022     /*
7023     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7024     printf("U:");
7025     int r;
7026     for(r=1;r<=CCREG;r++) {
7027       if((unneeded_reg[i]>>r)&1) {
7028         if(r==HIREG) printf(" HI");
7029         else if(r==LOREG) printf(" LO");
7030         else printf(" r%d",r);
7031       }
7032     }
7033     printf(" UU:");
7034     for(r=1;r<=CCREG;r++) {
7035       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7036         if(r==HIREG) printf(" HI");
7037         else if(r==LOREG) printf(" LO");
7038         else printf(" r%d",r);
7039       }
7040     }
7041     printf("\n");*/
7042   }
7043 #ifdef FORCE32
7044   for (i=iend;i>=istart;i--)
7045   {
7046     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7047   }
7048 #endif
7049 }
7050
7051 // Identify registers which are likely to contain 32-bit values
7052 // This is used to predict whether any branches will jump to a
7053 // location with 64-bit values in registers.
7054 static void provisional_32bit()
7055 {
7056   int i,j;
7057   uint64_t is32=1;
7058   uint64_t lastbranch=1;
7059
7060   for(i=0;i<slen;i++)
7061   {
7062     if(i>0) {
7063       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7064         if(i>1) is32=lastbranch;
7065         else is32=1;
7066       }
7067     }
7068     if(i>1)
7069     {
7070       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7071         if(likely[i-2]) {
7072           if(i>2) is32=lastbranch;
7073           else is32=1;
7074         }
7075       }
7076       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7077       {
7078         if(rs1[i-2]==0||rs2[i-2]==0)
7079         {
7080           if(rs1[i-2]) {
7081             is32|=1LL<<rs1[i-2];
7082           }
7083           if(rs2[i-2]) {
7084             is32|=1LL<<rs2[i-2];
7085           }
7086         }
7087       }
7088     }
7089     // If something jumps here with 64-bit values
7090     // then promote those registers to 64 bits
7091     if(bt[i])
7092     {
7093       uint64_t temp_is32=is32;
7094       for(j=i-1;j>=0;j--)
7095       {
7096         if(ba[j]==start+i*4)
7097           //temp_is32&=branch_regs[j].is32;
7098           temp_is32&=p32[j];
7099       }
7100       for(j=i;j<slen;j++)
7101       {
7102         if(ba[j]==start+i*4)
7103           temp_is32=1;
7104       }
7105       is32=temp_is32;
7106     }
7107     int type=itype[i];
7108     int op=opcode[i];
7109     int op2=opcode2[i];
7110     int rt=rt1[i];
7111     int s1=rs1[i];
7112     int s2=rs2[i];
7113     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7114       // Branches don't write registers, consider the delay slot instead.
7115       type=itype[i+1];
7116       op=opcode[i+1];
7117       op2=opcode2[i+1];
7118       rt=rt1[i+1];
7119       s1=rs1[i+1];
7120       s2=rs2[i+1];
7121       lastbranch=is32;
7122     }
7123     switch(type) {
7124       case LOAD:
7125         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7126            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7127           is32&=~(1LL<<rt);
7128         else
7129           is32|=1LL<<rt;
7130         break;
7131       case STORE:
7132       case STORELR:
7133         break;
7134       case LOADLR:
7135         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7136         if(op==0x22) is32|=1LL<<rt; // LWL
7137         break;
7138       case IMM16:
7139         if (op==0x08||op==0x09|| // ADDI/ADDIU
7140             op==0x0a||op==0x0b|| // SLTI/SLTIU
7141             op==0x0c|| // ANDI
7142             op==0x0f)  // LUI
7143         {
7144           is32|=1LL<<rt;
7145         }
7146         if(op==0x18||op==0x19) { // DADDI/DADDIU
7147           is32&=~(1LL<<rt);
7148           //if(imm[i]==0)
7149           //  is32|=((is32>>s1)&1LL)<<rt;
7150         }
7151         if(op==0x0d||op==0x0e) { // ORI/XORI
7152           uint64_t sr=((is32>>s1)&1LL);
7153           is32&=~(1LL<<rt);
7154           is32|=sr<<rt;
7155         }
7156         break;
7157       case UJUMP:
7158         break;
7159       case RJUMP:
7160         break;
7161       case CJUMP:
7162         break;
7163       case SJUMP:
7164         break;
7165       case FJUMP:
7166         break;
7167       case ALU:
7168         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7169           is32|=1LL<<rt;
7170         }
7171         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7172           is32|=1LL<<rt;
7173         }
7174         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7175           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7176           is32&=~(1LL<<rt);
7177           is32|=sr<<rt;
7178         }
7179         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7180           if(s1==0&&s2==0) {
7181             is32|=1LL<<rt;
7182           }
7183           else if(s2==0) {
7184             uint64_t sr=((is32>>s1)&1LL);
7185             is32&=~(1LL<<rt);
7186             is32|=sr<<rt;
7187           }
7188           else if(s1==0) {
7189             uint64_t sr=((is32>>s2)&1LL);
7190             is32&=~(1LL<<rt);
7191             is32|=sr<<rt;
7192           }
7193           else {
7194             is32&=~(1LL<<rt);
7195           }
7196         }
7197         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7198           if(s1==0&&s2==0) {
7199             is32|=1LL<<rt;
7200           }
7201           else if(s2==0) {
7202             uint64_t sr=((is32>>s1)&1LL);
7203             is32&=~(1LL<<rt);
7204             is32|=sr<<rt;
7205           }
7206           else {
7207             is32&=~(1LL<<rt);
7208           }
7209         }
7210         break;
7211       case MULTDIV:
7212         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7213           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7214         }
7215         else {
7216           is32|=(1LL<<HIREG)|(1LL<<LOREG);
7217         }
7218         break;
7219       case MOV:
7220         {
7221           uint64_t sr=((is32>>s1)&1LL);
7222           is32&=~(1LL<<rt);
7223           is32|=sr<<rt;
7224         }
7225         break;
7226       case SHIFT:
7227         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7228         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7229         break;
7230       case SHIFTIMM:
7231         is32|=1LL<<rt;
7232         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7233         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7234         break;
7235       case COP0:
7236         if(op2==0) is32|=1LL<<rt; // MFC0
7237         break;
7238       case COP1:
7239       case COP2:
7240         if(op2==0) is32|=1LL<<rt; // MFC1
7241         if(op2==1) is32&=~(1LL<<rt); // DMFC1
7242         if(op2==2) is32|=1LL<<rt; // CFC1
7243         break;
7244       case C1LS:
7245       case C2LS:
7246         break;
7247       case FLOAT:
7248       case FCONV:
7249         break;
7250       case FCOMP:
7251         break;
7252       case C2OP:
7253       case SYSCALL:
7254       case HLECALL:
7255         break;
7256       default:
7257         break;
7258     }
7259     is32|=1;
7260     p32[i]=is32;
7261
7262     if(i>0)
7263     {
7264       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7265       {
7266         if(rt1[i-1]==31) // JAL/JALR
7267         {
7268           // Subroutine call will return here, don't alloc any registers
7269           is32=1;
7270         }
7271         else if(i+1<slen)
7272         {
7273           // Internal branch will jump here, match registers to caller
7274           is32=0x3FFFFFFFFLL;
7275         }
7276       }
7277     }
7278   }
7279 }
7280
7281 // Identify registers which may be assumed to contain 32-bit values
7282 // and where optimizations will rely on this.
7283 // This is used to determine whether backward branches can safely
7284 // jump to a location with 64-bit values in registers.
7285 static void provisional_r32()
7286 {
7287   u_int r32=0;
7288   int i;
7289
7290   for (i=slen-1;i>=0;i--)
7291   {
7292     int hr;
7293     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7294     {
7295       if(ba[i]<start || ba[i]>=(start+slen*4))
7296       {
7297         // Branch out of this block, don't need anything
7298         r32=0;
7299       }
7300       else
7301       {
7302         // Internal branch
7303         // Need whatever matches the target
7304         // (and doesn't get overwritten by the delay slot instruction)
7305         r32=0;
7306         int t=(ba[i]-start)>>2;
7307         if(ba[i]>start+i*4) {
7308           // Forward branch
7309           //if(!(requires_32bit[t]&~regs[i].was32))
7310           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7311           if(!(pr32[t]&~regs[i].was32))
7312             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7313         }else{
7314           // Backward branch
7315           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7316             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7317         }
7318       }
7319       // Conditional branch may need registers for following instructions
7320       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7321       {
7322         if(i<slen-2) {
7323           //r32|=requires_32bit[i+2];
7324           r32|=pr32[i+2];
7325           r32&=regs[i].was32;
7326           // Mark this address as a branch target since it may be called
7327           // upon return from interrupt
7328           //bt[i+2]=1;
7329         }
7330       }
7331       // Merge in delay slot
7332       if(!likely[i]) {
7333         // These are overwritten unless the branch is "likely"
7334         // and the delay slot is nullified if not taken
7335         r32&=~(1LL<<rt1[i+1]);
7336         r32&=~(1LL<<rt2[i+1]);
7337       }
7338       // Assume these are needed (delay slot)
7339       if(us1[i+1]>0)
7340       {
7341         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7342       }
7343       if(us2[i+1]>0)
7344       {
7345         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7346       }
7347       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7348       {
7349         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7350       }
7351       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7352       {
7353         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7354       }
7355     }
7356     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7357     {
7358       // SYSCALL instruction (software interrupt)
7359       r32=0;
7360     }
7361     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7362     {
7363       // ERET instruction (return from interrupt)
7364       r32=0;
7365     }
7366     // Check 32 bits
7367     r32&=~(1LL<<rt1[i]);
7368     r32&=~(1LL<<rt2[i]);
7369     if(us1[i]>0)
7370     {
7371       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7372     }
7373     if(us2[i]>0)
7374     {
7375       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7376     }
7377     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7378     {
7379       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7380     }
7381     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7382     {
7383       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7384     }
7385     //requires_32bit[i]=r32;
7386     pr32[i]=r32;
7387
7388     // Dirty registers which are 32-bit, require 32-bit input
7389     // as they will be written as 32-bit values
7390     for(hr=0;hr<HOST_REGS;hr++)
7391     {
7392       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7393         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7394           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7395           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7396           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7397         }
7398       }
7399     }
7400   }
7401 }
7402
7403 // Write back dirty registers as soon as we will no longer modify them,
7404 // so that we don't end up with lots of writes at the branches.
7405 void clean_registers(int istart,int iend,int wr)
7406 {
7407   int i;
7408   int r;
7409   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7410   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7411   if(iend==slen-1) {
7412     will_dirty_i=will_dirty_next=0;
7413     wont_dirty_i=wont_dirty_next=0;
7414   }else{
7415     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7416     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7417   }
7418   for (i=iend;i>=istart;i--)
7419   {
7420     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7421     {
7422       if(ba[i]<start || ba[i]>=(start+slen*4))
7423       {
7424         // Branch out of this block, flush all regs
7425         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7426         {
7427           // Unconditional branch
7428           will_dirty_i=0;
7429           wont_dirty_i=0;
7430           // Merge in delay slot (will dirty)
7431           for(r=0;r<HOST_REGS;r++) {
7432             if(r!=EXCLUDE_REG) {
7433               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7434               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7435               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7436               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7437               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7438               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7439               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7440               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7441               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7442               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7443               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7444               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7445               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7446               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7447             }
7448           }
7449         }
7450         else
7451         {
7452           // Conditional branch
7453           will_dirty_i=0;
7454           wont_dirty_i=wont_dirty_next;
7455           // Merge in delay slot (will dirty)
7456           for(r=0;r<HOST_REGS;r++) {
7457             if(r!=EXCLUDE_REG) {
7458               if(!likely[i]) {
7459                 // Might not dirty if likely branch is not taken
7460                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7461                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7462                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7463                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7464                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7465                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7466                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7467                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7468                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7469                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7470                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7471                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7472                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7473                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7474               }
7475             }
7476           }
7477         }
7478         // Merge in delay slot (wont dirty)
7479         for(r=0;r<HOST_REGS;r++) {
7480           if(r!=EXCLUDE_REG) {
7481             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7482             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7483             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7484             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7485             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7486             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7487             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7488             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7489             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7490             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7491           }
7492         }
7493         if(wr) {
7494           #ifndef DESTRUCTIVE_WRITEBACK
7495           branch_regs[i].dirty&=wont_dirty_i;
7496           #endif
7497           branch_regs[i].dirty|=will_dirty_i;
7498         }
7499       }
7500       else
7501       {
7502         // Internal branch
7503         if(ba[i]<=start+i*4) {
7504           // Backward branch
7505           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7506           {
7507             // Unconditional branch
7508             temp_will_dirty=0;
7509             temp_wont_dirty=0;
7510             // Merge in delay slot (will dirty)
7511             for(r=0;r<HOST_REGS;r++) {
7512               if(r!=EXCLUDE_REG) {
7513                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7514                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7515                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7516                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7517                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7518                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7519                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7520                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7521                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7522                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7523                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7524                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7525                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7526                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7527               }
7528             }
7529           } else {
7530             // Conditional branch (not taken case)
7531             temp_will_dirty=will_dirty_next;
7532             temp_wont_dirty=wont_dirty_next;
7533             // Merge in delay slot (will dirty)
7534             for(r=0;r<HOST_REGS;r++) {
7535               if(r!=EXCLUDE_REG) {
7536                 if(!likely[i]) {
7537                   // Will not dirty if likely branch is not taken
7538                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7539                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7540                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7541                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7542                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7543                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7544                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7545                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7546                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7547                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7548                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7549                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7550                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7551                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7552                 }
7553               }
7554             }
7555           }
7556           // Merge in delay slot (wont dirty)
7557           for(r=0;r<HOST_REGS;r++) {
7558             if(r!=EXCLUDE_REG) {
7559               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7560               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7561               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7562               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7563               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7564               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7565               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7566               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7567               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7568               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7569             }
7570           }
7571           // Deal with changed mappings
7572           if(i<iend) {
7573             for(r=0;r<HOST_REGS;r++) {
7574               if(r!=EXCLUDE_REG) {
7575                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7576                   temp_will_dirty&=~(1<<r);
7577                   temp_wont_dirty&=~(1<<r);
7578                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7579                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7580                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7581                   } else {
7582                     temp_will_dirty|=1<<r;
7583                     temp_wont_dirty|=1<<r;
7584                   }
7585                 }
7586               }
7587             }
7588           }
7589           if(wr) {
7590             will_dirty[i]=temp_will_dirty;
7591             wont_dirty[i]=temp_wont_dirty;
7592             clean_registers((ba[i]-start)>>2,i-1,0);
7593           }else{
7594             // Limit recursion.  It can take an excessive amount
7595             // of time if there are a lot of nested loops.
7596             will_dirty[(ba[i]-start)>>2]=0;
7597             wont_dirty[(ba[i]-start)>>2]=-1;
7598           }
7599         }
7600         /*else*/ if(1)
7601         {
7602           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7603           {
7604             // Unconditional branch
7605             will_dirty_i=0;
7606             wont_dirty_i=0;
7607           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7608             for(r=0;r<HOST_REGS;r++) {
7609               if(r!=EXCLUDE_REG) {
7610                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7611                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7612                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7613                 }
7614                 if(branch_regs[i].regmap[r]>=0) {
7615                   will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7616                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7617                 }
7618               }
7619             }
7620           //}
7621             // Merge in delay slot
7622             for(r=0;r<HOST_REGS;r++) {
7623               if(r!=EXCLUDE_REG) {
7624                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7625                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7626                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7627                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7628                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7629                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7630                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7631                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7632                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7633                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7634                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7635                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7636                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7637                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7638               }
7639             }
7640           } else {
7641             // Conditional branch
7642             will_dirty_i=will_dirty_next;
7643             wont_dirty_i=wont_dirty_next;
7644           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7645             for(r=0;r<HOST_REGS;r++) {
7646               if(r!=EXCLUDE_REG) {
7647                 signed char target_reg=branch_regs[i].regmap[r];
7648                 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7649                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7650                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7651                 }
7652                 else if(target_reg>=0) {
7653                   will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7654                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7655                 }
7656                 // Treat delay slot as part of branch too
7657                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7658                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7659                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7660                 }
7661                 else
7662                 {
7663                   will_dirty[i+1]&=~(1<<r);
7664                 }*/
7665               }
7666             }
7667           //}
7668             // Merge in delay slot
7669             for(r=0;r<HOST_REGS;r++) {
7670               if(r!=EXCLUDE_REG) {
7671                 if(!likely[i]) {
7672                   // Might not dirty if likely branch is not taken
7673                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7674                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7675                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7676                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7677                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7678                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7679                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7680                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7681                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7682                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7683                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7684                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7685                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7686                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7687                 }
7688               }
7689             }
7690           }
7691           // Merge in delay slot (won't dirty)
7692           for(r=0;r<HOST_REGS;r++) {
7693             if(r!=EXCLUDE_REG) {
7694               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7695               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7696               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7697               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7698               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7699               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7700               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7701               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7702               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7703               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7704             }
7705           }
7706           if(wr) {
7707             #ifndef DESTRUCTIVE_WRITEBACK
7708             branch_regs[i].dirty&=wont_dirty_i;
7709             #endif
7710             branch_regs[i].dirty|=will_dirty_i;
7711           }
7712         }
7713       }
7714     }
7715     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7716     {
7717       // SYSCALL instruction (software interrupt)
7718       will_dirty_i=0;
7719       wont_dirty_i=0;
7720     }
7721     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7722     {
7723       // ERET instruction (return from interrupt)
7724       will_dirty_i=0;
7725       wont_dirty_i=0;
7726     }
7727     will_dirty_next=will_dirty_i;
7728     wont_dirty_next=wont_dirty_i;
7729     for(r=0;r<HOST_REGS;r++) {
7730       if(r!=EXCLUDE_REG) {
7731         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7732         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7733         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7734         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7735         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7736         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7737         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7738         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7739         if(i>istart) {
7740           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7741           {
7742             // Don't store a register immediately after writing it,
7743             // may prevent dual-issue.
7744             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7745             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7746           }
7747         }
7748       }
7749     }
7750     // Save it
7751     will_dirty[i]=will_dirty_i;
7752     wont_dirty[i]=wont_dirty_i;
7753     // Mark registers that won't be dirtied as not dirty
7754     if(wr) {
7755       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7756       for(r=0;r<HOST_REGS;r++) {
7757         if((will_dirty_i>>r)&1) {
7758           printf(" r%d",r);
7759         }
7760       }
7761       printf("\n");*/
7762
7763       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7764         regs[i].dirty|=will_dirty_i;
7765         #ifndef DESTRUCTIVE_WRITEBACK
7766         regs[i].dirty&=wont_dirty_i;
7767         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7768         {
7769           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7770             for(r=0;r<HOST_REGS;r++) {
7771               if(r!=EXCLUDE_REG) {
7772                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7773                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7774                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7775               }
7776             }
7777           }
7778         }
7779         else
7780         {
7781           if(i<iend) {
7782             for(r=0;r<HOST_REGS;r++) {
7783               if(r!=EXCLUDE_REG) {
7784                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7785                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7786                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7787               }
7788             }
7789           }
7790         }
7791         #endif
7792       //}
7793     }
7794     // Deal with changed mappings
7795     temp_will_dirty=will_dirty_i;
7796     temp_wont_dirty=wont_dirty_i;
7797     for(r=0;r<HOST_REGS;r++) {
7798       if(r!=EXCLUDE_REG) {
7799         int nr;
7800         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7801           if(wr) {
7802             #ifndef DESTRUCTIVE_WRITEBACK
7803             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7804             #endif
7805             regs[i].wasdirty|=will_dirty_i&(1<<r);
7806           }
7807         }
7808         else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7809           // Register moved to a different register
7810           will_dirty_i&=~(1<<r);
7811           wont_dirty_i&=~(1<<r);
7812           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7813           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7814           if(wr) {
7815             #ifndef DESTRUCTIVE_WRITEBACK
7816             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7817             #endif
7818             regs[i].wasdirty|=will_dirty_i&(1<<r);
7819           }
7820         }
7821         else {
7822           will_dirty_i&=~(1<<r);
7823           wont_dirty_i&=~(1<<r);
7824           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7825             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7826             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7827           } else {
7828             wont_dirty_i|=1<<r;
7829             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7830           }
7831         }
7832       }
7833     }
7834   }
7835 }
7836
7837 #ifdef DISASM
7838   /* disassembly */
7839 void disassemble_inst(int i)
7840 {
7841     if (bt[i]) printf("*"); else printf(" ");
7842     switch(itype[i]) {
7843       case UJUMP:
7844         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7845       case CJUMP:
7846         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7847       case SJUMP:
7848         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7849       case FJUMP:
7850         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7851       case RJUMP:
7852         if (opcode[i]==0x9&&rt1[i]!=31)
7853           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7854         else
7855           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7856         break;
7857       case SPAN:
7858         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7859       case IMM16:
7860         if(opcode[i]==0xf) //LUI
7861           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7862         else
7863           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7864         break;
7865       case LOAD:
7866       case LOADLR:
7867         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7868         break;
7869       case STORE:
7870       case STORELR:
7871         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7872         break;
7873       case ALU:
7874       case SHIFT:
7875         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7876         break;
7877       case MULTDIV:
7878         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7879         break;
7880       case SHIFTIMM:
7881         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7882         break;
7883       case MOV:
7884         if((opcode2[i]&0x1d)==0x10)
7885           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7886         else if((opcode2[i]&0x1d)==0x11)
7887           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7888         else
7889           printf (" %x: %s\n",start+i*4,insn[i]);
7890         break;
7891       case COP0:
7892         if(opcode2[i]==0)
7893           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7894         else if(opcode2[i]==4)
7895           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7896         else printf (" %x: %s\n",start+i*4,insn[i]);
7897         break;
7898       case COP1:
7899         if(opcode2[i]<3)
7900           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7901         else if(opcode2[i]>3)
7902           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7903         else printf (" %x: %s\n",start+i*4,insn[i]);
7904         break;
7905       case COP2:
7906         if(opcode2[i]<3)
7907           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7908         else if(opcode2[i]>3)
7909           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7910         else printf (" %x: %s\n",start+i*4,insn[i]);
7911         break;
7912       case C1LS:
7913         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7914         break;
7915       case C2LS:
7916         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7917         break;
7918       case INTCALL:
7919         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7920         break;
7921       default:
7922         //printf (" %s %8x\n",insn[i],source[i]);
7923         printf (" %x: %s\n",start+i*4,insn[i]);
7924     }
7925 }
7926 #else
7927 static void disassemble_inst(int i) {}
7928 #endif // DISASM
7929
7930 // clear the state completely, instead of just marking
7931 // things invalid like invalidate_all_pages() does
7932 void new_dynarec_clear_full()
7933 {
7934   int n;
7935   out=(u_char *)BASE_ADDR;
7936   memset(invalid_code,1,sizeof(invalid_code));
7937   memset(hash_table,0xff,sizeof(hash_table));
7938   memset(mini_ht,-1,sizeof(mini_ht));
7939   memset(restore_candidate,0,sizeof(restore_candidate));
7940   memset(shadow,0,sizeof(shadow));
7941   copy=shadow;
7942   expirep=16384; // Expiry pointer, +2 blocks
7943   pending_exception=0;
7944   literalcount=0;
7945   stop_after_jal=0;
7946   inv_code_start=inv_code_end=~0;
7947   gte_reads_flags=0;
7948   // TLB
7949 #ifndef DISABLE_TLB
7950   using_tlb=0;
7951   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7952     memory_map[n]=-1;
7953   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7954     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7955   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7956     memory_map[n]=-1;
7957 #endif
7958   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7959   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7960   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7961 }
7962
7963 void new_dynarec_init()
7964 {
7965   printf("Init new dynarec\n");
7966   out=(u_char *)BASE_ADDR;
7967   if (mmap (out, 1<<TARGET_SIZE_2,
7968             PROT_READ | PROT_WRITE | PROT_EXEC,
7969             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7970             -1, 0) <= 0) {printf("mmap() failed\n");}
7971 #ifdef MUPEN64
7972   rdword=&readmem_dword;
7973   fake_pc.f.r.rs=&readmem_dword;
7974   fake_pc.f.r.rt=&readmem_dword;
7975   fake_pc.f.r.rd=&readmem_dword;
7976 #endif
7977   int n;
7978   cycle_multiplier=200;
7979   new_dynarec_clear_full();
7980 #ifdef HOST_IMM8
7981   // Copy this into local area so we don't have to put it in every literal pool
7982   invc_ptr=invalid_code;
7983 #endif
7984 #ifdef MUPEN64
7985   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7986     writemem[n] = write_nomem_new;
7987     writememb[n] = write_nomemb_new;
7988     writememh[n] = write_nomemh_new;
7989 #ifndef FORCE32
7990     writememd[n] = write_nomemd_new;
7991 #endif
7992     readmem[n] = read_nomem_new;
7993     readmemb[n] = read_nomemb_new;
7994     readmemh[n] = read_nomemh_new;
7995 #ifndef FORCE32
7996     readmemd[n] = read_nomemd_new;
7997 #endif
7998   }
7999   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
8000     writemem[n] = write_rdram_new;
8001     writememb[n] = write_rdramb_new;
8002     writememh[n] = write_rdramh_new;
8003 #ifndef FORCE32
8004     writememd[n] = write_rdramd_new;
8005 #endif
8006   }
8007   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
8008     writemem[n] = write_nomem_new;
8009     writememb[n] = write_nomemb_new;
8010     writememh[n] = write_nomemh_new;
8011 #ifndef FORCE32
8012     writememd[n] = write_nomemd_new;
8013 #endif
8014     readmem[n] = read_nomem_new;
8015     readmemb[n] = read_nomemb_new;
8016     readmemh[n] = read_nomemh_new;
8017 #ifndef FORCE32
8018     readmemd[n] = read_nomemd_new;
8019 #endif
8020   }
8021 #endif
8022   tlb_hacks();
8023   arch_init();
8024 }
8025
8026 void new_dynarec_cleanup()
8027 {
8028   int n;
8029   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
8030   for(n=0;n<4096;n++) ll_clear(jump_in+n);
8031   for(n=0;n<4096;n++) ll_clear(jump_out+n);
8032   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8033   #ifdef ROM_COPY
8034   if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
8035   #endif
8036 }
8037
8038 int new_recompile_block(int addr)
8039 {
8040 /*
8041   if(addr==0x800cd050) {
8042     int block;
8043     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8044     int n;
8045     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8046   }
8047 */
8048   //if(Count==365117028) tracedebug=1;
8049   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8050   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8051   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8052   //if(debug)
8053   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8054   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8055   /*if(Count>=312978186) {
8056     rlist();
8057   }*/
8058   //rlist();
8059   start = (u_int)addr&~3;
8060   //assert(((u_int)addr&1)==0);
8061   new_dynarec_did_compile=1;
8062 #ifdef PCSX
8063   if (Config.HLE && start == 0x80001000) // hlecall
8064   {
8065     // XXX: is this enough? Maybe check hleSoftCall?
8066     u_int beginning=(u_int)out;
8067     u_int page=get_page(start);
8068     invalid_code[start>>12]=0;
8069     emit_movimm(start,0);
8070     emit_writeword(0,(int)&pcaddr);
8071     emit_jmp((int)new_dyna_leave);
8072     literal_pool(0);
8073 #ifdef __arm__
8074     __clear_cache((void *)beginning,out);
8075 #endif
8076     ll_add(jump_in+page,start,(void *)beginning);
8077     return 0;
8078   }
8079   else if ((u_int)addr < 0x00200000 ||
8080     (0xa0000000 <= addr && addr < 0xa0200000)) {
8081     // used for BIOS calls mostly?
8082     source = (u_int *)((u_int)rdram+(start&0x1fffff));
8083     pagelimit = (addr&0xa0000000)|0x00200000;
8084   }
8085   else if (!Config.HLE && (
8086 /*    (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8087     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8088     // BIOS
8089     source = (u_int *)((u_int)psxR+(start&0x7ffff));
8090     pagelimit = (addr&0xfff00000)|0x80000;
8091   }
8092   else
8093 #endif
8094 #ifdef MUPEN64
8095   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8096     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8097     pagelimit = 0xa4001000;
8098   }
8099   else
8100 #endif
8101   if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8102     source = (u_int *)((u_int)rdram+start-0x80000000);
8103     pagelimit = 0x80000000+RAM_SIZE;
8104   }
8105 #ifndef DISABLE_TLB
8106   else if ((signed int)addr >= (signed int)0xC0000000) {
8107     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8108     //if(tlb_LUT_r[start>>12])
8109       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8110     if((signed int)memory_map[start>>12]>=0) {
8111       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8112       pagelimit=(start+4096)&0xFFFFF000;
8113       int map=memory_map[start>>12];
8114       int i;
8115       for(i=0;i<5;i++) {
8116         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8117         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8118       }
8119       assem_debug("pagelimit=%x\n",pagelimit);
8120       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8121     }
8122     else {
8123       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8124       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8125       return -1; // Caller will invoke exception handler
8126     }
8127     //printf("source= %x\n",(int)source);
8128   }
8129 #endif
8130   else {
8131     printf("Compile at bogus memory address: %x \n", (int)addr);
8132     exit(1);
8133   }
8134
8135   /* Pass 1: disassemble */
8136   /* Pass 2: register dependencies, branch targets */
8137   /* Pass 3: register allocation */
8138   /* Pass 4: branch dependencies */
8139   /* Pass 5: pre-alloc */
8140   /* Pass 6: optimize clean/dirty state */
8141   /* Pass 7: flag 32-bit registers */
8142   /* Pass 8: assembly */
8143   /* Pass 9: linker */
8144   /* Pass 10: garbage collection / free memory */
8145
8146   int i,j;
8147   int done=0;
8148   unsigned int type,op,op2;
8149
8150   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8151
8152   /* Pass 1 disassembly */
8153
8154   for(i=0;!done;i++) {
8155     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8156     minimum_free_regs[i]=0;
8157     opcode[i]=op=source[i]>>26;
8158     switch(op)
8159     {
8160       case 0x00: strcpy(insn[i],"special"); type=NI;
8161         op2=source[i]&0x3f;
8162         switch(op2)
8163         {
8164           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8165           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8166           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8167           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8168           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8169           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8170           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8171           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8172           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8173           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8174           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8175           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8176           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8177           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8178           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8179           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8180           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8181           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8182           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8183           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8184           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8185           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8186           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8187           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8188           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8189           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8190           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8191           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8192           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8193           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8194           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8195           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8196           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8197           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8198           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8199 #ifndef FORCE32
8200           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8201           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8202           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8203           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8204           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8205           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8206           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8207           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8208           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8209           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8210           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8211           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8212           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8213           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8214           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8215           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8216           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8217 #endif
8218         }
8219         break;
8220       case 0x01: strcpy(insn[i],"regimm"); type=NI;
8221         op2=(source[i]>>16)&0x1f;
8222         switch(op2)
8223         {
8224           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8225           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8226           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8227           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8228           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8229           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8230           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8231           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8232           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8233           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8234           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8235           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8236           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8237           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8238         }
8239         break;
8240       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8241       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8242       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8243       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8244       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8245       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8246       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8247       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8248       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8249       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8250       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8251       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8252       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8253       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8254       case 0x10: strcpy(insn[i],"cop0"); type=NI;
8255         op2=(source[i]>>21)&0x1f;
8256         switch(op2)
8257         {
8258           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8259           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8260           case 0x10: strcpy(insn[i],"tlb"); type=NI;
8261           switch(source[i]&0x3f)
8262           {
8263             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8264             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8265             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8266             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8267 #ifdef PCSX
8268             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8269 #else
8270             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8271 #endif
8272           }
8273         }
8274         break;
8275       case 0x11: strcpy(insn[i],"cop1"); type=NI;
8276         op2=(source[i]>>21)&0x1f;
8277         switch(op2)
8278         {
8279           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8280           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8281           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8282           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8283           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8284           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8285           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8286           switch((source[i]>>16)&0x3)
8287           {
8288             case 0x00: strcpy(insn[i],"BC1F"); break;
8289             case 0x01: strcpy(insn[i],"BC1T"); break;
8290             case 0x02: strcpy(insn[i],"BC1FL"); break;
8291             case 0x03: strcpy(insn[i],"BC1TL"); break;
8292           }
8293           break;
8294           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8295           switch(source[i]&0x3f)
8296           {
8297             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8298             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8299             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8300             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8301             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8302             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8303             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8304             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8305             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8306             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8307             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8308             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8309             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8310             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8311             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8312             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8313             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8314             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8315             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8316             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8317             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8318             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8319             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8320             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8321             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8322             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8323             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8324             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8325             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8326             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8327             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8328             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8329             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8330             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8331             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8332           }
8333           break;
8334           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8335           switch(source[i]&0x3f)
8336           {
8337             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8338             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8339             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8340             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8341             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8342             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8343             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8344             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8345             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8346             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8347             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8348             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8349             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8350             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8351             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8352             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8353             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8354             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8355             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8356             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8357             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8358             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8359             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8360             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8361             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8362             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8363             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8364             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8365             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8366             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8367             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8368             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8369             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8370             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8371             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8372           }
8373           break;
8374           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8375           switch(source[i]&0x3f)
8376           {
8377             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8378             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8379           }
8380           break;
8381           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8382           switch(source[i]&0x3f)
8383           {
8384             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8385             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8386           }
8387           break;
8388         }
8389         break;
8390 #ifndef FORCE32
8391       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8392       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8393       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8394       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8395       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8396       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8397       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8398       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8399 #endif
8400       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8401       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8402       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8403       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8404       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8405       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8406       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8407 #ifndef FORCE32
8408       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8409 #endif
8410       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8411       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8412       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8413       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8414 #ifndef FORCE32
8415       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8416       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8417 #endif
8418       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8419       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8420       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8421       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8422 #ifndef FORCE32
8423       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8424       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8425       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8426 #endif
8427       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8428       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8429 #ifndef FORCE32
8430       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8431       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8432       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8433 #endif
8434 #ifdef PCSX
8435       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8436         op2=(source[i]>>21)&0x1f;
8437         //if (op2 & 0x10) {
8438         if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8439           if (gte_handlers[source[i]&0x3f]!=NULL) {
8440             if (gte_regnames[source[i]&0x3f]!=NULL)
8441               strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8442             else
8443               snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8444             type=C2OP;
8445           }
8446         }
8447         else switch(op2)
8448         {
8449           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8450           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8451           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8452           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8453         }
8454         break;
8455       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8456       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8457       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8458 #endif
8459       default: strcpy(insn[i],"???"); type=NI;
8460         printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8461         break;
8462     }
8463     itype[i]=type;
8464     opcode2[i]=op2;
8465     /* Get registers/immediates */
8466     lt1[i]=0;
8467     us1[i]=0;
8468     us2[i]=0;
8469     dep1[i]=0;
8470     dep2[i]=0;
8471     gte_rs[i]=gte_rt[i]=0;
8472     switch(type) {
8473       case LOAD:
8474         rs1[i]=(source[i]>>21)&0x1f;
8475         rs2[i]=0;
8476         rt1[i]=(source[i]>>16)&0x1f;
8477         rt2[i]=0;
8478         imm[i]=(short)source[i];
8479         break;
8480       case STORE:
8481       case STORELR:
8482         rs1[i]=(source[i]>>21)&0x1f;
8483         rs2[i]=(source[i]>>16)&0x1f;
8484         rt1[i]=0;
8485         rt2[i]=0;
8486         imm[i]=(short)source[i];
8487         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8488         break;
8489       case LOADLR:
8490         // LWL/LWR only load part of the register,
8491         // therefore the target register must be treated as a source too
8492         rs1[i]=(source[i]>>21)&0x1f;
8493         rs2[i]=(source[i]>>16)&0x1f;
8494         rt1[i]=(source[i]>>16)&0x1f;
8495         rt2[i]=0;
8496         imm[i]=(short)source[i];
8497         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8498         if(op==0x26) dep1[i]=rt1[i]; // LWR
8499         break;
8500       case IMM16:
8501         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8502         else rs1[i]=(source[i]>>21)&0x1f;
8503         rs2[i]=0;
8504         rt1[i]=(source[i]>>16)&0x1f;
8505         rt2[i]=0;
8506         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8507           imm[i]=(unsigned short)source[i];
8508         }else{
8509           imm[i]=(short)source[i];
8510         }
8511         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8512         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8513         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8514         break;
8515       case UJUMP:
8516         rs1[i]=0;
8517         rs2[i]=0;
8518         rt1[i]=0;
8519         rt2[i]=0;
8520         // The JAL instruction writes to r31.
8521         if (op&1) {
8522           rt1[i]=31;
8523         }
8524         rs2[i]=CCREG;
8525         break;
8526       case RJUMP:
8527         rs1[i]=(source[i]>>21)&0x1f;
8528         rs2[i]=0;
8529         rt1[i]=0;
8530         rt2[i]=0;
8531         // The JALR instruction writes to rd.
8532         if (op2&1) {
8533           rt1[i]=(source[i]>>11)&0x1f;
8534         }
8535         rs2[i]=CCREG;
8536         break;
8537       case CJUMP:
8538         rs1[i]=(source[i]>>21)&0x1f;
8539         rs2[i]=(source[i]>>16)&0x1f;
8540         rt1[i]=0;
8541         rt2[i]=0;
8542         if(op&2) { // BGTZ/BLEZ
8543           rs2[i]=0;
8544         }
8545         us1[i]=rs1[i];
8546         us2[i]=rs2[i];
8547         likely[i]=op>>4;
8548         break;
8549       case SJUMP:
8550         rs1[i]=(source[i]>>21)&0x1f;
8551         rs2[i]=CCREG;
8552         rt1[i]=0;
8553         rt2[i]=0;
8554         us1[i]=rs1[i];
8555         if(op2&0x10) { // BxxAL
8556           rt1[i]=31;
8557           // NOTE: If the branch is not taken, r31 is still overwritten
8558         }
8559         likely[i]=(op2&2)>>1;
8560         break;
8561       case FJUMP:
8562         rs1[i]=FSREG;
8563         rs2[i]=CSREG;
8564         rt1[i]=0;
8565         rt2[i]=0;
8566         likely[i]=((source[i])>>17)&1;
8567         break;
8568       case ALU:
8569         rs1[i]=(source[i]>>21)&0x1f; // source
8570         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8571         rt1[i]=(source[i]>>11)&0x1f; // destination
8572         rt2[i]=0;
8573         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8574           us1[i]=rs1[i];us2[i]=rs2[i];
8575         }
8576         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8577           dep1[i]=rs1[i];dep2[i]=rs2[i];
8578         }
8579         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8580           dep1[i]=rs1[i];dep2[i]=rs2[i];
8581         }
8582         break;
8583       case MULTDIV:
8584         rs1[i]=(source[i]>>21)&0x1f; // source
8585         rs2[i]=(source[i]>>16)&0x1f; // divisor
8586         rt1[i]=HIREG;
8587         rt2[i]=LOREG;
8588         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8589           us1[i]=rs1[i];us2[i]=rs2[i];
8590         }
8591         break;
8592       case MOV:
8593         rs1[i]=0;
8594         rs2[i]=0;
8595         rt1[i]=0;
8596         rt2[i]=0;
8597         if(op2==0x10) rs1[i]=HIREG; // MFHI
8598         if(op2==0x11) rt1[i]=HIREG; // MTHI
8599         if(op2==0x12) rs1[i]=LOREG; // MFLO
8600         if(op2==0x13) rt1[i]=LOREG; // MTLO
8601         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8602         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8603         dep1[i]=rs1[i];
8604         break;
8605       case SHIFT:
8606         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8607         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8608         rt1[i]=(source[i]>>11)&0x1f; // destination
8609         rt2[i]=0;
8610         // DSLLV/DSRLV/DSRAV are 64-bit
8611         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8612         break;
8613       case SHIFTIMM:
8614         rs1[i]=(source[i]>>16)&0x1f;
8615         rs2[i]=0;
8616         rt1[i]=(source[i]>>11)&0x1f;
8617         rt2[i]=0;
8618         imm[i]=(source[i]>>6)&0x1f;
8619         // DSxx32 instructions
8620         if(op2>=0x3c) imm[i]|=0x20;
8621         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8622         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8623         break;
8624       case COP0:
8625         rs1[i]=0;
8626         rs2[i]=0;
8627         rt1[i]=0;
8628         rt2[i]=0;
8629         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8630         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8631         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8632         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8633         break;
8634       case COP1:
8635         rs1[i]=0;
8636         rs2[i]=0;
8637         rt1[i]=0;
8638         rt2[i]=0;
8639         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8640         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8641         if(op2==5) us1[i]=rs1[i]; // DMTC1
8642         rs2[i]=CSREG;
8643         break;
8644       case COP2:
8645         rs1[i]=0;
8646         rs2[i]=0;
8647         rt1[i]=0;
8648         rt2[i]=0;
8649         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8650         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8651         rs2[i]=CSREG;
8652         int gr=(source[i]>>11)&0x1F;
8653         switch(op2)
8654         {
8655           case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8656           case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8657           case 0x02: gte_rs[i]=1ll<<(gr+32); // CFC2
8658             if(gr==31&&!gte_reads_flags) {
8659               assem_debug("gte flag read encountered @%08x\n",addr + i*4);
8660               gte_reads_flags=1;
8661             }
8662             break;
8663           case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8664         }
8665         break;
8666       case C1LS:
8667         rs1[i]=(source[i]>>21)&0x1F;
8668         rs2[i]=CSREG;
8669         rt1[i]=0;
8670         rt2[i]=0;
8671         imm[i]=(short)source[i];
8672         break;
8673       case C2LS:
8674         rs1[i]=(source[i]>>21)&0x1F;
8675         rs2[i]=0;
8676         rt1[i]=0;
8677         rt2[i]=0;
8678         imm[i]=(short)source[i];
8679         if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8680         else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8681         break;
8682       case C2OP:
8683         rs1[i]=0;
8684         rs2[i]=0;
8685         rt1[i]=0;
8686         rt2[i]=0;
8687         gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8688         gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8689         gte_rt[i]|=1ll<<63; // every op changes flags
8690         break;
8691       case FLOAT:
8692       case FCONV:
8693         rs1[i]=0;
8694         rs2[i]=CSREG;
8695         rt1[i]=0;
8696         rt2[i]=0;
8697         break;
8698       case FCOMP:
8699         rs1[i]=FSREG;
8700         rs2[i]=CSREG;
8701         rt1[i]=FSREG;
8702         rt2[i]=0;
8703         break;
8704       case SYSCALL:
8705       case HLECALL:
8706       case INTCALL:
8707         rs1[i]=CCREG;
8708         rs2[i]=0;
8709         rt1[i]=0;
8710         rt2[i]=0;
8711         break;
8712       default:
8713         rs1[i]=0;
8714         rs2[i]=0;
8715         rt1[i]=0;
8716         rt2[i]=0;
8717     }
8718     /* Calculate branch target addresses */
8719     if(type==UJUMP)
8720       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8721     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8722       ba[i]=start+i*4+8; // Ignore never taken branch
8723     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8724       ba[i]=start+i*4+8; // Ignore never taken branch
8725     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8726       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8727     else ba[i]=-1;
8728 #ifdef PCSX
8729     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8730       int do_in_intrp=0;
8731       // branch in delay slot?
8732       if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8733         // don't handle first branch and call interpreter if it's hit
8734         printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8735         do_in_intrp=1;
8736       }
8737       // basic load delay detection
8738       else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8739         int t=(ba[i-1]-start)/4;
8740         if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8741           // jump target wants DS result - potential load delay effect
8742           printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8743           do_in_intrp=1;
8744           bt[t+1]=1; // expected return from interpreter
8745         }
8746         else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8747               !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8748           // v0 overwrite like this is a sign of trouble, bail out
8749           printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8750           do_in_intrp=1;
8751         }
8752       }
8753       if(do_in_intrp) {
8754         rs1[i-1]=CCREG;
8755         rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8756         ba[i-1]=-1;
8757         itype[i-1]=INTCALL;
8758         done=2;
8759         i--; // don't compile the DS
8760       }
8761     }
8762 #endif
8763     /* Is this the end of the block? */
8764     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8765       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8766         done=2;
8767       }
8768       else {
8769         if(stop_after_jal) done=1;
8770         // Stop on BREAK
8771         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8772       }
8773       // Don't recompile stuff that's already compiled
8774       if(check_addr(start+i*4+4)) done=1;
8775       // Don't get too close to the limit
8776       if(i>MAXBLOCK/2) done=1;
8777     }
8778     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8779     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8780     if(done==2) {
8781       // Does the block continue due to a branch?
8782       for(j=i-1;j>=0;j--)
8783       {
8784         if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8785         if(ba[j]==start+i*4+4) done=j=0;
8786         if(ba[j]==start+i*4+8) done=j=0;
8787       }
8788     }
8789     //assert(i<MAXBLOCK-1);
8790     if(start+i*4==pagelimit-4) done=1;
8791     assert(start+i*4<pagelimit);
8792     if (i==MAXBLOCK-1) done=1;
8793     // Stop if we're compiling junk
8794     if(itype[i]==NI&&opcode[i]==0x11) {
8795       done=stop_after_jal=1;
8796       printf("Disabled speculative precompilation\n");
8797     }
8798   }
8799   slen=i;
8800   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8801     if(start+i*4==pagelimit) {
8802       itype[i-1]=SPAN;
8803     }
8804   }
8805   assert(slen>0);
8806
8807   /* Pass 2 - Register dependencies and branch targets */
8808
8809   unneeded_registers(0,slen-1,0);
8810
8811   /* Pass 3 - Register allocation */
8812
8813   struct regstat current; // Current register allocations/status
8814   current.is32=1;
8815   current.dirty=0;
8816   current.u=unneeded_reg[0];
8817   current.uu=unneeded_reg_upper[0];
8818   clear_all_regs(current.regmap);
8819   alloc_reg(&current,0,CCREG);
8820   dirty_reg(&current,CCREG);
8821   current.isconst=0;
8822   current.wasconst=0;
8823   current.waswritten=0;
8824   int ds=0;
8825   int cc=0;
8826   int hr=-1;
8827
8828 #ifndef FORCE32
8829   provisional_32bit();
8830 #endif
8831   if((u_int)addr&1) {
8832     // First instruction is delay slot
8833     cc=-1;
8834     bt[1]=1;
8835     ds=1;
8836     unneeded_reg[0]=1;
8837     unneeded_reg_upper[0]=1;
8838     current.regmap[HOST_BTREG]=BTREG;
8839   }
8840
8841   for(i=0;i<slen;i++)
8842   {
8843     if(bt[i])
8844     {
8845       int hr;
8846       for(hr=0;hr<HOST_REGS;hr++)
8847       {
8848         // Is this really necessary?
8849         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8850       }
8851       current.isconst=0;
8852       current.waswritten=0;
8853     }
8854     if(i>1)
8855     {
8856       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8857       {
8858         if(rs1[i-2]==0||rs2[i-2]==0)
8859         {
8860           if(rs1[i-2]) {
8861             current.is32|=1LL<<rs1[i-2];
8862             int hr=get_reg(current.regmap,rs1[i-2]|64);
8863             if(hr>=0) current.regmap[hr]=-1;
8864           }
8865           if(rs2[i-2]) {
8866             current.is32|=1LL<<rs2[i-2];
8867             int hr=get_reg(current.regmap,rs2[i-2]|64);
8868             if(hr>=0) current.regmap[hr]=-1;
8869           }
8870         }
8871       }
8872     }
8873 #ifndef FORCE32
8874     // If something jumps here with 64-bit values
8875     // then promote those registers to 64 bits
8876     if(bt[i])
8877     {
8878       uint64_t temp_is32=current.is32;
8879       for(j=i-1;j>=0;j--)
8880       {
8881         if(ba[j]==start+i*4)
8882           temp_is32&=branch_regs[j].is32;
8883       }
8884       for(j=i;j<slen;j++)
8885       {
8886         if(ba[j]==start+i*4)
8887           //temp_is32=1;
8888           temp_is32&=p32[j];
8889       }
8890       if(temp_is32!=current.is32) {
8891         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8892         #ifndef DESTRUCTIVE_WRITEBACK
8893         if(ds)
8894         #endif
8895         for(hr=0;hr<HOST_REGS;hr++)
8896         {
8897           int r=current.regmap[hr];
8898           if(r>0&&r<64)
8899           {
8900             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8901               temp_is32|=1LL<<r;
8902               //printf("restore %d\n",r);
8903             }
8904           }
8905         }
8906         current.is32=temp_is32;
8907       }
8908     }
8909 #else
8910     current.is32=-1LL;
8911 #endif
8912
8913     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8914     regs[i].wasconst=current.isconst;
8915     regs[i].was32=current.is32;
8916     regs[i].wasdirty=current.dirty;
8917     regs[i].loadedconst=0;
8918     #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8919     // To change a dirty register from 32 to 64 bits, we must write
8920     // it out during the previous cycle (for branches, 2 cycles)
8921     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8922     {
8923       uint64_t temp_is32=current.is32;
8924       for(j=i-1;j>=0;j--)
8925       {
8926         if(ba[j]==start+i*4+4)
8927           temp_is32&=branch_regs[j].is32;
8928       }
8929       for(j=i;j<slen;j++)
8930       {
8931         if(ba[j]==start+i*4+4)
8932           //temp_is32=1;
8933           temp_is32&=p32[j];
8934       }
8935       if(temp_is32!=current.is32) {
8936         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8937         for(hr=0;hr<HOST_REGS;hr++)
8938         {
8939           int r=current.regmap[hr];
8940           if(r>0)
8941           {
8942             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8943               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8944               {
8945                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8946                 {
8947                   //printf("dump %d/r%d\n",hr,r);
8948                   current.regmap[hr]=-1;
8949                   if(get_reg(current.regmap,r|64)>=0)
8950                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8951                 }
8952               }
8953             }
8954           }
8955         }
8956       }
8957     }
8958     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8959     {
8960       uint64_t temp_is32=current.is32;
8961       for(j=i-1;j>=0;j--)
8962       {
8963         if(ba[j]==start+i*4+8)
8964           temp_is32&=branch_regs[j].is32;
8965       }
8966       for(j=i;j<slen;j++)
8967       {
8968         if(ba[j]==start+i*4+8)
8969           //temp_is32=1;
8970           temp_is32&=p32[j];
8971       }
8972       if(temp_is32!=current.is32) {
8973         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8974         for(hr=0;hr<HOST_REGS;hr++)
8975         {
8976           int r=current.regmap[hr];
8977           if(r>0)
8978           {
8979             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8980               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8981               {
8982                 //printf("dump %d/r%d\n",hr,r);
8983                 current.regmap[hr]=-1;
8984                 if(get_reg(current.regmap,r|64)>=0)
8985                   current.regmap[get_reg(current.regmap,r|64)]=-1;
8986               }
8987             }
8988           }
8989         }
8990       }
8991     }
8992     #endif
8993     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8994       if(i+1<slen) {
8995         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8996         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8997         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8998         current.u|=1;
8999         current.uu|=1;
9000       } else {
9001         current.u=1;
9002         current.uu=1;
9003       }
9004     } else {
9005       if(i+1<slen) {
9006         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
9007         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9008         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9009         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9010         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9011         current.u|=1;
9012         current.uu|=1;
9013       } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
9014     }
9015     is_ds[i]=ds;
9016     if(ds) {
9017       ds=0; // Skip delay slot, already allocated as part of branch
9018       // ...but we need to alloc it in case something jumps here
9019       if(i+1<slen) {
9020         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
9021         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
9022       }else{
9023         current.u=branch_unneeded_reg[i-1];
9024         current.uu=branch_unneeded_reg_upper[i-1];
9025       }
9026       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9027       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9028       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9029       current.u|=1;
9030       current.uu|=1;
9031       struct regstat temp;
9032       memcpy(&temp,&current,sizeof(current));
9033       temp.wasdirty=temp.dirty;
9034       temp.was32=temp.is32;
9035       // TODO: Take into account unconditional branches, as below
9036       delayslot_alloc(&temp,i);
9037       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9038       regs[i].wasdirty=temp.wasdirty;
9039       regs[i].was32=temp.was32;
9040       regs[i].dirty=temp.dirty;
9041       regs[i].is32=temp.is32;
9042       regs[i].isconst=0;
9043       regs[i].wasconst=0;
9044       current.isconst=0;
9045       // Create entry (branch target) regmap
9046       for(hr=0;hr<HOST_REGS;hr++)
9047       {
9048         int r=temp.regmap[hr];
9049         if(r>=0) {
9050           if(r!=regmap_pre[i][hr]) {
9051             regs[i].regmap_entry[hr]=-1;
9052           }
9053           else
9054           {
9055             if(r<64){
9056               if((current.u>>r)&1) {
9057                 regs[i].regmap_entry[hr]=-1;
9058                 regs[i].regmap[hr]=-1;
9059                 //Don't clear regs in the delay slot as the branch might need them
9060                 //current.regmap[hr]=-1;
9061               }else
9062                 regs[i].regmap_entry[hr]=r;
9063             }
9064             else {
9065               if((current.uu>>(r&63))&1) {
9066                 regs[i].regmap_entry[hr]=-1;
9067                 regs[i].regmap[hr]=-1;
9068                 //Don't clear regs in the delay slot as the branch might need them
9069                 //current.regmap[hr]=-1;
9070               }else
9071                 regs[i].regmap_entry[hr]=r;
9072             }
9073           }
9074         } else {
9075           // First instruction expects CCREG to be allocated
9076           if(i==0&&hr==HOST_CCREG)
9077             regs[i].regmap_entry[hr]=CCREG;
9078           else
9079             regs[i].regmap_entry[hr]=-1;
9080         }
9081       }
9082     }
9083     else { // Not delay slot
9084       switch(itype[i]) {
9085         case UJUMP:
9086           //current.isconst=0; // DEBUG
9087           //current.wasconst=0; // DEBUG
9088           //regs[i].wasconst=0; // DEBUG
9089           clear_const(&current,rt1[i]);
9090           alloc_cc(&current,i);
9091           dirty_reg(&current,CCREG);
9092           if (rt1[i]==31) {
9093             alloc_reg(&current,i,31);
9094             dirty_reg(&current,31);
9095             //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9096             //assert(rt1[i+1]!=rt1[i]);
9097             #ifdef REG_PREFETCH
9098             alloc_reg(&current,i,PTEMP);
9099             #endif
9100             //current.is32|=1LL<<rt1[i];
9101           }
9102           ooo[i]=1;
9103           delayslot_alloc(&current,i+1);
9104           //current.isconst=0; // DEBUG
9105           ds=1;
9106           //printf("i=%d, isconst=%x\n",i,current.isconst);
9107           break;
9108         case RJUMP:
9109           //current.isconst=0;
9110           //current.wasconst=0;
9111           //regs[i].wasconst=0;
9112           clear_const(&current,rs1[i]);
9113           clear_const(&current,rt1[i]);
9114           alloc_cc(&current,i);
9115           dirty_reg(&current,CCREG);
9116           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9117             alloc_reg(&current,i,rs1[i]);
9118             if (rt1[i]!=0) {
9119               alloc_reg(&current,i,rt1[i]);
9120               dirty_reg(&current,rt1[i]);
9121               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9122               assert(rt1[i+1]!=rt1[i]);
9123               #ifdef REG_PREFETCH
9124               alloc_reg(&current,i,PTEMP);
9125               #endif
9126             }
9127             #ifdef USE_MINI_HT
9128             if(rs1[i]==31) { // JALR
9129               alloc_reg(&current,i,RHASH);
9130               #ifndef HOST_IMM_ADDR32
9131               alloc_reg(&current,i,RHTBL);
9132               #endif
9133             }
9134             #endif
9135             delayslot_alloc(&current,i+1);
9136           } else {
9137             // The delay slot overwrites our source register,
9138             // allocate a temporary register to hold the old value.
9139             current.isconst=0;
9140             current.wasconst=0;
9141             regs[i].wasconst=0;
9142             delayslot_alloc(&current,i+1);
9143             current.isconst=0;
9144             alloc_reg(&current,i,RTEMP);
9145           }
9146           //current.isconst=0; // DEBUG
9147           ooo[i]=1;
9148           ds=1;
9149           break;
9150         case CJUMP:
9151           //current.isconst=0;
9152           //current.wasconst=0;
9153           //regs[i].wasconst=0;
9154           clear_const(&current,rs1[i]);
9155           clear_const(&current,rs2[i]);
9156           if((opcode[i]&0x3E)==4) // BEQ/BNE
9157           {
9158             alloc_cc(&current,i);
9159             dirty_reg(&current,CCREG);
9160             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9161             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9162             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9163             {
9164               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9165               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9166             }
9167             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9168                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9169               // The delay slot overwrites one of our conditions.
9170               // Allocate the branch condition registers instead.
9171               current.isconst=0;
9172               current.wasconst=0;
9173               regs[i].wasconst=0;
9174               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9175               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9176               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9177               {
9178                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9179                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9180               }
9181             }
9182             else
9183             {
9184               ooo[i]=1;
9185               delayslot_alloc(&current,i+1);
9186             }
9187           }
9188           else
9189           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9190           {
9191             alloc_cc(&current,i);
9192             dirty_reg(&current,CCREG);
9193             alloc_reg(&current,i,rs1[i]);
9194             if(!(current.is32>>rs1[i]&1))
9195             {
9196               alloc_reg64(&current,i,rs1[i]);
9197             }
9198             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9199               // The delay slot overwrites one of our conditions.
9200               // Allocate the branch condition registers instead.
9201               current.isconst=0;
9202               current.wasconst=0;
9203               regs[i].wasconst=0;
9204               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9205               if(!((current.is32>>rs1[i])&1))
9206               {
9207                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9208               }
9209             }
9210             else
9211             {
9212               ooo[i]=1;
9213               delayslot_alloc(&current,i+1);
9214             }
9215           }
9216           else
9217           // Don't alloc the delay slot yet because we might not execute it
9218           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9219           {
9220             current.isconst=0;
9221             current.wasconst=0;
9222             regs[i].wasconst=0;
9223             alloc_cc(&current,i);
9224             dirty_reg(&current,CCREG);
9225             alloc_reg(&current,i,rs1[i]);
9226             alloc_reg(&current,i,rs2[i]);
9227             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9228             {
9229               alloc_reg64(&current,i,rs1[i]);
9230               alloc_reg64(&current,i,rs2[i]);
9231             }
9232           }
9233           else
9234           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9235           {
9236             current.isconst=0;
9237             current.wasconst=0;
9238             regs[i].wasconst=0;
9239             alloc_cc(&current,i);
9240             dirty_reg(&current,CCREG);
9241             alloc_reg(&current,i,rs1[i]);
9242             if(!(current.is32>>rs1[i]&1))
9243             {
9244               alloc_reg64(&current,i,rs1[i]);
9245             }
9246           }
9247           ds=1;
9248           //current.isconst=0;
9249           break;
9250         case SJUMP:
9251           //current.isconst=0;
9252           //current.wasconst=0;
9253           //regs[i].wasconst=0;
9254           clear_const(&current,rs1[i]);
9255           clear_const(&current,rt1[i]);
9256           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9257           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9258           {
9259             alloc_cc(&current,i);
9260             dirty_reg(&current,CCREG);
9261             alloc_reg(&current,i,rs1[i]);
9262             if(!(current.is32>>rs1[i]&1))
9263             {
9264               alloc_reg64(&current,i,rs1[i]);
9265             }
9266             if (rt1[i]==31) { // BLTZAL/BGEZAL
9267               alloc_reg(&current,i,31);
9268               dirty_reg(&current,31);
9269               //#ifdef REG_PREFETCH
9270               //alloc_reg(&current,i,PTEMP);
9271               //#endif
9272               //current.is32|=1LL<<rt1[i];
9273             }
9274             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9275                ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9276               // Allocate the branch condition registers instead.
9277               current.isconst=0;
9278               current.wasconst=0;
9279               regs[i].wasconst=0;
9280               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9281               if(!((current.is32>>rs1[i])&1))
9282               {
9283                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9284               }
9285             }
9286             else
9287             {
9288               ooo[i]=1;
9289               delayslot_alloc(&current,i+1);
9290             }
9291           }
9292           else
9293           // Don't alloc the delay slot yet because we might not execute it
9294           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9295           {
9296             current.isconst=0;
9297             current.wasconst=0;
9298             regs[i].wasconst=0;
9299             alloc_cc(&current,i);
9300             dirty_reg(&current,CCREG);
9301             alloc_reg(&current,i,rs1[i]);
9302             if(!(current.is32>>rs1[i]&1))
9303             {
9304               alloc_reg64(&current,i,rs1[i]);
9305             }
9306           }
9307           ds=1;
9308           //current.isconst=0;
9309           break;
9310         case FJUMP:
9311           current.isconst=0;
9312           current.wasconst=0;
9313           regs[i].wasconst=0;
9314           if(likely[i]==0) // BC1F/BC1T
9315           {
9316             // TODO: Theoretically we can run out of registers here on x86.
9317             // The delay slot can allocate up to six, and we need to check
9318             // CSREG before executing the delay slot.  Possibly we can drop
9319             // the cycle count and then reload it after checking that the
9320             // FPU is in a usable state, or don't do out-of-order execution.
9321             alloc_cc(&current,i);
9322             dirty_reg(&current,CCREG);
9323             alloc_reg(&current,i,FSREG);
9324             alloc_reg(&current,i,CSREG);
9325             if(itype[i+1]==FCOMP) {
9326               // The delay slot overwrites the branch condition.
9327               // Allocate the branch condition registers instead.
9328               alloc_cc(&current,i);
9329               dirty_reg(&current,CCREG);
9330               alloc_reg(&current,i,CSREG);
9331               alloc_reg(&current,i,FSREG);
9332             }
9333             else {
9334               ooo[i]=1;
9335               delayslot_alloc(&current,i+1);
9336               alloc_reg(&current,i+1,CSREG);
9337             }
9338           }
9339           else
9340           // Don't alloc the delay slot yet because we might not execute it
9341           if(likely[i]) // BC1FL/BC1TL
9342           {
9343             alloc_cc(&current,i);
9344             dirty_reg(&current,CCREG);
9345             alloc_reg(&current,i,CSREG);
9346             alloc_reg(&current,i,FSREG);
9347           }
9348           ds=1;
9349           current.isconst=0;
9350           break;
9351         case IMM16:
9352           imm16_alloc(&current,i);
9353           break;
9354         case LOAD:
9355         case LOADLR:
9356           load_alloc(&current,i);
9357           break;
9358         case STORE:
9359         case STORELR:
9360           store_alloc(&current,i);
9361           break;
9362         case ALU:
9363           alu_alloc(&current,i);
9364           break;
9365         case SHIFT:
9366           shift_alloc(&current,i);
9367           break;
9368         case MULTDIV:
9369           multdiv_alloc(&current,i);
9370           break;
9371         case SHIFTIMM:
9372           shiftimm_alloc(&current,i);
9373           break;
9374         case MOV:
9375           mov_alloc(&current,i);
9376           break;
9377         case COP0:
9378           cop0_alloc(&current,i);
9379           break;
9380         case COP1:
9381         case COP2:
9382           cop1_alloc(&current,i);
9383           break;
9384         case C1LS:
9385           c1ls_alloc(&current,i);
9386           break;
9387         case C2LS:
9388           c2ls_alloc(&current,i);
9389           break;
9390         case C2OP:
9391           c2op_alloc(&current,i);
9392           break;
9393         case FCONV:
9394           fconv_alloc(&current,i);
9395           break;
9396         case FLOAT:
9397           float_alloc(&current,i);
9398           break;
9399         case FCOMP:
9400           fcomp_alloc(&current,i);
9401           break;
9402         case SYSCALL:
9403         case HLECALL:
9404         case INTCALL:
9405           syscall_alloc(&current,i);
9406           break;
9407         case SPAN:
9408           pagespan_alloc(&current,i);
9409           break;
9410       }
9411
9412       // Drop the upper half of registers that have become 32-bit
9413       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9414       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9415         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9416         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9417         current.uu|=1;
9418       } else {
9419         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9420         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9421         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9422         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9423         current.uu|=1;
9424       }
9425
9426       // Create entry (branch target) regmap
9427       for(hr=0;hr<HOST_REGS;hr++)
9428       {
9429         int r,or,er;
9430         r=current.regmap[hr];
9431         if(r>=0) {
9432           if(r!=regmap_pre[i][hr]) {
9433             // TODO: delay slot (?)
9434             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9435             if(or<0||(r&63)>=TEMPREG){
9436               regs[i].regmap_entry[hr]=-1;
9437             }
9438             else
9439             {
9440               // Just move it to a different register
9441               regs[i].regmap_entry[hr]=r;
9442               // If it was dirty before, it's still dirty
9443               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9444             }
9445           }
9446           else
9447           {
9448             // Unneeded
9449             if(r==0){
9450               regs[i].regmap_entry[hr]=0;
9451             }
9452             else
9453             if(r<64){
9454               if((current.u>>r)&1) {
9455                 regs[i].regmap_entry[hr]=-1;
9456                 //regs[i].regmap[hr]=-1;
9457                 current.regmap[hr]=-1;
9458               }else
9459                 regs[i].regmap_entry[hr]=r;
9460             }
9461             else {
9462               if((current.uu>>(r&63))&1) {
9463                 regs[i].regmap_entry[hr]=-1;
9464                 //regs[i].regmap[hr]=-1;
9465                 current.regmap[hr]=-1;
9466               }else
9467                 regs[i].regmap_entry[hr]=r;
9468             }
9469           }
9470         } else {
9471           // Branches expect CCREG to be allocated at the target
9472           if(regmap_pre[i][hr]==CCREG)
9473             regs[i].regmap_entry[hr]=CCREG;
9474           else
9475             regs[i].regmap_entry[hr]=-1;
9476         }
9477       }
9478       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9479     }
9480
9481     if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9482       current.waswritten|=1<<rs1[i-1];
9483     current.waswritten&=~(1<<rt1[i]);
9484     current.waswritten&=~(1<<rt2[i]);
9485     if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9486       current.waswritten&=~(1<<rs1[i]);
9487
9488     /* Branch post-alloc */
9489     if(i>0)
9490     {
9491       current.was32=current.is32;
9492       current.wasdirty=current.dirty;
9493       switch(itype[i-1]) {
9494         case UJUMP:
9495           memcpy(&branch_regs[i-1],&current,sizeof(current));
9496           branch_regs[i-1].isconst=0;
9497           branch_regs[i-1].wasconst=0;
9498           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9499           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9500           alloc_cc(&branch_regs[i-1],i-1);
9501           dirty_reg(&branch_regs[i-1],CCREG);
9502           if(rt1[i-1]==31) { // JAL
9503             alloc_reg(&branch_regs[i-1],i-1,31);
9504             dirty_reg(&branch_regs[i-1],31);
9505             branch_regs[i-1].is32|=1LL<<31;
9506           }
9507           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9508           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9509           break;
9510         case RJUMP:
9511           memcpy(&branch_regs[i-1],&current,sizeof(current));
9512           branch_regs[i-1].isconst=0;
9513           branch_regs[i-1].wasconst=0;
9514           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9515           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9516           alloc_cc(&branch_regs[i-1],i-1);
9517           dirty_reg(&branch_regs[i-1],CCREG);
9518           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9519           if(rt1[i-1]!=0) { // JALR
9520             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9521             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9522             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9523           }
9524           #ifdef USE_MINI_HT
9525           if(rs1[i-1]==31) { // JALR
9526             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9527             #ifndef HOST_IMM_ADDR32
9528             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9529             #endif
9530           }
9531           #endif
9532           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9533           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9534           break;
9535         case CJUMP:
9536           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9537           {
9538             alloc_cc(&current,i-1);
9539             dirty_reg(&current,CCREG);
9540             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9541                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9542               // The delay slot overwrote one of our conditions
9543               // Delay slot goes after the test (in order)
9544               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9545               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9546               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9547               current.u|=1;
9548               current.uu|=1;
9549               delayslot_alloc(&current,i);
9550               current.isconst=0;
9551             }
9552             else
9553             {
9554               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9555               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9556               // Alloc the branch condition registers
9557               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9558               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9559               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9560               {
9561                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9562                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9563               }
9564             }
9565             memcpy(&branch_regs[i-1],&current,sizeof(current));
9566             branch_regs[i-1].isconst=0;
9567             branch_regs[i-1].wasconst=0;
9568             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9569             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9570           }
9571           else
9572           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9573           {
9574             alloc_cc(&current,i-1);
9575             dirty_reg(&current,CCREG);
9576             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9577               // The delay slot overwrote the branch condition
9578               // Delay slot goes after the test (in order)
9579               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9580               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9581               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9582               current.u|=1;
9583               current.uu|=1;
9584               delayslot_alloc(&current,i);
9585               current.isconst=0;
9586             }
9587             else
9588             {
9589               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9590               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9591               // Alloc the branch condition register
9592               alloc_reg(&current,i-1,rs1[i-1]);
9593               if(!(current.is32>>rs1[i-1]&1))
9594               {
9595                 alloc_reg64(&current,i-1,rs1[i-1]);
9596               }
9597             }
9598             memcpy(&branch_regs[i-1],&current,sizeof(current));
9599             branch_regs[i-1].isconst=0;
9600             branch_regs[i-1].wasconst=0;
9601             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9602             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9603           }
9604           else
9605           // Alloc the delay slot in case the branch is taken
9606           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9607           {
9608             memcpy(&branch_regs[i-1],&current,sizeof(current));
9609             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9610             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9611             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9612             alloc_cc(&branch_regs[i-1],i);
9613             dirty_reg(&branch_regs[i-1],CCREG);
9614             delayslot_alloc(&branch_regs[i-1],i);
9615             branch_regs[i-1].isconst=0;
9616             alloc_reg(&current,i,CCREG); // Not taken path
9617             dirty_reg(&current,CCREG);
9618             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9619           }
9620           else
9621           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9622           {
9623             memcpy(&branch_regs[i-1],&current,sizeof(current));
9624             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9625             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9626             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9627             alloc_cc(&branch_regs[i-1],i);
9628             dirty_reg(&branch_regs[i-1],CCREG);
9629             delayslot_alloc(&branch_regs[i-1],i);
9630             branch_regs[i-1].isconst=0;
9631             alloc_reg(&current,i,CCREG); // Not taken path
9632             dirty_reg(&current,CCREG);
9633             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9634           }
9635           break;
9636         case SJUMP:
9637           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9638           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9639           {
9640             alloc_cc(&current,i-1);
9641             dirty_reg(&current,CCREG);
9642             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9643               // The delay slot overwrote the branch condition
9644               // Delay slot goes after the test (in order)
9645               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9646               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9647               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9648               current.u|=1;
9649               current.uu|=1;
9650               delayslot_alloc(&current,i);
9651               current.isconst=0;
9652             }
9653             else
9654             {
9655               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9656               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9657               // Alloc the branch condition register
9658               alloc_reg(&current,i-1,rs1[i-1]);
9659               if(!(current.is32>>rs1[i-1]&1))
9660               {
9661                 alloc_reg64(&current,i-1,rs1[i-1]);
9662               }
9663             }
9664             memcpy(&branch_regs[i-1],&current,sizeof(current));
9665             branch_regs[i-1].isconst=0;
9666             branch_regs[i-1].wasconst=0;
9667             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9668             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9669           }
9670           else
9671           // Alloc the delay slot in case the branch is taken
9672           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9673           {
9674             memcpy(&branch_regs[i-1],&current,sizeof(current));
9675             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9676             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9677             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9678             alloc_cc(&branch_regs[i-1],i);
9679             dirty_reg(&branch_regs[i-1],CCREG);
9680             delayslot_alloc(&branch_regs[i-1],i);
9681             branch_regs[i-1].isconst=0;
9682             alloc_reg(&current,i,CCREG); // Not taken path
9683             dirty_reg(&current,CCREG);
9684             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9685           }
9686           // FIXME: BLTZAL/BGEZAL
9687           if(opcode2[i-1]&0x10) { // BxxZAL
9688             alloc_reg(&branch_regs[i-1],i-1,31);
9689             dirty_reg(&branch_regs[i-1],31);
9690             branch_regs[i-1].is32|=1LL<<31;
9691           }
9692           break;
9693         case FJUMP:
9694           if(likely[i-1]==0) // BC1F/BC1T
9695           {
9696             alloc_cc(&current,i-1);
9697             dirty_reg(&current,CCREG);
9698             if(itype[i]==FCOMP) {
9699               // The delay slot overwrote the branch condition
9700               // Delay slot goes after the test (in order)
9701               delayslot_alloc(&current,i);
9702               current.isconst=0;
9703             }
9704             else
9705             {
9706               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9707               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9708               // Alloc the branch condition register
9709               alloc_reg(&current,i-1,FSREG);
9710             }
9711             memcpy(&branch_regs[i-1],&current,sizeof(current));
9712             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9713           }
9714           else // BC1FL/BC1TL
9715           {
9716             // Alloc the delay slot in case the branch is taken
9717             memcpy(&branch_regs[i-1],&current,sizeof(current));
9718             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9719             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9720             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9721             alloc_cc(&branch_regs[i-1],i);
9722             dirty_reg(&branch_regs[i-1],CCREG);
9723             delayslot_alloc(&branch_regs[i-1],i);
9724             branch_regs[i-1].isconst=0;
9725             alloc_reg(&current,i,CCREG); // Not taken path
9726             dirty_reg(&current,CCREG);
9727             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9728           }
9729           break;
9730       }
9731
9732       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9733       {
9734         if(rt1[i-1]==31) // JAL/JALR
9735         {
9736           // Subroutine call will return here, don't alloc any registers
9737           current.is32=1;
9738           current.dirty=0;
9739           clear_all_regs(current.regmap);
9740           alloc_reg(&current,i,CCREG);
9741           dirty_reg(&current,CCREG);
9742         }
9743         else if(i+1<slen)
9744         {
9745           // Internal branch will jump here, match registers to caller
9746           current.is32=0x3FFFFFFFFLL;
9747           current.dirty=0;
9748           clear_all_regs(current.regmap);
9749           alloc_reg(&current,i,CCREG);
9750           dirty_reg(&current,CCREG);
9751           for(j=i-1;j>=0;j--)
9752           {
9753             if(ba[j]==start+i*4+4) {
9754               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9755               current.is32=branch_regs[j].is32;
9756               current.dirty=branch_regs[j].dirty;
9757               break;
9758             }
9759           }
9760           while(j>=0) {
9761             if(ba[j]==start+i*4+4) {
9762               for(hr=0;hr<HOST_REGS;hr++) {
9763                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9764                   current.regmap[hr]=-1;
9765                 }
9766                 current.is32&=branch_regs[j].is32;
9767                 current.dirty&=branch_regs[j].dirty;
9768               }
9769             }
9770             j--;
9771           }
9772         }
9773       }
9774     }
9775
9776     // Count cycles in between branches
9777     ccadj[i]=cc;
9778     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9779     {
9780       cc=0;
9781     }
9782 #ifdef PCSX
9783     else if(itype[i]==C2OP&&gte_cycletab[source[i]&0x3f]>2)
9784     {
9785       // GTE runs in parallel until accessed, divide by 2 for a rough guess
9786       cc+=gte_cycletab[source[i]&0x3f]/2;
9787     }
9788     else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9789     {
9790       cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9791     }
9792     else if(itype[i]==C2LS)
9793     {
9794       cc+=4;
9795     }
9796 #endif
9797     else
9798     {
9799       cc++;
9800     }
9801
9802     flush_dirty_uppers(&current);
9803     if(!is_ds[i]) {
9804       regs[i].is32=current.is32;
9805       regs[i].dirty=current.dirty;
9806       regs[i].isconst=current.isconst;
9807       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9808     }
9809     for(hr=0;hr<HOST_REGS;hr++) {
9810       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9811         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9812           regs[i].wasconst&=~(1<<hr);
9813         }
9814       }
9815     }
9816     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9817     regs[i].waswritten=current.waswritten;
9818   }
9819
9820   /* Pass 4 - Cull unused host registers */
9821
9822   uint64_t nr=0;
9823
9824   for (i=slen-1;i>=0;i--)
9825   {
9826     int hr;
9827     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9828     {
9829       if(ba[i]<start || ba[i]>=(start+slen*4))
9830       {
9831         // Branch out of this block, don't need anything
9832         nr=0;
9833       }
9834       else
9835       {
9836         // Internal branch
9837         // Need whatever matches the target
9838         nr=0;
9839         int t=(ba[i]-start)>>2;
9840         for(hr=0;hr<HOST_REGS;hr++)
9841         {
9842           if(regs[i].regmap_entry[hr]>=0) {
9843             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9844           }
9845         }
9846       }
9847       // Conditional branch may need registers for following instructions
9848       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9849       {
9850         if(i<slen-2) {
9851           nr|=needed_reg[i+2];
9852           for(hr=0;hr<HOST_REGS;hr++)
9853           {
9854             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9855             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9856           }
9857         }
9858       }
9859       // Don't need stuff which is overwritten
9860       //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9861       //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9862       // Merge in delay slot
9863       for(hr=0;hr<HOST_REGS;hr++)
9864       {
9865         if(!likely[i]) {
9866           // These are overwritten unless the branch is "likely"
9867           // and the delay slot is nullified if not taken
9868           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9869           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9870         }
9871         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9872         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9873         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9874         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9875         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9876         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9877         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9878         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9879         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9880           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9881           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9882         }
9883         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9884           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9885           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9886         }
9887         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9888           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9889           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9890         }
9891       }
9892     }
9893     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9894     {
9895       // SYSCALL instruction (software interrupt)
9896       nr=0;
9897     }
9898     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9899     {
9900       // ERET instruction (return from interrupt)
9901       nr=0;
9902     }
9903     else // Non-branch
9904     {
9905       if(i<slen-1) {
9906         for(hr=0;hr<HOST_REGS;hr++) {
9907           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9908           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9909           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9910           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9911         }
9912       }
9913     }
9914     for(hr=0;hr<HOST_REGS;hr++)
9915     {
9916       // Overwritten registers are not needed
9917       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9918       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9919       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9920       // Source registers are needed
9921       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9922       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9923       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9924       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9925       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9926       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9927       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9928       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9929       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9930         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9931         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9932       }
9933       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9934         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9935         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9936       }
9937       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9938         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9939         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9940       }
9941       // Don't store a register immediately after writing it,
9942       // may prevent dual-issue.
9943       // But do so if this is a branch target, otherwise we
9944       // might have to load the register before the branch.
9945       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9946         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9947            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9948           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9949           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9950         }
9951         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9952            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9953           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9954           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9955         }
9956       }
9957     }
9958     // Cycle count is needed at branches.  Assume it is needed at the target too.
9959     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9960       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9961       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9962     }
9963     // Save it
9964     needed_reg[i]=nr;
9965
9966     // Deallocate unneeded registers
9967     for(hr=0;hr<HOST_REGS;hr++)
9968     {
9969       if(!((nr>>hr)&1)) {
9970         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9971         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9972            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9973            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9974         {
9975           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9976           {
9977             if(likely[i]) {
9978               regs[i].regmap[hr]=-1;
9979               regs[i].isconst&=~(1<<hr);
9980               if(i<slen-2) {
9981                 regmap_pre[i+2][hr]=-1;
9982                 regs[i+2].wasconst&=~(1<<hr);
9983               }
9984             }
9985           }
9986         }
9987         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9988         {
9989           int d1=0,d2=0,map=0,temp=0;
9990           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9991           {
9992             d1=dep1[i+1];
9993             d2=dep2[i+1];
9994           }
9995           if(using_tlb) {
9996             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9997                itype[i+1]==STORE || itype[i+1]==STORELR ||
9998                itype[i+1]==C1LS || itype[i+1]==C2LS)
9999             map=TLREG;
10000           } else
10001           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
10002              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10003             map=INVCP;
10004           }
10005           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
10006              itype[i+1]==C1LS || itype[i+1]==C2LS)
10007             temp=FTEMP;
10008           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10009              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10010              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
10011              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
10012              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10013              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
10014              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
10015              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
10016              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
10017              regs[i].regmap[hr]!=map )
10018           {
10019             regs[i].regmap[hr]=-1;
10020             regs[i].isconst&=~(1<<hr);
10021             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
10022                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
10023                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
10024                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
10025                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
10026                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
10027                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
10028                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
10029                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
10030                branch_regs[i].regmap[hr]!=map)
10031             {
10032               branch_regs[i].regmap[hr]=-1;
10033               branch_regs[i].regmap_entry[hr]=-1;
10034               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10035               {
10036                 if(!likely[i]&&i<slen-2) {
10037                   regmap_pre[i+2][hr]=-1;
10038                   regs[i+2].wasconst&=~(1<<hr);
10039                 }
10040               }
10041             }
10042           }
10043         }
10044         else
10045         {
10046           // Non-branch
10047           if(i>0)
10048           {
10049             int d1=0,d2=0,map=-1,temp=-1;
10050             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10051             {
10052               d1=dep1[i];
10053               d2=dep2[i];
10054             }
10055             if(using_tlb) {
10056               if(itype[i]==LOAD || itype[i]==LOADLR ||
10057                  itype[i]==STORE || itype[i]==STORELR ||
10058                  itype[i]==C1LS || itype[i]==C2LS)
10059               map=TLREG;
10060             } else if(itype[i]==STORE || itype[i]==STORELR ||
10061                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10062               map=INVCP;
10063             }
10064             if(itype[i]==LOADLR || itype[i]==STORELR ||
10065                itype[i]==C1LS || itype[i]==C2LS)
10066               temp=FTEMP;
10067             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10068                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10069                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10070                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10071                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10072                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10073             {
10074               if(i<slen-1&&!is_ds[i]) {
10075                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10076                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10077                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10078                 {
10079                   printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10080                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10081                 }
10082                 regmap_pre[i+1][hr]=-1;
10083                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10084                 regs[i+1].wasconst&=~(1<<hr);
10085               }
10086               regs[i].regmap[hr]=-1;
10087               regs[i].isconst&=~(1<<hr);
10088             }
10089           }
10090         }
10091       }
10092     }
10093   }
10094
10095   /* Pass 5 - Pre-allocate registers */
10096
10097   // If a register is allocated during a loop, try to allocate it for the
10098   // entire loop, if possible.  This avoids loading/storing registers
10099   // inside of the loop.
10100
10101   signed char f_regmap[HOST_REGS];
10102   clear_all_regs(f_regmap);
10103   for(i=0;i<slen-1;i++)
10104   {
10105     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10106     {
10107       if(ba[i]>=start && ba[i]<(start+i*4))
10108       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10109       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10110       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10111       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10112       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10113       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10114       {
10115         int t=(ba[i]-start)>>2;
10116         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10117         if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10118         for(hr=0;hr<HOST_REGS;hr++)
10119         {
10120           if(regs[i].regmap[hr]>64) {
10121             if(!((regs[i].dirty>>hr)&1))
10122               f_regmap[hr]=regs[i].regmap[hr];
10123             else f_regmap[hr]=-1;
10124           }
10125           else if(regs[i].regmap[hr]>=0) {
10126             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10127               // dealloc old register
10128               int n;
10129               for(n=0;n<HOST_REGS;n++)
10130               {
10131                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10132               }
10133               // and alloc new one
10134               f_regmap[hr]=regs[i].regmap[hr];
10135             }
10136           }
10137           if(branch_regs[i].regmap[hr]>64) {
10138             if(!((branch_regs[i].dirty>>hr)&1))
10139               f_regmap[hr]=branch_regs[i].regmap[hr];
10140             else f_regmap[hr]=-1;
10141           }
10142           else if(branch_regs[i].regmap[hr]>=0) {
10143             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10144               // dealloc old register
10145               int n;
10146               for(n=0;n<HOST_REGS;n++)
10147               {
10148                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10149               }
10150               // and alloc new one
10151               f_regmap[hr]=branch_regs[i].regmap[hr];
10152             }
10153           }
10154           if(ooo[i]) {
10155             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10156               f_regmap[hr]=branch_regs[i].regmap[hr];
10157           }else{
10158             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10159               f_regmap[hr]=branch_regs[i].regmap[hr];
10160           }
10161           // Avoid dirty->clean transition
10162           #ifdef DESTRUCTIVE_WRITEBACK
10163           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10164           #endif
10165           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10166           // case above, however it's always a good idea.  We can't hoist the
10167           // load if the register was already allocated, so there's no point
10168           // wasting time analyzing most of these cases.  It only "succeeds"
10169           // when the mapping was different and the load can be replaced with
10170           // a mov, which is of negligible benefit.  So such cases are
10171           // skipped below.
10172           if(f_regmap[hr]>0) {
10173             if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10174               int r=f_regmap[hr];
10175               for(j=t;j<=i;j++)
10176               {
10177                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10178                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10179                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10180                 if(r>63) {
10181                   // NB This can exclude the case where the upper-half
10182                   // register is lower numbered than the lower-half
10183                   // register.  Not sure if it's worth fixing...
10184                   if(get_reg(regs[j].regmap,r&63)<0) break;
10185                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10186                   if(regs[j].is32&(1LL<<(r&63))) break;
10187                 }
10188                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10189                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10190                   int k;
10191                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10192                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10193                     if(r>63) {
10194                       if(get_reg(regs[i].regmap,r&63)<0) break;
10195                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10196                     }
10197                     k=i;
10198                     while(k>1&&regs[k-1].regmap[hr]==-1) {
10199                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10200                         //printf("no free regs for store %x\n",start+(k-1)*4);
10201                         break;
10202                       }
10203                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10204                         //printf("no-match due to different register\n");
10205                         break;
10206                       }
10207                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10208                         //printf("no-match due to branch\n");
10209                         break;
10210                       }
10211                       // call/ret fast path assumes no registers allocated
10212                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10213                         break;
10214                       }
10215                       if(r>63) {
10216                         // NB This can exclude the case where the upper-half
10217                         // register is lower numbered than the lower-half
10218                         // register.  Not sure if it's worth fixing...
10219                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
10220                         if(regs[k-1].is32&(1LL<<(r&63))) break;
10221                       }
10222                       k--;
10223                     }
10224                     if(i<slen-1) {
10225                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10226                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10227                         //printf("bad match after branch\n");
10228                         break;
10229                       }
10230                     }
10231                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10232                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
10233                       while(k<i) {
10234                         regs[k].regmap_entry[hr]=f_regmap[hr];
10235                         regs[k].regmap[hr]=f_regmap[hr];
10236                         regmap_pre[k+1][hr]=f_regmap[hr];
10237                         regs[k].wasdirty&=~(1<<hr);
10238                         regs[k].dirty&=~(1<<hr);
10239                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10240                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10241                         regs[k].wasconst&=~(1<<hr);
10242                         regs[k].isconst&=~(1<<hr);
10243                         k++;
10244                       }
10245                     }
10246                     else {
10247                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10248                       break;
10249                     }
10250                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10251                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10252                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
10253                       regs[i].regmap_entry[hr]=f_regmap[hr];
10254                       regs[i].regmap[hr]=f_regmap[hr];
10255                       regs[i].wasdirty&=~(1<<hr);
10256                       regs[i].dirty&=~(1<<hr);
10257                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10258                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10259                       regs[i].wasconst&=~(1<<hr);
10260                       regs[i].isconst&=~(1<<hr);
10261                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10262                       branch_regs[i].wasdirty&=~(1<<hr);
10263                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10264                       branch_regs[i].regmap[hr]=f_regmap[hr];
10265                       branch_regs[i].dirty&=~(1<<hr);
10266                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10267                       branch_regs[i].wasconst&=~(1<<hr);
10268                       branch_regs[i].isconst&=~(1<<hr);
10269                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10270                         regmap_pre[i+2][hr]=f_regmap[hr];
10271                         regs[i+2].wasdirty&=~(1<<hr);
10272                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10273                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10274                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
10275                       }
10276                     }
10277                   }
10278                   for(k=t;k<j;k++) {
10279                     // Alloc register clean at beginning of loop,
10280                     // but may dirty it in pass 6
10281                     regs[k].regmap_entry[hr]=f_regmap[hr];
10282                     regs[k].regmap[hr]=f_regmap[hr];
10283                     regs[k].dirty&=~(1<<hr);
10284                     regs[k].wasconst&=~(1<<hr);
10285                     regs[k].isconst&=~(1<<hr);
10286                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10287                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10288                       branch_regs[k].regmap[hr]=f_regmap[hr];
10289                       branch_regs[k].dirty&=~(1<<hr);
10290                       branch_regs[k].wasconst&=~(1<<hr);
10291                       branch_regs[k].isconst&=~(1<<hr);
10292                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10293                         regmap_pre[k+2][hr]=f_regmap[hr];
10294                         regs[k+2].wasdirty&=~(1<<hr);
10295                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10296                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
10297                       }
10298                     }
10299                     else
10300                     {
10301                       regmap_pre[k+1][hr]=f_regmap[hr];
10302                       regs[k+1].wasdirty&=~(1<<hr);
10303                     }
10304                   }
10305                   if(regs[j].regmap[hr]==f_regmap[hr])
10306                     regs[j].regmap_entry[hr]=f_regmap[hr];
10307                   break;
10308                 }
10309                 if(j==i) break;
10310                 if(regs[j].regmap[hr]>=0)
10311                   break;
10312                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10313                   //printf("no-match due to different register\n");
10314                   break;
10315                 }
10316                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10317                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10318                   break;
10319                 }
10320                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10321                 {
10322                   // Stop on unconditional branch
10323                   break;
10324                 }
10325                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10326                 {
10327                   if(ooo[j]) {
10328                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10329                       break;
10330                   }else{
10331                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10332                       break;
10333                   }
10334                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10335                     //printf("no-match due to different register (branch)\n");
10336                     break;
10337                   }
10338                 }
10339                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10340                   //printf("No free regs for store %x\n",start+j*4);
10341                   break;
10342                 }
10343                 if(f_regmap[hr]>=64) {
10344                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10345                     break;
10346                   }
10347                   else
10348                   {
10349                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10350                       break;
10351                     }
10352                   }
10353                 }
10354               }
10355             }
10356           }
10357         }
10358       }
10359     }else{
10360       // Non branch or undetermined branch target
10361       for(hr=0;hr<HOST_REGS;hr++)
10362       {
10363         if(hr!=EXCLUDE_REG) {
10364           if(regs[i].regmap[hr]>64) {
10365             if(!((regs[i].dirty>>hr)&1))
10366               f_regmap[hr]=regs[i].regmap[hr];
10367           }
10368           else if(regs[i].regmap[hr]>=0) {
10369             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10370               // dealloc old register
10371               int n;
10372               for(n=0;n<HOST_REGS;n++)
10373               {
10374                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10375               }
10376               // and alloc new one
10377               f_regmap[hr]=regs[i].regmap[hr];
10378             }
10379           }
10380         }
10381       }
10382       // Try to restore cycle count at branch targets
10383       if(bt[i]) {
10384         for(j=i;j<slen-1;j++) {
10385           if(regs[j].regmap[HOST_CCREG]!=-1) break;
10386           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10387             //printf("no free regs for store %x\n",start+j*4);
10388             break;
10389           }
10390         }
10391         if(regs[j].regmap[HOST_CCREG]==CCREG) {
10392           int k=i;
10393           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10394           while(k<j) {
10395             regs[k].regmap_entry[HOST_CCREG]=CCREG;
10396             regs[k].regmap[HOST_CCREG]=CCREG;
10397             regmap_pre[k+1][HOST_CCREG]=CCREG;
10398             regs[k+1].wasdirty|=1<<HOST_CCREG;
10399             regs[k].dirty|=1<<HOST_CCREG;
10400             regs[k].wasconst&=~(1<<HOST_CCREG);
10401             regs[k].isconst&=~(1<<HOST_CCREG);
10402             k++;
10403           }
10404           regs[j].regmap_entry[HOST_CCREG]=CCREG;
10405         }
10406         // Work backwards from the branch target
10407         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10408         {
10409           //printf("Extend backwards\n");
10410           int k;
10411           k=i;
10412           while(regs[k-1].regmap[HOST_CCREG]==-1) {
10413             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10414               //printf("no free regs for store %x\n",start+(k-1)*4);
10415               break;
10416             }
10417             k--;
10418           }
10419           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10420             //printf("Extend CC, %x ->\n",start+k*4);
10421             while(k<=i) {
10422               regs[k].regmap_entry[HOST_CCREG]=CCREG;
10423               regs[k].regmap[HOST_CCREG]=CCREG;
10424               regmap_pre[k+1][HOST_CCREG]=CCREG;
10425               regs[k+1].wasdirty|=1<<HOST_CCREG;
10426               regs[k].dirty|=1<<HOST_CCREG;
10427               regs[k].wasconst&=~(1<<HOST_CCREG);
10428               regs[k].isconst&=~(1<<HOST_CCREG);
10429               k++;
10430             }
10431           }
10432           else {
10433             //printf("Fail Extend CC, %x ->\n",start+k*4);
10434           }
10435         }
10436       }
10437       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10438          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10439          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10440          itype[i]!=FCONV&&itype[i]!=FCOMP)
10441       {
10442         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10443       }
10444     }
10445   }
10446
10447   // Cache memory offset or tlb map pointer if a register is available
10448   #ifndef HOST_IMM_ADDR32
10449   #ifndef RAM_OFFSET
10450   if(using_tlb)
10451   #endif
10452   {
10453     int earliest_available[HOST_REGS];
10454     int loop_start[HOST_REGS];
10455     int score[HOST_REGS];
10456     int end[HOST_REGS];
10457     int reg=using_tlb?MMREG:ROREG;
10458
10459     // Init
10460     for(hr=0;hr<HOST_REGS;hr++) {
10461       score[hr]=0;earliest_available[hr]=0;
10462       loop_start[hr]=MAXBLOCK;
10463     }
10464     for(i=0;i<slen-1;i++)
10465     {
10466       // Can't do anything if no registers are available
10467       if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10468         for(hr=0;hr<HOST_REGS;hr++) {
10469           score[hr]=0;earliest_available[hr]=i+1;
10470           loop_start[hr]=MAXBLOCK;
10471         }
10472       }
10473       if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10474         if(!ooo[i]) {
10475           if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10476             for(hr=0;hr<HOST_REGS;hr++) {
10477               score[hr]=0;earliest_available[hr]=i+1;
10478               loop_start[hr]=MAXBLOCK;
10479             }
10480           }
10481         }else{
10482           if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10483             for(hr=0;hr<HOST_REGS;hr++) {
10484               score[hr]=0;earliest_available[hr]=i+1;
10485               loop_start[hr]=MAXBLOCK;
10486             }
10487           }
10488         }
10489       }
10490       // Mark unavailable registers
10491       for(hr=0;hr<HOST_REGS;hr++) {
10492         if(regs[i].regmap[hr]>=0) {
10493           score[hr]=0;earliest_available[hr]=i+1;
10494           loop_start[hr]=MAXBLOCK;
10495         }
10496         if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10497           if(branch_regs[i].regmap[hr]>=0) {
10498             score[hr]=0;earliest_available[hr]=i+2;
10499             loop_start[hr]=MAXBLOCK;
10500           }
10501         }
10502       }
10503       // No register allocations after unconditional jumps
10504       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10505       {
10506         for(hr=0;hr<HOST_REGS;hr++) {
10507           score[hr]=0;earliest_available[hr]=i+2;
10508           loop_start[hr]=MAXBLOCK;
10509         }
10510         i++; // Skip delay slot too
10511         //printf("skip delay slot: %x\n",start+i*4);
10512       }
10513       else
10514       // Possible match
10515       if(itype[i]==LOAD||itype[i]==LOADLR||
10516          itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10517         for(hr=0;hr<HOST_REGS;hr++) {
10518           if(hr!=EXCLUDE_REG) {
10519             end[hr]=i-1;
10520             for(j=i;j<slen-1;j++) {
10521               if(regs[j].regmap[hr]>=0) break;
10522               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10523                 if(branch_regs[j].regmap[hr]>=0) break;
10524                 if(ooo[j]) {
10525                   if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10526                 }else{
10527                   if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10528                 }
10529               }
10530               else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10531               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10532                 int t=(ba[j]-start)>>2;
10533                 if(t<j&&t>=earliest_available[hr]) {
10534                   if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10535                     // Score a point for hoisting loop invariant
10536                     if(t<loop_start[hr]) loop_start[hr]=t;
10537                     //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10538                     score[hr]++;
10539                     end[hr]=j;
10540                   }
10541                 }
10542                 else if(t<j) {
10543                   if(regs[t].regmap[hr]==reg) {
10544                     // Score a point if the branch target matches this register
10545                     score[hr]++;
10546                     end[hr]=j;
10547                   }
10548                 }
10549                 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10550                    itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10551                   score[hr]++;
10552                   end[hr]=j;
10553                 }
10554               }
10555               if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10556               {
10557                 // Stop on unconditional branch
10558                 break;
10559               }
10560               else
10561               if(itype[j]==LOAD||itype[j]==LOADLR||
10562                  itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10563                 score[hr]++;
10564                 end[hr]=j;
10565               }
10566             }
10567           }
10568         }
10569         // Find highest score and allocate that register
10570         int maxscore=0;
10571         for(hr=0;hr<HOST_REGS;hr++) {
10572           if(hr!=EXCLUDE_REG) {
10573             if(score[hr]>score[maxscore]) {
10574               maxscore=hr;
10575               //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10576             }
10577           }
10578         }
10579         if(score[maxscore]>1)
10580         {
10581           if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10582           for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10583             //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10584             assert(regs[j].regmap[maxscore]<0);
10585             if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10586             regs[j].regmap[maxscore]=reg;
10587             regs[j].dirty&=~(1<<maxscore);
10588             regs[j].wasconst&=~(1<<maxscore);
10589             regs[j].isconst&=~(1<<maxscore);
10590             if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10591               branch_regs[j].regmap[maxscore]=reg;
10592               branch_regs[j].wasdirty&=~(1<<maxscore);
10593               branch_regs[j].dirty&=~(1<<maxscore);
10594               branch_regs[j].wasconst&=~(1<<maxscore);
10595               branch_regs[j].isconst&=~(1<<maxscore);
10596               if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10597                 regmap_pre[j+2][maxscore]=reg;
10598                 regs[j+2].wasdirty&=~(1<<maxscore);
10599               }
10600               // loop optimization (loop_preload)
10601               int t=(ba[j]-start)>>2;
10602               if(t==loop_start[maxscore]) {
10603                 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10604                   regs[t].regmap_entry[maxscore]=reg;
10605               }
10606             }
10607             else
10608             {
10609               if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10610                 regmap_pre[j+1][maxscore]=reg;
10611                 regs[j+1].wasdirty&=~(1<<maxscore);
10612               }
10613             }
10614           }
10615           i=j-1;
10616           if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10617           for(hr=0;hr<HOST_REGS;hr++) {
10618             score[hr]=0;earliest_available[hr]=i+i;
10619             loop_start[hr]=MAXBLOCK;
10620           }
10621         }
10622       }
10623     }
10624   }
10625   #endif
10626
10627   // This allocates registers (if possible) one instruction prior
10628   // to use, which can avoid a load-use penalty on certain CPUs.
10629   for(i=0;i<slen-1;i++)
10630   {
10631     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10632     {
10633       if(!bt[i+1])
10634       {
10635         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10636            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10637         {
10638           if(rs1[i+1]) {
10639             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10640             {
10641               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10642               {
10643                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10644                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10645                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10646                 regs[i].isconst&=~(1<<hr);
10647                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10648                 constmap[i][hr]=constmap[i+1][hr];
10649                 regs[i+1].wasdirty&=~(1<<hr);
10650                 regs[i].dirty&=~(1<<hr);
10651               }
10652             }
10653           }
10654           if(rs2[i+1]) {
10655             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10656             {
10657               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10658               {
10659                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10660                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10661                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10662                 regs[i].isconst&=~(1<<hr);
10663                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10664                 constmap[i][hr]=constmap[i+1][hr];
10665                 regs[i+1].wasdirty&=~(1<<hr);
10666                 regs[i].dirty&=~(1<<hr);
10667               }
10668             }
10669           }
10670           // Preload target address for load instruction (non-constant)
10671           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10672             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10673             {
10674               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10675               {
10676                 regs[i].regmap[hr]=rs1[i+1];
10677                 regmap_pre[i+1][hr]=rs1[i+1];
10678                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10679                 regs[i].isconst&=~(1<<hr);
10680                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10681                 constmap[i][hr]=constmap[i+1][hr];
10682                 regs[i+1].wasdirty&=~(1<<hr);
10683                 regs[i].dirty&=~(1<<hr);
10684               }
10685             }
10686           }
10687           // Load source into target register
10688           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10689             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10690             {
10691               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10692               {
10693                 regs[i].regmap[hr]=rs1[i+1];
10694                 regmap_pre[i+1][hr]=rs1[i+1];
10695                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10696                 regs[i].isconst&=~(1<<hr);
10697                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10698                 constmap[i][hr]=constmap[i+1][hr];
10699                 regs[i+1].wasdirty&=~(1<<hr);
10700                 regs[i].dirty&=~(1<<hr);
10701               }
10702             }
10703           }
10704           // Preload map address
10705           #ifndef HOST_IMM_ADDR32
10706           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10707             hr=get_reg(regs[i+1].regmap,TLREG);
10708             if(hr>=0) {
10709               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10710               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10711                 int nr;
10712                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10713                 {
10714                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10715                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10716                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10717                   regs[i].isconst&=~(1<<hr);
10718                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10719                   constmap[i][hr]=constmap[i+1][hr];
10720                   regs[i+1].wasdirty&=~(1<<hr);
10721                   regs[i].dirty&=~(1<<hr);
10722                 }
10723                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10724                 {
10725                   // move it to another register
10726                   regs[i+1].regmap[hr]=-1;
10727                   regmap_pre[i+2][hr]=-1;
10728                   regs[i+1].regmap[nr]=TLREG;
10729                   regmap_pre[i+2][nr]=TLREG;
10730                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10731                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10732                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10733                   regs[i].isconst&=~(1<<nr);
10734                   regs[i+1].isconst&=~(1<<nr);
10735                   regs[i].dirty&=~(1<<nr);
10736                   regs[i+1].wasdirty&=~(1<<nr);
10737                   regs[i+1].dirty&=~(1<<nr);
10738                   regs[i+2].wasdirty&=~(1<<nr);
10739                 }
10740               }
10741             }
10742           }
10743           #endif
10744           // Address for store instruction (non-constant)
10745           if(itype[i+1]==STORE||itype[i+1]==STORELR
10746              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10747             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10748               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10749               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10750               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10751               assert(hr>=0);
10752               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10753               {
10754                 regs[i].regmap[hr]=rs1[i+1];
10755                 regmap_pre[i+1][hr]=rs1[i+1];
10756                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10757                 regs[i].isconst&=~(1<<hr);
10758                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10759                 constmap[i][hr]=constmap[i+1][hr];
10760                 regs[i+1].wasdirty&=~(1<<hr);
10761                 regs[i].dirty&=~(1<<hr);
10762               }
10763             }
10764           }
10765           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10766             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10767               int nr;
10768               hr=get_reg(regs[i+1].regmap,FTEMP);
10769               assert(hr>=0);
10770               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10771               {
10772                 regs[i].regmap[hr]=rs1[i+1];
10773                 regmap_pre[i+1][hr]=rs1[i+1];
10774                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10775                 regs[i].isconst&=~(1<<hr);
10776                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10777                 constmap[i][hr]=constmap[i+1][hr];
10778                 regs[i+1].wasdirty&=~(1<<hr);
10779                 regs[i].dirty&=~(1<<hr);
10780               }
10781               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10782               {
10783                 // move it to another register
10784                 regs[i+1].regmap[hr]=-1;
10785                 regmap_pre[i+2][hr]=-1;
10786                 regs[i+1].regmap[nr]=FTEMP;
10787                 regmap_pre[i+2][nr]=FTEMP;
10788                 regs[i].regmap[nr]=rs1[i+1];
10789                 regmap_pre[i+1][nr]=rs1[i+1];
10790                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10791                 regs[i].isconst&=~(1<<nr);
10792                 regs[i+1].isconst&=~(1<<nr);
10793                 regs[i].dirty&=~(1<<nr);
10794                 regs[i+1].wasdirty&=~(1<<nr);
10795                 regs[i+1].dirty&=~(1<<nr);
10796                 regs[i+2].wasdirty&=~(1<<nr);
10797               }
10798             }
10799           }
10800           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10801             if(itype[i+1]==LOAD)
10802               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10803             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10804               hr=get_reg(regs[i+1].regmap,FTEMP);
10805             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10806               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10807               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10808             }
10809             if(hr>=0&&regs[i].regmap[hr]<0) {
10810               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10811               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10812                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10813                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10814                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10815                 regs[i].isconst&=~(1<<hr);
10816                 regs[i+1].wasdirty&=~(1<<hr);
10817                 regs[i].dirty&=~(1<<hr);
10818               }
10819             }
10820           }
10821         }
10822       }
10823     }
10824   }
10825
10826   /* Pass 6 - Optimize clean/dirty state */
10827   clean_registers(0,slen-1,1);
10828
10829   /* Pass 7 - Identify 32-bit registers */
10830 #ifndef FORCE32
10831   provisional_r32();
10832
10833   u_int r32=0;
10834
10835   for (i=slen-1;i>=0;i--)
10836   {
10837     int hr;
10838     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10839     {
10840       if(ba[i]<start || ba[i]>=(start+slen*4))
10841       {
10842         // Branch out of this block, don't need anything
10843         r32=0;
10844       }
10845       else
10846       {
10847         // Internal branch
10848         // Need whatever matches the target
10849         // (and doesn't get overwritten by the delay slot instruction)
10850         r32=0;
10851         int t=(ba[i]-start)>>2;
10852         if(ba[i]>start+i*4) {
10853           // Forward branch
10854           if(!(requires_32bit[t]&~regs[i].was32))
10855             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10856         }else{
10857           // Backward branch
10858           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10859           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10860           if(!(pr32[t]&~regs[i].was32))
10861             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10862         }
10863       }
10864       // Conditional branch may need registers for following instructions
10865       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10866       {
10867         if(i<slen-2) {
10868           r32|=requires_32bit[i+2];
10869           r32&=regs[i].was32;
10870           // Mark this address as a branch target since it may be called
10871           // upon return from interrupt
10872           bt[i+2]=1;
10873         }
10874       }
10875       // Merge in delay slot
10876       if(!likely[i]) {
10877         // These are overwritten unless the branch is "likely"
10878         // and the delay slot is nullified if not taken
10879         r32&=~(1LL<<rt1[i+1]);
10880         r32&=~(1LL<<rt2[i+1]);
10881       }
10882       // Assume these are needed (delay slot)
10883       if(us1[i+1]>0)
10884       {
10885         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10886       }
10887       if(us2[i+1]>0)
10888       {
10889         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10890       }
10891       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10892       {
10893         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10894       }
10895       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10896       {
10897         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10898       }
10899     }
10900     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10901     {
10902       // SYSCALL instruction (software interrupt)
10903       r32=0;
10904     }
10905     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10906     {
10907       // ERET instruction (return from interrupt)
10908       r32=0;
10909     }
10910     // Check 32 bits
10911     r32&=~(1LL<<rt1[i]);
10912     r32&=~(1LL<<rt2[i]);
10913     if(us1[i]>0)
10914     {
10915       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10916     }
10917     if(us2[i]>0)
10918     {
10919       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10920     }
10921     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10922     {
10923       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10924     }
10925     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10926     {
10927       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10928     }
10929     requires_32bit[i]=r32;
10930
10931     // Dirty registers which are 32-bit, require 32-bit input
10932     // as they will be written as 32-bit values
10933     for(hr=0;hr<HOST_REGS;hr++)
10934     {
10935       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10936         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10937           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10938           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10939         }
10940       }
10941     }
10942     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10943   }
10944 #else
10945   for (i=slen-1;i>=0;i--)
10946   {
10947     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10948     {
10949       // Conditional branch
10950       if((source[i]>>16)!=0x1000&&i<slen-2) {
10951         // Mark this address as a branch target since it may be called
10952         // upon return from interrupt
10953         bt[i+2]=1;
10954       }
10955     }
10956   }
10957 #endif
10958
10959   if(itype[slen-1]==SPAN) {
10960     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10961   }
10962
10963 #ifdef DISASM
10964   /* Debug/disassembly */
10965   for(i=0;i<slen;i++)
10966   {
10967     printf("U:");
10968     int r;
10969     for(r=1;r<=CCREG;r++) {
10970       if((unneeded_reg[i]>>r)&1) {
10971         if(r==HIREG) printf(" HI");
10972         else if(r==LOREG) printf(" LO");
10973         else printf(" r%d",r);
10974       }
10975     }
10976 #ifndef FORCE32
10977     printf(" UU:");
10978     for(r=1;r<=CCREG;r++) {
10979       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10980         if(r==HIREG) printf(" HI");
10981         else if(r==LOREG) printf(" LO");
10982         else printf(" r%d",r);
10983       }
10984     }
10985     printf(" 32:");
10986     for(r=0;r<=CCREG;r++) {
10987       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10988       if((regs[i].was32>>r)&1) {
10989         if(r==CCREG) printf(" CC");
10990         else if(r==HIREG) printf(" HI");
10991         else if(r==LOREG) printf(" LO");
10992         else printf(" r%d",r);
10993       }
10994     }
10995 #endif
10996     printf("\n");
10997     #if defined(__i386__) || defined(__x86_64__)
10998     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10999     #endif
11000     #ifdef __arm__
11001     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
11002     #endif
11003     printf("needs: ");
11004     if(needed_reg[i]&1) printf("eax ");
11005     if((needed_reg[i]>>1)&1) printf("ecx ");
11006     if((needed_reg[i]>>2)&1) printf("edx ");
11007     if((needed_reg[i]>>3)&1) printf("ebx ");
11008     if((needed_reg[i]>>5)&1) printf("ebp ");
11009     if((needed_reg[i]>>6)&1) printf("esi ");
11010     if((needed_reg[i]>>7)&1) printf("edi ");
11011     printf("r:");
11012     for(r=0;r<=CCREG;r++) {
11013       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11014       if((requires_32bit[i]>>r)&1) {
11015         if(r==CCREG) printf(" CC");
11016         else if(r==HIREG) printf(" HI");
11017         else if(r==LOREG) printf(" LO");
11018         else printf(" r%d",r);
11019       }
11020     }
11021     printf("\n");
11022     /*printf("pr:");
11023     for(r=0;r<=CCREG;r++) {
11024       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11025       if((pr32[i]>>r)&1) {
11026         if(r==CCREG) printf(" CC");
11027         else if(r==HIREG) printf(" HI");
11028         else if(r==LOREG) printf(" LO");
11029         else printf(" r%d",r);
11030       }
11031     }
11032     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11033     printf("\n");*/
11034     #if defined(__i386__) || defined(__x86_64__)
11035     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11036     printf("dirty: ");
11037     if(regs[i].wasdirty&1) printf("eax ");
11038     if((regs[i].wasdirty>>1)&1) printf("ecx ");
11039     if((regs[i].wasdirty>>2)&1) printf("edx ");
11040     if((regs[i].wasdirty>>3)&1) printf("ebx ");
11041     if((regs[i].wasdirty>>5)&1) printf("ebp ");
11042     if((regs[i].wasdirty>>6)&1) printf("esi ");
11043     if((regs[i].wasdirty>>7)&1) printf("edi ");
11044     #endif
11045     #ifdef __arm__
11046     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11047     printf("dirty: ");
11048     if(regs[i].wasdirty&1) printf("r0 ");
11049     if((regs[i].wasdirty>>1)&1) printf("r1 ");
11050     if((regs[i].wasdirty>>2)&1) printf("r2 ");
11051     if((regs[i].wasdirty>>3)&1) printf("r3 ");
11052     if((regs[i].wasdirty>>4)&1) printf("r4 ");
11053     if((regs[i].wasdirty>>5)&1) printf("r5 ");
11054     if((regs[i].wasdirty>>6)&1) printf("r6 ");
11055     if((regs[i].wasdirty>>7)&1) printf("r7 ");
11056     if((regs[i].wasdirty>>8)&1) printf("r8 ");
11057     if((regs[i].wasdirty>>9)&1) printf("r9 ");
11058     if((regs[i].wasdirty>>10)&1) printf("r10 ");
11059     if((regs[i].wasdirty>>12)&1) printf("r12 ");
11060     #endif
11061     printf("\n");
11062     disassemble_inst(i);
11063     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11064     #if defined(__i386__) || defined(__x86_64__)
11065     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11066     if(regs[i].dirty&1) printf("eax ");
11067     if((regs[i].dirty>>1)&1) printf("ecx ");
11068     if((regs[i].dirty>>2)&1) printf("edx ");
11069     if((regs[i].dirty>>3)&1) printf("ebx ");
11070     if((regs[i].dirty>>5)&1) printf("ebp ");
11071     if((regs[i].dirty>>6)&1) printf("esi ");
11072     if((regs[i].dirty>>7)&1) printf("edi ");
11073     #endif
11074     #ifdef __arm__
11075     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11076     if(regs[i].dirty&1) printf("r0 ");
11077     if((regs[i].dirty>>1)&1) printf("r1 ");
11078     if((regs[i].dirty>>2)&1) printf("r2 ");
11079     if((regs[i].dirty>>3)&1) printf("r3 ");
11080     if((regs[i].dirty>>4)&1) printf("r4 ");
11081     if((regs[i].dirty>>5)&1) printf("r5 ");
11082     if((regs[i].dirty>>6)&1) printf("r6 ");
11083     if((regs[i].dirty>>7)&1) printf("r7 ");
11084     if((regs[i].dirty>>8)&1) printf("r8 ");
11085     if((regs[i].dirty>>9)&1) printf("r9 ");
11086     if((regs[i].dirty>>10)&1) printf("r10 ");
11087     if((regs[i].dirty>>12)&1) printf("r12 ");
11088     #endif
11089     printf("\n");
11090     if(regs[i].isconst) {
11091       printf("constants: ");
11092       #if defined(__i386__) || defined(__x86_64__)
11093       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11094       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11095       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11096       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11097       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11098       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11099       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11100       #endif
11101       #ifdef __arm__
11102       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11103       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11104       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11105       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11106       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11107       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11108       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11109       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11110       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11111       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11112       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11113       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11114       #endif
11115       printf("\n");
11116     }
11117 #ifndef FORCE32
11118     printf(" 32:");
11119     for(r=0;r<=CCREG;r++) {
11120       if((regs[i].is32>>r)&1) {
11121         if(r==CCREG) printf(" CC");
11122         else if(r==HIREG) printf(" HI");
11123         else if(r==LOREG) printf(" LO");
11124         else printf(" r%d",r);
11125       }
11126     }
11127     printf("\n");
11128 #endif
11129     /*printf(" p32:");
11130     for(r=0;r<=CCREG;r++) {
11131       if((p32[i]>>r)&1) {
11132         if(r==CCREG) printf(" CC");
11133         else if(r==HIREG) printf(" HI");
11134         else if(r==LOREG) printf(" LO");
11135         else printf(" r%d",r);
11136       }
11137     }
11138     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11139     else printf("\n");*/
11140     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11141       #if defined(__i386__) || defined(__x86_64__)
11142       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11143       if(branch_regs[i].dirty&1) printf("eax ");
11144       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11145       if((branch_regs[i].dirty>>2)&1) printf("edx ");
11146       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11147       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11148       if((branch_regs[i].dirty>>6)&1) printf("esi ");
11149       if((branch_regs[i].dirty>>7)&1) printf("edi ");
11150       #endif
11151       #ifdef __arm__
11152       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11153       if(branch_regs[i].dirty&1) printf("r0 ");
11154       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11155       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11156       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11157       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11158       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11159       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11160       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11161       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11162       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11163       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11164       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11165       #endif
11166 #ifndef FORCE32
11167       printf(" 32:");
11168       for(r=0;r<=CCREG;r++) {
11169         if((branch_regs[i].is32>>r)&1) {
11170           if(r==CCREG) printf(" CC");
11171           else if(r==HIREG) printf(" HI");
11172           else if(r==LOREG) printf(" LO");
11173           else printf(" r%d",r);
11174         }
11175       }
11176       printf("\n");
11177 #endif
11178     }
11179   }
11180 #endif // DISASM
11181
11182   /* Pass 8 - Assembly */
11183   linkcount=0;stubcount=0;
11184   ds=0;is_delayslot=0;
11185   cop1_usable=0;
11186   uint64_t is32_pre=0;
11187   u_int dirty_pre=0;
11188   u_int beginning=(u_int)out;
11189   if((u_int)addr&1) {
11190     ds=1;
11191     pagespan_ds();
11192   }
11193   u_int instr_addr0_override=0;
11194
11195 #ifdef PCSX
11196   if (start == 0x80030000) {
11197     // nasty hack for fastbios thing
11198     // override block entry to this code
11199     instr_addr0_override=(u_int)out;
11200     emit_movimm(start,0);
11201     // abuse io address var as a flag that we
11202     // have already returned here once
11203     emit_readword((int)&address,1);
11204     emit_writeword(0,(int)&pcaddr);
11205     emit_writeword(0,(int)&address);
11206     emit_cmp(0,1);
11207     emit_jne((int)new_dyna_leave);
11208   }
11209 #endif
11210   for(i=0;i<slen;i++)
11211   {
11212     //if(ds) printf("ds: ");
11213     disassemble_inst(i);
11214     if(ds) {
11215       ds=0; // Skip delay slot
11216       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11217       instr_addr[i]=0;
11218     } else {
11219       speculate_register_values(i);
11220       #ifndef DESTRUCTIVE_WRITEBACK
11221       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11222       {
11223         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11224               unneeded_reg[i],unneeded_reg_upper[i]);
11225         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11226               unneeded_reg[i],unneeded_reg_upper[i]);
11227       }
11228       if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11229         is32_pre=branch_regs[i].is32;
11230         dirty_pre=branch_regs[i].dirty;
11231       }else{
11232         is32_pre=regs[i].is32;
11233         dirty_pre=regs[i].dirty;
11234       }
11235       #endif
11236       // write back
11237       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11238       {
11239         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11240                       unneeded_reg[i],unneeded_reg_upper[i]);
11241         loop_preload(regmap_pre[i],regs[i].regmap_entry);
11242       }
11243       // branch target entry point
11244       instr_addr[i]=(u_int)out;
11245       assem_debug("<->\n");
11246       // load regs
11247       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
11248         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11249       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11250       address_generation(i,&regs[i],regs[i].regmap_entry);
11251       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11252       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11253       {
11254         // Load the delay slot registers if necessary
11255         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11256           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11257         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11258           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11259         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11260           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11261       }
11262       else if(i+1<slen)
11263       {
11264         // Preload registers for following instruction
11265         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11266           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11267             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11268         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11269           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11270             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11271       }
11272       // TODO: if(is_ooo(i)) address_generation(i+1);
11273       if(itype[i]==CJUMP||itype[i]==FJUMP)
11274         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11275       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11276         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11277       if(bt[i]) cop1_usable=0;
11278       // assemble
11279       switch(itype[i]) {
11280         case ALU:
11281           alu_assemble(i,&regs[i]);break;
11282         case IMM16:
11283           imm16_assemble(i,&regs[i]);break;
11284         case SHIFT:
11285           shift_assemble(i,&regs[i]);break;
11286         case SHIFTIMM:
11287           shiftimm_assemble(i,&regs[i]);break;
11288         case LOAD:
11289           load_assemble(i,&regs[i]);break;
11290         case LOADLR:
11291           loadlr_assemble(i,&regs[i]);break;
11292         case STORE:
11293           store_assemble(i,&regs[i]);break;
11294         case STORELR:
11295           storelr_assemble(i,&regs[i]);break;
11296         case COP0:
11297           cop0_assemble(i,&regs[i]);break;
11298         case COP1:
11299           cop1_assemble(i,&regs[i]);break;
11300         case C1LS:
11301           c1ls_assemble(i,&regs[i]);break;
11302         case COP2:
11303           cop2_assemble(i,&regs[i]);break;
11304         case C2LS:
11305           c2ls_assemble(i,&regs[i]);break;
11306         case C2OP:
11307           c2op_assemble(i,&regs[i]);break;
11308         case FCONV:
11309           fconv_assemble(i,&regs[i]);break;
11310         case FLOAT:
11311           float_assemble(i,&regs[i]);break;
11312         case FCOMP:
11313           fcomp_assemble(i,&regs[i]);break;
11314         case MULTDIV:
11315           multdiv_assemble(i,&regs[i]);break;
11316         case MOV:
11317           mov_assemble(i,&regs[i]);break;
11318         case SYSCALL:
11319           syscall_assemble(i,&regs[i]);break;
11320         case HLECALL:
11321           hlecall_assemble(i,&regs[i]);break;
11322         case INTCALL:
11323           intcall_assemble(i,&regs[i]);break;
11324         case UJUMP:
11325           ujump_assemble(i,&regs[i]);ds=1;break;
11326         case RJUMP:
11327           rjump_assemble(i,&regs[i]);ds=1;break;
11328         case CJUMP:
11329           cjump_assemble(i,&regs[i]);ds=1;break;
11330         case SJUMP:
11331           sjump_assemble(i,&regs[i]);ds=1;break;
11332         case FJUMP:
11333           fjump_assemble(i,&regs[i]);ds=1;break;
11334         case SPAN:
11335           pagespan_assemble(i,&regs[i]);break;
11336       }
11337       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11338         literal_pool(1024);
11339       else
11340         literal_pool_jumpover(256);
11341     }
11342   }
11343   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11344   // If the block did not end with an unconditional branch,
11345   // add a jump to the next instruction.
11346   if(i>1) {
11347     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11348       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11349       assert(i==slen);
11350       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11351         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11352         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11353           emit_loadreg(CCREG,HOST_CCREG);
11354         emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11355       }
11356       else if(!likely[i-2])
11357       {
11358         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11359         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11360       }
11361       else
11362       {
11363         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11364         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11365       }
11366       add_to_linker((int)out,start+i*4,0);
11367       emit_jmp(0);
11368     }
11369   }
11370   else
11371   {
11372     assert(i>0);
11373     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11374     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11375     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11376       emit_loadreg(CCREG,HOST_CCREG);
11377     emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11378     add_to_linker((int)out,start+i*4,0);
11379     emit_jmp(0);
11380   }
11381
11382   // TODO: delay slot stubs?
11383   // Stubs
11384   for(i=0;i<stubcount;i++)
11385   {
11386     switch(stubs[i][0])
11387     {
11388       case LOADB_STUB:
11389       case LOADH_STUB:
11390       case LOADW_STUB:
11391       case LOADD_STUB:
11392       case LOADBU_STUB:
11393       case LOADHU_STUB:
11394         do_readstub(i);break;
11395       case STOREB_STUB:
11396       case STOREH_STUB:
11397       case STOREW_STUB:
11398       case STORED_STUB:
11399         do_writestub(i);break;
11400       case CC_STUB:
11401         do_ccstub(i);break;
11402       case INVCODE_STUB:
11403         do_invstub(i);break;
11404       case FP_STUB:
11405         do_cop1stub(i);break;
11406       case STORELR_STUB:
11407         do_unalignedwritestub(i);break;
11408     }
11409   }
11410
11411   if (instr_addr0_override)
11412     instr_addr[0] = instr_addr0_override;
11413
11414   /* Pass 9 - Linker */
11415   for(i=0;i<linkcount;i++)
11416   {
11417     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11418     literal_pool(64);
11419     if(!link_addr[i][2])
11420     {
11421       void *stub=out;
11422       void *addr=check_addr(link_addr[i][1]);
11423       emit_extjump(link_addr[i][0],link_addr[i][1]);
11424       if(addr) {
11425         set_jump_target(link_addr[i][0],(int)addr);
11426         add_link(link_addr[i][1],stub);
11427       }
11428       else set_jump_target(link_addr[i][0],(int)stub);
11429     }
11430     else
11431     {
11432       // Internal branch
11433       int target=(link_addr[i][1]-start)>>2;
11434       assert(target>=0&&target<slen);
11435       assert(instr_addr[target]);
11436       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11437       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11438       //#else
11439       set_jump_target(link_addr[i][0],instr_addr[target]);
11440       //#endif
11441     }
11442   }
11443   // External Branch Targets (jump_in)
11444   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11445   for(i=0;i<slen;i++)
11446   {
11447     if(bt[i]||i==0)
11448     {
11449       if(instr_addr[i]) // TODO - delay slots (=null)
11450       {
11451         u_int vaddr=start+i*4;
11452         u_int page=get_page(vaddr);
11453         u_int vpage=get_vpage(vaddr);
11454         literal_pool(256);
11455         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11456 #ifndef FORCE32
11457         if(!requires_32bit[i])
11458 #else
11459         if(1)
11460 #endif
11461         {
11462           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11463           assem_debug("jump_in: %x\n",start+i*4);
11464           ll_add(jump_dirty+vpage,vaddr,(void *)out);
11465           int entry_point=do_dirty_stub(i);
11466           ll_add(jump_in+page,vaddr,(void *)entry_point);
11467           // If there was an existing entry in the hash table,
11468           // replace it with the new address.
11469           // Don't add new entries.  We'll insert the
11470           // ones that actually get used in check_addr().
11471           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11472           if(ht_bin[0]==vaddr) {
11473             ht_bin[1]=entry_point;
11474           }
11475           if(ht_bin[2]==vaddr) {
11476             ht_bin[3]=entry_point;
11477           }
11478         }
11479         else
11480         {
11481           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11482           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11483           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11484           //int entry_point=(int)out;
11485           ////assem_debug("entry_point: %x\n",entry_point);
11486           //load_regs_entry(i);
11487           //if(entry_point==(int)out)
11488           //  entry_point=instr_addr[i];
11489           //else
11490           //  emit_jmp(instr_addr[i]);
11491           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11492           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11493           int entry_point=do_dirty_stub(i);
11494           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11495         }
11496       }
11497     }
11498   }
11499   // Write out the literal pool if necessary
11500   literal_pool(0);
11501   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11502   // Align code
11503   if(((u_int)out)&7) emit_addnop(13);
11504   #endif
11505   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11506   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11507   memcpy(copy,source,slen*4);
11508   copy+=slen*4;
11509
11510   #ifdef __arm__
11511   __clear_cache((void *)beginning,out);
11512   #endif
11513
11514   // If we're within 256K of the end of the buffer,
11515   // start over from the beginning. (Is 256K enough?)
11516   if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11517
11518   // Trap writes to any of the pages we compiled
11519   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11520     invalid_code[i]=0;
11521 #ifndef DISABLE_TLB
11522     memory_map[i]|=0x40000000;
11523     if((signed int)start>=(signed int)0xC0000000) {
11524       assert(using_tlb);
11525       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11526       invalid_code[j]=0;
11527       memory_map[j]|=0x40000000;
11528       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11529     }
11530 #endif
11531   }
11532   inv_code_start=inv_code_end=~0;
11533 #ifdef PCSX
11534   // for PCSX we need to mark all mirrors too
11535   if(get_page(start)<(RAM_SIZE>>12))
11536     for(i=start>>12;i<=(start+slen*4)>>12;i++)
11537       invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11538       invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11539       invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11540 #endif
11541
11542   /* Pass 10 - Free memory by expiring oldest blocks */
11543
11544   int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11545   while(expirep!=end)
11546   {
11547     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11548     int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11549     inv_debug("EXP: Phase %d\n",expirep);
11550     switch((expirep>>11)&3)
11551     {
11552       case 0:
11553         // Clear jump_in and jump_dirty
11554         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11555         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11556         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11557         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11558         break;
11559       case 1:
11560         // Clear pointers
11561         ll_kill_pointers(jump_out[expirep&2047],base,shift);
11562         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11563         break;
11564       case 2:
11565         // Clear hash table
11566         for(i=0;i<32;i++) {
11567           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11568           if((ht_bin[3]>>shift)==(base>>shift) ||
11569              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11570             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11571             ht_bin[2]=ht_bin[3]=-1;
11572           }
11573           if((ht_bin[1]>>shift)==(base>>shift) ||
11574              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11575             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11576             ht_bin[0]=ht_bin[2];
11577             ht_bin[1]=ht_bin[3];
11578             ht_bin[2]=ht_bin[3]=-1;
11579           }
11580         }
11581         break;
11582       case 3:
11583         // Clear jump_out
11584         #ifdef __arm__
11585         if((expirep&2047)==0)
11586           do_clear_cache();
11587         #endif
11588         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11589         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11590         break;
11591     }
11592     expirep=(expirep+1)&65535;
11593   }
11594   return 0;
11595 }
11596
11597 // vim:shiftwidth=2:expandtab