libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24 #include <sys/mman.h>
  25
  26 #include "emu_if.h" //emulator interface
  27
  28 //#define DISASM
  29 //#define assem_debug printf
  30 //#define inv_debug printf
  31 #define assem_debug(...)
  32 #define inv_debug(...)
  33
  34 #ifdef __i386__
  35 #include "assem_x86.h"
  36 #endif
  37 #ifdef __x86_64__
  38 #include "assem_x64.h"
  39 #endif
  40 #ifdef __arm__
  41 #include "assem_arm.h"
  42 #endif
  43
  44 #define MAXBLOCK 4096
  45 #define MAX_OUTPUT_BLOCK_SIZE 262144
  46
  47 struct regstat
  48 {
  49   signed char regmap_entry[HOST_REGS];
  50   signed char regmap[HOST_REGS];
  51   uint64_t was32;
  52   uint64_t is32;
  53   uint64_t wasdirty;
  54   uint64_t dirty;
  55   uint64_t u;
  56   uint64_t uu;
  57   u_int wasconst;
  58   u_int isconst;
  59   u_int loadedconst;             // host regs that have constants loaded
  60   u_int waswritten;              // MIPS regs that were used as store base before
  61 };
  62
  63 struct ll_entry
  64 {
  65   u_int vaddr;
  66   u_int reg32;
  67   void *addr;
  68   struct ll_entry *next;
  69 };
  70
  71   u_int start;
  72   u_int *source;
  73   u_int pagelimit;
  74   char insn[MAXBLOCK][10];
  75   u_char itype[MAXBLOCK];
  76   u_char opcode[MAXBLOCK];
  77   u_char opcode2[MAXBLOCK];
  78   u_char bt[MAXBLOCK];
  79   u_char rs1[MAXBLOCK];
  80   u_char rs2[MAXBLOCK];
  81   u_char rt1[MAXBLOCK];
  82   u_char rt2[MAXBLOCK];
  83   u_char us1[MAXBLOCK];
  84   u_char us2[MAXBLOCK];
  85   u_char dep1[MAXBLOCK];
  86   u_char dep2[MAXBLOCK];
  87   u_char lt1[MAXBLOCK];
  88   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
  89   static uint64_t gte_rt[MAXBLOCK];
  90   static uint64_t gte_unneeded[MAXBLOCK];
  91   static u_int smrv[32]; // speculated MIPS register values
  92   static u_int smrv_strong; // mask or regs that are likely to have correct values
  93   static u_int smrv_weak; // same, but somewhat less likely
  94   static u_int smrv_strong_next; // same, but after current insn executes
  95   static u_int smrv_weak_next;
  96   int imm[MAXBLOCK];
  97   u_int ba[MAXBLOCK];
  98   char likely[MAXBLOCK];
  99   char is_ds[MAXBLOCK];
 100   char ooo[MAXBLOCK];
 101   uint64_t unneeded_reg[MAXBLOCK];
 102   uint64_t unneeded_reg_upper[MAXBLOCK];
 103   uint64_t branch_unneeded_reg[MAXBLOCK];
 104   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
 105   uint64_t p32[MAXBLOCK];
 106   uint64_t pr32[MAXBLOCK];
 107   signed char regmap_pre[MAXBLOCK][HOST_REGS];
 108   static uint64_t current_constmap[HOST_REGS];
 109   static uint64_t constmap[MAXBLOCK][HOST_REGS];
 110   static struct regstat regs[MAXBLOCK];
 111   static struct regstat branch_regs[MAXBLOCK];
 112   signed char minimum_free_regs[MAXBLOCK];
 113   u_int needed_reg[MAXBLOCK];
 114   uint64_t requires_32bit[MAXBLOCK];
 115   u_int wont_dirty[MAXBLOCK];
 116   u_int will_dirty[MAXBLOCK];
 117   int ccadj[MAXBLOCK];
 118   int slen;
 119   u_int instr_addr[MAXBLOCK];
 120   u_int link_addr[MAXBLOCK][3];
 121   int linkcount;
 122   u_int stubs[MAXBLOCK*3][8];
 123   int stubcount;
 124   u_int literals[1024][2];
 125   int literalcount;
 126   int is_delayslot;
 127   int cop1_usable;
 128   u_char *out;
 129   struct ll_entry *jump_in[4096];
 130   struct ll_entry *jump_out[4096];
 131   struct ll_entry *jump_dirty[4096];
 132   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 133   char shadow[1048576]  __attribute__((aligned(16)));
 134   void *copy;
 135   int expirep;
 136 #ifndef PCSX
 137   u_int using_tlb;
 138 #else
 139   static const u_int using_tlb=0;
 140 #endif
 141   int new_dynarec_did_compile;
 142   int new_dynarec_hacks;
 143   u_int stop_after_jal;
 144   extern u_char restore_candidate[512];
 145   extern int cycle_count;
 146
 147   /* registers that may be allocated */
 148   /* 1-31 gpr */
 149 #define HIREG 32 // hi
 150 #define LOREG 33 // lo
 151 #define FSREG 34 // FPU status (FCSR)
 152 #define CSREG 35 // Coprocessor status
 153 #define CCREG 36 // Cycle count
 154 #define INVCP 37 // Pointer to invalid_code
 155 #define MMREG 38 // Pointer to memory_map
 156 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 157 #define TEMPREG 40
 158 #define FTEMP 40 // FPU temporary register
 159 #define PTEMP 41 // Prefetch temporary register
 160 #define TLREG 42 // TLB mapping offset
 161 #define RHASH 43 // Return address hash
 162 #define RHTBL 44 // Return address hash table address
 163 #define RTEMP 45 // JR/JALR address register
 164 #define MAXREG 45
 165 #define AGEN1 46 // Address generation temporary register
 166 #define AGEN2 47 // Address generation temporary register
 167 #define MGEN1 48 // Maptable address generation temporary register
 168 #define MGEN2 49 // Maptable address generation temporary register
 169 #define BTREG 50 // Branch target temporary register
 170
 171   /* instruction types */
 172 #define NOP 0     // No operation
 173 #define LOAD 1    // Load
 174 #define STORE 2   // Store
 175 #define LOADLR 3  // Unaligned load
 176 #define STORELR 4 // Unaligned store
 177 #define MOV 5     // Move
 178 #define ALU 6     // Arithmetic/logic
 179 #define MULTDIV 7 // Multiply/divide
 180 #define SHIFT 8   // Shift by register
 181 #define SHIFTIMM 9// Shift by immediate
 182 #define IMM16 10  // 16-bit immediate
 183 #define RJUMP 11  // Unconditional jump to register
 184 #define UJUMP 12  // Unconditional jump
 185 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 186 #define SJUMP 14  // Conditional branch (regimm format)
 187 #define COP0 15   // Coprocessor 0
 188 #define COP1 16   // Coprocessor 1
 189 #define C1LS 17   // Coprocessor 1 load/store
 190 #define FJUMP 18  // Conditional branch (floating point)
 191 #define FLOAT 19  // Floating point unit
 192 #define FCONV 20  // Convert integer to float
 193 #define FCOMP 21  // Floating point compare (sets FSREG)
 194 #define SYSCALL 22// SYSCALL
 195 #define OTHER 23  // Other
 196 #define SPAN 24   // Branch/delay slot spans 2 pages
 197 #define NI 25     // Not implemented
 198 #define HLECALL 26// PCSX fake opcodes for HLE
 199 #define COP2 27   // Coprocessor 2 move
 200 #define C2LS 28   // Coprocessor 2 load/store
 201 #define C2OP 29   // Coprocessor 2 operation
 202 #define INTCALL 30// Call interpreter to handle rare corner cases
 203
 204   /* stubs */
 205 #define CC_STUB 1
 206 #define FP_STUB 2
 207 #define LOADB_STUB 3
 208 #define LOADH_STUB 4
 209 #define LOADW_STUB 5
 210 #define LOADD_STUB 6
 211 #define LOADBU_STUB 7
 212 #define LOADHU_STUB 8
 213 #define STOREB_STUB 9
 214 #define STOREH_STUB 10
 215 #define STOREW_STUB 11
 216 #define STORED_STUB 12
 217 #define STORELR_STUB 13
 218 #define INVCODE_STUB 14
 219
 220   /* branch codes */
 221 #define TAKEN 1
 222 #define NOTTAKEN 2
 223 #define NULLDS 3
 224
 225 // asm linkage
 226 int new_recompile_block(int addr);
 227 void *get_addr_ht(u_int vaddr);
 228 void invalidate_block(u_int block);
 229 void invalidate_addr(u_int addr);
 230 void remove_hash(int vaddr);
 231 void jump_vaddr();
 232 void dyna_linker();
 233 void dyna_linker_ds();
 234 void verify_code();
 235 void verify_code_vm();
 236 void verify_code_ds();
 237 void cc_interrupt();
 238 void fp_exception();
 239 void fp_exception_ds();
 240 void jump_syscall();
 241 void jump_syscall_hle();
 242 void jump_eret();
 243 void jump_hlecall();
 244 void jump_intcall();
 245 void new_dyna_leave();
 246
 247 // TLB
 248 void TLBWI_new();
 249 void TLBWR_new();
 250 void read_nomem_new();
 251 void read_nomemb_new();
 252 void read_nomemh_new();
 253 void read_nomemd_new();
 254 void write_nomem_new();
 255 void write_nomemb_new();
 256 void write_nomemh_new();
 257 void write_nomemd_new();
 258 void write_rdram_new();
 259 void write_rdramb_new();
 260 void write_rdramh_new();
 261 void write_rdramd_new();
 262 extern u_int memory_map[1048576];
 263
 264 // Needed by assembler
 265 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 266 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 267 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 268 void load_all_regs(signed char i_regmap[]);
 269 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 270 void load_regs_entry(int t);
 271 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 272
 273 int tracedebug=0;
 274
 275 //#define DEBUG_CYCLE_COUNT 1
 276
 277 int cycle_multiplier; // 100 for 1.0
 278
 279 static int CLOCK_ADJUST(int x)
 280 {
 281   int s=(x>>31)|1;
 282   return (x * cycle_multiplier + s * 50) / 100;
 283 }
 284
 285 static void tlb_hacks()
 286 {
 287 #ifndef DISABLE_TLB
 288   // Goldeneye hack
 289   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 290   {
 291     u_int addr;
 292     int n;
 293     switch (ROM_HEADER->Country_code&0xFF)
 294     {
 295       case 0x45: // U
 296         addr=0x34b30;
 297         break;
 298       case 0x4A: // J
 299         addr=0x34b70;
 300         break;
 301       case 0x50: // E
 302         addr=0x329f0;
 303         break;
 304       default:
 305         // Unknown country code
 306         addr=0;
 307         break;
 308     }
 309     u_int rom_addr=(u_int)rom;
 310     #ifdef ROM_COPY
 311     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 312     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 313     if((void *)rom>(void *)0xffffffff) {
 314       munmap(ROM_COPY, 67108864);
 315       if(mmap(ROM_COPY, 12582912,
 316               PROT_READ | PROT_WRITE,
 317               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 318               -1, 0) <= 0) {printf("mmap() failed\n");}
 319       memcpy(ROM_COPY,rom,12582912);
 320       rom_addr=(u_int)ROM_COPY;
 321     }
 322     #endif
 323     if(addr) {
 324       for(n=0x7F000;n<0x80000;n++) {
 325         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 326       }
 327     }
 328   }
 329 #endif
 330 }
 331
 332 static u_int get_page(u_int vaddr)
 333 {
 334 #ifndef PCSX
 335   u_int page=(vaddr^0x80000000)>>12;
 336 #else
 337   u_int page=vaddr&~0xe0000000;
 338   if (page < 0x1000000)
 339     page &= ~0x0e00000; // RAM mirrors
 340   page>>=12;
 341 #endif
 342 #ifndef DISABLE_TLB
 343   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 344 #endif
 345   if(page>2048) page=2048+(page&2047);
 346   return page;
 347 }
 348
 349 #ifndef PCSX
 350 static u_int get_vpage(u_int vaddr)
 351 {
 352   u_int vpage=(vaddr^0x80000000)>>12;
 353 #ifndef DISABLE_TLB
 354   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 355 #endif
 356   if(vpage>2048) vpage=2048+(vpage&2047);
 357   return vpage;
 358 }
 359 #else
 360 // no virtual mem in PCSX
 361 static u_int get_vpage(u_int vaddr)
 362 {
 363   return get_page(vaddr);
 364 }
 365 #endif
 366
 367 // Get address from virtual address
 368 // This is called from the recompiled JR/JALR instructions
 369 void *get_addr(u_int vaddr)
 370 {
 371   u_int page=get_page(vaddr);
 372   u_int vpage=get_vpage(vaddr);
 373   struct ll_entry *head;
 374   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 375   head=jump_in[page];
 376   while(head!=NULL) {
 377     if(head->vaddr==vaddr&&head->reg32==0) {
 378   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 379       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 380       ht_bin[3]=ht_bin[1];
 381       ht_bin[2]=ht_bin[0];
 382       ht_bin[1]=(int)head->addr;
 383       ht_bin[0]=vaddr;
 384       return head->addr;
 385     }
 386     head=head->next;
 387   }
 388   head=jump_dirty[vpage];
 389   while(head!=NULL) {
 390     if(head->vaddr==vaddr&&head->reg32==0) {
 391       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 392       // Don't restore blocks which are about to expire from the cache
 393       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 394       if(verify_dirty(head->addr)) {
 395         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 396         invalid_code[vaddr>>12]=0;
 397         inv_code_start=inv_code_end=~0;
 398 #ifndef DISABLE_TLB
 399         memory_map[vaddr>>12]|=0x40000000;
 400 #endif
 401         if(vpage<2048) {
 402 #ifndef DISABLE_TLB
 403           if(tlb_LUT_r[vaddr>>12]) {
 404             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 405             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 406           }
 407 #endif
 408           restore_candidate[vpage>>3]|=1<<(vpage&7);
 409         }
 410         else restore_candidate[page>>3]|=1<<(page&7);
 411         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 412         if(ht_bin[0]==vaddr) {
 413           ht_bin[1]=(int)head->addr; // Replace existing entry
 414         }
 415         else
 416         {
 417           ht_bin[3]=ht_bin[1];
 418           ht_bin[2]=ht_bin[0];
 419           ht_bin[1]=(int)head->addr;
 420           ht_bin[0]=vaddr;
 421         }
 422         return head->addr;
 423       }
 424     }
 425     head=head->next;
 426   }
 427   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 428   int r=new_recompile_block(vaddr);
 429   if(r==0) return get_addr(vaddr);
 430   // Execute in unmapped page, generate pagefault execption
 431   Status|=2;
 432   Cause=(vaddr<<31)|0x8;
 433   EPC=(vaddr&1)?vaddr-5:vaddr;
 434   BadVAddr=(vaddr&~1);
 435   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 436   EntryHi=BadVAddr&0xFFFFE000;
 437   return get_addr_ht(0x80000000);
 438 }
 439 // Look up address in hash table first
 440 void *get_addr_ht(u_int vaddr)
 441 {
 442   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 443   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 444   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 445   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 446   return get_addr(vaddr);
 447 }
 448
 449 void *get_addr_32(u_int vaddr,u_int flags)
 450 {
 451 #ifdef FORCE32
 452   return get_addr(vaddr);
 453 #else
 454   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 455   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 456   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 457   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 458   u_int page=get_page(vaddr);
 459   u_int vpage=get_vpage(vaddr);
 460   struct ll_entry *head;
 461   head=jump_in[page];
 462   while(head!=NULL) {
 463     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 464       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 465       if(head->reg32==0) {
 466         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 467         if(ht_bin[0]==-1) {
 468           ht_bin[1]=(int)head->addr;
 469           ht_bin[0]=vaddr;
 470         }else if(ht_bin[2]==-1) {
 471           ht_bin[3]=(int)head->addr;
 472           ht_bin[2]=vaddr;
 473         }
 474         //ht_bin[3]=ht_bin[1];
 475         //ht_bin[2]=ht_bin[0];
 476         //ht_bin[1]=(int)head->addr;
 477         //ht_bin[0]=vaddr;
 478       }
 479       return head->addr;
 480     }
 481     head=head->next;
 482   }
 483   head=jump_dirty[vpage];
 484   while(head!=NULL) {
 485     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 486       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 487       // Don't restore blocks which are about to expire from the cache
 488       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 489       if(verify_dirty(head->addr)) {
 490         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 491         invalid_code[vaddr>>12]=0;
 492         inv_code_start=inv_code_end=~0;
 493         memory_map[vaddr>>12]|=0x40000000;
 494         if(vpage<2048) {
 495 #ifndef DISABLE_TLB
 496           if(tlb_LUT_r[vaddr>>12]) {
 497             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 498             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 499           }
 500 #endif
 501           restore_candidate[vpage>>3]|=1<<(vpage&7);
 502         }
 503         else restore_candidate[page>>3]|=1<<(page&7);
 504         if(head->reg32==0) {
 505           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 506           if(ht_bin[0]==-1) {
 507             ht_bin[1]=(int)head->addr;
 508             ht_bin[0]=vaddr;
 509           }else if(ht_bin[2]==-1) {
 510             ht_bin[3]=(int)head->addr;
 511             ht_bin[2]=vaddr;
 512           }
 513           //ht_bin[3]=ht_bin[1];
 514           //ht_bin[2]=ht_bin[0];
 515           //ht_bin[1]=(int)head->addr;
 516           //ht_bin[0]=vaddr;
 517         }
 518         return head->addr;
 519       }
 520     }
 521     head=head->next;
 522   }
 523   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 524   int r=new_recompile_block(vaddr);
 525   if(r==0) return get_addr(vaddr);
 526   // Execute in unmapped page, generate pagefault execption
 527   Status|=2;
 528   Cause=(vaddr<<31)|0x8;
 529   EPC=(vaddr&1)?vaddr-5:vaddr;
 530   BadVAddr=(vaddr&~1);
 531   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 532   EntryHi=BadVAddr&0xFFFFE000;
 533   return get_addr_ht(0x80000000);
 534 #endif
 535 }
 536
 537 void clear_all_regs(signed char regmap[])
 538 {
 539   int hr;
 540   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 541 }
 542
 543 signed char get_reg(signed char regmap[],int r)
 544 {
 545   int hr;
 546   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 547   return -1;
 548 }
 549
 550 // Find a register that is available for two consecutive cycles
 551 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 552 {
 553   int hr;
 554   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 555   return -1;
 556 }
 557
 558 int count_free_regs(signed char regmap[])
 559 {
 560   int count=0;
 561   int hr;
 562   for(hr=0;hr<HOST_REGS;hr++)
 563   {
 564     if(hr!=EXCLUDE_REG) {
 565       if(regmap[hr]<0) count++;
 566     }
 567   }
 568   return count;
 569 }
 570
 571 void dirty_reg(struct regstat *cur,signed char reg)
 572 {
 573   int hr;
 574   if(!reg) return;
 575   for (hr=0;hr<HOST_REGS;hr++) {
 576     if((cur->regmap[hr]&63)==reg) {
 577       cur->dirty|=1<<hr;
 578     }
 579   }
 580 }
 581
 582 // If we dirty the lower half of a 64 bit register which is now being
 583 // sign-extended, we need to dump the upper half.
 584 // Note: Do this only after completion of the instruction, because
 585 // some instructions may need to read the full 64-bit value even if
 586 // overwriting it (eg SLTI, DSRA32).
 587 static void flush_dirty_uppers(struct regstat *cur)
 588 {
 589   int hr,reg;
 590   for (hr=0;hr<HOST_REGS;hr++) {
 591     if((cur->dirty>>hr)&1) {
 592       reg=cur->regmap[hr];
 593       if(reg>=64)
 594         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 595     }
 596   }
 597 }
 598
 599 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 600 {
 601   int hr;
 602   if(!reg) return;
 603   for (hr=0;hr<HOST_REGS;hr++) {
 604     if(cur->regmap[hr]==reg) {
 605       cur->isconst|=1<<hr;
 606       current_constmap[hr]=value;
 607     }
 608     else if((cur->regmap[hr]^64)==reg) {
 609       cur->isconst|=1<<hr;
 610       current_constmap[hr]=value>>32;
 611     }
 612   }
 613 }
 614
 615 void clear_const(struct regstat *cur,signed char reg)
 616 {
 617   int hr;
 618   if(!reg) return;
 619   for (hr=0;hr<HOST_REGS;hr++) {
 620     if((cur->regmap[hr]&63)==reg) {
 621       cur->isconst&=~(1<<hr);
 622     }
 623   }
 624 }
 625
 626 int is_const(struct regstat *cur,signed char reg)
 627 {
 628   int hr;
 629   if(reg<0) return 0;
 630   if(!reg) return 1;
 631   for (hr=0;hr<HOST_REGS;hr++) {
 632     if((cur->regmap[hr]&63)==reg) {
 633       return (cur->isconst>>hr)&1;
 634     }
 635   }
 636   return 0;
 637 }
 638 uint64_t get_const(struct regstat *cur,signed char reg)
 639 {
 640   int hr;
 641   if(!reg) return 0;
 642   for (hr=0;hr<HOST_REGS;hr++) {
 643     if(cur->regmap[hr]==reg) {
 644       return current_constmap[hr];
 645     }
 646   }
 647   printf("Unknown constant in r%d\n",reg);
 648   exit(1);
 649 }
 650
 651 // Least soon needed registers
 652 // Look at the next ten instructions and see which registers
 653 // will be used.  Try not to reallocate these.
 654 void lsn(u_char hsn[], int i, int *preferred_reg)
 655 {
 656   int j;
 657   int b=-1;
 658   for(j=0;j<9;j++)
 659   {
 660     if(i+j>=slen) {
 661       j=slen-i-1;
 662       break;
 663     }
 664     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 665     {
 666       // Don't go past an unconditonal jump
 667       j++;
 668       break;
 669     }
 670   }
 671   for(;j>=0;j--)
 672   {
 673     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 674     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 675     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 676     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 677     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 678       // Stores can allocate zero
 679       hsn[rs1[i+j]]=j;
 680       hsn[rs2[i+j]]=j;
 681     }
 682     // On some architectures stores need invc_ptr
 683     #if defined(HOST_IMM8)
 684     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 685       hsn[INVCP]=j;
 686     }
 687     #endif
 688     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 689     {
 690       hsn[CCREG]=j;
 691       b=j;
 692     }
 693   }
 694   if(b>=0)
 695   {
 696     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 697     {
 698       // Follow first branch
 699       int t=(ba[i+b]-start)>>2;
 700       j=7-b;if(t+j>=slen) j=slen-t-1;
 701       for(;j>=0;j--)
 702       {
 703         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 704         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 705         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 706         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 707       }
 708     }
 709     // TODO: preferred register based on backward branch
 710   }
 711   // Delay slot should preferably not overwrite branch conditions or cycle count
 712   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 713     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 714     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 715     hsn[CCREG]=1;
 716     // ...or hash tables
 717     hsn[RHASH]=1;
 718     hsn[RHTBL]=1;
 719   }
 720   // Coprocessor load/store needs FTEMP, even if not declared
 721   if(itype[i]==C1LS||itype[i]==C2LS) {
 722     hsn[FTEMP]=0;
 723   }
 724   // Load L/R also uses FTEMP as a temporary register
 725   if(itype[i]==LOADLR) {
 726     hsn[FTEMP]=0;
 727   }
 728   // Also SWL/SWR/SDL/SDR
 729   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 730     hsn[FTEMP]=0;
 731   }
 732   // Don't remove the TLB registers either
 733   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 734     hsn[TLREG]=0;
 735   }
 736   // Don't remove the miniht registers
 737   if(itype[i]==UJUMP||itype[i]==RJUMP)
 738   {
 739     hsn[RHASH]=0;
 740     hsn[RHTBL]=0;
 741   }
 742 }
 743
 744 // We only want to allocate registers if we're going to use them again soon
 745 int needed_again(int r, int i)
 746 {
 747   int j;
 748   int b=-1;
 749   int rn=10;
 750
 751   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 752   {
 753     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 754       return 0; // Don't need any registers if exiting the block
 755   }
 756   for(j=0;j<9;j++)
 757   {
 758     if(i+j>=slen) {
 759       j=slen-i-1;
 760       break;
 761     }
 762     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 763     {
 764       // Don't go past an unconditonal jump
 765       j++;
 766       break;
 767     }
 768     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 769     {
 770       break;
 771     }
 772   }
 773   for(;j>=1;j--)
 774   {
 775     if(rs1[i+j]==r) rn=j;
 776     if(rs2[i+j]==r) rn=j;
 777     if((unneeded_reg[i+j]>>r)&1) rn=10;
 778     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 779     {
 780       b=j;
 781     }
 782   }
 783   /*
 784   if(b>=0)
 785   {
 786     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 787     {
 788       // Follow first branch
 789       int o=rn;
 790       int t=(ba[i+b]-start)>>2;
 791       j=7-b;if(t+j>=slen) j=slen-t-1;
 792       for(;j>=0;j--)
 793       {
 794         if(!((unneeded_reg[t+j]>>r)&1)) {
 795           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 796           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 797         }
 798         else rn=o;
 799       }
 800     }
 801   }*/
 802   if(rn<10) return 1;
 803   return 0;
 804 }
 805
 806 // Try to match register allocations at the end of a loop with those
 807 // at the beginning
 808 int loop_reg(int i, int r, int hr)
 809 {
 810   int j,k;
 811   for(j=0;j<9;j++)
 812   {
 813     if(i+j>=slen) {
 814       j=slen-i-1;
 815       break;
 816     }
 817     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 818     {
 819       // Don't go past an unconditonal jump
 820       j++;
 821       break;
 822     }
 823   }
 824   k=0;
 825   if(i>0){
 826     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 827       k--;
 828   }
 829   for(;k<j;k++)
 830   {
 831     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 832     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 833     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 834     {
 835       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 836       {
 837         int t=(ba[i+k]-start)>>2;
 838         int reg=get_reg(regs[t].regmap_entry,r);
 839         if(reg>=0) return reg;
 840         //reg=get_reg(regs[t+1].regmap_entry,r);
 841         //if(reg>=0) return reg;
 842       }
 843     }
 844   }
 845   return hr;
 846 }
 847
 848
 849 // Allocate every register, preserving source/target regs
 850 void alloc_all(struct regstat *cur,int i)
 851 {
 852   int hr;
 853
 854   for(hr=0;hr<HOST_REGS;hr++) {
 855     if(hr!=EXCLUDE_REG) {
 856       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 857          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 858       {
 859         cur->regmap[hr]=-1;
 860         cur->dirty&=~(1<<hr);
 861       }
 862       // Don't need zeros
 863       if((cur->regmap[hr]&63)==0)
 864       {
 865         cur->regmap[hr]=-1;
 866         cur->dirty&=~(1<<hr);
 867       }
 868     }
 869   }
 870 }
 871
 872 #ifndef FORCE32
 873 void div64(int64_t dividend,int64_t divisor)
 874 {
 875   lo=dividend/divisor;
 876   hi=dividend%divisor;
 877   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 878   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 879 }
 880 void divu64(uint64_t dividend,uint64_t divisor)
 881 {
 882   lo=dividend/divisor;
 883   hi=dividend%divisor;
 884   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 885   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 886 }
 887
 888 void mult64(uint64_t m1,uint64_t m2)
 889 {
 890    unsigned long long int op1, op2, op3, op4;
 891    unsigned long long int result1, result2, result3, result4;
 892    unsigned long long int temp1, temp2, temp3, temp4;
 893    int sign = 0;
 894
 895    if (m1 < 0)
 896      {
 897     op2 = -m1;
 898     sign = 1 - sign;
 899      }
 900    else op2 = m1;
 901    if (m2 < 0)
 902      {
 903     op4 = -m2;
 904     sign = 1 - sign;
 905      }
 906    else op4 = m2;
 907
 908    op1 = op2 & 0xFFFFFFFF;
 909    op2 = (op2 >> 32) & 0xFFFFFFFF;
 910    op3 = op4 & 0xFFFFFFFF;
 911    op4 = (op4 >> 32) & 0xFFFFFFFF;
 912
 913    temp1 = op1 * op3;
 914    temp2 = (temp1 >> 32) + op1 * op4;
 915    temp3 = op2 * op3;
 916    temp4 = (temp3 >> 32) + op2 * op4;
 917
 918    result1 = temp1 & 0xFFFFFFFF;
 919    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 920    result3 = (result2 >> 32) + temp4;
 921    result4 = (result3 >> 32);
 922
 923    lo = result1 | (result2 << 32);
 924    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 925    if (sign)
 926      {
 927     hi = ~hi;
 928     if (!lo) hi++;
 929     else lo = ~lo + 1;
 930      }
 931 }
 932
 933 void multu64(uint64_t m1,uint64_t m2)
 934 {
 935    unsigned long long int op1, op2, op3, op4;
 936    unsigned long long int result1, result2, result3, result4;
 937    unsigned long long int temp1, temp2, temp3, temp4;
 938
 939    op1 = m1 & 0xFFFFFFFF;
 940    op2 = (m1 >> 32) & 0xFFFFFFFF;
 941    op3 = m2 & 0xFFFFFFFF;
 942    op4 = (m2 >> 32) & 0xFFFFFFFF;
 943
 944    temp1 = op1 * op3;
 945    temp2 = (temp1 >> 32) + op1 * op4;
 946    temp3 = op2 * op3;
 947    temp4 = (temp3 >> 32) + op2 * op4;
 948
 949    result1 = temp1 & 0xFFFFFFFF;
 950    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 951    result3 = (result2 >> 32) + temp4;
 952    result4 = (result3 >> 32);
 953
 954    lo = result1 | (result2 << 32);
 955    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 956
 957   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 958   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 959 }
 960
 961 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 962 {
 963   if(bits) {
 964     original<<=64-bits;
 965     original>>=64-bits;
 966     loaded<<=bits;
 967     original|=loaded;
 968   }
 969   else original=loaded;
 970   return original;
 971 }
 972 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 973 {
 974   if(bits^56) {
 975     original>>=64-(bits^56);
 976     original<<=64-(bits^56);
 977     loaded>>=bits^56;
 978     original|=loaded;
 979   }
 980   else original=loaded;
 981   return original;
 982 }
 983 #endif
 984
 985 #ifdef __i386__
 986 #include "assem_x86.c"
 987 #endif
 988 #ifdef __x86_64__
 989 #include "assem_x64.c"
 990 #endif
 991 #ifdef __arm__
 992 #include "assem_arm.c"
 993 #endif
 994
 995 // Add virtual address mapping to linked list
 996 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 997 {
 998   struct ll_entry *new_entry;
 999   new_entry=malloc(sizeof(struct ll_entry));
1000   assert(new_entry!=NULL);
1001   new_entry->vaddr=vaddr;
1002   new_entry->reg32=0;
1003   new_entry->addr=addr;
1004   new_entry->next=*head;
1005   *head=new_entry;
1006 }
1007
1008 // Add virtual address mapping for 32-bit compiled block
1009 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1010 {
1011   ll_add(head,vaddr,addr);
1012 #ifndef FORCE32
1013   (*head)->reg32=reg32;
1014 #endif
1015 }
1016
1017 // Check if an address is already compiled
1018 // but don't return addresses which are about to expire from the cache
1019 void *check_addr(u_int vaddr)
1020 {
1021   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1022   if(ht_bin[0]==vaddr) {
1023     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1024       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1025   }
1026   if(ht_bin[2]==vaddr) {
1027     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1028       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1029   }
1030   u_int page=get_page(vaddr);
1031   struct ll_entry *head;
1032   head=jump_in[page];
1033   while(head!=NULL) {
1034     if(head->vaddr==vaddr&&head->reg32==0) {
1035       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1036         // Update existing entry with current address
1037         if(ht_bin[0]==vaddr) {
1038           ht_bin[1]=(int)head->addr;
1039           return head->addr;
1040         }
1041         if(ht_bin[2]==vaddr) {
1042           ht_bin[3]=(int)head->addr;
1043           return head->addr;
1044         }
1045         // Insert into hash table with low priority.
1046         // Don't evict existing entries, as they are probably
1047         // addresses that are being accessed frequently.
1048         if(ht_bin[0]==-1) {
1049           ht_bin[1]=(int)head->addr;
1050           ht_bin[0]=vaddr;
1051         }else if(ht_bin[2]==-1) {
1052           ht_bin[3]=(int)head->addr;
1053           ht_bin[2]=vaddr;
1054         }
1055         return head->addr;
1056       }
1057     }
1058     head=head->next;
1059   }
1060   return 0;
1061 }
1062
1063 void remove_hash(int vaddr)
1064 {
1065   //printf("remove hash: %x\n",vaddr);
1066   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1067   if(ht_bin[2]==vaddr) {
1068     ht_bin[2]=ht_bin[3]=-1;
1069   }
1070   if(ht_bin[0]==vaddr) {
1071     ht_bin[0]=ht_bin[2];
1072     ht_bin[1]=ht_bin[3];
1073     ht_bin[2]=ht_bin[3]=-1;
1074   }
1075 }
1076
1077 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1078 {
1079   struct ll_entry *next;
1080   while(*head) {
1081     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1082        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1083     {
1084       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1085       remove_hash((*head)->vaddr);
1086       next=(*head)->next;
1087       free(*head);
1088       *head=next;
1089     }
1090     else
1091     {
1092       head=&((*head)->next);
1093     }
1094   }
1095 }
1096
1097 // Remove all entries from linked list
1098 void ll_clear(struct ll_entry **head)
1099 {
1100   struct ll_entry *cur;
1101   struct ll_entry *next;
1102   if(cur=*head) {
1103     *head=0;
1104     while(cur) {
1105       next=cur->next;
1106       free(cur);
1107       cur=next;
1108     }
1109   }
1110 }
1111
1112 // Dereference the pointers and remove if it matches
1113 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1114 {
1115   while(head) {
1116     int ptr=get_pointer(head->addr);
1117     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1118     if(((ptr>>shift)==(addr>>shift)) ||
1119        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1120     {
1121       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1122       u_int host_addr=(u_int)kill_pointer(head->addr);
1123       #ifdef __arm__
1124         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1125       #endif
1126     }
1127     head=head->next;
1128   }
1129 }
1130
1131 // This is called when we write to a compiled block (see do_invstub)
1132 void invalidate_page(u_int page)
1133 {
1134   struct ll_entry *head;
1135   struct ll_entry *next;
1136   head=jump_in[page];
1137   jump_in[page]=0;
1138   while(head!=NULL) {
1139     inv_debug("INVALIDATE: %x\n",head->vaddr);
1140     remove_hash(head->vaddr);
1141     next=head->next;
1142     free(head);
1143     head=next;
1144   }
1145   head=jump_out[page];
1146   jump_out[page]=0;
1147   while(head!=NULL) {
1148     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1149     u_int host_addr=(u_int)kill_pointer(head->addr);
1150     #ifdef __arm__
1151       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1152     #endif
1153     next=head->next;
1154     free(head);
1155     head=next;
1156   }
1157 }
1158
1159 static void invalidate_block_range(u_int block, u_int first, u_int last)
1160 {
1161   u_int page=get_page(block<<12);
1162   //printf("first=%d last=%d\n",first,last);
1163   invalidate_page(page);
1164   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1165   assert(last<page+5);
1166   // Invalidate the adjacent pages if a block crosses a 4K boundary
1167   while(first<page) {
1168     invalidate_page(first);
1169     first++;
1170   }
1171   for(first=page+1;first<last;first++) {
1172     invalidate_page(first);
1173   }
1174   #ifdef __arm__
1175     do_clear_cache();
1176   #endif
1177
1178   // Don't trap writes
1179   invalid_code[block]=1;
1180 #ifndef DISABLE_TLB
1181   // If there is a valid TLB entry for this page, remove write protect
1182   if(tlb_LUT_w[block]) {
1183     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1184     // CHECK: Is this right?
1185     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1186     u_int real_block=tlb_LUT_w[block]>>12;
1187     invalid_code[real_block]=1;
1188     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1189   }
1190   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1191 #endif
1192
1193   #ifdef USE_MINI_HT
1194   memset(mini_ht,-1,sizeof(mini_ht));
1195   #endif
1196 }
1197
1198 void invalidate_block(u_int block)
1199 {
1200   u_int page=get_page(block<<12);
1201   u_int vpage=get_vpage(block<<12);
1202   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1203   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1204   u_int first,last;
1205   first=last=page;
1206   struct ll_entry *head;
1207   head=jump_dirty[vpage];
1208   //printf("page=%d vpage=%d\n",page,vpage);
1209   while(head!=NULL) {
1210     u_int start,end;
1211     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1212       get_bounds((int)head->addr,&start,&end);
1213       //printf("start: %x end: %x\n",start,end);
1214       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1215         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1216           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1217           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1218         }
1219       }
1220 #ifndef DISABLE_TLB
1221       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1222         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1223           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1224           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1225         }
1226       }
1227 #endif
1228     }
1229     head=head->next;
1230   }
1231   invalidate_block_range(block,first,last);
1232 }
1233
1234 void invalidate_addr(u_int addr)
1235 {
1236 #ifdef PCSX
1237   //static int rhits;
1238   // this check is done by the caller
1239   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1240   u_int page=get_vpage(addr);
1241   if(page<2048) { // RAM
1242     struct ll_entry *head;
1243     u_int addr_min=~0, addr_max=0;
1244     int mask=RAM_SIZE-1;
1245     int pg1;
1246     inv_code_start=addr&~0xfff;
1247     inv_code_end=addr|0xfff;
1248     pg1=page;
1249     if (pg1>0) {
1250       // must check previous page too because of spans..
1251       pg1--;
1252       inv_code_start-=0x1000;
1253     }
1254     for(;pg1<=page;pg1++) {
1255       for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1256         u_int start,end;
1257         get_bounds((int)head->addr,&start,&end);
1258         if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1259           if(start<addr_min) addr_min=start;
1260           if(end>addr_max) addr_max=end;
1261         }
1262         else if(addr<start) {
1263           if(start<inv_code_end)
1264             inv_code_end=start-1;
1265         }
1266         else {
1267           if(end>inv_code_start)
1268             inv_code_start=end;
1269         }
1270       }
1271     }
1272     if (addr_min!=~0) {
1273       inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1274       inv_code_start=inv_code_end=~0;
1275       invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1276       return;
1277     }
1278     else {
1279       inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1280       return;
1281     }
1282   }
1283 #endif
1284   invalidate_block(addr>>12);
1285 }
1286
1287 // This is called when loading a save state.
1288 // Anything could have changed, so invalidate everything.
1289 void invalidate_all_pages()
1290 {
1291   u_int page,n;
1292   for(page=0;page<4096;page++)
1293     invalidate_page(page);
1294   for(page=0;page<1048576;page++)
1295     if(!invalid_code[page]) {
1296       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1297       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1298     }
1299   #ifdef __arm__
1300   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1301   #endif
1302   #ifdef USE_MINI_HT
1303   memset(mini_ht,-1,sizeof(mini_ht));
1304   #endif
1305   #ifndef DISABLE_TLB
1306   // TLB
1307   for(page=0;page<0x100000;page++) {
1308     if(tlb_LUT_r[page]) {
1309       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1310       if(!tlb_LUT_w[page]||!invalid_code[page])
1311         memory_map[page]|=0x40000000; // Write protect
1312     }
1313     else memory_map[page]=-1;
1314     if(page==0x80000) page=0xC0000;
1315   }
1316   tlb_hacks();
1317   #endif
1318 }
1319
1320 // Add an entry to jump_out after making a link
1321 void add_link(u_int vaddr,void *src)
1322 {
1323   u_int page=get_page(vaddr);
1324   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1325   int *ptr=(int *)(src+4);
1326   assert((*ptr&0x0fff0000)==0x059f0000);
1327   ll_add(jump_out+page,vaddr,src);
1328   //int ptr=get_pointer(src);
1329   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1330 }
1331
1332 // If a code block was found to be unmodified (bit was set in
1333 // restore_candidate) and it remains unmodified (bit is clear
1334 // in invalid_code) then move the entries for that 4K page from
1335 // the dirty list to the clean list.
1336 void clean_blocks(u_int page)
1337 {
1338   struct ll_entry *head;
1339   inv_debug("INV: clean_blocks page=%d\n",page);
1340   head=jump_dirty[page];
1341   while(head!=NULL) {
1342     if(!invalid_code[head->vaddr>>12]) {
1343       // Don't restore blocks which are about to expire from the cache
1344       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1345         u_int start,end;
1346         if(verify_dirty((int)head->addr)) {
1347           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1348           u_int i;
1349           u_int inv=0;
1350           get_bounds((int)head->addr,&start,&end);
1351           if(start-(u_int)rdram<RAM_SIZE) {
1352             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1353               inv|=invalid_code[i];
1354             }
1355           }
1356 #ifndef DISABLE_TLB
1357           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1358             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1359             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1360             if(addr<start||addr>=end) inv=1;
1361           }
1362 #endif
1363           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1364             inv=1;
1365           }
1366           if(!inv) {
1367             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1368             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1369               u_int ppage=page;
1370 #ifndef DISABLE_TLB
1371               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1372 #endif
1373               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1374               //printf("page=%x, addr=%x\n",page,head->vaddr);
1375               //assert(head->vaddr>>12==(page|0x80000));
1376               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1377               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1378               if(!head->reg32) {
1379                 if(ht_bin[0]==head->vaddr) {
1380                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1381                 }
1382                 if(ht_bin[2]==head->vaddr) {
1383                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1384                 }
1385               }
1386             }
1387           }
1388         }
1389       }
1390     }
1391     head=head->next;
1392   }
1393 }
1394
1395
1396 void mov_alloc(struct regstat *current,int i)
1397 {
1398   // Note: Don't need to actually alloc the source registers
1399   if((~current->is32>>rs1[i])&1) {
1400     //alloc_reg64(current,i,rs1[i]);
1401     alloc_reg64(current,i,rt1[i]);
1402     current->is32&=~(1LL<<rt1[i]);
1403   } else {
1404     //alloc_reg(current,i,rs1[i]);
1405     alloc_reg(current,i,rt1[i]);
1406     current->is32|=(1LL<<rt1[i]);
1407   }
1408   clear_const(current,rs1[i]);
1409   clear_const(current,rt1[i]);
1410   dirty_reg(current,rt1[i]);
1411 }
1412
1413 void shiftimm_alloc(struct regstat *current,int i)
1414 {
1415   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1416   {
1417     if(rt1[i]) {
1418       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1419       else lt1[i]=rs1[i];
1420       alloc_reg(current,i,rt1[i]);
1421       current->is32|=1LL<<rt1[i];
1422       dirty_reg(current,rt1[i]);
1423       if(is_const(current,rs1[i])) {
1424         int v=get_const(current,rs1[i]);
1425         if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1426         if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1427         if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1428       }
1429       else clear_const(current,rt1[i]);
1430     }
1431   }
1432   else
1433   {
1434     clear_const(current,rs1[i]);
1435     clear_const(current,rt1[i]);
1436   }
1437
1438   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1439   {
1440     if(rt1[i]) {
1441       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1442       alloc_reg64(current,i,rt1[i]);
1443       current->is32&=~(1LL<<rt1[i]);
1444       dirty_reg(current,rt1[i]);
1445     }
1446   }
1447   if(opcode2[i]==0x3c) // DSLL32
1448   {
1449     if(rt1[i]) {
1450       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1451       alloc_reg64(current,i,rt1[i]);
1452       current->is32&=~(1LL<<rt1[i]);
1453       dirty_reg(current,rt1[i]);
1454     }
1455   }
1456   if(opcode2[i]==0x3e) // DSRL32
1457   {
1458     if(rt1[i]) {
1459       alloc_reg64(current,i,rs1[i]);
1460       if(imm[i]==32) {
1461         alloc_reg64(current,i,rt1[i]);
1462         current->is32&=~(1LL<<rt1[i]);
1463       } else {
1464         alloc_reg(current,i,rt1[i]);
1465         current->is32|=1LL<<rt1[i];
1466       }
1467       dirty_reg(current,rt1[i]);
1468     }
1469   }
1470   if(opcode2[i]==0x3f) // DSRA32
1471   {
1472     if(rt1[i]) {
1473       alloc_reg64(current,i,rs1[i]);
1474       alloc_reg(current,i,rt1[i]);
1475       current->is32|=1LL<<rt1[i];
1476       dirty_reg(current,rt1[i]);
1477     }
1478   }
1479 }
1480
1481 void shift_alloc(struct regstat *current,int i)
1482 {
1483   if(rt1[i]) {
1484     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1485     {
1486       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1487       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1488       alloc_reg(current,i,rt1[i]);
1489       if(rt1[i]==rs2[i]) {
1490         alloc_reg_temp(current,i,-1);
1491         minimum_free_regs[i]=1;
1492       }
1493       current->is32|=1LL<<rt1[i];
1494     } else { // DSLLV/DSRLV/DSRAV
1495       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1496       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1497       alloc_reg64(current,i,rt1[i]);
1498       current->is32&=~(1LL<<rt1[i]);
1499       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1500       {
1501         alloc_reg_temp(current,i,-1);
1502         minimum_free_regs[i]=1;
1503       }
1504     }
1505     clear_const(current,rs1[i]);
1506     clear_const(current,rs2[i]);
1507     clear_const(current,rt1[i]);
1508     dirty_reg(current,rt1[i]);
1509   }
1510 }
1511
1512 void alu_alloc(struct regstat *current,int i)
1513 {
1514   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1515     if(rt1[i]) {
1516       if(rs1[i]&&rs2[i]) {
1517         alloc_reg(current,i,rs1[i]);
1518         alloc_reg(current,i,rs2[i]);
1519       }
1520       else {
1521         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1522         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1523       }
1524       alloc_reg(current,i,rt1[i]);
1525     }
1526     current->is32|=1LL<<rt1[i];
1527   }
1528   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1529     if(rt1[i]) {
1530       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1531       {
1532         alloc_reg64(current,i,rs1[i]);
1533         alloc_reg64(current,i,rs2[i]);
1534         alloc_reg(current,i,rt1[i]);
1535       } else {
1536         alloc_reg(current,i,rs1[i]);
1537         alloc_reg(current,i,rs2[i]);
1538         alloc_reg(current,i,rt1[i]);
1539       }
1540     }
1541     current->is32|=1LL<<rt1[i];
1542   }
1543   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1544     if(rt1[i]) {
1545       if(rs1[i]&&rs2[i]) {
1546         alloc_reg(current,i,rs1[i]);
1547         alloc_reg(current,i,rs2[i]);
1548       }
1549       else
1550       {
1551         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1552         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1553       }
1554       alloc_reg(current,i,rt1[i]);
1555       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1556       {
1557         if(!((current->uu>>rt1[i])&1)) {
1558           alloc_reg64(current,i,rt1[i]);
1559         }
1560         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1561           if(rs1[i]&&rs2[i]) {
1562             alloc_reg64(current,i,rs1[i]);
1563             alloc_reg64(current,i,rs2[i]);
1564           }
1565           else
1566           {
1567             // Is is really worth it to keep 64-bit values in registers?
1568             #ifdef NATIVE_64BIT
1569             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1570             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1571             #endif
1572           }
1573         }
1574         current->is32&=~(1LL<<rt1[i]);
1575       } else {
1576         current->is32|=1LL<<rt1[i];
1577       }
1578     }
1579   }
1580   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1581     if(rt1[i]) {
1582       if(rs1[i]&&rs2[i]) {
1583         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1584           alloc_reg64(current,i,rs1[i]);
1585           alloc_reg64(current,i,rs2[i]);
1586           alloc_reg64(current,i,rt1[i]);
1587         } else {
1588           alloc_reg(current,i,rs1[i]);
1589           alloc_reg(current,i,rs2[i]);
1590           alloc_reg(current,i,rt1[i]);
1591         }
1592       }
1593       else {
1594         alloc_reg(current,i,rt1[i]);
1595         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1596           // DADD used as move, or zeroing
1597           // If we have a 64-bit source, then make the target 64 bits too
1598           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1599             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1600             alloc_reg64(current,i,rt1[i]);
1601           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1602             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1603             alloc_reg64(current,i,rt1[i]);
1604           }
1605           if(opcode2[i]>=0x2e&&rs2[i]) {
1606             // DSUB used as negation - 64-bit result
1607             // If we have a 32-bit register, extend it to 64 bits
1608             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1609             alloc_reg64(current,i,rt1[i]);
1610           }
1611         }
1612       }
1613       if(rs1[i]&&rs2[i]) {
1614         current->is32&=~(1LL<<rt1[i]);
1615       } else if(rs1[i]) {
1616         current->is32&=~(1LL<<rt1[i]);
1617         if((current->is32>>rs1[i])&1)
1618           current->is32|=1LL<<rt1[i];
1619       } else if(rs2[i]) {
1620         current->is32&=~(1LL<<rt1[i]);
1621         if((current->is32>>rs2[i])&1)
1622           current->is32|=1LL<<rt1[i];
1623       } else {
1624         current->is32|=1LL<<rt1[i];
1625       }
1626     }
1627   }
1628   clear_const(current,rs1[i]);
1629   clear_const(current,rs2[i]);
1630   clear_const(current,rt1[i]);
1631   dirty_reg(current,rt1[i]);
1632 }
1633
1634 void imm16_alloc(struct regstat *current,int i)
1635 {
1636   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1637   else lt1[i]=rs1[i];
1638   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1639   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1640     current->is32&=~(1LL<<rt1[i]);
1641     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1642       // TODO: Could preserve the 32-bit flag if the immediate is zero
1643       alloc_reg64(current,i,rt1[i]);
1644       alloc_reg64(current,i,rs1[i]);
1645     }
1646     clear_const(current,rs1[i]);
1647     clear_const(current,rt1[i]);
1648   }
1649   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1650     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1651     current->is32|=1LL<<rt1[i];
1652     clear_const(current,rs1[i]);
1653     clear_const(current,rt1[i]);
1654   }
1655   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1656     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1657       if(rs1[i]!=rt1[i]) {
1658         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1659         alloc_reg64(current,i,rt1[i]);
1660         current->is32&=~(1LL<<rt1[i]);
1661       }
1662     }
1663     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1664     if(is_const(current,rs1[i])) {
1665       int v=get_const(current,rs1[i]);
1666       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1667       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1668       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1669     }
1670     else clear_const(current,rt1[i]);
1671   }
1672   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1673     if(is_const(current,rs1[i])) {
1674       int v=get_const(current,rs1[i]);
1675       set_const(current,rt1[i],v+imm[i]);
1676     }
1677     else clear_const(current,rt1[i]);
1678     current->is32|=1LL<<rt1[i];
1679   }
1680   else {
1681     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1682     current->is32|=1LL<<rt1[i];
1683   }
1684   dirty_reg(current,rt1[i]);
1685 }
1686
1687 void load_alloc(struct regstat *current,int i)
1688 {
1689   clear_const(current,rt1[i]);
1690   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1691   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1692   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1693   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1694     alloc_reg(current,i,rt1[i]);
1695     assert(get_reg(current->regmap,rt1[i])>=0);
1696     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1697     {
1698       current->is32&=~(1LL<<rt1[i]);
1699       alloc_reg64(current,i,rt1[i]);
1700     }
1701     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1702     {
1703       current->is32&=~(1LL<<rt1[i]);
1704       alloc_reg64(current,i,rt1[i]);
1705       alloc_all(current,i);
1706       alloc_reg64(current,i,FTEMP);
1707       minimum_free_regs[i]=HOST_REGS;
1708     }
1709     else current->is32|=1LL<<rt1[i];
1710     dirty_reg(current,rt1[i]);
1711     // If using TLB, need a register for pointer to the mapping table
1712     if(using_tlb) alloc_reg(current,i,TLREG);
1713     // LWL/LWR need a temporary register for the old value
1714     if(opcode[i]==0x22||opcode[i]==0x26)
1715     {
1716       alloc_reg(current,i,FTEMP);
1717       alloc_reg_temp(current,i,-1);
1718       minimum_free_regs[i]=1;
1719     }
1720   }
1721   else
1722   {
1723     // Load to r0 or unneeded register (dummy load)
1724     // but we still need a register to calculate the address
1725     if(opcode[i]==0x22||opcode[i]==0x26)
1726     {
1727       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1728     }
1729     // If using TLB, need a register for pointer to the mapping table
1730     if(using_tlb) alloc_reg(current,i,TLREG);
1731     alloc_reg_temp(current,i,-1);
1732     minimum_free_regs[i]=1;
1733     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1734     {
1735       alloc_all(current,i);
1736       alloc_reg64(current,i,FTEMP);
1737       minimum_free_regs[i]=HOST_REGS;
1738     }
1739   }
1740 }
1741
1742 void store_alloc(struct regstat *current,int i)
1743 {
1744   clear_const(current,rs2[i]);
1745   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1746   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1747   alloc_reg(current,i,rs2[i]);
1748   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1749     alloc_reg64(current,i,rs2[i]);
1750     if(rs2[i]) alloc_reg(current,i,FTEMP);
1751   }
1752   // If using TLB, need a register for pointer to the mapping table
1753   if(using_tlb) alloc_reg(current,i,TLREG);
1754   #if defined(HOST_IMM8)
1755   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1756   else alloc_reg(current,i,INVCP);
1757   #endif
1758   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1759     alloc_reg(current,i,FTEMP);
1760   }
1761   // We need a temporary register for address generation
1762   alloc_reg_temp(current,i,-1);
1763   minimum_free_regs[i]=1;
1764 }
1765
1766 void c1ls_alloc(struct regstat *current,int i)
1767 {
1768   //clear_const(current,rs1[i]); // FIXME
1769   clear_const(current,rt1[i]);
1770   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1771   alloc_reg(current,i,CSREG); // Status
1772   alloc_reg(current,i,FTEMP);
1773   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1774     alloc_reg64(current,i,FTEMP);
1775   }
1776   // If using TLB, need a register for pointer to the mapping table
1777   if(using_tlb) alloc_reg(current,i,TLREG);
1778   #if defined(HOST_IMM8)
1779   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1780   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1781     alloc_reg(current,i,INVCP);
1782   #endif
1783   // We need a temporary register for address generation
1784   alloc_reg_temp(current,i,-1);
1785 }
1786
1787 void c2ls_alloc(struct regstat *current,int i)
1788 {
1789   clear_const(current,rt1[i]);
1790   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1791   alloc_reg(current,i,FTEMP);
1792   // If using TLB, need a register for pointer to the mapping table
1793   if(using_tlb) alloc_reg(current,i,TLREG);
1794   #if defined(HOST_IMM8)
1795   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1796   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1797     alloc_reg(current,i,INVCP);
1798   #endif
1799   // We need a temporary register for address generation
1800   alloc_reg_temp(current,i,-1);
1801   minimum_free_regs[i]=1;
1802 }
1803
1804 #ifndef multdiv_alloc
1805 void multdiv_alloc(struct regstat *current,int i)
1806 {
1807   //  case 0x18: MULT
1808   //  case 0x19: MULTU
1809   //  case 0x1A: DIV
1810   //  case 0x1B: DIVU
1811   //  case 0x1C: DMULT
1812   //  case 0x1D: DMULTU
1813   //  case 0x1E: DDIV
1814   //  case 0x1F: DDIVU
1815   clear_const(current,rs1[i]);
1816   clear_const(current,rs2[i]);
1817   if(rs1[i]&&rs2[i])
1818   {
1819     if((opcode2[i]&4)==0) // 32-bit
1820     {
1821       current->u&=~(1LL<<HIREG);
1822       current->u&=~(1LL<<LOREG);
1823       alloc_reg(current,i,HIREG);
1824       alloc_reg(current,i,LOREG);
1825       alloc_reg(current,i,rs1[i]);
1826       alloc_reg(current,i,rs2[i]);
1827       current->is32|=1LL<<HIREG;
1828       current->is32|=1LL<<LOREG;
1829       dirty_reg(current,HIREG);
1830       dirty_reg(current,LOREG);
1831     }
1832     else // 64-bit
1833     {
1834       current->u&=~(1LL<<HIREG);
1835       current->u&=~(1LL<<LOREG);
1836       current->uu&=~(1LL<<HIREG);
1837       current->uu&=~(1LL<<LOREG);
1838       alloc_reg64(current,i,HIREG);
1839       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1840       alloc_reg64(current,i,rs1[i]);
1841       alloc_reg64(current,i,rs2[i]);
1842       alloc_all(current,i);
1843       current->is32&=~(1LL<<HIREG);
1844       current->is32&=~(1LL<<LOREG);
1845       dirty_reg(current,HIREG);
1846       dirty_reg(current,LOREG);
1847       minimum_free_regs[i]=HOST_REGS;
1848     }
1849   }
1850   else
1851   {
1852     // Multiply by zero is zero.
1853     // MIPS does not have a divide by zero exception.
1854     // The result is undefined, we return zero.
1855     alloc_reg(current,i,HIREG);
1856     alloc_reg(current,i,LOREG);
1857     current->is32|=1LL<<HIREG;
1858     current->is32|=1LL<<LOREG;
1859     dirty_reg(current,HIREG);
1860     dirty_reg(current,LOREG);
1861   }
1862 }
1863 #endif
1864
1865 void cop0_alloc(struct regstat *current,int i)
1866 {
1867   if(opcode2[i]==0) // MFC0
1868   {
1869     if(rt1[i]) {
1870       clear_const(current,rt1[i]);
1871       alloc_all(current,i);
1872       alloc_reg(current,i,rt1[i]);
1873       current->is32|=1LL<<rt1[i];
1874       dirty_reg(current,rt1[i]);
1875     }
1876   }
1877   else if(opcode2[i]==4) // MTC0
1878   {
1879     if(rs1[i]){
1880       clear_const(current,rs1[i]);
1881       alloc_reg(current,i,rs1[i]);
1882       alloc_all(current,i);
1883     }
1884     else {
1885       alloc_all(current,i); // FIXME: Keep r0
1886       current->u&=~1LL;
1887       alloc_reg(current,i,0);
1888     }
1889   }
1890   else
1891   {
1892     // TLBR/TLBWI/TLBWR/TLBP/ERET
1893     assert(opcode2[i]==0x10);
1894     alloc_all(current,i);
1895   }
1896   minimum_free_regs[i]=HOST_REGS;
1897 }
1898
1899 void cop1_alloc(struct regstat *current,int i)
1900 {
1901   alloc_reg(current,i,CSREG); // Load status
1902   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1903   {
1904     if(rt1[i]){
1905       clear_const(current,rt1[i]);
1906       if(opcode2[i]==1) {
1907         alloc_reg64(current,i,rt1[i]); // DMFC1
1908         current->is32&=~(1LL<<rt1[i]);
1909       }else{
1910         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1911         current->is32|=1LL<<rt1[i];
1912       }
1913       dirty_reg(current,rt1[i]);
1914     }
1915     alloc_reg_temp(current,i,-1);
1916   }
1917   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1918   {
1919     if(rs1[i]){
1920       clear_const(current,rs1[i]);
1921       if(opcode2[i]==5)
1922         alloc_reg64(current,i,rs1[i]); // DMTC1
1923       else
1924         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1925       alloc_reg_temp(current,i,-1);
1926     }
1927     else {
1928       current->u&=~1LL;
1929       alloc_reg(current,i,0);
1930       alloc_reg_temp(current,i,-1);
1931     }
1932   }
1933   minimum_free_regs[i]=1;
1934 }
1935 void fconv_alloc(struct regstat *current,int i)
1936 {
1937   alloc_reg(current,i,CSREG); // Load status
1938   alloc_reg_temp(current,i,-1);
1939   minimum_free_regs[i]=1;
1940 }
1941 void float_alloc(struct regstat *current,int i)
1942 {
1943   alloc_reg(current,i,CSREG); // Load status
1944   alloc_reg_temp(current,i,-1);
1945   minimum_free_regs[i]=1;
1946 }
1947 void c2op_alloc(struct regstat *current,int i)
1948 {
1949   alloc_reg_temp(current,i,-1);
1950 }
1951 void fcomp_alloc(struct regstat *current,int i)
1952 {
1953   alloc_reg(current,i,CSREG); // Load status
1954   alloc_reg(current,i,FSREG); // Load flags
1955   dirty_reg(current,FSREG); // Flag will be modified
1956   alloc_reg_temp(current,i,-1);
1957   minimum_free_regs[i]=1;
1958 }
1959
1960 void syscall_alloc(struct regstat *current,int i)
1961 {
1962   alloc_cc(current,i);
1963   dirty_reg(current,CCREG);
1964   alloc_all(current,i);
1965   minimum_free_regs[i]=HOST_REGS;
1966   current->isconst=0;
1967 }
1968
1969 void delayslot_alloc(struct regstat *current,int i)
1970 {
1971   switch(itype[i]) {
1972     case UJUMP:
1973     case CJUMP:
1974     case SJUMP:
1975     case RJUMP:
1976     case FJUMP:
1977     case SYSCALL:
1978     case HLECALL:
1979     case SPAN:
1980       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1981       printf("Disabled speculative precompilation\n");
1982       stop_after_jal=1;
1983       break;
1984     case IMM16:
1985       imm16_alloc(current,i);
1986       break;
1987     case LOAD:
1988     case LOADLR:
1989       load_alloc(current,i);
1990       break;
1991     case STORE:
1992     case STORELR:
1993       store_alloc(current,i);
1994       break;
1995     case ALU:
1996       alu_alloc(current,i);
1997       break;
1998     case SHIFT:
1999       shift_alloc(current,i);
2000       break;
2001     case MULTDIV:
2002       multdiv_alloc(current,i);
2003       break;
2004     case SHIFTIMM:
2005       shiftimm_alloc(current,i);
2006       break;
2007     case MOV:
2008       mov_alloc(current,i);
2009       break;
2010     case COP0:
2011       cop0_alloc(current,i);
2012       break;
2013     case COP1:
2014     case COP2:
2015       cop1_alloc(current,i);
2016       break;
2017     case C1LS:
2018       c1ls_alloc(current,i);
2019       break;
2020     case C2LS:
2021       c2ls_alloc(current,i);
2022       break;
2023     case FCONV:
2024       fconv_alloc(current,i);
2025       break;
2026     case FLOAT:
2027       float_alloc(current,i);
2028       break;
2029     case FCOMP:
2030       fcomp_alloc(current,i);
2031       break;
2032     case C2OP:
2033       c2op_alloc(current,i);
2034       break;
2035   }
2036 }
2037
2038 // Special case where a branch and delay slot span two pages in virtual memory
2039 static void pagespan_alloc(struct regstat *current,int i)
2040 {
2041   current->isconst=0;
2042   current->wasconst=0;
2043   regs[i].wasconst=0;
2044   minimum_free_regs[i]=HOST_REGS;
2045   alloc_all(current,i);
2046   alloc_cc(current,i);
2047   dirty_reg(current,CCREG);
2048   if(opcode[i]==3) // JAL
2049   {
2050     alloc_reg(current,i,31);
2051     dirty_reg(current,31);
2052   }
2053   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2054   {
2055     alloc_reg(current,i,rs1[i]);
2056     if (rt1[i]!=0) {
2057       alloc_reg(current,i,rt1[i]);
2058       dirty_reg(current,rt1[i]);
2059     }
2060   }
2061   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2062   {
2063     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2064     if(rs2[i]) alloc_reg(current,i,rs2[i]);
2065     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2066     {
2067       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2068       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2069     }
2070   }
2071   else
2072   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2073   {
2074     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2075     if(!((current->is32>>rs1[i])&1))
2076     {
2077       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2078     }
2079   }
2080   else
2081   if(opcode[i]==0x11) // BC1
2082   {
2083     alloc_reg(current,i,FSREG);
2084     alloc_reg(current,i,CSREG);
2085   }
2086   //else ...
2087 }
2088
2089 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2090 {
2091   stubs[stubcount][0]=type;
2092   stubs[stubcount][1]=addr;
2093   stubs[stubcount][2]=retaddr;
2094   stubs[stubcount][3]=a;
2095   stubs[stubcount][4]=b;
2096   stubs[stubcount][5]=c;
2097   stubs[stubcount][6]=d;
2098   stubs[stubcount][7]=e;
2099   stubcount++;
2100 }
2101
2102 // Write out a single register
2103 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2104 {
2105   int hr;
2106   for(hr=0;hr<HOST_REGS;hr++) {
2107     if(hr!=EXCLUDE_REG) {
2108       if((regmap[hr]&63)==r) {
2109         if((dirty>>hr)&1) {
2110           if(regmap[hr]<64) {
2111             emit_storereg(r,hr);
2112 #ifndef FORCE32
2113             if((is32>>regmap[hr])&1) {
2114               emit_sarimm(hr,31,hr);
2115               emit_storereg(r|64,hr);
2116             }
2117 #endif
2118           }else{
2119             emit_storereg(r|64,hr);
2120           }
2121         }
2122       }
2123     }
2124   }
2125 }
2126
2127 int mchecksum()
2128 {
2129   //if(!tracedebug) return 0;
2130   int i;
2131   int sum=0;
2132   for(i=0;i<2097152;i++) {
2133     unsigned int temp=sum;
2134     sum<<=1;
2135     sum|=(~temp)>>31;
2136     sum^=((u_int *)rdram)[i];
2137   }
2138   return sum;
2139 }
2140 int rchecksum()
2141 {
2142   int i;
2143   int sum=0;
2144   for(i=0;i<64;i++)
2145     sum^=((u_int *)reg)[i];
2146   return sum;
2147 }
2148 void rlist()
2149 {
2150   int i;
2151   printf("TRACE: ");
2152   for(i=0;i<32;i++)
2153     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2154   printf("\n");
2155 #ifndef DISABLE_COP1
2156   printf("TRACE: ");
2157   for(i=0;i<32;i++)
2158     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2159   printf("\n");
2160 #endif
2161 }
2162
2163 void enabletrace()
2164 {
2165   tracedebug=1;
2166 }
2167
2168 void memdebug(int i)
2169 {
2170   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2171   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2172   //rlist();
2173   //if(tracedebug) {
2174   //if(Count>=-2084597794) {
2175   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2176   //if(0) {
2177     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2178     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2179     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2180     rlist();
2181     #ifdef __i386__
2182     printf("TRACE: %x\n",(&i)[-1]);
2183     #endif
2184     #ifdef __arm__
2185     int j;
2186     printf("TRACE: %x \n",(&j)[10]);
2187     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2188     #endif
2189     //fflush(stdout);
2190   }
2191   //printf("TRACE: %x\n",(&i)[-1]);
2192 }
2193
2194 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2195 {
2196   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2197 }
2198
2199 void alu_assemble(int i,struct regstat *i_regs)
2200 {
2201   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2202     if(rt1[i]) {
2203       signed char s1,s2,t;
2204       t=get_reg(i_regs->regmap,rt1[i]);
2205       if(t>=0) {
2206         s1=get_reg(i_regs->regmap,rs1[i]);
2207         s2=get_reg(i_regs->regmap,rs2[i]);
2208         if(rs1[i]&&rs2[i]) {
2209           assert(s1>=0);
2210           assert(s2>=0);
2211           if(opcode2[i]&2) emit_sub(s1,s2,t);
2212           else emit_add(s1,s2,t);
2213         }
2214         else if(rs1[i]) {
2215           if(s1>=0) emit_mov(s1,t);
2216           else emit_loadreg(rs1[i],t);
2217         }
2218         else if(rs2[i]) {
2219           if(s2>=0) {
2220             if(opcode2[i]&2) emit_neg(s2,t);
2221             else emit_mov(s2,t);
2222           }
2223           else {
2224             emit_loadreg(rs2[i],t);
2225             if(opcode2[i]&2) emit_neg(t,t);
2226           }
2227         }
2228         else emit_zeroreg(t);
2229       }
2230     }
2231   }
2232   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2233     if(rt1[i]) {
2234       signed char s1l,s2l,s1h,s2h,tl,th;
2235       tl=get_reg(i_regs->regmap,rt1[i]);
2236       th=get_reg(i_regs->regmap,rt1[i]|64);
2237       if(tl>=0) {
2238         s1l=get_reg(i_regs->regmap,rs1[i]);
2239         s2l=get_reg(i_regs->regmap,rs2[i]);
2240         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2241         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2242         if(rs1[i]&&rs2[i]) {
2243           assert(s1l>=0);
2244           assert(s2l>=0);
2245           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2246           else emit_adds(s1l,s2l,tl);
2247           if(th>=0) {
2248             #ifdef INVERTED_CARRY
2249             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2250             #else
2251             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2252             #endif
2253             else emit_add(s1h,s2h,th);
2254           }
2255         }
2256         else if(rs1[i]) {
2257           if(s1l>=0) emit_mov(s1l,tl);
2258           else emit_loadreg(rs1[i],tl);
2259           if(th>=0) {
2260             if(s1h>=0) emit_mov(s1h,th);
2261             else emit_loadreg(rs1[i]|64,th);
2262           }
2263         }
2264         else if(rs2[i]) {
2265           if(s2l>=0) {
2266             if(opcode2[i]&2) emit_negs(s2l,tl);
2267             else emit_mov(s2l,tl);
2268           }
2269           else {
2270             emit_loadreg(rs2[i],tl);
2271             if(opcode2[i]&2) emit_negs(tl,tl);
2272           }
2273           if(th>=0) {
2274             #ifdef INVERTED_CARRY
2275             if(s2h>=0) emit_mov(s2h,th);
2276             else emit_loadreg(rs2[i]|64,th);
2277             if(opcode2[i]&2) {
2278               emit_adcimm(-1,th); // x86 has inverted carry flag
2279               emit_not(th,th);
2280             }
2281             #else
2282             if(opcode2[i]&2) {
2283               if(s2h>=0) emit_rscimm(s2h,0,th);
2284               else {
2285                 emit_loadreg(rs2[i]|64,th);
2286                 emit_rscimm(th,0,th);
2287               }
2288             }else{
2289               if(s2h>=0) emit_mov(s2h,th);
2290               else emit_loadreg(rs2[i]|64,th);
2291             }
2292             #endif
2293           }
2294         }
2295         else {
2296           emit_zeroreg(tl);
2297           if(th>=0) emit_zeroreg(th);
2298         }
2299       }
2300     }
2301   }
2302   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2303     if(rt1[i]) {
2304       signed char s1l,s1h,s2l,s2h,t;
2305       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2306       {
2307         t=get_reg(i_regs->regmap,rt1[i]);
2308         //assert(t>=0);
2309         if(t>=0) {
2310           s1l=get_reg(i_regs->regmap,rs1[i]);
2311           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2312           s2l=get_reg(i_regs->regmap,rs2[i]);
2313           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2314           if(rs2[i]==0) // rx<r0
2315           {
2316             assert(s1h>=0);
2317             if(opcode2[i]==0x2a) // SLT
2318               emit_shrimm(s1h,31,t);
2319             else // SLTU (unsigned can not be less than zero)
2320               emit_zeroreg(t);
2321           }
2322           else if(rs1[i]==0) // r0<rx
2323           {
2324             assert(s2h>=0);
2325             if(opcode2[i]==0x2a) // SLT
2326               emit_set_gz64_32(s2h,s2l,t);
2327             else // SLTU (set if not zero)
2328               emit_set_nz64_32(s2h,s2l,t);
2329           }
2330           else {
2331             assert(s1l>=0);assert(s1h>=0);
2332             assert(s2l>=0);assert(s2h>=0);
2333             if(opcode2[i]==0x2a) // SLT
2334               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2335             else // SLTU
2336               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2337           }
2338         }
2339       } else {
2340         t=get_reg(i_regs->regmap,rt1[i]);
2341         //assert(t>=0);
2342         if(t>=0) {
2343           s1l=get_reg(i_regs->regmap,rs1[i]);
2344           s2l=get_reg(i_regs->regmap,rs2[i]);
2345           if(rs2[i]==0) // rx<r0
2346           {
2347             assert(s1l>=0);
2348             if(opcode2[i]==0x2a) // SLT
2349               emit_shrimm(s1l,31,t);
2350             else // SLTU (unsigned can not be less than zero)
2351               emit_zeroreg(t);
2352           }
2353           else if(rs1[i]==0) // r0<rx
2354           {
2355             assert(s2l>=0);
2356             if(opcode2[i]==0x2a) // SLT
2357               emit_set_gz32(s2l,t);
2358             else // SLTU (set if not zero)
2359               emit_set_nz32(s2l,t);
2360           }
2361           else{
2362             assert(s1l>=0);assert(s2l>=0);
2363             if(opcode2[i]==0x2a) // SLT
2364               emit_set_if_less32(s1l,s2l,t);
2365             else // SLTU
2366               emit_set_if_carry32(s1l,s2l,t);
2367           }
2368         }
2369       }
2370     }
2371   }
2372   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2373     if(rt1[i]) {
2374       signed char s1l,s1h,s2l,s2h,th,tl;
2375       tl=get_reg(i_regs->regmap,rt1[i]);
2376       th=get_reg(i_regs->regmap,rt1[i]|64);
2377       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2378       {
2379         assert(tl>=0);
2380         if(tl>=0) {
2381           s1l=get_reg(i_regs->regmap,rs1[i]);
2382           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2383           s2l=get_reg(i_regs->regmap,rs2[i]);
2384           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2385           if(rs1[i]&&rs2[i]) {
2386             assert(s1l>=0);assert(s1h>=0);
2387             assert(s2l>=0);assert(s2h>=0);
2388             if(opcode2[i]==0x24) { // AND
2389               emit_and(s1l,s2l,tl);
2390               emit_and(s1h,s2h,th);
2391             } else
2392             if(opcode2[i]==0x25) { // OR
2393               emit_or(s1l,s2l,tl);
2394               emit_or(s1h,s2h,th);
2395             } else
2396             if(opcode2[i]==0x26) { // XOR
2397               emit_xor(s1l,s2l,tl);
2398               emit_xor(s1h,s2h,th);
2399             } else
2400             if(opcode2[i]==0x27) { // NOR
2401               emit_or(s1l,s2l,tl);
2402               emit_or(s1h,s2h,th);
2403               emit_not(tl,tl);
2404               emit_not(th,th);
2405             }
2406           }
2407           else
2408           {
2409             if(opcode2[i]==0x24) { // AND
2410               emit_zeroreg(tl);
2411               emit_zeroreg(th);
2412             } else
2413             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2414               if(rs1[i]){
2415                 if(s1l>=0) emit_mov(s1l,tl);
2416                 else emit_loadreg(rs1[i],tl);
2417                 if(s1h>=0) emit_mov(s1h,th);
2418                 else emit_loadreg(rs1[i]|64,th);
2419               }
2420               else
2421               if(rs2[i]){
2422                 if(s2l>=0) emit_mov(s2l,tl);
2423                 else emit_loadreg(rs2[i],tl);
2424                 if(s2h>=0) emit_mov(s2h,th);
2425                 else emit_loadreg(rs2[i]|64,th);
2426               }
2427               else{
2428                 emit_zeroreg(tl);
2429                 emit_zeroreg(th);
2430               }
2431             } else
2432             if(opcode2[i]==0x27) { // NOR
2433               if(rs1[i]){
2434                 if(s1l>=0) emit_not(s1l,tl);
2435                 else{
2436                   emit_loadreg(rs1[i],tl);
2437                   emit_not(tl,tl);
2438                 }
2439                 if(s1h>=0) emit_not(s1h,th);
2440                 else{
2441                   emit_loadreg(rs1[i]|64,th);
2442                   emit_not(th,th);
2443                 }
2444               }
2445               else
2446               if(rs2[i]){
2447                 if(s2l>=0) emit_not(s2l,tl);
2448                 else{
2449                   emit_loadreg(rs2[i],tl);
2450                   emit_not(tl,tl);
2451                 }
2452                 if(s2h>=0) emit_not(s2h,th);
2453                 else{
2454                   emit_loadreg(rs2[i]|64,th);
2455                   emit_not(th,th);
2456                 }
2457               }
2458               else {
2459                 emit_movimm(-1,tl);
2460                 emit_movimm(-1,th);
2461               }
2462             }
2463           }
2464         }
2465       }
2466       else
2467       {
2468         // 32 bit
2469         if(tl>=0) {
2470           s1l=get_reg(i_regs->regmap,rs1[i]);
2471           s2l=get_reg(i_regs->regmap,rs2[i]);
2472           if(rs1[i]&&rs2[i]) {
2473             assert(s1l>=0);
2474             assert(s2l>=0);
2475             if(opcode2[i]==0x24) { // AND
2476               emit_and(s1l,s2l,tl);
2477             } else
2478             if(opcode2[i]==0x25) { // OR
2479               emit_or(s1l,s2l,tl);
2480             } else
2481             if(opcode2[i]==0x26) { // XOR
2482               emit_xor(s1l,s2l,tl);
2483             } else
2484             if(opcode2[i]==0x27) { // NOR
2485               emit_or(s1l,s2l,tl);
2486               emit_not(tl,tl);
2487             }
2488           }
2489           else
2490           {
2491             if(opcode2[i]==0x24) { // AND
2492               emit_zeroreg(tl);
2493             } else
2494             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2495               if(rs1[i]){
2496                 if(s1l>=0) emit_mov(s1l,tl);
2497                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2498               }
2499               else
2500               if(rs2[i]){
2501                 if(s2l>=0) emit_mov(s2l,tl);
2502                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2503               }
2504               else emit_zeroreg(tl);
2505             } else
2506             if(opcode2[i]==0x27) { // NOR
2507               if(rs1[i]){
2508                 if(s1l>=0) emit_not(s1l,tl);
2509                 else {
2510                   emit_loadreg(rs1[i],tl);
2511                   emit_not(tl,tl);
2512                 }
2513               }
2514               else
2515               if(rs2[i]){
2516                 if(s2l>=0) emit_not(s2l,tl);
2517                 else {
2518                   emit_loadreg(rs2[i],tl);
2519                   emit_not(tl,tl);
2520                 }
2521               }
2522               else emit_movimm(-1,tl);
2523             }
2524           }
2525         }
2526       }
2527     }
2528   }
2529 }
2530
2531 void imm16_assemble(int i,struct regstat *i_regs)
2532 {
2533   if (opcode[i]==0x0f) { // LUI
2534     if(rt1[i]) {
2535       signed char t;
2536       t=get_reg(i_regs->regmap,rt1[i]);
2537       //assert(t>=0);
2538       if(t>=0) {
2539         if(!((i_regs->isconst>>t)&1))
2540           emit_movimm(imm[i]<<16,t);
2541       }
2542     }
2543   }
2544   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2545     if(rt1[i]) {
2546       signed char s,t;
2547       t=get_reg(i_regs->regmap,rt1[i]);
2548       s=get_reg(i_regs->regmap,rs1[i]);
2549       if(rs1[i]) {
2550         //assert(t>=0);
2551         //assert(s>=0);
2552         if(t>=0) {
2553           if(!((i_regs->isconst>>t)&1)) {
2554             if(s<0) {
2555               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2556               emit_addimm(t,imm[i],t);
2557             }else{
2558               if(!((i_regs->wasconst>>s)&1))
2559                 emit_addimm(s,imm[i],t);
2560               else
2561                 emit_movimm(constmap[i][s]+imm[i],t);
2562             }
2563           }
2564         }
2565       } else {
2566         if(t>=0) {
2567           if(!((i_regs->isconst>>t)&1))
2568             emit_movimm(imm[i],t);
2569         }
2570       }
2571     }
2572   }
2573   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2574     if(rt1[i]) {
2575       signed char sh,sl,th,tl;
2576       th=get_reg(i_regs->regmap,rt1[i]|64);
2577       tl=get_reg(i_regs->regmap,rt1[i]);
2578       sh=get_reg(i_regs->regmap,rs1[i]|64);
2579       sl=get_reg(i_regs->regmap,rs1[i]);
2580       if(tl>=0) {
2581         if(rs1[i]) {
2582           assert(sh>=0);
2583           assert(sl>=0);
2584           if(th>=0) {
2585             emit_addimm64_32(sh,sl,imm[i],th,tl);
2586           }
2587           else {
2588             emit_addimm(sl,imm[i],tl);
2589           }
2590         } else {
2591           emit_movimm(imm[i],tl);
2592           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2593         }
2594       }
2595     }
2596   }
2597   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2598     if(rt1[i]) {
2599       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2600       signed char sh,sl,t;
2601       t=get_reg(i_regs->regmap,rt1[i]);
2602       sh=get_reg(i_regs->regmap,rs1[i]|64);
2603       sl=get_reg(i_regs->regmap,rs1[i]);
2604       //assert(t>=0);
2605       if(t>=0) {
2606         if(rs1[i]>0) {
2607           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2608           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2609             if(opcode[i]==0x0a) { // SLTI
2610               if(sl<0) {
2611                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2612                 emit_slti32(t,imm[i],t);
2613               }else{
2614                 emit_slti32(sl,imm[i],t);
2615               }
2616             }
2617             else { // SLTIU
2618               if(sl<0) {
2619                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2620                 emit_sltiu32(t,imm[i],t);
2621               }else{
2622                 emit_sltiu32(sl,imm[i],t);
2623               }
2624             }
2625           }else{ // 64-bit
2626             assert(sl>=0);
2627             if(opcode[i]==0x0a) // SLTI
2628               emit_slti64_32(sh,sl,imm[i],t);
2629             else // SLTIU
2630               emit_sltiu64_32(sh,sl,imm[i],t);
2631           }
2632         }else{
2633           // SLTI(U) with r0 is just stupid,
2634           // nonetheless examples can be found
2635           if(opcode[i]==0x0a) // SLTI
2636             if(0<imm[i]) emit_movimm(1,t);
2637             else emit_zeroreg(t);
2638           else // SLTIU
2639           {
2640             if(imm[i]) emit_movimm(1,t);
2641             else emit_zeroreg(t);
2642           }
2643         }
2644       }
2645     }
2646   }
2647   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2648     if(rt1[i]) {
2649       signed char sh,sl,th,tl;
2650       th=get_reg(i_regs->regmap,rt1[i]|64);
2651       tl=get_reg(i_regs->regmap,rt1[i]);
2652       sh=get_reg(i_regs->regmap,rs1[i]|64);
2653       sl=get_reg(i_regs->regmap,rs1[i]);
2654       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2655         if(opcode[i]==0x0c) //ANDI
2656         {
2657           if(rs1[i]) {
2658             if(sl<0) {
2659               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2660               emit_andimm(tl,imm[i],tl);
2661             }else{
2662               if(!((i_regs->wasconst>>sl)&1))
2663                 emit_andimm(sl,imm[i],tl);
2664               else
2665                 emit_movimm(constmap[i][sl]&imm[i],tl);
2666             }
2667           }
2668           else
2669             emit_zeroreg(tl);
2670           if(th>=0) emit_zeroreg(th);
2671         }
2672         else
2673         {
2674           if(rs1[i]) {
2675             if(sl<0) {
2676               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2677             }
2678             if(th>=0) {
2679               if(sh<0) {
2680                 emit_loadreg(rs1[i]|64,th);
2681               }else{
2682                 emit_mov(sh,th);
2683               }
2684             }
2685             if(opcode[i]==0x0d) //ORI
2686             if(sl<0) {
2687               emit_orimm(tl,imm[i],tl);
2688             }else{
2689               if(!((i_regs->wasconst>>sl)&1))
2690                 emit_orimm(sl,imm[i],tl);
2691               else
2692                 emit_movimm(constmap[i][sl]|imm[i],tl);
2693             }
2694             if(opcode[i]==0x0e) //XORI
2695             if(sl<0) {
2696               emit_xorimm(tl,imm[i],tl);
2697             }else{
2698               if(!((i_regs->wasconst>>sl)&1))
2699                 emit_xorimm(sl,imm[i],tl);
2700               else
2701                 emit_movimm(constmap[i][sl]^imm[i],tl);
2702             }
2703           }
2704           else {
2705             emit_movimm(imm[i],tl);
2706             if(th>=0) emit_zeroreg(th);
2707           }
2708         }
2709       }
2710     }
2711   }
2712 }
2713
2714 void shiftimm_assemble(int i,struct regstat *i_regs)
2715 {
2716   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2717   {
2718     if(rt1[i]) {
2719       signed char s,t;
2720       t=get_reg(i_regs->regmap,rt1[i]);
2721       s=get_reg(i_regs->regmap,rs1[i]);
2722       //assert(t>=0);
2723       if(t>=0&&!((i_regs->isconst>>t)&1)){
2724         if(rs1[i]==0)
2725         {
2726           emit_zeroreg(t);
2727         }
2728         else
2729         {
2730           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2731           if(imm[i]) {
2732             if(opcode2[i]==0) // SLL
2733             {
2734               emit_shlimm(s<0?t:s,imm[i],t);
2735             }
2736             if(opcode2[i]==2) // SRL
2737             {
2738               emit_shrimm(s<0?t:s,imm[i],t);
2739             }
2740             if(opcode2[i]==3) // SRA
2741             {
2742               emit_sarimm(s<0?t:s,imm[i],t);
2743             }
2744           }else{
2745             // Shift by zero
2746             if(s>=0 && s!=t) emit_mov(s,t);
2747           }
2748         }
2749       }
2750       //emit_storereg(rt1[i],t); //DEBUG
2751     }
2752   }
2753   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2754   {
2755     if(rt1[i]) {
2756       signed char sh,sl,th,tl;
2757       th=get_reg(i_regs->regmap,rt1[i]|64);
2758       tl=get_reg(i_regs->regmap,rt1[i]);
2759       sh=get_reg(i_regs->regmap,rs1[i]|64);
2760       sl=get_reg(i_regs->regmap,rs1[i]);
2761       if(tl>=0) {
2762         if(rs1[i]==0)
2763         {
2764           emit_zeroreg(tl);
2765           if(th>=0) emit_zeroreg(th);
2766         }
2767         else
2768         {
2769           assert(sl>=0);
2770           assert(sh>=0);
2771           if(imm[i]) {
2772             if(opcode2[i]==0x38) // DSLL
2773             {
2774               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2775               emit_shlimm(sl,imm[i],tl);
2776             }
2777             if(opcode2[i]==0x3a) // DSRL
2778             {
2779               emit_shrdimm(sl,sh,imm[i],tl);
2780               if(th>=0) emit_shrimm(sh,imm[i],th);
2781             }
2782             if(opcode2[i]==0x3b) // DSRA
2783             {
2784               emit_shrdimm(sl,sh,imm[i],tl);
2785               if(th>=0) emit_sarimm(sh,imm[i],th);
2786             }
2787           }else{
2788             // Shift by zero
2789             if(sl!=tl) emit_mov(sl,tl);
2790             if(th>=0&&sh!=th) emit_mov(sh,th);
2791           }
2792         }
2793       }
2794     }
2795   }
2796   if(opcode2[i]==0x3c) // DSLL32
2797   {
2798     if(rt1[i]) {
2799       signed char sl,tl,th;
2800       tl=get_reg(i_regs->regmap,rt1[i]);
2801       th=get_reg(i_regs->regmap,rt1[i]|64);
2802       sl=get_reg(i_regs->regmap,rs1[i]);
2803       if(th>=0||tl>=0){
2804         assert(tl>=0);
2805         assert(th>=0);
2806         assert(sl>=0);
2807         emit_mov(sl,th);
2808         emit_zeroreg(tl);
2809         if(imm[i]>32)
2810         {
2811           emit_shlimm(th,imm[i]&31,th);
2812         }
2813       }
2814     }
2815   }
2816   if(opcode2[i]==0x3e) // DSRL32
2817   {
2818     if(rt1[i]) {
2819       signed char sh,tl,th;
2820       tl=get_reg(i_regs->regmap,rt1[i]);
2821       th=get_reg(i_regs->regmap,rt1[i]|64);
2822       sh=get_reg(i_regs->regmap,rs1[i]|64);
2823       if(tl>=0){
2824         assert(sh>=0);
2825         emit_mov(sh,tl);
2826         if(th>=0) emit_zeroreg(th);
2827         if(imm[i]>32)
2828         {
2829           emit_shrimm(tl,imm[i]&31,tl);
2830         }
2831       }
2832     }
2833   }
2834   if(opcode2[i]==0x3f) // DSRA32
2835   {
2836     if(rt1[i]) {
2837       signed char sh,tl;
2838       tl=get_reg(i_regs->regmap,rt1[i]);
2839       sh=get_reg(i_regs->regmap,rs1[i]|64);
2840       if(tl>=0){
2841         assert(sh>=0);
2842         emit_mov(sh,tl);
2843         if(imm[i]>32)
2844         {
2845           emit_sarimm(tl,imm[i]&31,tl);
2846         }
2847       }
2848     }
2849   }
2850 }
2851
2852 #ifndef shift_assemble
2853 void shift_assemble(int i,struct regstat *i_regs)
2854 {
2855   printf("Need shift_assemble for this architecture.\n");
2856   exit(1);
2857 }
2858 #endif
2859
2860 void load_assemble(int i,struct regstat *i_regs)
2861 {
2862   int s,th,tl,addr,map=-1;
2863   int offset;
2864   int jaddr=0;
2865   int memtarget=0,c=0;
2866   int fastload_reg_override=0;
2867   u_int hr,reglist=0;
2868   th=get_reg(i_regs->regmap,rt1[i]|64);
2869   tl=get_reg(i_regs->regmap,rt1[i]);
2870   s=get_reg(i_regs->regmap,rs1[i]);
2871   offset=imm[i];
2872   for(hr=0;hr<HOST_REGS;hr++) {
2873     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2874   }
2875   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2876   if(s>=0) {
2877     c=(i_regs->wasconst>>s)&1;
2878     if (c) {
2879       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2880       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2881     }
2882   }
2883   //printf("load_assemble: c=%d\n",c);
2884   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2885   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2886 #ifdef PCSX
2887   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2888     ||rt1[i]==0) {
2889       // could be FIFO, must perform the read
2890       // ||dummy read
2891       assem_debug("(forced read)\n");
2892       tl=get_reg(i_regs->regmap,-1);
2893       assert(tl>=0);
2894   }
2895 #endif
2896   if(offset||s<0||c) addr=tl;
2897   else addr=s;
2898   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2899  if(tl>=0) {
2900   //printf("load_assemble: c=%d\n",c);
2901   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2902   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2903   reglist&=~(1<<tl);
2904   if(th>=0) reglist&=~(1<<th);
2905   if(!using_tlb) {
2906     if(!c) {
2907       #ifdef RAM_OFFSET
2908       map=get_reg(i_regs->regmap,ROREG);
2909       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2910       #endif
2911 //#define R29_HACK 1
2912       #ifdef R29_HACK
2913       // Strmnnrmn's speed hack
2914       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2915       #endif
2916       {
2917         jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2918       }
2919     }
2920   }else{ // using tlb
2921     int x=0;
2922     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2923     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2924     map=get_reg(i_regs->regmap,TLREG);
2925     assert(map>=0);
2926     reglist&=~(1<<map);
2927     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2928     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2929   }
2930   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2931   if (opcode[i]==0x20) { // LB
2932     if(!c||memtarget) {
2933       if(!dummy) {
2934         #ifdef HOST_IMM_ADDR32
2935         if(c)
2936           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2937         else
2938         #endif
2939         {
2940           //emit_xorimm(addr,3,tl);
2941           //gen_tlb_addr_r(tl,map);
2942           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2943           int x=0,a=tl;
2944 #ifdef BIG_ENDIAN_MIPS
2945           if(!c) emit_xorimm(addr,3,tl);
2946           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2947 #else
2948           if(!c) a=addr;
2949 #endif
2950           if(fastload_reg_override) a=fastload_reg_override;
2951
2952           emit_movsbl_indexed_tlb(x,a,map,tl);
2953         }
2954       }
2955       if(jaddr)
2956         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2957     }
2958     else
2959       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2960   }
2961   if (opcode[i]==0x21) { // LH
2962     if(!c||memtarget) {
2963       if(!dummy) {
2964         #ifdef HOST_IMM_ADDR32
2965         if(c)
2966           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2967         else
2968         #endif
2969         {
2970           int x=0,a=tl;
2971 #ifdef BIG_ENDIAN_MIPS
2972           if(!c) emit_xorimm(addr,2,tl);
2973           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2974 #else
2975           if(!c) a=addr;
2976 #endif
2977           if(fastload_reg_override) a=fastload_reg_override;
2978           //#ifdef
2979           //emit_movswl_indexed_tlb(x,tl,map,tl);
2980           //else
2981           if(map>=0) {
2982             gen_tlb_addr_r(a,map);
2983             emit_movswl_indexed(x,a,tl);
2984           }else{
2985             #ifdef RAM_OFFSET
2986             emit_movswl_indexed(x,a,tl);
2987             #else
2988             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2989             #endif
2990           }
2991         }
2992       }
2993       if(jaddr)
2994         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2995     }
2996     else
2997       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2998   }
2999   if (opcode[i]==0x23) { // LW
3000     if(!c||memtarget) {
3001       if(!dummy) {
3002         int a=addr;
3003         if(fastload_reg_override) a=fastload_reg_override;
3004         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3005         #ifdef HOST_IMM_ADDR32
3006         if(c)
3007           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3008         else
3009         #endif
3010         emit_readword_indexed_tlb(0,a,map,tl);
3011       }
3012       if(jaddr)
3013         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3014     }
3015     else
3016       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3017   }
3018   if (opcode[i]==0x24) { // LBU
3019     if(!c||memtarget) {
3020       if(!dummy) {
3021         #ifdef HOST_IMM_ADDR32
3022         if(c)
3023           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3024         else
3025         #endif
3026         {
3027           //emit_xorimm(addr,3,tl);
3028           //gen_tlb_addr_r(tl,map);
3029           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3030           int x=0,a=tl;
3031 #ifdef BIG_ENDIAN_MIPS
3032           if(!c) emit_xorimm(addr,3,tl);
3033           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3034 #else
3035           if(!c) a=addr;
3036 #endif
3037           if(fastload_reg_override) a=fastload_reg_override;
3038
3039           emit_movzbl_indexed_tlb(x,a,map,tl);
3040         }
3041       }
3042       if(jaddr)
3043         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3044     }
3045     else
3046       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3047   }
3048   if (opcode[i]==0x25) { // LHU
3049     if(!c||memtarget) {
3050       if(!dummy) {
3051         #ifdef HOST_IMM_ADDR32
3052         if(c)
3053           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3054         else
3055         #endif
3056         {
3057           int x=0,a=tl;
3058 #ifdef BIG_ENDIAN_MIPS
3059           if(!c) emit_xorimm(addr,2,tl);
3060           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3061 #else
3062           if(!c) a=addr;
3063 #endif
3064           if(fastload_reg_override) a=fastload_reg_override;
3065           //#ifdef
3066           //emit_movzwl_indexed_tlb(x,tl,map,tl);
3067           //#else
3068           if(map>=0) {
3069             gen_tlb_addr_r(a,map);
3070             emit_movzwl_indexed(x,a,tl);
3071           }else{
3072             #ifdef RAM_OFFSET
3073             emit_movzwl_indexed(x,a,tl);
3074             #else
3075             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3076             #endif
3077           }
3078         }
3079       }
3080       if(jaddr)
3081         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3082     }
3083     else
3084       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3085   }
3086   if (opcode[i]==0x27) { // LWU
3087     assert(th>=0);
3088     if(!c||memtarget) {
3089       if(!dummy) {
3090         int a=addr;
3091         if(fastload_reg_override) a=fastload_reg_override;
3092         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3093         #ifdef HOST_IMM_ADDR32
3094         if(c)
3095           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3096         else
3097         #endif
3098         emit_readword_indexed_tlb(0,a,map,tl);
3099       }
3100       if(jaddr)
3101         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3102     }
3103     else {
3104       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3105     }
3106     emit_zeroreg(th);
3107   }
3108   if (opcode[i]==0x37) { // LD
3109     if(!c||memtarget) {
3110       if(!dummy) {
3111         int a=addr;
3112         if(fastload_reg_override) a=fastload_reg_override;
3113         //gen_tlb_addr_r(tl,map);
3114         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3115         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3116         #ifdef HOST_IMM_ADDR32
3117         if(c)
3118           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3119         else
3120         #endif
3121         emit_readdword_indexed_tlb(0,a,map,th,tl);
3122       }
3123       if(jaddr)
3124         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3125     }
3126     else
3127       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3128   }
3129  }
3130   //emit_storereg(rt1[i],tl); // DEBUG
3131   //if(opcode[i]==0x23)
3132   //if(opcode[i]==0x24)
3133   //if(opcode[i]==0x23||opcode[i]==0x24)
3134   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3135   {
3136     //emit_pusha();
3137     save_regs(0x100f);
3138         emit_readword((int)&last_count,ECX);
3139         #ifdef __i386__
3140         if(get_reg(i_regs->regmap,CCREG)<0)
3141           emit_loadreg(CCREG,HOST_CCREG);
3142         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3143         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3144         emit_writeword(HOST_CCREG,(int)&Count);
3145         #endif
3146         #ifdef __arm__
3147         if(get_reg(i_regs->regmap,CCREG)<0)
3148           emit_loadreg(CCREG,0);
3149         else
3150           emit_mov(HOST_CCREG,0);
3151         emit_add(0,ECX,0);
3152         emit_addimm(0,2*ccadj[i],0);
3153         emit_writeword(0,(int)&Count);
3154         #endif
3155     emit_call((int)memdebug);
3156     //emit_popa();
3157     restore_regs(0x100f);
3158   }/**/
3159 }
3160
3161 #ifndef loadlr_assemble
3162 void loadlr_assemble(int i,struct regstat *i_regs)
3163 {
3164   printf("Need loadlr_assemble for this architecture.\n");
3165   exit(1);
3166 }
3167 #endif
3168
3169 void store_assemble(int i,struct regstat *i_regs)
3170 {
3171   int s,th,tl,map=-1;
3172   int addr,temp;
3173   int offset;
3174   int jaddr=0,jaddr2,type;
3175   int memtarget=0,c=0;
3176   int agr=AGEN1+(i&1);
3177   int faststore_reg_override=0;
3178   u_int hr,reglist=0;
3179   th=get_reg(i_regs->regmap,rs2[i]|64);
3180   tl=get_reg(i_regs->regmap,rs2[i]);
3181   s=get_reg(i_regs->regmap,rs1[i]);
3182   temp=get_reg(i_regs->regmap,agr);
3183   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3184   offset=imm[i];
3185   if(s>=0) {
3186     c=(i_regs->wasconst>>s)&1;
3187     if(c) {
3188       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3189       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3190     }
3191   }
3192   assert(tl>=0);
3193   assert(temp>=0);
3194   for(hr=0;hr<HOST_REGS;hr++) {
3195     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3196   }
3197   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3198   if(offset||s<0||c) addr=temp;
3199   else addr=s;
3200   if(!using_tlb) {
3201     if(!c) {
3202       #ifndef PCSX
3203       #ifdef R29_HACK
3204       // Strmnnrmn's speed hack
3205       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3206       #endif
3207       emit_cmpimm(addr,RAM_SIZE);
3208       #ifdef DESTRUCTIVE_SHIFT
3209       if(s==addr) emit_mov(s,temp);
3210       #endif
3211       #ifdef R29_HACK
3212       memtarget=1;
3213       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3214       #endif
3215       {
3216         jaddr=(int)out;
3217         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3218         // Hint to branch predictor that the branch is unlikely to be taken
3219         if(rs1[i]>=28)
3220           emit_jno_unlikely(0);
3221         else
3222         #endif
3223         emit_jno(0);
3224       }
3225       #else
3226         jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3227       #endif
3228     }
3229   }else{ // using tlb
3230     int x=0;
3231     if (opcode[i]==0x28) x=3; // SB
3232     if (opcode[i]==0x29) x=2; // SH
3233     map=get_reg(i_regs->regmap,TLREG);
3234     assert(map>=0);
3235     reglist&=~(1<<map);
3236     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3237     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3238   }
3239
3240   if (opcode[i]==0x28) { // SB
3241     if(!c||memtarget) {
3242       int x=0,a=temp;
3243 #ifdef BIG_ENDIAN_MIPS
3244       if(!c) emit_xorimm(addr,3,temp);
3245       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3246 #else
3247       if(!c) a=addr;
3248 #endif
3249       if(faststore_reg_override) a=faststore_reg_override;
3250       //gen_tlb_addr_w(temp,map);
3251       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3252       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3253     }
3254     type=STOREB_STUB;
3255   }
3256   if (opcode[i]==0x29) { // SH
3257     if(!c||memtarget) {
3258       int x=0,a=temp;
3259 #ifdef BIG_ENDIAN_MIPS
3260       if(!c) emit_xorimm(addr,2,temp);
3261       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3262 #else
3263       if(!c) a=addr;
3264 #endif
3265       if(faststore_reg_override) a=faststore_reg_override;
3266       //#ifdef
3267       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3268       //#else
3269       if(map>=0) {
3270         gen_tlb_addr_w(a,map);
3271         emit_writehword_indexed(tl,x,a);
3272       }else
3273         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3274     }
3275     type=STOREH_STUB;
3276   }
3277   if (opcode[i]==0x2B) { // SW
3278     if(!c||memtarget) {
3279       int a=addr;
3280       if(faststore_reg_override) a=faststore_reg_override;
3281       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3282       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3283     }
3284     type=STOREW_STUB;
3285   }
3286   if (opcode[i]==0x3F) { // SD
3287     if(!c||memtarget) {
3288       int a=addr;
3289       if(faststore_reg_override) a=faststore_reg_override;
3290       if(rs2[i]) {
3291         assert(th>=0);
3292         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3293         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3294         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3295       }else{
3296         // Store zero
3297         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3298         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3299         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3300       }
3301     }
3302     type=STORED_STUB;
3303   }
3304 #ifdef PCSX
3305   if(jaddr) {
3306     // PCSX store handlers don't check invcode again
3307     reglist|=1<<addr;
3308     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3309     jaddr=0;
3310   }
3311 #endif
3312   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3313     if(!c||memtarget) {
3314       #ifdef DESTRUCTIVE_SHIFT
3315       // The x86 shift operation is 'destructive'; it overwrites the
3316       // source register, so we need to make a copy first and use that.
3317       addr=temp;
3318       #endif
3319       #if defined(HOST_IMM8)
3320       int ir=get_reg(i_regs->regmap,INVCP);
3321       assert(ir>=0);
3322       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3323       #else
3324       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3325       #endif
3326       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3327       emit_callne(invalidate_addr_reg[addr]);
3328       #else
3329       jaddr2=(int)out;
3330       emit_jne(0);
3331       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3332       #endif
3333     }
3334   }
3335   if(jaddr) {
3336     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3337   } else if(c&&!memtarget) {
3338     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3339   }
3340   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3341   //if(opcode[i]==0x2B || opcode[i]==0x28)
3342   //if(opcode[i]==0x2B || opcode[i]==0x29)
3343   //if(opcode[i]==0x2B)
3344   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3345   {
3346     #ifdef __i386__
3347     emit_pusha();
3348     #endif
3349     #ifdef __arm__
3350     save_regs(0x100f);
3351     #endif
3352         emit_readword((int)&last_count,ECX);
3353         #ifdef __i386__
3354         if(get_reg(i_regs->regmap,CCREG)<0)
3355           emit_loadreg(CCREG,HOST_CCREG);
3356         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3357         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3358         emit_writeword(HOST_CCREG,(int)&Count);
3359         #endif
3360         #ifdef __arm__
3361         if(get_reg(i_regs->regmap,CCREG)<0)
3362           emit_loadreg(CCREG,0);
3363         else
3364           emit_mov(HOST_CCREG,0);
3365         emit_add(0,ECX,0);
3366         emit_addimm(0,2*ccadj[i],0);
3367         emit_writeword(0,(int)&Count);
3368         #endif
3369     emit_call((int)memdebug);
3370     #ifdef __i386__
3371     emit_popa();
3372     #endif
3373     #ifdef __arm__
3374     restore_regs(0x100f);
3375     #endif