libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2010 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24
  25 #include "emu_if.h" //emulator interface
  26
  27 #include <sys/mman.h>
  28
  29 #ifdef __i386__
  30 #include "assem_x86.h"
  31 #endif
  32 #ifdef __x86_64__
  33 #include "assem_x64.h"
  34 #endif
  35 #ifdef __arm__
  36 #include "assem_arm.h"
  37 #endif
  38
  39 #define MAXBLOCK 4096
  40 #define MAX_OUTPUT_BLOCK_SIZE 262144
  41 #define CLOCK_DIVIDER 2
  42
  43 struct regstat
  44 {
  45   signed char regmap_entry[HOST_REGS];
  46   signed char regmap[HOST_REGS];
  47   uint64_t was32;
  48   uint64_t is32;
  49   uint64_t wasdirty;
  50   uint64_t dirty;
  51   uint64_t u;
  52   uint64_t uu;
  53   u_int wasconst;
  54   u_int isconst;
  55   uint64_t constmap[HOST_REGS];
  56 };
  57
  58 struct ll_entry
  59 {
  60   u_int vaddr;
  61   u_int reg32;
  62   void *addr;
  63   struct ll_entry *next;
  64 };
  65
  66   u_int start;
  67   u_int *source;
  68   u_int pagelimit;
  69   char insn[MAXBLOCK][10];
  70   u_char itype[MAXBLOCK];
  71   u_char opcode[MAXBLOCK];
  72   u_char opcode2[MAXBLOCK];
  73   u_char bt[MAXBLOCK];
  74   u_char rs1[MAXBLOCK];
  75   u_char rs2[MAXBLOCK];
  76   u_char rt1[MAXBLOCK];
  77   u_char rt2[MAXBLOCK];
  78   u_char us1[MAXBLOCK];
  79   u_char us2[MAXBLOCK];
  80   u_char dep1[MAXBLOCK];
  81   u_char dep2[MAXBLOCK];
  82   u_char lt1[MAXBLOCK];
  83   int imm[MAXBLOCK];
  84   u_int ba[MAXBLOCK];
  85   char likely[MAXBLOCK];
  86   char is_ds[MAXBLOCK];
  87   char ooo[MAXBLOCK];
  88   uint64_t unneeded_reg[MAXBLOCK];
  89   uint64_t unneeded_reg_upper[MAXBLOCK];
  90   uint64_t branch_unneeded_reg[MAXBLOCK];
  91   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
  92   uint64_t p32[MAXBLOCK];
  93   uint64_t pr32[MAXBLOCK];
  94   signed char regmap_pre[MAXBLOCK][HOST_REGS];
  95   signed char regmap[MAXBLOCK][HOST_REGS];
  96   signed char regmap_entry[MAXBLOCK][HOST_REGS];
  97   uint64_t constmap[MAXBLOCK][HOST_REGS];
  98   struct regstat regs[MAXBLOCK];
  99   struct regstat branch_regs[MAXBLOCK];
 100   signed char minimum_free_regs[MAXBLOCK];
 101   u_int needed_reg[MAXBLOCK];
 102   uint64_t requires_32bit[MAXBLOCK];
 103   u_int wont_dirty[MAXBLOCK];
 104   u_int will_dirty[MAXBLOCK];
 105   int ccadj[MAXBLOCK];
 106   int slen;
 107   u_int instr_addr[MAXBLOCK];
 108   u_int link_addr[MAXBLOCK][3];
 109   int linkcount;
 110   u_int stubs[MAXBLOCK*3][8];
 111   int stubcount;
 112   u_int literals[1024][2];
 113   int literalcount;
 114   int is_delayslot;
 115   int cop1_usable;
 116   u_char *out;
 117   struct ll_entry *jump_in[4096];
 118   struct ll_entry *jump_out[4096];
 119   struct ll_entry *jump_dirty[4096];
 120   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 121   char shadow[1048576]  __attribute__((aligned(16)));
 122   void *copy;
 123   int expirep;
 124   u_int using_tlb;
 125   u_int stop_after_jal;
 126   extern u_char restore_candidate[512];
 127   extern int cycle_count;
 128
 129   /* registers that may be allocated */
 130   /* 1-31 gpr */
 131 #define HIREG 32 // hi
 132 #define LOREG 33 // lo
 133 #define FSREG 34 // FPU status (FCSR)
 134 #define CSREG 35 // Coprocessor status
 135 #define CCREG 36 // Cycle count
 136 #define INVCP 37 // Pointer to invalid_code
 137 #define TEMPREG 38
 138 #define FTEMP 38 // FPU/LDL/LDR temporary register
 139 #define PTEMP 39 // Prefetch temporary register
 140 #define TLREG 40 // TLB mapping offset
 141 #define RHASH 41 // Return address hash
 142 #define RHTBL 42 // Return address hash table address
 143 #define RTEMP 43 // JR/JALR address register
 144 #define MAXREG 43
 145 #define AGEN1 44 // Address generation temporary register
 146 #define AGEN2 45 // Address generation temporary register
 147 #define MGEN1 46 // Maptable address generation temporary register
 148 #define MGEN2 47 // Maptable address generation temporary register
 149 #define BTREG 48 // Branch target temporary register
 150
 151   /* instruction types */
 152 #define NOP 0     // No operation
 153 #define LOAD 1    // Load
 154 #define STORE 2   // Store
 155 #define LOADLR 3  // Unaligned load
 156 #define STORELR 4 // Unaligned store
 157 #define MOV 5     // Move
 158 #define ALU 6     // Arithmetic/logic
 159 #define MULTDIV 7 // Multiply/divide
 160 #define SHIFT 8   // Shift by register
 161 #define SHIFTIMM 9// Shift by immediate
 162 #define IMM16 10  // 16-bit immediate
 163 #define RJUMP 11  // Unconditional jump to register
 164 #define UJUMP 12  // Unconditional jump
 165 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 166 #define SJUMP 14  // Conditional branch (regimm format)
 167 #define COP0 15   // Coprocessor 0
 168 #define COP1 16   // Coprocessor 1
 169 #define C1LS 17   // Coprocessor 1 load/store
 170 #define FJUMP 18  // Conditional branch (floating point)
 171 #define FLOAT 19  // Floating point unit
 172 #define FCONV 20  // Convert integer to float
 173 #define FCOMP 21  // Floating point compare (sets FSREG)
 174 #define SYSCALL 22// SYSCALL
 175 #define OTHER 23  // Other
 176 #define SPAN 24   // Branch/delay slot spans 2 pages
 177 #define NI 25     // Not implemented
 178 #define HLECALL 26// PCSX fake opcodes for HLE
 179 #define COP2 27   // Coprocessor 2 move
 180 #define C2LS 28   // Coprocessor 2 load/store
 181 #define C2OP 29   // Coprocessor 2 operation
 182 #define INTCALL 30// Call interpreter to handle rare corner cases
 183
 184   /* stubs */
 185 #define CC_STUB 1
 186 #define FP_STUB 2
 187 #define LOADB_STUB 3
 188 #define LOADH_STUB 4
 189 #define LOADW_STUB 5
 190 #define LOADD_STUB 6
 191 #define LOADBU_STUB 7
 192 #define LOADHU_STUB 8
 193 #define STOREB_STUB 9
 194 #define STOREH_STUB 10
 195 #define STOREW_STUB 11
 196 #define STORED_STUB 12
 197 #define STORELR_STUB 13
 198 #define INVCODE_STUB 14
 199
 200   /* branch codes */
 201 #define TAKEN 1
 202 #define NOTTAKEN 2
 203 #define NULLDS 3
 204
 205 // asm linkage
 206 int new_recompile_block(int addr);
 207 void *get_addr_ht(u_int vaddr);
 208 void invalidate_block(u_int block);
 209 void invalidate_addr(u_int addr);
 210 void remove_hash(int vaddr);
 211 void jump_vaddr();
 212 void dyna_linker();
 213 void dyna_linker_ds();
 214 void verify_code();
 215 void verify_code_vm();
 216 void verify_code_ds();
 217 void cc_interrupt();
 218 void fp_exception();
 219 void fp_exception_ds();
 220 void jump_syscall();
 221 void jump_syscall_hle();
 222 void jump_eret();
 223 void jump_hlecall();
 224 void jump_intcall();
 225 void new_dyna_leave();
 226
 227 // TLB
 228 void TLBWI_new();
 229 void TLBWR_new();
 230 void read_nomem_new();
 231 void read_nomemb_new();
 232 void read_nomemh_new();
 233 void read_nomemd_new();
 234 void write_nomem_new();
 235 void write_nomemb_new();
 236 void write_nomemh_new();
 237 void write_nomemd_new();
 238 void write_rdram_new();
 239 void write_rdramb_new();
 240 void write_rdramh_new();
 241 void write_rdramd_new();
 242 extern u_int memory_map[1048576];
 243
 244 // Needed by assembler
 245 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 246 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 247 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 248 void load_all_regs(signed char i_regmap[]);
 249 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 250 void load_regs_entry(int t);
 251 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 252
 253 int tracedebug=0;
 254
 255 //#define DEBUG_CYCLE_COUNT 1
 256
 257 void nullf() {}
 258 //#define assem_debug printf
 259 //#define inv_debug printf
 260 #define assem_debug nullf
 261 #define inv_debug nullf
 262
 263 static void tlb_hacks()
 264 {
 265 #ifndef DISABLE_TLB
 266   // Goldeneye hack
 267   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 268   {
 269     u_int addr;
 270     int n;
 271     switch (ROM_HEADER->Country_code&0xFF)
 272     {
 273       case 0x45: // U
 274         addr=0x34b30;
 275         break;
 276       case 0x4A: // J
 277         addr=0x34b70;
 278         break;
 279       case 0x50: // E
 280         addr=0x329f0;
 281         break;
 282       default:
 283         // Unknown country code
 284         addr=0;
 285         break;
 286     }
 287     u_int rom_addr=(u_int)rom;
 288     #ifdef ROM_COPY
 289     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 290     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 291     if((void *)rom>(void *)0xffffffff) {
 292       munmap(ROM_COPY, 67108864);
 293       if(mmap(ROM_COPY, 12582912,
 294               PROT_READ | PROT_WRITE,
 295               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 296               -1, 0) <= 0) {printf("mmap() failed\n");}
 297       memcpy(ROM_COPY,rom,12582912);
 298       rom_addr=(u_int)ROM_COPY;
 299     }
 300     #endif
 301     if(addr) {
 302       for(n=0x7F000;n<0x80000;n++) {
 303         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 304       }
 305     }
 306   }
 307 #endif
 308 }
 309
 310 static u_int get_page(u_int vaddr)
 311 {
 312 #ifndef PCSX
 313   u_int page=(vaddr^0x80000000)>>12;
 314 #else
 315   u_int page=vaddr&~0xe0000000;
 316   if (page < 0x1000000)
 317     page &= ~0x0e00000; // RAM mirrors
 318   page>>=12;
 319 #endif
 320 #ifndef DISABLE_TLB
 321   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 322 #endif
 323   if(page>2048) page=2048+(page&2047);
 324   return page;
 325 }
 326
 327 static u_int get_vpage(u_int vaddr)
 328 {
 329   u_int vpage=(vaddr^0x80000000)>>12;
 330 #ifndef DISABLE_TLB
 331   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 332 #endif
 333   if(vpage>2048) vpage=2048+(vpage&2047);
 334   return vpage;
 335 }
 336
 337 // Get address from virtual address
 338 // This is called from the recompiled JR/JALR instructions
 339 void *get_addr(u_int vaddr)
 340 {
 341   u_int page=get_page(vaddr);
 342   u_int vpage=get_vpage(vaddr);
 343   struct ll_entry *head;
 344   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 345   head=jump_in[page];
 346   while(head!=NULL) {
 347     if(head->vaddr==vaddr&&head->reg32==0) {
 348   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 349       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 350       ht_bin[3]=ht_bin[1];
 351       ht_bin[2]=ht_bin[0];
 352       ht_bin[1]=(int)head->addr;
 353       ht_bin[0]=vaddr;
 354       return head->addr;
 355     }
 356     head=head->next;
 357   }
 358   head=jump_dirty[vpage];
 359   while(head!=NULL) {
 360     if(head->vaddr==vaddr&&head->reg32==0) {
 361       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 362       // Don't restore blocks which are about to expire from the cache
 363       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 364       if(verify_dirty(head->addr)) {
 365         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 366         invalid_code[vaddr>>12]=0;
 367         memory_map[vaddr>>12]|=0x40000000;
 368         if(vpage<2048) {
 369 #ifndef DISABLE_TLB
 370           if(tlb_LUT_r[vaddr>>12]) {
 371             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 372             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 373           }
 374 #endif
 375           restore_candidate[vpage>>3]|=1<<(vpage&7);
 376         }
 377         else restore_candidate[page>>3]|=1<<(page&7);
 378         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 379         if(ht_bin[0]==vaddr) {
 380           ht_bin[1]=(int)head->addr; // Replace existing entry
 381         }
 382         else
 383         {
 384           ht_bin[3]=ht_bin[1];
 385           ht_bin[2]=ht_bin[0];
 386           ht_bin[1]=(int)head->addr;
 387           ht_bin[0]=vaddr;
 388         }
 389         return head->addr;
 390       }
 391     }
 392     head=head->next;
 393   }
 394   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 395   int r=new_recompile_block(vaddr);
 396   if(r==0) return get_addr(vaddr);
 397   // Execute in unmapped page, generate pagefault execption
 398   Status|=2;
 399   Cause=(vaddr<<31)|0x8;
 400   EPC=(vaddr&1)?vaddr-5:vaddr;
 401   BadVAddr=(vaddr&~1);
 402   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 403   EntryHi=BadVAddr&0xFFFFE000;
 404   return get_addr_ht(0x80000000);
 405 }
 406 // Look up address in hash table first
 407 void *get_addr_ht(u_int vaddr)
 408 {
 409   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 410   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 411   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 412   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 413   return get_addr(vaddr);
 414 }
 415
 416 void *get_addr_32(u_int vaddr,u_int flags)
 417 {
 418 #ifdef FORCE32
 419   return get_addr(vaddr);
 420 #else
 421   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 422   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 423   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 424   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 425   u_int page=get_page(vaddr);
 426   u_int vpage=get_vpage(vaddr);
 427   struct ll_entry *head;
 428   head=jump_in[page];
 429   while(head!=NULL) {
 430     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 431       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 432       if(head->reg32==0) {
 433         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 434         if(ht_bin[0]==-1) {
 435           ht_bin[1]=(int)head->addr;
 436           ht_bin[0]=vaddr;
 437         }else if(ht_bin[2]==-1) {
 438           ht_bin[3]=(int)head->addr;
 439           ht_bin[2]=vaddr;
 440         }
 441         //ht_bin[3]=ht_bin[1];
 442         //ht_bin[2]=ht_bin[0];
 443         //ht_bin[1]=(int)head->addr;
 444         //ht_bin[0]=vaddr;
 445       }
 446       return head->addr;
 447     }
 448     head=head->next;
 449   }
 450   head=jump_dirty[vpage];
 451   while(head!=NULL) {
 452     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 453       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 454       // Don't restore blocks which are about to expire from the cache
 455       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 456       if(verify_dirty(head->addr)) {
 457         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 458         invalid_code[vaddr>>12]=0;
 459         memory_map[vaddr>>12]|=0x40000000;
 460         if(vpage<2048) {
 461 #ifndef DISABLE_TLB
 462           if(tlb_LUT_r[vaddr>>12]) {
 463             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 464             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 465           }
 466 #endif
 467           restore_candidate[vpage>>3]|=1<<(vpage&7);
 468         }
 469         else restore_candidate[page>>3]|=1<<(page&7);
 470         if(head->reg32==0) {
 471           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 472           if(ht_bin[0]==-1) {
 473             ht_bin[1]=(int)head->addr;
 474             ht_bin[0]=vaddr;
 475           }else if(ht_bin[2]==-1) {
 476             ht_bin[3]=(int)head->addr;
 477             ht_bin[2]=vaddr;
 478           }
 479           //ht_bin[3]=ht_bin[1];
 480           //ht_bin[2]=ht_bin[0];
 481           //ht_bin[1]=(int)head->addr;
 482           //ht_bin[0]=vaddr;
 483         }
 484         return head->addr;
 485       }
 486     }
 487     head=head->next;
 488   }
 489   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 490   int r=new_recompile_block(vaddr);
 491   if(r==0) return get_addr(vaddr);
 492   // Execute in unmapped page, generate pagefault execption
 493   Status|=2;
 494   Cause=(vaddr<<31)|0x8;
 495   EPC=(vaddr&1)?vaddr-5:vaddr;
 496   BadVAddr=(vaddr&~1);
 497   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 498   EntryHi=BadVAddr&0xFFFFE000;
 499   return get_addr_ht(0x80000000);
 500 #endif
 501 }
 502
 503 void clear_all_regs(signed char regmap[])
 504 {
 505   int hr;
 506   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 507 }
 508
 509 signed char get_reg(signed char regmap[],int r)
 510 {
 511   int hr;
 512   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 513   return -1;
 514 }
 515
 516 // Find a register that is available for two consecutive cycles
 517 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 518 {
 519   int hr;
 520   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 521   return -1;
 522 }
 523
 524 int count_free_regs(signed char regmap[])
 525 {
 526   int count=0;
 527   int hr;
 528   for(hr=0;hr<HOST_REGS;hr++)
 529   {
 530     if(hr!=EXCLUDE_REG) {
 531       if(regmap[hr]<0) count++;
 532     }
 533   }
 534   return count;
 535 }
 536
 537 void dirty_reg(struct regstat *cur,signed char reg)
 538 {
 539   int hr;
 540   if(!reg) return;
 541   for (hr=0;hr<HOST_REGS;hr++) {
 542     if((cur->regmap[hr]&63)==reg) {
 543       cur->dirty|=1<<hr;
 544     }
 545   }
 546 }
 547
 548 // If we dirty the lower half of a 64 bit register which is now being
 549 // sign-extended, we need to dump the upper half.
 550 // Note: Do this only after completion of the instruction, because
 551 // some instructions may need to read the full 64-bit value even if
 552 // overwriting it (eg SLTI, DSRA32).
 553 static void flush_dirty_uppers(struct regstat *cur)
 554 {
 555   int hr,reg;
 556   for (hr=0;hr<HOST_REGS;hr++) {
 557     if((cur->dirty>>hr)&1) {
 558       reg=cur->regmap[hr];
 559       if(reg>=64)
 560         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 561     }
 562   }
 563 }
 564
 565 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 566 {
 567   int hr;
 568   if(!reg) return;
 569   for (hr=0;hr<HOST_REGS;hr++) {
 570     if(cur->regmap[hr]==reg) {
 571       cur->isconst|=1<<hr;
 572       cur->constmap[hr]=value;
 573     }
 574     else if((cur->regmap[hr]^64)==reg) {
 575       cur->isconst|=1<<hr;
 576       cur->constmap[hr]=value>>32;
 577     }
 578   }
 579 }
 580
 581 void clear_const(struct regstat *cur,signed char reg)
 582 {
 583   int hr;
 584   if(!reg) return;
 585   for (hr=0;hr<HOST_REGS;hr++) {
 586     if((cur->regmap[hr]&63)==reg) {
 587       cur->isconst&=~(1<<hr);
 588     }
 589   }
 590 }
 591
 592 int is_const(struct regstat *cur,signed char reg)
 593 {
 594   int hr;
 595   if(!reg) return 1;
 596   for (hr=0;hr<HOST_REGS;hr++) {
 597     if((cur->regmap[hr]&63)==reg) {
 598       return (cur->isconst>>hr)&1;
 599     }
 600   }
 601   return 0;
 602 }
 603 uint64_t get_const(struct regstat *cur,signed char reg)
 604 {
 605   int hr;
 606   if(!reg) return 0;
 607   for (hr=0;hr<HOST_REGS;hr++) {
 608     if(cur->regmap[hr]==reg) {
 609       return cur->constmap[hr];
 610     }
 611   }
 612   printf("Unknown constant in r%d\n",reg);
 613   exit(1);
 614 }
 615
 616 // Least soon needed registers
 617 // Look at the next ten instructions and see which registers
 618 // will be used.  Try not to reallocate these.
 619 void lsn(u_char hsn[], int i, int *preferred_reg)
 620 {
 621   int j;
 622   int b=-1;
 623   for(j=0;j<9;j++)
 624   {
 625     if(i+j>=slen) {
 626       j=slen-i-1;
 627       break;
 628     }
 629     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 630     {
 631       // Don't go past an unconditonal jump
 632       j++;
 633       break;
 634     }
 635   }
 636   for(;j>=0;j--)
 637   {
 638     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 639     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 640     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 641     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 642     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 643       // Stores can allocate zero
 644       hsn[rs1[i+j]]=j;
 645       hsn[rs2[i+j]]=j;
 646     }
 647     // On some architectures stores need invc_ptr
 648     #if defined(HOST_IMM8)
 649     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 650       hsn[INVCP]=j;
 651     }
 652     #endif
 653     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 654     {
 655       hsn[CCREG]=j;
 656       b=j;
 657     }
 658   }
 659   if(b>=0)
 660   {
 661     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 662     {
 663       // Follow first branch
 664       int t=(ba[i+b]-start)>>2;
 665       j=7-b;if(t+j>=slen) j=slen-t-1;
 666       for(;j>=0;j--)
 667       {
 668         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 669         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 670         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 671         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 672       }
 673     }
 674     // TODO: preferred register based on backward branch
 675   }
 676   // Delay slot should preferably not overwrite branch conditions or cycle count
 677   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 678     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 679     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 680     hsn[CCREG]=1;
 681     // ...or hash tables
 682     hsn[RHASH]=1;
 683     hsn[RHTBL]=1;
 684   }
 685   // Coprocessor load/store needs FTEMP, even if not declared
 686   if(itype[i]==C1LS||itype[i]==C2LS) {
 687     hsn[FTEMP]=0;
 688   }
 689   // Load L/R also uses FTEMP as a temporary register
 690   if(itype[i]==LOADLR) {
 691     hsn[FTEMP]=0;
 692   }
 693   // Also SWL/SWR/SDL/SDR
 694   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 695     hsn[FTEMP]=0;
 696   }
 697   // Don't remove the TLB registers either
 698   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 699     hsn[TLREG]=0;
 700   }
 701   // Don't remove the miniht registers
 702   if(itype[i]==UJUMP||itype[i]==RJUMP)
 703   {
 704     hsn[RHASH]=0;
 705     hsn[RHTBL]=0;
 706   }
 707 }
 708
 709 // We only want to allocate registers if we're going to use them again soon
 710 int needed_again(int r, int i)
 711 {
 712   int j;
 713   int b=-1;
 714   int rn=10;
 715   int hr;
 716   u_char hsn[MAXREG+1];
 717   int preferred_reg;
 718
 719   memset(hsn,10,sizeof(hsn));
 720   lsn(hsn,i,&preferred_reg);
 721
 722   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 723   {
 724     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 725       return 0; // Don't need any registers if exiting the block
 726   }
 727   for(j=0;j<9;j++)
 728   {
 729     if(i+j>=slen) {
 730       j=slen-i-1;
 731       break;
 732     }
 733     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 734     {
 735       // Don't go past an unconditonal jump
 736       j++;
 737       break;
 738     }
 739     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 740     {
 741       break;
 742     }
 743   }
 744   for(;j>=1;j--)
 745   {
 746     if(rs1[i+j]==r) rn=j;
 747     if(rs2[i+j]==r) rn=j;
 748     if((unneeded_reg[i+j]>>r)&1) rn=10;
 749     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 750     {
 751       b=j;
 752     }
 753   }
 754   /*
 755   if(b>=0)
 756   {
 757     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 758     {
 759       // Follow first branch
 760       int o=rn;
 761       int t=(ba[i+b]-start)>>2;
 762       j=7-b;if(t+j>=slen) j=slen-t-1;
 763       for(;j>=0;j--)
 764       {
 765         if(!((unneeded_reg[t+j]>>r)&1)) {
 766           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 767           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 768         }
 769         else rn=o;
 770       }
 771     }
 772   }*/
 773   for(hr=0;hr<HOST_REGS;hr++) {
 774     if(hr!=EXCLUDE_REG) {
 775       if(rn<hsn[hr]) return 1;
 776     }
 777   }
 778   return 0;
 779 }
 780
 781 // Try to match register allocations at the end of a loop with those
 782 // at the beginning
 783 int loop_reg(int i, int r, int hr)
 784 {
 785   int j,k;
 786   for(j=0;j<9;j++)
 787   {
 788     if(i+j>=slen) {
 789       j=slen-i-1;
 790       break;
 791     }
 792     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 793     {
 794       // Don't go past an unconditonal jump
 795       j++;
 796       break;
 797     }
 798   }
 799   k=0;
 800   if(i>0){
 801     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 802       k--;
 803   }
 804   for(;k<j;k++)
 805   {
 806     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 807     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 808     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 809     {
 810       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 811       {
 812         int t=(ba[i+k]-start)>>2;
 813         int reg=get_reg(regs[t].regmap_entry,r);
 814         if(reg>=0) return reg;
 815         //reg=get_reg(regs[t+1].regmap_entry,r);
 816         //if(reg>=0) return reg;
 817       }
 818     }
 819   }
 820   return hr;
 821 }
 822
 823
 824 // Allocate every register, preserving source/target regs
 825 void alloc_all(struct regstat *cur,int i)
 826 {
 827   int hr;
 828
 829   for(hr=0;hr<HOST_REGS;hr++) {
 830     if(hr!=EXCLUDE_REG) {
 831       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 832          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 833       {
 834         cur->regmap[hr]=-1;
 835         cur->dirty&=~(1<<hr);
 836       }
 837       // Don't need zeros
 838       if((cur->regmap[hr]&63)==0)
 839       {
 840         cur->regmap[hr]=-1;
 841         cur->dirty&=~(1<<hr);
 842       }
 843     }
 844   }
 845 }
 846
 847
 848 void div64(int64_t dividend,int64_t divisor)
 849 {
 850   lo=dividend/divisor;
 851   hi=dividend%divisor;
 852   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 853   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 854 }
 855 void divu64(uint64_t dividend,uint64_t divisor)
 856 {
 857   lo=dividend/divisor;
 858   hi=dividend%divisor;
 859   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 860   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 861 }
 862
 863 void mult64(uint64_t m1,uint64_t m2)
 864 {
 865    unsigned long long int op1, op2, op3, op4;
 866    unsigned long long int result1, result2, result3, result4;
 867    unsigned long long int temp1, temp2, temp3, temp4;
 868    int sign = 0;
 869
 870    if (m1 < 0)
 871      {
 872     op2 = -m1;
 873     sign = 1 - sign;
 874      }
 875    else op2 = m1;
 876    if (m2 < 0)
 877      {
 878     op4 = -m2;
 879     sign = 1 - sign;
 880      }
 881    else op4 = m2;
 882
 883    op1 = op2 & 0xFFFFFFFF;
 884    op2 = (op2 >> 32) & 0xFFFFFFFF;
 885    op3 = op4 & 0xFFFFFFFF;
 886    op4 = (op4 >> 32) & 0xFFFFFFFF;
 887
 888    temp1 = op1 * op3;
 889    temp2 = (temp1 >> 32) + op1 * op4;
 890    temp3 = op2 * op3;
 891    temp4 = (temp3 >> 32) + op2 * op4;
 892
 893    result1 = temp1 & 0xFFFFFFFF;
 894    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 895    result3 = (result2 >> 32) + temp4;
 896    result4 = (result3 >> 32);
 897
 898    lo = result1 | (result2 << 32);
 899    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 900    if (sign)
 901      {
 902     hi = ~hi;
 903     if (!lo) hi++;
 904     else lo = ~lo + 1;
 905      }
 906 }
 907
 908 void multu64(uint64_t m1,uint64_t m2)
 909 {
 910    unsigned long long int op1, op2, op3, op4;
 911    unsigned long long int result1, result2, result3, result4;
 912    unsigned long long int temp1, temp2, temp3, temp4;
 913
 914    op1 = m1 & 0xFFFFFFFF;
 915    op2 = (m1 >> 32) & 0xFFFFFFFF;
 916    op3 = m2 & 0xFFFFFFFF;
 917    op4 = (m2 >> 32) & 0xFFFFFFFF;
 918
 919    temp1 = op1 * op3;
 920    temp2 = (temp1 >> 32) + op1 * op4;
 921    temp3 = op2 * op3;
 922    temp4 = (temp3 >> 32) + op2 * op4;
 923
 924    result1 = temp1 & 0xFFFFFFFF;
 925    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 926    result3 = (result2 >> 32) + temp4;
 927    result4 = (result3 >> 32);
 928
 929    lo = result1 | (result2 << 32);
 930    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 931
 932   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 933   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 934 }
 935
 936 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 937 {
 938   if(bits) {
 939     original<<=64-bits;
 940     original>>=64-bits;
 941     loaded<<=bits;
 942     original|=loaded;
 943   }
 944   else original=loaded;
 945   return original;
 946 }
 947 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 948 {
 949   if(bits^56) {
 950     original>>=64-(bits^56);
 951     original<<=64-(bits^56);
 952     loaded>>=bits^56;
 953     original|=loaded;
 954   }
 955   else original=loaded;
 956   return original;
 957 }
 958
 959 #ifdef __i386__
 960 #include "assem_x86.c"
 961 #endif
 962 #ifdef __x86_64__
 963 #include "assem_x64.c"
 964 #endif
 965 #ifdef __arm__
 966 #include "assem_arm.c"
 967 #endif
 968
 969 // Add virtual address mapping to linked list
 970 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 971 {
 972   struct ll_entry *new_entry;
 973   new_entry=malloc(sizeof(struct ll_entry));
 974   assert(new_entry!=NULL);
 975   new_entry->vaddr=vaddr;
 976   new_entry->reg32=0;
 977   new_entry->addr=addr;
 978   new_entry->next=*head;
 979   *head=new_entry;
 980 }
 981
 982 // Add virtual address mapping for 32-bit compiled block
 983 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 984 {
 985   ll_add(head,vaddr,addr);
 986 #ifndef FORCE32
 987   (*head)->reg32=reg32;
 988 #endif
 989 }
 990
 991 // Check if an address is already compiled
 992 // but don't return addresses which are about to expire from the cache
 993 void *check_addr(u_int vaddr)
 994 {
 995   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 996   if(ht_bin[0]==vaddr) {
 997     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 998       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
 999   }
1000   if(ht_bin[2]==vaddr) {
1001     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1002       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1003   }
1004   u_int page=get_page(vaddr);
1005   struct ll_entry *head;
1006   head=jump_in[page];
1007   while(head!=NULL) {
1008     if(head->vaddr==vaddr&&head->reg32==0) {
1009       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1010         // Update existing entry with current address
1011         if(ht_bin[0]==vaddr) {
1012           ht_bin[1]=(int)head->addr;
1013           return head->addr;
1014         }
1015         if(ht_bin[2]==vaddr) {
1016           ht_bin[3]=(int)head->addr;
1017           return head->addr;
1018         }
1019         // Insert into hash table with low priority.
1020         // Don't evict existing entries, as they are probably
1021         // addresses that are being accessed frequently.
1022         if(ht_bin[0]==-1) {
1023           ht_bin[1]=(int)head->addr;
1024           ht_bin[0]=vaddr;
1025         }else if(ht_bin[2]==-1) {
1026           ht_bin[3]=(int)head->addr;
1027           ht_bin[2]=vaddr;
1028         }
1029         return head->addr;
1030       }
1031     }
1032     head=head->next;
1033   }
1034   return 0;
1035 }
1036
1037 void remove_hash(int vaddr)
1038 {
1039   //printf("remove hash: %x\n",vaddr);
1040   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1041   if(ht_bin[2]==vaddr) {
1042     ht_bin[2]=ht_bin[3]=-1;
1043   }
1044   if(ht_bin[0]==vaddr) {
1045     ht_bin[0]=ht_bin[2];
1046     ht_bin[1]=ht_bin[3];
1047     ht_bin[2]=ht_bin[3]=-1;
1048   }
1049 }
1050
1051 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1052 {
1053   struct ll_entry *next;
1054   while(*head) {
1055     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1056        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1057     {
1058       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1059       remove_hash((*head)->vaddr);
1060       next=(*head)->next;
1061       free(*head);
1062       *head=next;
1063     }
1064     else
1065     {
1066       head=&((*head)->next);
1067     }
1068   }
1069 }
1070
1071 // Remove all entries from linked list
1072 void ll_clear(struct ll_entry **head)
1073 {
1074   struct ll_entry *cur;
1075   struct ll_entry *next;
1076   if(cur=*head) {
1077     *head=0;
1078     while(cur) {
1079       next=cur->next;
1080       free(cur);
1081       cur=next;
1082     }
1083   }
1084 }
1085
1086 // Dereference the pointers and remove if it matches
1087 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1088 {
1089   while(head) {
1090     int ptr=get_pointer(head->addr);
1091     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1092     if(((ptr>>shift)==(addr>>shift)) ||
1093        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1094     {
1095       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1096       u_int host_addr=(u_int)kill_pointer(head->addr);
1097       #ifdef __arm__
1098         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1099       #endif
1100     }
1101     head=head->next;
1102   }
1103 }
1104
1105 // This is called when we write to a compiled block (see do_invstub)
1106 void invalidate_page(u_int page)
1107 {
1108   struct ll_entry *head;
1109   struct ll_entry *next;
1110   head=jump_in[page];
1111   jump_in[page]=0;
1112   while(head!=NULL) {
1113     inv_debug("INVALIDATE: %x\n",head->vaddr);
1114     remove_hash(head->vaddr);
1115     next=head->next;
1116     free(head);
1117     head=next;
1118   }
1119   head=jump_out[page];
1120   jump_out[page]=0;
1121   while(head!=NULL) {
1122     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1123     u_int host_addr=(u_int)kill_pointer(head->addr);
1124     #ifdef __arm__
1125       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1126     #endif
1127     next=head->next;
1128     free(head);
1129     head=next;
1130   }
1131 }
1132 void invalidate_block(u_int block)
1133 {
1134   u_int page=get_page(block<<12);
1135   u_int vpage=get_vpage(block<<12);
1136   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1137   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1138   u_int first,last;
1139   first=last=page;
1140   struct ll_entry *head;
1141   head=jump_dirty[vpage];
1142   //printf("page=%d vpage=%d\n",page,vpage);
1143   while(head!=NULL) {
1144     u_int start,end;
1145     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1146       get_bounds((int)head->addr,&start,&end);
1147       //printf("start: %x end: %x\n",start,end);
1148       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1149         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1150           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1151           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1152         }
1153       }
1154 #ifndef DISABLE_TLB
1155       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1156         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1157           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1158           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1159         }
1160       }
1161 #endif
1162     }
1163     head=head->next;
1164   }
1165   //printf("first=%d last=%d\n",first,last);
1166   invalidate_page(page);
1167   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1168   assert(last<page+5);
1169   // Invalidate the adjacent pages if a block crosses a 4K boundary
1170   while(first<page) {
1171     invalidate_page(first);
1172     first++;
1173   }
1174   for(first=page+1;first<last;first++) {
1175     invalidate_page(first);
1176   }
1177   #ifdef __arm__
1178     do_clear_cache();
1179   #endif
1180
1181   // Don't trap writes
1182   invalid_code[block]=1;
1183 #ifndef DISABLE_TLB
1184   // If there is a valid TLB entry for this page, remove write protect
1185   if(tlb_LUT_w[block]) {
1186     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1187     // CHECK: Is this right?
1188     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1189     u_int real_block=tlb_LUT_w[block]>>12;
1190     invalid_code[real_block]=1;
1191     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1192   }
1193   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1194 #endif
1195
1196   #ifdef USE_MINI_HT
1197   memset(mini_ht,-1,sizeof(mini_ht));
1198   #endif
1199 }
1200 void invalidate_addr(u_int addr)
1201 {
1202   invalidate_block(addr>>12);
1203 }
1204 // This is called when loading a save state.
1205 // Anything could have changed, so invalidate everything.
1206 void invalidate_all_pages()
1207 {
1208   u_int page,n;
1209   for(page=0;page<4096;page++)
1210     invalidate_page(page);
1211   for(page=0;page<1048576;page++)
1212     if(!invalid_code[page]) {
1213       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1214       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1215     }
1216   #ifdef __arm__
1217   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1218   #endif
1219   #ifdef USE_MINI_HT
1220   memset(mini_ht,-1,sizeof(mini_ht));
1221   #endif
1222   #ifndef DISABLE_TLB
1223   // TLB
1224   for(page=0;page<0x100000;page++) {
1225     if(tlb_LUT_r[page]) {
1226       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1227       if(!tlb_LUT_w[page]||!invalid_code[page])
1228         memory_map[page]|=0x40000000; // Write protect
1229     }
1230     else memory_map[page]=-1;
1231     if(page==0x80000) page=0xC0000;
1232   }
1233   tlb_hacks();
1234   #endif
1235 }
1236
1237 // Add an entry to jump_out after making a link
1238 void add_link(u_int vaddr,void *src)
1239 {
1240   u_int page=get_page(vaddr);
1241   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1242   ll_add(jump_out+page,vaddr,src);
1243   //int ptr=get_pointer(src);
1244   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1245 }
1246
1247 // If a code block was found to be unmodified (bit was set in
1248 // restore_candidate) and it remains unmodified (bit is clear
1249 // in invalid_code) then move the entries for that 4K page from
1250 // the dirty list to the clean list.
1251 void clean_blocks(u_int page)
1252 {
1253   struct ll_entry *head;
1254   inv_debug("INV: clean_blocks page=%d\n",page);
1255   head=jump_dirty[page];
1256   while(head!=NULL) {
1257     if(!invalid_code[head->vaddr>>12]) {
1258       // Don't restore blocks which are about to expire from the cache
1259       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1260         u_int start,end;
1261         if(verify_dirty((int)head->addr)) {
1262           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1263           u_int i;
1264           u_int inv=0;
1265           get_bounds((int)head->addr,&start,&end);
1266           if(start-(u_int)rdram<RAM_SIZE) {
1267             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1268               inv|=invalid_code[i];
1269             }
1270           }
1271           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1272             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1273             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1274             if(addr<start||addr>=end) inv=1;
1275           }
1276           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1277             inv=1;
1278           }
1279           if(!inv) {
1280             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1281             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1282               u_int ppage=page;
1283 #ifndef DISABLE_TLB
1284               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1285 #endif
1286               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1287               //printf("page=%x, addr=%x\n",page,head->vaddr);
1288               //assert(head->vaddr>>12==(page|0x80000));
1289               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1290               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1291               if(!head->reg32) {
1292                 if(ht_bin[0]==head->vaddr) {
1293                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1294                 }
1295                 if(ht_bin[2]==head->vaddr) {
1296                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1297                 }
1298               }
1299             }
1300           }
1301         }
1302       }
1303     }
1304     head=head->next;
1305   }
1306 }
1307
1308
1309 void mov_alloc(struct regstat *current,int i)
1310 {
1311   // Note: Don't need to actually alloc the source registers
1312   if((~current->is32>>rs1[i])&1) {
1313     //alloc_reg64(current,i,rs1[i]);
1314     alloc_reg64(current,i,rt1[i]);
1315     current->is32&=~(1LL<<rt1[i]);
1316   } else {
1317     //alloc_reg(current,i,rs1[i]);
1318     alloc_reg(current,i,rt1[i]);
1319     current->is32|=(1LL<<rt1[i]);
1320   }
1321   clear_const(current,rs1[i]);
1322   clear_const(current,rt1[i]);
1323   dirty_reg(current,rt1[i]);
1324 }
1325
1326 void shiftimm_alloc(struct regstat *current,int i)
1327 {
1328   clear_const(current,rs1[i]);
1329   clear_const(current,rt1[i]);
1330   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1331   {
1332     if(rt1[i]) {
1333       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1334       else lt1[i]=rs1[i];
1335       alloc_reg(current,i,rt1[i]);
1336       current->is32|=1LL<<rt1[i];
1337       dirty_reg(current,rt1[i]);
1338     }
1339   }
1340   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1341   {
1342     if(rt1[i]) {
1343       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1344       alloc_reg64(current,i,rt1[i]);
1345       current->is32&=~(1LL<<rt1[i]);
1346       dirty_reg(current,rt1[i]);
1347     }
1348   }
1349   if(opcode2[i]==0x3c) // DSLL32
1350   {
1351     if(rt1[i]) {
1352       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1353       alloc_reg64(current,i,rt1[i]);
1354       current->is32&=~(1LL<<rt1[i]);
1355       dirty_reg(current,rt1[i]);
1356     }
1357   }
1358   if(opcode2[i]==0x3e) // DSRL32
1359   {
1360     if(rt1[i]) {
1361       alloc_reg64(current,i,rs1[i]);
1362       if(imm[i]==32) {
1363         alloc_reg64(current,i,rt1[i]);
1364         current->is32&=~(1LL<<rt1[i]);
1365       } else {
1366         alloc_reg(current,i,rt1[i]);
1367         current->is32|=1LL<<rt1[i];
1368       }
1369       dirty_reg(current,rt1[i]);
1370     }
1371   }
1372   if(opcode2[i]==0x3f) // DSRA32
1373   {
1374     if(rt1[i]) {
1375       alloc_reg64(current,i,rs1[i]);
1376       alloc_reg(current,i,rt1[i]);
1377       current->is32|=1LL<<rt1[i];
1378       dirty_reg(current,rt1[i]);
1379     }
1380   }
1381 }
1382
1383 void shift_alloc(struct regstat *current,int i)
1384 {
1385   if(rt1[i]) {
1386     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1387     {
1388       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1389       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1390       alloc_reg(current,i,rt1[i]);
1391       if(rt1[i]==rs2[i]) {
1392         alloc_reg_temp(current,i,-1);
1393         minimum_free_regs[i]=1;
1394       }
1395       current->is32|=1LL<<rt1[i];
1396     } else { // DSLLV/DSRLV/DSRAV
1397       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1398       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1399       alloc_reg64(current,i,rt1[i]);
1400       current->is32&=~(1LL<<rt1[i]);
1401       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1402       {
1403         alloc_reg_temp(current,i,-1);
1404         minimum_free_regs[i]=1;
1405       }
1406     }
1407     clear_const(current,rs1[i]);
1408     clear_const(current,rs2[i]);
1409     clear_const(current,rt1[i]);
1410     dirty_reg(current,rt1[i]);
1411   }
1412 }
1413
1414 void alu_alloc(struct regstat *current,int i)
1415 {
1416   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1417     if(rt1[i]) {
1418       if(rs1[i]&&rs2[i]) {
1419         alloc_reg(current,i,rs1[i]);
1420         alloc_reg(current,i,rs2[i]);
1421       }
1422       else {
1423         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1424         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1425       }
1426       alloc_reg(current,i,rt1[i]);
1427     }
1428     current->is32|=1LL<<rt1[i];
1429   }
1430   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1431     if(rt1[i]) {
1432       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1433       {
1434         alloc_reg64(current,i,rs1[i]);
1435         alloc_reg64(current,i,rs2[i]);
1436         alloc_reg(current,i,rt1[i]);
1437       } else {
1438         alloc_reg(current,i,rs1[i]);
1439         alloc_reg(current,i,rs2[i]);
1440         alloc_reg(current,i,rt1[i]);
1441       }
1442     }
1443     current->is32|=1LL<<rt1[i];
1444   }
1445   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1446     if(rt1[i]) {
1447       if(rs1[i]&&rs2[i]) {
1448         alloc_reg(current,i,rs1[i]);
1449         alloc_reg(current,i,rs2[i]);
1450       }
1451       else
1452       {
1453         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1454         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1455       }
1456       alloc_reg(current,i,rt1[i]);
1457       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1458       {
1459         if(!((current->uu>>rt1[i])&1)) {
1460           alloc_reg64(current,i,rt1[i]);
1461         }
1462         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1463           if(rs1[i]&&rs2[i]) {
1464             alloc_reg64(current,i,rs1[i]);
1465             alloc_reg64(current,i,rs2[i]);
1466           }
1467           else
1468           {
1469             // Is is really worth it to keep 64-bit values in registers?
1470             #ifdef NATIVE_64BIT
1471             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1472             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1473             #endif
1474           }
1475         }
1476         current->is32&=~(1LL<<rt1[i]);
1477       } else {
1478         current->is32|=1LL<<rt1[i];
1479       }
1480     }
1481   }
1482   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1483     if(rt1[i]) {
1484       if(rs1[i]&&rs2[i]) {
1485         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1486           alloc_reg64(current,i,rs1[i]);
1487           alloc_reg64(current,i,rs2[i]);
1488           alloc_reg64(current,i,rt1[i]);
1489         } else {
1490           alloc_reg(current,i,rs1[i]);
1491           alloc_reg(current,i,rs2[i]);
1492           alloc_reg(current,i,rt1[i]);
1493         }
1494       }
1495       else {
1496         alloc_reg(current,i,rt1[i]);
1497         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1498           // DADD used as move, or zeroing
1499           // If we have a 64-bit source, then make the target 64 bits too
1500           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1501             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1502             alloc_reg64(current,i,rt1[i]);
1503           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1504             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1505             alloc_reg64(current,i,rt1[i]);
1506           }
1507           if(opcode2[i]>=0x2e&&rs2[i]) {
1508             // DSUB used as negation - 64-bit result
1509             // If we have a 32-bit register, extend it to 64 bits
1510             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1511             alloc_reg64(current,i,rt1[i]);
1512           }
1513         }
1514       }
1515       if(rs1[i]&&rs2[i]) {
1516         current->is32&=~(1LL<<rt1[i]);
1517       } else if(rs1[i]) {
1518         current->is32&=~(1LL<<rt1[i]);
1519         if((current->is32>>rs1[i])&1)
1520           current->is32|=1LL<<rt1[i];
1521       } else if(rs2[i]) {
1522         current->is32&=~(1LL<<rt1[i]);
1523         if((current->is32>>rs2[i])&1)
1524           current->is32|=1LL<<rt1[i];
1525       } else {
1526         current->is32|=1LL<<rt1[i];
1527       }
1528     }
1529   }
1530   clear_const(current,rs1[i]);
1531   clear_const(current,rs2[i]);
1532   clear_const(current,rt1[i]);
1533   dirty_reg(current,rt1[i]);
1534 }
1535
1536 void imm16_alloc(struct regstat *current,int i)
1537 {
1538   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1539   else lt1[i]=rs1[i];
1540   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1541   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1542     current->is32&=~(1LL<<rt1[i]);
1543     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1544       // TODO: Could preserve the 32-bit flag if the immediate is zero
1545       alloc_reg64(current,i,rt1[i]);
1546       alloc_reg64(current,i,rs1[i]);
1547     }
1548     clear_const(current,rs1[i]);
1549     clear_const(current,rt1[i]);
1550   }
1551   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1552     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1553     current->is32|=1LL<<rt1[i];
1554     clear_const(current,rs1[i]);
1555     clear_const(current,rt1[i]);
1556   }
1557   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1558     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1559       if(rs1[i]!=rt1[i]) {
1560         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1561         alloc_reg64(current,i,rt1[i]);
1562         current->is32&=~(1LL<<rt1[i]);
1563       }
1564     }
1565     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1566     if(is_const(current,rs1[i])) {
1567       int v=get_const(current,rs1[i]);
1568       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1569       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1570       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1571     }
1572     else clear_const(current,rt1[i]);
1573   }
1574   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1575     if(is_const(current,rs1[i])) {
1576       int v=get_const(current,rs1[i]);
1577       set_const(current,rt1[i],v+imm[i]);
1578     }
1579     else clear_const(current,rt1[i]);
1580     current->is32|=1LL<<rt1[i];
1581   }
1582   else {
1583     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1584     current->is32|=1LL<<rt1[i];
1585   }
1586   dirty_reg(current,rt1[i]);
1587 }
1588
1589 void load_alloc(struct regstat *current,int i)
1590 {
1591   clear_const(current,rt1[i]);
1592   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1593   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1594   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1595   if(rt1[i]) {
1596     alloc_reg(current,i,rt1[i]);
1597     if(get_reg(current->regmap,rt1[i])<0) {
1598       // dummy load, but we still need a register to calculate the address
1599       alloc_reg_temp(current,i,-1);
1600       minimum_free_regs[i]=1;
1601     }
1602     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1603     {
1604       current->is32&=~(1LL<<rt1[i]);
1605       alloc_reg64(current,i,rt1[i]);
1606     }
1607     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1608     {
1609       current->is32&=~(1LL<<rt1[i]);
1610       alloc_reg64(current,i,rt1[i]);
1611       alloc_all(current,i);
1612       alloc_reg64(current,i,FTEMP);
1613       minimum_free_regs[i]=HOST_REGS;
1614     }
1615     else current->is32|=1LL<<rt1[i];
1616     dirty_reg(current,rt1[i]);
1617     // If using TLB, need a register for pointer to the mapping table
1618     if(using_tlb) alloc_reg(current,i,TLREG);
1619     // LWL/LWR need a temporary register for the old value
1620     if(opcode[i]==0x22||opcode[i]==0x26)
1621     {
1622       alloc_reg(current,i,FTEMP);
1623       alloc_reg_temp(current,i,-1);
1624       minimum_free_regs[i]=1;
1625     }
1626   }
1627   else
1628   {
1629     // Load to r0 (dummy load)
1630     // but we still need a register to calculate the address
1631     if(opcode[i]==0x22||opcode[i]==0x26)
1632     {
1633       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1634     }
1635     alloc_reg_temp(current,i,-1);
1636     minimum_free_regs[i]=1;
1637     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1638     {
1639       alloc_all(current,i);
1640       alloc_reg64(current,i,FTEMP);
1641       minimum_free_regs[i]=HOST_REGS;
1642     }
1643   }
1644 }
1645
1646 void store_alloc(struct regstat *current,int i)
1647 {
1648   clear_const(current,rs2[i]);
1649   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1650   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1651   alloc_reg(current,i,rs2[i]);
1652   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1653     alloc_reg64(current,i,rs2[i]);
1654     if(rs2[i]) alloc_reg(current,i,FTEMP);
1655   }
1656   // If using TLB, need a register for pointer to the mapping table
1657   if(using_tlb) alloc_reg(current,i,TLREG);
1658   #if defined(HOST_IMM8)
1659   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1660   else alloc_reg(current,i,INVCP);
1661   #endif
1662   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1663     alloc_reg(current,i,FTEMP);
1664   }
1665   // We need a temporary register for address generation
1666   alloc_reg_temp(current,i,-1);
1667   minimum_free_regs[i]=1;
1668 }
1669
1670 void c1ls_alloc(struct regstat *current,int i)
1671 {
1672   //clear_const(current,rs1[i]); // FIXME
1673   clear_const(current,rt1[i]);
1674   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1675   alloc_reg(current,i,CSREG); // Status
1676   alloc_reg(current,i,FTEMP);
1677   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1678     alloc_reg64(current,i,FTEMP);
1679   }
1680   // If using TLB, need a register for pointer to the mapping table
1681   if(using_tlb) alloc_reg(current,i,TLREG);
1682   #if defined(HOST_IMM8)
1683   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1684   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1685     alloc_reg(current,i,INVCP);
1686   #endif
1687   // We need a temporary register for address generation
1688   alloc_reg_temp(current,i,-1);
1689 }
1690
1691 void c2ls_alloc(struct regstat *current,int i)
1692 {
1693   clear_const(current,rt1[i]);
1694   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1695   alloc_reg(current,i,FTEMP);
1696   // If using TLB, need a register for pointer to the mapping table
1697   if(using_tlb) alloc_reg(current,i,TLREG);
1698   #if defined(HOST_IMM8)
1699   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1700   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1701     alloc_reg(current,i,INVCP);
1702   #endif
1703   // We need a temporary register for address generation
1704   alloc_reg_temp(current,i,-1);
1705   minimum_free_regs[i]=1;
1706 }
1707
1708 #ifndef multdiv_alloc
1709 void multdiv_alloc(struct regstat *current,int i)
1710 {
1711   //  case 0x18: MULT
1712   //  case 0x19: MULTU
1713   //  case 0x1A: DIV
1714   //  case 0x1B: DIVU
1715   //  case 0x1C: DMULT
1716   //  case 0x1D: DMULTU
1717   //  case 0x1E: DDIV
1718   //  case 0x1F: DDIVU
1719   clear_const(current,rs1[i]);
1720   clear_const(current,rs2[i]);
1721   if(rs1[i]&&rs2[i])
1722   {
1723     if((opcode2[i]&4)==0) // 32-bit
1724     {
1725       current->u&=~(1LL<<HIREG);
1726       current->u&=~(1LL<<LOREG);
1727       alloc_reg(current,i,HIREG);
1728       alloc_reg(current,i,LOREG);
1729       alloc_reg(current,i,rs1[i]);
1730       alloc_reg(current,i,rs2[i]);
1731       current->is32|=1LL<<HIREG;
1732       current->is32|=1LL<<LOREG;
1733       dirty_reg(current,HIREG);
1734       dirty_reg(current,LOREG);
1735     }
1736     else // 64-bit
1737     {
1738       current->u&=~(1LL<<HIREG);
1739       current->u&=~(1LL<<LOREG);
1740       current->uu&=~(1LL<<HIREG);
1741       current->uu&=~(1LL<<LOREG);
1742       alloc_reg64(current,i,HIREG);
1743       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1744       alloc_reg64(current,i,rs1[i]);
1745       alloc_reg64(current,i,rs2[i]);
1746       alloc_all(current,i);
1747       current->is32&=~(1LL<<HIREG);
1748       current->is32&=~(1LL<<LOREG);
1749       dirty_reg(current,HIREG);
1750       dirty_reg(current,LOREG);
1751       minimum_free_regs[i]=HOST_REGS;
1752     }
1753   }
1754   else
1755   {
1756     // Multiply by zero is zero.
1757     // MIPS does not have a divide by zero exception.
1758     // The result is undefined, we return zero.
1759     alloc_reg(current,i,HIREG);
1760     alloc_reg(current,i,LOREG);
1761     current->is32|=1LL<<HIREG;
1762     current->is32|=1LL<<LOREG;
1763     dirty_reg(current,HIREG);
1764     dirty_reg(current,LOREG);
1765   }
1766 }
1767 #endif
1768
1769 void cop0_alloc(struct regstat *current,int i)
1770 {
1771   if(opcode2[i]==0) // MFC0
1772   {
1773     if(rt1[i]) {
1774       clear_const(current,rt1[i]);
1775       alloc_all(current,i);
1776       alloc_reg(current,i,rt1[i]);
1777       current->is32|=1LL<<rt1[i];
1778       dirty_reg(current,rt1[i]);
1779     }
1780   }
1781   else if(opcode2[i]==4) // MTC0
1782   {
1783     if(rs1[i]){
1784       clear_const(current,rs1[i]);
1785       alloc_reg(current,i,rs1[i]);
1786       alloc_all(current,i);
1787     }
1788     else {
1789       alloc_all(current,i); // FIXME: Keep r0
1790       current->u&=~1LL;
1791       alloc_reg(current,i,0);
1792     }
1793   }
1794   else
1795   {
1796     // TLBR/TLBWI/TLBWR/TLBP/ERET
1797     assert(opcode2[i]==0x10);
1798     alloc_all(current,i);
1799   }
1800   minimum_free_regs[i]=HOST_REGS;
1801 }
1802
1803 void cop1_alloc(struct regstat *current,int i)
1804 {
1805   alloc_reg(current,i,CSREG); // Load status
1806   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1807   {
1808     if(rt1[i]){
1809       clear_const(current,rt1[i]);
1810       if(opcode2[i]==1) {
1811         alloc_reg64(current,i,rt1[i]); // DMFC1
1812         current->is32&=~(1LL<<rt1[i]);
1813       }else{
1814         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1815         current->is32|=1LL<<rt1[i];
1816       }
1817       dirty_reg(current,rt1[i]);
1818     }
1819     alloc_reg_temp(current,i,-1);
1820   }
1821   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1822   {
1823     if(rs1[i]){
1824       clear_const(current,rs1[i]);
1825       if(opcode2[i]==5)
1826         alloc_reg64(current,i,rs1[i]); // DMTC1
1827       else
1828         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1829       alloc_reg_temp(current,i,-1);
1830     }
1831     else {
1832       current->u&=~1LL;
1833       alloc_reg(current,i,0);
1834       alloc_reg_temp(current,i,-1);
1835     }
1836   }
1837   minimum_free_regs[i]=1;
1838 }
1839 void fconv_alloc(struct regstat *current,int i)
1840 {
1841   alloc_reg(current,i,CSREG); // Load status
1842   alloc_reg_temp(current,i,-1);
1843   minimum_free_regs[i]=1;
1844 }
1845 void float_alloc(struct regstat *current,int i)
1846 {
1847   alloc_reg(current,i,CSREG); // Load status
1848   alloc_reg_temp(current,i,-1);
1849   minimum_free_regs[i]=1;
1850 }
1851 void c2op_alloc(struct regstat *current,int i)
1852 {
1853   alloc_reg_temp(current,i,-1);
1854 }
1855 void fcomp_alloc(struct regstat *current,int i)
1856 {
1857   alloc_reg(current,i,CSREG); // Load status
1858   alloc_reg(current,i,FSREG); // Load flags
1859   dirty_reg(current,FSREG); // Flag will be modified
1860   alloc_reg_temp(current,i,-1);
1861   minimum_free_regs[i]=1;
1862 }
1863
1864 void syscall_alloc(struct regstat *current,int i)
1865 {
1866   alloc_cc(current,i);
1867   dirty_reg(current,CCREG);
1868   alloc_all(current,i);
1869   minimum_free_regs[i]=HOST_REGS;
1870   current->isconst=0;
1871 }
1872
1873 void delayslot_alloc(struct regstat *current,int i)
1874 {
1875   switch(itype[i]) {
1876     case UJUMP:
1877     case CJUMP:
1878     case SJUMP:
1879     case RJUMP:
1880     case FJUMP:
1881     case SYSCALL:
1882     case HLECALL:
1883     case SPAN:
1884       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1885       printf("Disabled speculative precompilation\n");
1886       stop_after_jal=1;
1887       break;
1888     case IMM16:
1889       imm16_alloc(current,i);
1890       break;
1891     case LOAD:
1892     case LOADLR:
1893       load_alloc(current,i);
1894       break;
1895     case STORE:
1896     case STORELR:
1897       store_alloc(current,i);
1898       break;
1899     case ALU:
1900       alu_alloc(current,i);
1901       break;
1902     case SHIFT:
1903       shift_alloc(current,i);
1904       break;
1905     case MULTDIV:
1906       multdiv_alloc(current,i);
1907       break;
1908     case SHIFTIMM:
1909       shiftimm_alloc(current,i);
1910       break;
1911     case MOV:
1912       mov_alloc(current,i);
1913       break;
1914     case COP0:
1915       cop0_alloc(current,i);
1916       break;
1917     case COP1:
1918     case COP2:
1919       cop1_alloc(current,i);
1920       break;
1921     case C1LS:
1922       c1ls_alloc(current,i);
1923       break;
1924     case C2LS:
1925       c2ls_alloc(current,i);
1926       break;
1927     case FCONV:
1928       fconv_alloc(current,i);
1929       break;
1930     case FLOAT:
1931       float_alloc(current,i);
1932       break;
1933     case FCOMP:
1934       fcomp_alloc(current,i);
1935       break;
1936     case C2OP:
1937       c2op_alloc(current,i);
1938       break;
1939   }
1940 }
1941
1942 // Special case where a branch and delay slot span two pages in virtual memory
1943 static void pagespan_alloc(struct regstat *current,int i)
1944 {
1945   current->isconst=0;
1946   current->wasconst=0;
1947   regs[i].wasconst=0;
1948   minimum_free_regs[i]=HOST_REGS;
1949   alloc_all(current,i);
1950   alloc_cc(current,i);
1951   dirty_reg(current,CCREG);
1952   if(opcode[i]==3) // JAL
1953   {
1954     alloc_reg(current,i,31);
1955     dirty_reg(current,31);
1956   }
1957   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1958   {
1959     alloc_reg(current,i,rs1[i]);
1960     if (rt1[i]!=0) {
1961       alloc_reg(current,i,rt1[i]);
1962       dirty_reg(current,rt1[i]);
1963     }
1964   }
1965   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1966   {
1967     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1968     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1969     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1970     {
1971       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1972       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1973     }
1974   }
1975   else
1976   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1977   {
1978     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1979     if(!((current->is32>>rs1[i])&1))
1980     {
1981       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1982     }
1983   }
1984   else
1985   if(opcode[i]==0x11) // BC1
1986   {
1987     alloc_reg(current,i,FSREG);
1988     alloc_reg(current,i,CSREG);
1989   }
1990   //else ...
1991 }
1992
1993 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1994 {
1995   stubs[stubcount][0]=type;
1996   stubs[stubcount][1]=addr;
1997   stubs[stubcount][2]=retaddr;
1998   stubs[stubcount][3]=a;
1999   stubs[stubcount][4]=b;
2000   stubs[stubcount][5]=c;
2001   stubs[stubcount][6]=d;
2002   stubs[stubcount][7]=e;
2003   stubcount++;
2004 }
2005
2006 // Write out a single register
2007 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2008 {
2009   int hr;
2010   for(hr=0;hr<HOST_REGS;hr++) {
2011     if(hr!=EXCLUDE_REG) {
2012       if((regmap[hr]&63)==r) {
2013         if((dirty>>hr)&1) {
2014           if(regmap[hr]<64) {
2015             emit_storereg(r,hr);
2016 #ifndef FORCE32
2017             if((is32>>regmap[hr])&1) {
2018               emit_sarimm(hr,31,hr);
2019               emit_storereg(r|64,hr);
2020             }
2021 #endif
2022           }else{
2023             emit_storereg(r|64,hr);
2024           }
2025         }
2026       }
2027     }
2028   }
2029 }
2030
2031 int mchecksum()
2032 {
2033   //if(!tracedebug) return 0;
2034   int i;
2035   int sum=0;
2036   for(i=0;i<2097152;i++) {
2037     unsigned int temp=sum;
2038     sum<<=1;
2039     sum|=(~temp)>>31;
2040     sum^=((u_int *)rdram)[i];
2041   }
2042   return sum;
2043 }
2044 int rchecksum()
2045 {
2046   int i;
2047   int sum=0;
2048   for(i=0;i<64;i++)
2049     sum^=((u_int *)reg)[i];
2050   return sum;
2051 }
2052 void rlist()
2053 {
2054   int i;
2055   printf("TRACE: ");
2056   for(i=0;i<32;i++)
2057     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2058   printf("\n");
2059 #ifndef DISABLE_COP1
2060   printf("TRACE: ");
2061   for(i=0;i<32;i++)
2062     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2063   printf("\n");
2064 #endif
2065 }
2066
2067 void enabletrace()
2068 {
2069   tracedebug=1;
2070 }
2071
2072 void memdebug(int i)
2073 {
2074   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2075   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2076   //rlist();
2077   //if(tracedebug) {
2078   //if(Count>=-2084597794) {
2079   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2080   //if(0) {
2081     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2082     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2083     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2084     rlist();
2085     #ifdef __i386__
2086     printf("TRACE: %x\n",(&i)[-1]);
2087     #endif
2088     #ifdef __arm__
2089     int j;
2090     printf("TRACE: %x \n",(&j)[10]);
2091     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2092     #endif
2093     //fflush(stdout);
2094   }
2095   //printf("TRACE: %x\n",(&i)[-1]);
2096 }
2097
2098 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2099 {
2100   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2101 }
2102
2103 void alu_assemble(int i,struct regstat *i_regs)
2104 {
2105   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2106     if(rt1[i]) {
2107       signed char s1,s2,t;
2108       t=get_reg(i_regs->regmap,rt1[i]);
2109       if(t>=0) {
2110         s1=get_reg(i_regs->regmap,rs1[i]);
2111         s2=get_reg(i_regs->regmap,rs2[i]);
2112         if(rs1[i]&&rs2[i]) {
2113           assert(s1>=0);
2114           assert(s2>=0);
2115           if(opcode2[i]&2) emit_sub(s1,s2,t);
2116           else emit_add(s1,s2,t);
2117         }
2118         else if(rs1[i]) {
2119           if(s1>=0) emit_mov(s1,t);
2120           else emit_loadreg(rs1[i],t);
2121         }
2122         else if(rs2[i]) {
2123           if(s2>=0) {
2124             if(opcode2[i]&2) emit_neg(s2,t);
2125             else emit_mov(s2,t);
2126           }
2127           else {
2128             emit_loadreg(rs2[i],t);
2129             if(opcode2[i]&2) emit_neg(t,t);
2130           }
2131         }
2132         else emit_zeroreg(t);
2133       }
2134     }
2135   }
2136   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2137     if(rt1[i]) {
2138       signed char s1l,s2l,s1h,s2h,tl,th;
2139       tl=get_reg(i_regs->regmap,rt1[i]);
2140       th=get_reg(i_regs->regmap,rt1[i]|64);
2141       if(tl>=0) {
2142         s1l=get_reg(i_regs->regmap,rs1[i]);
2143         s2l=get_reg(i_regs->regmap,rs2[i]);
2144         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2145         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2146         if(rs1[i]&&rs2[i]) {
2147           assert(s1l>=0);
2148           assert(s2l>=0);
2149           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2150           else emit_adds(s1l,s2l,tl);
2151           if(th>=0) {
2152             #ifdef INVERTED_CARRY
2153             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2154             #else
2155             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2156             #endif
2157             else emit_add(s1h,s2h,th);
2158           }
2159         }
2160         else if(rs1[i]) {
2161           if(s1l>=0) emit_mov(s1l,tl);
2162           else emit_loadreg(rs1[i],tl);
2163           if(th>=0) {
2164             if(s1h>=0) emit_mov(s1h,th);
2165             else emit_loadreg(rs1[i]|64,th);
2166           }
2167         }
2168         else if(rs2[i]) {
2169           if(s2l>=0) {
2170             if(opcode2[i]&2) emit_negs(s2l,tl);
2171             else emit_mov(s2l,tl);
2172           }
2173           else {
2174             emit_loadreg(rs2[i],tl);
2175             if(opcode2[i]&2) emit_negs(tl,tl);
2176           }
2177           if(th>=0) {
2178             #ifdef INVERTED_CARRY
2179             if(s2h>=0) emit_mov(s2h,th);
2180             else emit_loadreg(rs2[i]|64,th);
2181             if(opcode2[i]&2) {
2182               emit_adcimm(-1,th); // x86 has inverted carry flag
2183               emit_not(th,th);
2184             }
2185             #else
2186             if(opcode2[i]&2) {
2187               if(s2h>=0) emit_rscimm(s2h,0,th);
2188               else {
2189                 emit_loadreg(rs2[i]|64,th);
2190                 emit_rscimm(th,0,th);
2191               }
2192             }else{
2193               if(s2h>=0) emit_mov(s2h,th);
2194               else emit_loadreg(rs2[i]|64,th);
2195             }
2196             #endif
2197           }
2198         }
2199         else {
2200           emit_zeroreg(tl);
2201           if(th>=0) emit_zeroreg(th);
2202         }
2203       }
2204     }
2205   }
2206   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2207     if(rt1[i]) {
2208       signed char s1l,s1h,s2l,s2h,t;
2209       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2210       {
2211         t=get_reg(i_regs->regmap,rt1[i]);
2212         //assert(t>=0);
2213         if(t>=0) {
2214           s1l=get_reg(i_regs->regmap,rs1[i]);
2215           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2216           s2l=get_reg(i_regs->regmap,rs2[i]);
2217           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2218           if(rs2[i]==0) // rx<r0
2219           {
2220             assert(s1h>=0);
2221             if(opcode2[i]==0x2a) // SLT
2222               emit_shrimm(s1h,31,t);
2223             else // SLTU (unsigned can not be less than zero)
2224               emit_zeroreg(t);
2225           }
2226           else if(rs1[i]==0) // r0<rx
2227           {
2228             assert(s2h>=0);
2229             if(opcode2[i]==0x2a) // SLT
2230               emit_set_gz64_32(s2h,s2l,t);
2231             else // SLTU (set if not zero)
2232               emit_set_nz64_32(s2h,s2l,t);
2233           }
2234           else {
2235             assert(s1l>=0);assert(s1h>=0);
2236             assert(s2l>=0);assert(s2h>=0);
2237             if(opcode2[i]==0x2a) // SLT
2238               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2239             else // SLTU
2240               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2241           }
2242         }
2243       } else {
2244         t=get_reg(i_regs->regmap,rt1[i]);
2245         //assert(t>=0);
2246         if(t>=0) {
2247           s1l=get_reg(i_regs->regmap,rs1[i]);
2248           s2l=get_reg(i_regs->regmap,rs2[i]);
2249           if(rs2[i]==0) // rx<r0
2250           {
2251             assert(s1l>=0);
2252             if(opcode2[i]==0x2a) // SLT
2253               emit_shrimm(s1l,31,t);
2254             else // SLTU (unsigned can not be less than zero)
2255               emit_zeroreg(t);
2256           }
2257           else if(rs1[i]==0) // r0<rx
2258           {
2259             assert(s2l>=0);
2260             if(opcode2[i]==0x2a) // SLT
2261               emit_set_gz32(s2l,t);
2262             else // SLTU (set if not zero)
2263               emit_set_nz32(s2l,t);
2264           }
2265           else{
2266             assert(s1l>=0);assert(s2l>=0);
2267             if(opcode2[i]==0x2a) // SLT
2268               emit_set_if_less32(s1l,s2l,t);
2269             else // SLTU
2270               emit_set_if_carry32(s1l,s2l,t);
2271           }
2272         }
2273       }
2274     }
2275   }
2276   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2277     if(rt1[i]) {
2278       signed char s1l,s1h,s2l,s2h,th,tl;
2279       tl=get_reg(i_regs->regmap,rt1[i]);
2280       th=get_reg(i_regs->regmap,rt1[i]|64);
2281       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2282       {
2283         assert(tl>=0);
2284         if(tl>=0) {
2285           s1l=get_reg(i_regs->regmap,rs1[i]);
2286           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2287           s2l=get_reg(i_regs->regmap,rs2[i]);
2288           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2289           if(rs1[i]&&rs2[i]) {
2290             assert(s1l>=0);assert(s1h>=0);
2291             assert(s2l>=0);assert(s2h>=0);
2292             if(opcode2[i]==0x24) { // AND
2293               emit_and(s1l,s2l,tl);
2294               emit_and(s1h,s2h,th);
2295             } else
2296             if(opcode2[i]==0x25) { // OR
2297               emit_or(s1l,s2l,tl);
2298               emit_or(s1h,s2h,th);
2299             } else
2300             if(opcode2[i]==0x26) { // XOR
2301               emit_xor(s1l,s2l,tl);
2302               emit_xor(s1h,s2h,th);
2303             } else
2304             if(opcode2[i]==0x27) { // NOR
2305               emit_or(s1l,s2l,tl);
2306               emit_or(s1h,s2h,th);
2307               emit_not(tl,tl);
2308               emit_not(th,th);
2309             }
2310           }
2311           else
2312           {
2313             if(opcode2[i]==0x24) { // AND
2314               emit_zeroreg(tl);
2315               emit_zeroreg(th);
2316             } else
2317             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2318               if(rs1[i]){
2319                 if(s1l>=0) emit_mov(s1l,tl);
2320                 else emit_loadreg(rs1[i],tl);
2321                 if(s1h>=0) emit_mov(s1h,th);
2322                 else emit_loadreg(rs1[i]|64,th);
2323               }
2324               else
2325               if(rs2[i]){
2326                 if(s2l>=0) emit_mov(s2l,tl);
2327                 else emit_loadreg(rs2[i],tl);
2328                 if(s2h>=0) emit_mov(s2h,th);
2329                 else emit_loadreg(rs2[i]|64,th);
2330               }
2331               else{
2332                 emit_zeroreg(tl);
2333                 emit_zeroreg(th);
2334               }
2335             } else
2336             if(opcode2[i]==0x27) { // NOR
2337               if(rs1[i]){
2338                 if(s1l>=0) emit_not(s1l,tl);
2339                 else{
2340                   emit_loadreg(rs1[i],tl);
2341                   emit_not(tl,tl);
2342                 }
2343                 if(s1h>=0) emit_not(s1h,th);
2344                 else{
2345                   emit_loadreg(rs1[i]|64,th);
2346                   emit_not(th,th);
2347                 }
2348               }
2349               else
2350               if(rs2[i]){
2351                 if(s2l>=0) emit_not(s2l,tl);
2352                 else{
2353                   emit_loadreg(rs2[i],tl);
2354                   emit_not(tl,tl);
2355                 }
2356                 if(s2h>=0) emit_not(s2h,th);
2357                 else{
2358                   emit_loadreg(rs2[i]|64,th);
2359                   emit_not(th,th);
2360                 }
2361               }
2362               else {
2363                 emit_movimm(-1,tl);
2364                 emit_movimm(-1,th);
2365               }
2366             }
2367           }
2368         }
2369       }
2370       else
2371       {
2372         // 32 bit
2373         if(tl>=0) {
2374           s1l=get_reg(i_regs->regmap,rs1[i]);
2375           s2l=get_reg(i_regs->regmap,rs2[i]);
2376           if(rs1[i]&&rs2[i]) {
2377             assert(s1l>=0);
2378             assert(s2l>=0);
2379             if(opcode2[i]==0x24) { // AND
2380               emit_and(s1l,s2l,tl);
2381             } else
2382             if(opcode2[i]==0x25) { // OR
2383               emit_or(s1l,s2l,tl);
2384             } else
2385             if(opcode2[i]==0x26) { // XOR
2386               emit_xor(s1l,s2l,tl);
2387             } else
2388             if(opcode2[i]==0x27) { // NOR
2389               emit_or(s1l,s2l,tl);
2390               emit_not(tl,tl);
2391             }
2392           }
2393           else
2394           {
2395             if(opcode2[i]==0x24) { // AND
2396               emit_zeroreg(tl);
2397             } else
2398             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2399               if(rs1[i]){
2400                 if(s1l>=0) emit_mov(s1l,tl);
2401                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2402               }
2403               else
2404               if(rs2[i]){
2405                 if(s2l>=0) emit_mov(s2l,tl);
2406                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2407               }
2408               else emit_zeroreg(tl);
2409             } else
2410             if(opcode2[i]==0x27) { // NOR
2411               if(rs1[i]){
2412                 if(s1l>=0) emit_not(s1l,tl);
2413                 else {
2414                   emit_loadreg(rs1[i],tl);
2415                   emit_not(tl,tl);
2416                 }
2417               }
2418               else
2419               if(rs2[i]){
2420                 if(s2l>=0) emit_not(s2l,tl);
2421                 else {
2422                   emit_loadreg(rs2[i],tl);
2423                   emit_not(tl,tl);
2424                 }
2425               }
2426               else emit_movimm(-1,tl);
2427             }
2428           }
2429         }
2430       }
2431     }
2432   }
2433 }
2434
2435 void imm16_assemble(int i,struct regstat *i_regs)
2436 {
2437   if (opcode[i]==0x0f) { // LUI
2438     if(rt1[i]) {
2439       signed char t;
2440       t=get_reg(i_regs->regmap,rt1[i]);
2441       //assert(t>=0);
2442       if(t>=0) {
2443         if(!((i_regs->isconst>>t)&1))
2444           emit_movimm(imm[i]<<16,t);
2445       }
2446     }
2447   }
2448   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2449     if(rt1[i]) {
2450       signed char s,t;
2451       t=get_reg(i_regs->regmap,rt1[i]);
2452       s=get_reg(i_regs->regmap,rs1[i]);
2453       if(rs1[i]) {
2454         //assert(t>=0);
2455         //assert(s>=0);
2456         if(t>=0) {
2457           if(!((i_regs->isconst>>t)&1)) {
2458             if(s<0) {
2459               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2460               emit_addimm(t,imm[i],t);
2461             }else{
2462               if(!((i_regs->wasconst>>s)&1))
2463                 emit_addimm(s,imm[i],t);
2464               else
2465                 emit_movimm(constmap[i][s]+imm[i],t);
2466             }
2467           }
2468         }
2469       } else {
2470         if(t>=0) {
2471           if(!((i_regs->isconst>>t)&1))
2472             emit_movimm(imm[i],t);
2473         }
2474       }
2475     }
2476   }
2477   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2478     if(rt1[i]) {
2479       signed char sh,sl,th,tl;
2480       th=get_reg(i_regs->regmap,rt1[i]|64);
2481       tl=get_reg(i_regs->regmap,rt1[i]);
2482       sh=get_reg(i_regs->regmap,rs1[i]|64);
2483       sl=get_reg(i_regs->regmap,rs1[i]);
2484       if(tl>=0) {
2485         if(rs1[i]) {
2486           assert(sh>=0);
2487           assert(sl>=0);
2488           if(th>=0) {
2489             emit_addimm64_32(sh,sl,imm[i],th,tl);
2490           }
2491           else {
2492             emit_addimm(sl,imm[i],tl);
2493           }
2494         } else {
2495           emit_movimm(imm[i],tl);
2496           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2497         }
2498       }
2499     }
2500   }
2501   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2502     if(rt1[i]) {
2503       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2504       signed char sh,sl,t;
2505       t=get_reg(i_regs->regmap,rt1[i]);
2506       sh=get_reg(i_regs->regmap,rs1[i]|64);
2507       sl=get_reg(i_regs->regmap,rs1[i]);
2508       //assert(t>=0);
2509       if(t>=0) {
2510         if(rs1[i]>0) {
2511           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2512           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2513             if(opcode[i]==0x0a) { // SLTI
2514               if(sl<0) {
2515                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2516                 emit_slti32(t,imm[i],t);
2517               }else{
2518                 emit_slti32(sl,imm[i],t);
2519               }
2520             }
2521             else { // SLTIU
2522               if(sl<0) {
2523                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2524                 emit_sltiu32(t,imm[i],t);
2525               }else{
2526                 emit_sltiu32(sl,imm[i],t);
2527               }
2528             }
2529           }else{ // 64-bit
2530             assert(sl>=0);
2531             if(opcode[i]==0x0a) // SLTI
2532               emit_slti64_32(sh,sl,imm[i],t);
2533             else // SLTIU
2534               emit_sltiu64_32(sh,sl,imm[i],t);
2535           }
2536         }else{
2537           // SLTI(U) with r0 is just stupid,
2538           // nonetheless examples can be found
2539           if(opcode[i]==0x0a) // SLTI
2540             if(0<imm[i]) emit_movimm(1,t);
2541             else emit_zeroreg(t);
2542           else // SLTIU
2543           {
2544             if(imm[i]) emit_movimm(1,t);
2545             else emit_zeroreg(t);
2546           }
2547         }
2548       }
2549     }
2550   }
2551   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2552     if(rt1[i]) {
2553       signed char sh,sl,th,tl;
2554       th=get_reg(i_regs->regmap,rt1[i]|64);
2555       tl=get_reg(i_regs->regmap,rt1[i]);
2556       sh=get_reg(i_regs->regmap,rs1[i]|64);
2557       sl=get_reg(i_regs->regmap,rs1[i]);
2558       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2559         if(opcode[i]==0x0c) //ANDI
2560         {
2561           if(rs1[i]) {
2562             if(sl<0) {
2563               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2564               emit_andimm(tl,imm[i],tl);
2565             }else{
2566               if(!((i_regs->wasconst>>sl)&1))
2567                 emit_andimm(sl,imm[i],tl);
2568               else
2569                 emit_movimm(constmap[i][sl]&imm[i],tl);
2570             }
2571           }
2572           else
2573             emit_zeroreg(tl);
2574           if(th>=0) emit_zeroreg(th);
2575         }
2576         else
2577         {
2578           if(rs1[i]) {
2579             if(sl<0) {
2580               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2581             }
2582             if(th>=0) {
2583               if(sh<0) {
2584                 emit_loadreg(rs1[i]|64,th);
2585               }else{
2586                 emit_mov(sh,th);
2587               }
2588             }
2589             if(opcode[i]==0x0d) //ORI
2590             if(sl<0) {
2591               emit_orimm(tl,imm[i],tl);
2592             }else{
2593               if(!((i_regs->wasconst>>sl)&1))
2594                 emit_orimm(sl,imm[i],tl);
2595               else
2596                 emit_movimm(constmap[i][sl]|imm[i],tl);
2597             }
2598             if(opcode[i]==0x0e) //XORI
2599             if(sl<0) {
2600               emit_xorimm(tl,imm[i],tl);
2601             }else{
2602               if(!((i_regs->wasconst>>sl)&1))
2603                 emit_xorimm(sl,imm[i],tl);
2604               else
2605                 emit_movimm(constmap[i][sl]^imm[i],tl);
2606             }
2607           }
2608           else {
2609             emit_movimm(imm[i],tl);
2610             if(th>=0) emit_zeroreg(th);
2611           }
2612         }
2613       }
2614     }
2615   }
2616 }
2617
2618 void shiftimm_assemble(int i,struct regstat *i_regs)
2619 {
2620   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2621   {
2622     if(rt1[i]) {
2623       signed char s,t;
2624       t=get_reg(i_regs->regmap,rt1[i]);
2625       s=get_reg(i_regs->regmap,rs1[i]);
2626       //assert(t>=0);
2627       if(t>=0){
2628         if(rs1[i]==0)
2629         {
2630           emit_zeroreg(t);
2631         }
2632         else
2633         {
2634           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2635           if(imm[i]) {
2636             if(opcode2[i]==0) // SLL
2637             {
2638               emit_shlimm(s<0?t:s,imm[i],t);
2639             }
2640             if(opcode2[i]==2) // SRL
2641             {
2642               emit_shrimm(s<0?t:s,imm[i],t);
2643             }
2644             if(opcode2[i]==3) // SRA
2645             {
2646               emit_sarimm(s<0?t:s,imm[i],t);
2647             }
2648           }else{
2649             // Shift by zero
2650             if(s>=0 && s!=t) emit_mov(s,t);
2651           }
2652         }
2653       }
2654       //emit_storereg(rt1[i],t); //DEBUG
2655     }
2656   }
2657   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2658   {
2659     if(rt1[i]) {
2660       signed char sh,sl,th,tl;
2661       th=get_reg(i_regs->regmap,rt1[i]|64);
2662       tl=get_reg(i_regs->regmap,rt1[i]);
2663       sh=get_reg(i_regs->regmap,rs1[i]|64);
2664       sl=get_reg(i_regs->regmap,rs1[i]);
2665       if(tl>=0) {
2666         if(rs1[i]==0)
2667         {
2668           emit_zeroreg(tl);
2669           if(th>=0) emit_zeroreg(th);
2670         }
2671         else
2672         {
2673           assert(sl>=0);
2674           assert(sh>=0);
2675           if(imm[i]) {
2676             if(opcode2[i]==0x38) // DSLL
2677             {
2678               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2679               emit_shlimm(sl,imm[i],tl);
2680             }
2681             if(opcode2[i]==0x3a) // DSRL
2682             {
2683               emit_shrdimm(sl,sh,imm[i],tl);
2684               if(th>=0) emit_shrimm(sh,imm[i],th);
2685             }
2686             if(opcode2[i]==0x3b) // DSRA
2687             {
2688               emit_shrdimm(sl,sh,imm[i],tl);
2689               if(th>=0) emit_sarimm(sh,imm[i],th);
2690             }
2691           }else{
2692             // Shift by zero
2693             if(sl!=tl) emit_mov(sl,tl);
2694             if(th>=0&&sh!=th) emit_mov(sh,th);
2695           }
2696         }
2697       }
2698     }
2699   }
2700   if(opcode2[i]==0x3c) // DSLL32
2701   {
2702     if(rt1[i]) {
2703       signed char sl,tl,th;
2704       tl=get_reg(i_regs->regmap,rt1[i]);
2705       th=get_reg(i_regs->regmap,rt1[i]|64);
2706       sl=get_reg(i_regs->regmap,rs1[i]);
2707       if(th>=0||tl>=0){
2708         assert(tl>=0);
2709         assert(th>=0);
2710         assert(sl>=0);
2711         emit_mov(sl,th);
2712         emit_zeroreg(tl);
2713         if(imm[i]>32)
2714         {
2715           emit_shlimm(th,imm[i]&31,th);
2716         }
2717       }
2718     }
2719   }
2720   if(opcode2[i]==0x3e) // DSRL32
2721   {
2722     if(rt1[i]) {
2723       signed char sh,tl,th;
2724       tl=get_reg(i_regs->regmap,rt1[i]);
2725       th=get_reg(i_regs->regmap,rt1[i]|64);
2726       sh=get_reg(i_regs->regmap,rs1[i]|64);
2727       if(tl>=0){
2728         assert(sh>=0);
2729         emit_mov(sh,tl);
2730         if(th>=0) emit_zeroreg(th);
2731         if(imm[i]>32)
2732         {
2733           emit_shrimm(tl,imm[i]&31,tl);
2734         }
2735       }
2736     }
2737   }
2738   if(opcode2[i]==0x3f) // DSRA32
2739   {
2740     if(rt1[i]) {
2741       signed char sh,tl;
2742       tl=get_reg(i_regs->regmap,rt1[i]);
2743       sh=get_reg(i_regs->regmap,rs1[i]|64);
2744       if(tl>=0){
2745         assert(sh>=0);
2746         emit_mov(sh,tl);
2747         if(imm[i]>32)
2748         {
2749           emit_sarimm(tl,imm[i]&31,tl);
2750         }
2751       }
2752     }
2753   }
2754 }
2755
2756 #ifndef shift_assemble
2757 void shift_assemble(int i,struct regstat *i_regs)
2758 {
2759   printf("Need shift_assemble for this architecture.\n");
2760   exit(1);
2761 }
2762 #endif
2763
2764 void load_assemble(int i,struct regstat *i_regs)
2765 {
2766   int s,th,tl,addr,map=-1;
2767   int offset;
2768   int jaddr=0;
2769   int memtarget=0,c=0;
2770   u_int hr,reglist=0;
2771   th=get_reg(i_regs->regmap,rt1[i]|64);
2772   tl=get_reg(i_regs->regmap,rt1[i]);
2773   s=get_reg(i_regs->regmap,rs1[i]);
2774   offset=imm[i];
2775   for(hr=0;hr<HOST_REGS;hr++) {
2776     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2777   }
2778   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2779   if(s>=0) {
2780     c=(i_regs->wasconst>>s)&1;
2781     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2782     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2783   }
2784   //printf("load_assemble: c=%d\n",c);
2785   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2786   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2787 #ifdef PCSX
2788   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2789     ||rt1[i]==0) {
2790       // could be FIFO, must perform the read
2791       // ||dummy read
2792       assem_debug("(forced read)\n");
2793       tl=get_reg(i_regs->regmap,-1);
2794       assert(tl>=0);
2795   }
2796 #endif
2797   if(offset||s<0||c) addr=tl;
2798   else addr=s;
2799   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2800  if(tl>=0) {
2801   //printf("load_assemble: c=%d\n",c);
2802   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2803   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2804   reglist&=~(1<<tl);
2805   if(th>=0) reglist&=~(1<<th);
2806   if(!using_tlb) {
2807     if(!c) {
2808       #ifdef RAM_OFFSET
2809       map=get_reg(i_regs->regmap,ROREG);
2810       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2811       #endif
2812 //#define R29_HACK 1
2813       #ifdef R29_HACK
2814       // Strmnnrmn's speed hack
2815       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2816       #endif
2817       {
2818         emit_cmpimm(addr,RAM_SIZE);
2819         jaddr=(int)out;
2820         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2821         // Hint to branch predictor that the branch is unlikely to be taken
2822         if(rs1[i]>=28)
2823           emit_jno_unlikely(0);
2824         else
2825         #endif
2826         emit_jno(0);
2827       }
2828     }
2829   }else{ // using tlb
2830     int x=0;
2831     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2832     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2833     map=get_reg(i_regs->regmap,TLREG);
2834     assert(map>=0);
2835     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2836     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2837   }
2838   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2839   if (opcode[i]==0x20) { // LB
2840     if(!c||memtarget) {
2841       if(!dummy) {
2842         #ifdef HOST_IMM_ADDR32
2843         if(c)
2844           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2845         else
2846         #endif
2847         {
2848           //emit_xorimm(addr,3,tl);
2849           //gen_tlb_addr_r(tl,map);
2850           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2851           int x=0,a=tl;
2852 #ifdef BIG_ENDIAN_MIPS
2853           if(!c) emit_xorimm(addr,3,tl);
2854           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2855 #else
2856           if(!c) a=addr;
2857 #endif
2858           emit_movsbl_indexed_tlb(x,a,map,tl);
2859         }
2860       }
2861       if(jaddr)
2862         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2863     }
2864     else
2865       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2866   }
2867   if (opcode[i]==0x21) { // LH
2868     if(!c||memtarget) {
2869       if(!dummy) {
2870         #ifdef HOST_IMM_ADDR32
2871         if(c)
2872           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2873         else
2874         #endif
2875         {
2876           int x=0,a=tl;
2877 #ifdef BIG_ENDIAN_MIPS
2878           if(!c) emit_xorimm(addr,2,tl);
2879           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2880 #else
2881           if(!c) a=addr;
2882 #endif
2883           //#ifdef
2884           //emit_movswl_indexed_tlb(x,tl,map,tl);
2885           //else
2886           if(map>=0) {
2887             gen_tlb_addr_r(a,map);
2888             emit_movswl_indexed(x,a,tl);
2889           }else{
2890             #ifdef RAM_OFFSET
2891             emit_movswl_indexed(x,a,tl);
2892             #else
2893             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2894             #endif
2895           }
2896         }
2897       }
2898       if(jaddr)
2899         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2900     }
2901     else
2902       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2903   }
2904   if (opcode[i]==0x23) { // LW
2905     if(!c||memtarget) {
2906       if(!dummy) {
2907         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2908         #ifdef HOST_IMM_ADDR32
2909         if(c)
2910           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2911         else
2912         #endif
2913         emit_readword_indexed_tlb(0,addr,map,tl);
2914       }
2915       if(jaddr)
2916         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2917     }
2918     else
2919       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2920   }
2921   if (opcode[i]==0x24) { // LBU
2922     if(!c||memtarget) {
2923       if(!dummy) {
2924         #ifdef HOST_IMM_ADDR32
2925         if(c)
2926           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2927         else
2928         #endif
2929         {
2930           //emit_xorimm(addr,3,tl);
2931           //gen_tlb_addr_r(tl,map);
2932           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2933           int x=0,a=tl;
2934 #ifdef BIG_ENDIAN_MIPS
2935           if(!c) emit_xorimm(addr,3,tl);
2936           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2937 #else
2938           if(!c) a=addr;
2939 #endif
2940           emit_movzbl_indexed_tlb(x,a,map,tl);
2941         }
2942       }
2943       if(jaddr)
2944         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2945     }
2946     else
2947       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2948   }
2949   if (opcode[i]==0x25) { // LHU
2950     if(!c||memtarget) {
2951       if(!dummy) {
2952         #ifdef HOST_IMM_ADDR32
2953         if(c)
2954           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2955         else
2956         #endif
2957         {
2958           int x=0,a=tl;
2959 #ifdef BIG_ENDIAN_MIPS
2960           if(!c) emit_xorimm(addr,2,tl);
2961           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2962 #else
2963           if(!c) a=addr;
2964 #endif
2965           //#ifdef
2966           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2967           //#else
2968           if(map>=0) {
2969             gen_tlb_addr_r(a,map);
2970             emit_movzwl_indexed(x,a,tl);
2971           }else{
2972             #ifdef RAM_OFFSET
2973             emit_movzwl_indexed(x,a,tl);
2974             #else
2975             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2976             #endif
2977           }
2978         }
2979       }
2980       if(jaddr)
2981         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2982     }
2983     else
2984       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2985   }
2986   if (opcode[i]==0x27) { // LWU
2987     assert(th>=0);
2988     if(!c||memtarget) {
2989       if(!dummy) {
2990         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2991         #ifdef HOST_IMM_ADDR32
2992         if(c)
2993           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2994         else
2995         #endif
2996         emit_readword_indexed_tlb(0,addr,map,tl);
2997       }
2998       if(jaddr)
2999         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3000     }
3001     else {
3002       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3003     }
3004     emit_zeroreg(th);
3005   }
3006   if (opcode[i]==0x37) { // LD
3007     if(!c||memtarget) {
3008       if(!dummy) {
3009         //gen_tlb_addr_r(tl,map);
3010         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3011         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3012         #ifdef HOST_IMM_ADDR32
3013         if(c)
3014           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3015         else
3016         #endif
3017         emit_readdword_indexed_tlb(0,addr,map,th,tl);
3018       }
3019       if(jaddr)
3020         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3021     }
3022     else
3023       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3024   }
3025  }
3026   //emit_storereg(rt1[i],tl); // DEBUG
3027   //if(opcode[i]==0x23)
3028   //if(opcode[i]==0x24)
3029   //if(opcode[i]==0x23||opcode[i]==0x24)
3030   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3031   {
3032     //emit_pusha();
3033     save_regs(0x100f);
3034         emit_readword((int)&last_count,ECX);
3035         #ifdef __i386__
3036         if(get_reg(i_regs->regmap,CCREG)<0)
3037           emit_loadreg(CCREG,HOST_CCREG);
3038         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3039         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3040         emit_writeword(HOST_CCREG,(int)&Count);
3041         #endif
3042         #ifdef __arm__
3043         if(get_reg(i_regs->regmap,CCREG)<0)
3044           emit_loadreg(CCREG,0);
3045         else
3046           emit_mov(HOST_CCREG,0);
3047         emit_add(0,ECX,0);
3048         emit_addimm(0,2*ccadj[i],0);
3049         emit_writeword(0,(int)&Count);
3050         #endif
3051     emit_call((int)memdebug);
3052     //emit_popa();
3053     restore_regs(0x100f);
3054   }/**/
3055 }
3056
3057 #ifndef loadlr_assemble
3058 void loadlr_assemble(int i,struct regstat *i_regs)
3059 {
3060   printf("Need loadlr_assemble for this architecture.\n");
3061   exit(1);
3062 }
3063 #endif
3064
3065 void store_assemble(int i,struct regstat *i_regs)
3066 {
3067   int s,th,tl,map=-1;
3068   int addr,temp;
3069   int offset;
3070   int jaddr=0,jaddr2,type;
3071   int memtarget=0,c=0;
3072   int agr=AGEN1+(i&1);
3073   u_int hr,reglist=0;
3074   th=get_reg(i_regs->regmap,rs2[i]|64);
3075   tl=get_reg(i_regs->regmap,rs2[i]);
3076   s=get_reg(i_regs->regmap,rs1[i]);
3077   temp=get_reg(i_regs->regmap,agr);
3078   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3079   offset=imm[i];
3080   if(s>=0) {
3081     c=(i_regs->wasconst>>s)&1;
3082     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3083     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3084   }
3085   assert(tl>=0);
3086   assert(temp>=0);
3087   for(hr=0;hr<HOST_REGS;hr++) {
3088     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3089   }
3090   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3091   if(offset||s<0||c) addr=temp;
3092   else addr=s;
3093   if(!using_tlb) {
3094     if(!c) {
3095       #ifdef R29_HACK
3096       // Strmnnrmn's speed hack
3097       memtarget=1;
3098       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3099       #endif
3100       emit_cmpimm(addr,RAM_SIZE);
3101       #ifdef DESTRUCTIVE_SHIFT
3102       if(s==addr) emit_mov(s,temp);
3103       #endif
3104       #ifdef R29_HACK
3105       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3106       #endif
3107       {
3108         jaddr=(int)out;
3109         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3110         // Hint to branch predictor that the branch is unlikely to be taken
3111         if(rs1[i]>=28)
3112           emit_jno_unlikely(0);
3113         else
3114         #endif
3115         emit_jno(0);
3116       }
3117     }
3118   }else{ // using tlb
3119     int x=0;
3120     if (opcode[i]==0x28) x=3; // SB
3121     if (opcode[i]==0x29) x=2; // SH
3122     map=get_reg(i_regs->regmap,TLREG);
3123     assert(map>=0);
3124     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3125     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3126   }
3127
3128   if (opcode[i]==0x28) { // SB
3129     if(!c||memtarget) {
3130       int x=0;
3131 #ifdef BIG_ENDIAN_MIPS
3132       if(!c) emit_xorimm(addr,3,temp);
3133       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3134 #else
3135       if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3136       else if (addr!=temp) emit_mov(addr,temp);
3137 #endif
3138       //gen_tlb_addr_w(temp,map);
3139       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3140       emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3141     }
3142     type=STOREB_STUB;
3143   }
3144   if (opcode[i]==0x29) { // SH
3145     if(!c||memtarget) {
3146       int x=0;
3147 #ifdef BIG_ENDIAN_MIPS
3148       if(!c) emit_xorimm(addr,2,temp);
3149       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3150 #else
3151       if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3152       else if (addr!=temp) emit_mov(addr,temp);
3153 #endif
3154       //#ifdef
3155       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3156       //#else
3157       if(map>=0) {
3158         gen_tlb_addr_w(temp,map);
3159         emit_writehword_indexed(tl,x,temp);
3160       }else
3161         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3162     }
3163     type=STOREH_STUB;
3164   }
3165   if (opcode[i]==0x2B) { // SW
3166     if(!c||memtarget)
3167       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3168       emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3169     type=STOREW_STUB;
3170   }
3171   if (opcode[i]==0x3F) { // SD
3172     if(!c||memtarget) {
3173       if(rs2[i]) {
3174         assert(th>=0);
3175         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3176         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3177         emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3178       }else{
3179         // Store zero
3180         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3181         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3182         emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3183       }
3184     }
3185     type=STORED_STUB;
3186   }
3187   if(!using_tlb&&(!c||memtarget))
3188     // addr could be a temp, make sure it survives STORE*_STUB
3189     reglist|=1<<addr;
3190   if(jaddr) {
3191     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3192   } else if(!memtarget) {
3193     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3194   }
3195   if(!using_tlb) {
3196     if(!c||memtarget) {
3197       #ifdef DESTRUCTIVE_SHIFT
3198       // The x86 shift operation is 'destructive'; it overwrites the
3199       // source register, so we need to make a copy first and use that.
3200       addr=temp;
3201       #endif
3202       #if defined(HOST_IMM8)
3203       int ir=get_reg(i_regs->regmap,INVCP);
3204       assert(ir>=0);
3205       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3206       #else
3207       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3208       #endif
3209       jaddr2=(int)out;
3210       emit_jne(0);
3211       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3212     }
3213   }
3214   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3215   //if(opcode[i]==0x2B || opcode[i]==0x28)
3216   //if(opcode[i]==0x2B || opcode[i]==0x29)
3217   //if(opcode[i]==0x2B)
3218   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3219   {
3220     //emit_pusha();
3221     save_regs(0x100f);
3222         emit_readword((int)&last_count,ECX);
3223         #ifdef __i386__
3224         if(get_reg(i_regs->regmap,CCREG)<0)
3225           emit_loadreg(CCREG,HOST_CCREG);
3226         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3227         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3228         emit_writeword(HOST_CCREG,(int)&Count);
3229         #endif
3230         #ifdef __arm__
3231         if(get_reg(i_regs->regmap,CCREG)<0)
3232           emit_loadreg(CCREG,0);
3233         else
3234           emit_mov(HOST_CCREG,0);
3235         emit_add(0,ECX,0);
3236         emit_addimm(0,2*ccadj[i],0);
3237         emit_writeword(0,(int)&Count);
3238         #endif
3239     emit_call((int)memdebug);
3240     //emit_popa();
3241     restore_regs(0x100f);
3242   }/**/
3243 }
3244
3245 void storelr_assemble(int i,struct regstat *i_regs)
3246 {
3247   int s,th,tl;
3248   int temp;
3249   int temp2;
3250   int offset;
3251   int jaddr=0,jaddr2;
3252   int case1,case2,case3;
3253   int done0,done1,done2;
3254   int memtarget,c=0;
3255   int agr=AGEN1+(i&1);
3256   u_int hr,reglist=0;
3257   th=get_reg(i_regs->regmap,rs2[i]|64);
3258   tl=get_reg(i_regs->regmap,rs2[i]);
3259   s=get_reg(i_regs->regmap,rs1[i]);
3260   temp=get_reg(i_regs->regmap,agr);
3261   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3262   offset=imm[i];
3263   if(s>=0) {
3264     c=(i_regs->isconst>>s)&1;
3265     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3266     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3267   }
3268   assert(tl>=0);
3269   for(hr=0;hr<HOST_REGS;hr++) {
3270     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3271   }
3272   assert(temp>=0);
3273   if(!using_tlb) {
3274     if(!c) {
3275       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3276       if(!offset&&s!=temp) emit_mov(s,temp);
3277       jaddr=(int)out;
3278       emit_jno(0);
3279     }
3280     else
3281     {
3282       if(!memtarget||!rs1[i]) {
3283         jaddr=(int)out;
3284         emit_jmp(0);
3285       }
3286     }
3287     #ifdef RAM_OFFSET
3288     int map=get_reg(i_regs->regmap,ROREG);
3289     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3290     gen_tlb_addr_w(temp,map);
3291     #else
3292     if((u_int)rdram!=0x80000000)
3293       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3294     #endif
3295   }else{ // using tlb
3296     int map=get_reg(i_regs->regmap,TLREG);
3297     assert(map>=0);
3298     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3299     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3300     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3301     if(!jaddr&&!memtarget) {
3302       jaddr=(int)out;
3303       emit_jmp(0);
3304     }
3305     gen_tlb_addr_w(temp,map);
3306   }
3307
3308   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3309     temp2=get_reg(i_regs->regmap,FTEMP);
3310     if(!rs2[i]) temp2=th=tl;
3311   }
3312
3313 #ifndef BIG_ENDIAN_MIPS
3314     emit_xorimm(temp,3,temp);
3315 #endif
3316   emit_testimm(temp,2);
3317   case2=(int)out;
3318   emit_jne(0);
3319   emit_testimm(temp,1);
3320   case1=(int)out;
3321   emit_jne(0);
3322   // 0
3323   if (opcode[i]==0x2A) { // SWL
3324     emit_writeword_indexed(tl,0,temp);
3325   }
3326   if (opcode[i]==0x2E) { // SWR
3327     emit_writebyte_indexed(tl,3,temp);
3328   }
3329   if (opcode[i]==0x2C) { // SDL
3330     emit_writeword_indexed(th,0,temp);
3331     if(rs2[i]) emit_mov(tl,temp2);
3332   }
3333   if (opcode[i]==0x2D) { // SDR
3334     emit_writebyte_indexed(tl,3,temp);
3335     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3336   }
3337   done0=(int)out;
3338   emit_jmp(0);
3339   // 1
3340   set_jump_target(case1,(int)out);
3341   if (opcode[i]==0x2A) { // SWL
3342     // Write 3 msb into three least significant bytes
3343     if(rs2[i]) emit_rorimm(tl,8,tl);
3344     emit_writehword_indexed(tl,-1,temp);
3345     if(rs2[i]) emit_rorimm(tl,16,tl);
3346     emit_writebyte_indexed(tl,1,temp);
3347     if(rs2[i]) emit_rorimm(tl,8,tl);
3348   }
3349   if (opcode[i]==0x2E) { // SWR
3350     // Write two lsb into two most significant bytes
3351     emit_writehword_indexed(tl,1,temp);
3352   }
3353   if (opcode[i]==0x2C) { // SDL
3354     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3355     // Write 3 msb into three least significant bytes
3356     if(rs2[i]) emit_rorimm(th,8,th);
3357     emit_writehword_indexed(th,-1,temp);
3358     if(rs2[i]) emit_rorimm(th,16,th);
3359     emit_writebyte_indexed(th,1,temp);
3360     if(rs2[i]) emit_rorimm(th,8,th);
3361   }
3362   if (opcode[i]==0x2D) { // SDR
3363     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3364     // Write two lsb into two most significant bytes
3365     emit_writehword_indexed(tl,1,temp);
3366   }
3367   done1=(int)out;
3368   emit_jmp(0);
3369   // 2
3370   set_jump_target(case2,(int)out);
3371   emit_testimm(temp,1);
3372   case3=(int)out;
3373   emit_jne(0);
3374   if (opcode[i]==0x2A) { // SWL
3375     // Write two msb into two least significant bytes
3376     if(rs2[i]) emit_rorimm(tl,16,tl);
3377     emit_writehword_indexed(tl,-2,temp);
3378     if(rs2[i]) emit_rorimm(tl,16,tl);
3379   }
3380   if (opcode[i]==0x2E) { // SWR
3381     // Write 3 lsb into three most significant bytes
3382     emit_writebyte_indexed(tl,-1,temp);
3383     if(rs2[i]) emit_rorimm(tl,8,tl);
3384     emit_writehword_indexed(tl,0,temp);
3385     if(rs2[i]) emit_rorimm(tl,24,tl);
3386   }
3387   if (opcode[i]==0x2C) { // SDL
3388     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3389     // Write two msb into two least significant bytes
3390     if(rs2[i]) emit_rorimm(th,16,th);
3391     emit_writehword_indexed(th,-2,temp);
3392     if(rs2[i]) emit_rorimm(th,16,th);
3393   }
3394   if (opcode[i]==0x2D) { // SDR
3395     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3396     // Write 3 lsb into three most significant bytes
3397     emit_writebyte_indexed(tl,-1,temp);
3398     if(rs2[i]) emit_rorimm(tl,8,tl);
3399     emit_writehword_indexed(tl,0,temp);
3400     if(rs2[i]) emit_rorimm(tl,24,tl);
3401   }
3402   done2=(int)out;
3403   emit_jmp(0);
3404   // 3
3405   set_jump_target(case3,(int)out);
3406   if (opcode[i]==0x2A) { // SWL
3407     // Write msb into least significant byte
3408     if(rs2[i]) emit_rorimm(tl,24,tl);
3409     emit_writebyte_indexed(tl,-3,temp);
3410     if(rs2[i]) emit_rorimm(tl,8,tl);
3411   }
3412   if (opcode[i]==0x2E) { // SWR
3413     // Write entire word
3414     emit_writeword_indexed(tl,-3,temp);
3415   }
3416   if (opcode[i]==0x2C) { // SDL
3417     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3418     // Write msb into least significant byte
3419     if(rs2[i]) emit_rorimm(th,24,th);
3420     emit_writebyte_indexed(th,-3,temp);
3421     if(rs2[i]) emit_rorimm(th,8,th);
3422   }
3423   if (opcode[i]==0x2D) { // SDR
3424     if(rs2[i]) emit_mov(th,temp2);
3425     // Write entire word
3426     emit_writeword_indexed(tl,-3,temp);
3427   }
3428   set_jump_target(done0,(int)out);
3429   set_jump_target(done1,(int)out);
3430   set_jump_target(done2,(int)out);
3431   if (opcode[i]==0x2C) { // SDL
3432     emit_testimm(temp,4);
3433     done0=(int)out;
3434     emit_jne(0);
3435     emit_andimm(temp,~3,temp);
3436     emit_writeword_indexed(temp2,4,temp);
3437     set_jump_target(done0,(int)out);
3438   }
3439   if (opcode[i]==0x2D) { // SDR
3440     emit_testimm(temp,4);
3441     done0=(int)out;
3442     emit_jeq(0);
3443     emit_andimm(temp,~3,temp);
3444     emit_writeword_indexed(temp2,-4,temp);
3445     set_jump_target(done0,(int)out);
3446   }
3447   if(!c||!memtarget)
3448     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3449   if(!using_tlb) {
3450     #ifdef RAM_OFFSET
3451     int map=get_reg(i_regs->regmap,ROREG);
3452     if(map<0) map=HOST_TEMPREG;
3453     gen_orig_addr_w(temp,map);
3454     #else
3455     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3456     #endif
3457     #if defined(HOST_IMM8)
3458     int ir=get_reg(i_regs->regmap,INVCP);
3459     assert(ir>=0);
3460     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3461     #else
3462     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3463     #endif
3464     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3465     emit_callne(invalidate_addr_reg[temp]);
3466     #else
3467     jaddr2=(int)out;
3468     emit_jne(0);
3469     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3470     #endif
3471   }
3472   /*
3473     emit_pusha();
3474     //save_regs(0x100f);
3475         emit_readword((int)&last_count,ECX);
3476         if(get_reg(i_regs->regmap,CCREG)<0)
3477           emit_loadreg(CCREG,HOST_CCREG);
3478         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3479         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3480         emit_writeword(HOST_CCREG,(int)&Count);
3481     emit_call((int)memdebug);
3482     emit_popa();
3483     //restore_regs(0x100f);
3484   /**/
3485 }
3486
3487 void c1ls_assemble(int i,struct regstat *i_regs)
3488 {
3489 #ifndef DISABLE_COP1
3490   int s,th,tl;
3491   int temp,ar;
3492   int map=-1;
3493   int offset;
3494   int c=0;
3495   int jaddr,jaddr2=0,jaddr3,type;
3496   int agr=AGEN1+(i&1);
3497   u_int hr,reglist=0;
3498   th=get_reg(i_regs->regmap,FTEMP|64);
3499   tl=get_reg(i_regs->regmap,FTEMP);
3500   s=get_reg(i_regs->regmap,rs1[i]);
3501   temp=get_reg(i_regs->regmap,agr);
3502   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3503   offset=imm[i];
3504   assert(tl>=0);
3505   assert(rs1[i]>0);
3506   assert(temp>=0);
3507   for(hr=0;hr<HOST_REGS;hr++) {
3508     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3509   }
3510   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3511   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3512   {
3513     // Loads use a temporary register which we need to save
3514     reglist|=1<<temp;
3515   }
3516   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3517     ar=temp;
3518   else // LWC1/LDC1
3519     ar=tl;
3520   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3521   //else c=(i_regs->wasconst>>s)&1;
3522   if(s>=0) c=(i_regs->wasconst>>s)&1;
3523   // Check cop1 unusable
3524   if(!cop1_usable) {
3525     signed char rs=get_reg(i_regs->regmap,CSREG);
3526     assert(rs>=0);
3527     emit_testimm(rs,0x20000000);
3528     jaddr=(int)out;
3529     emit_jeq(0);
3530     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3531     cop1_usable=1;
3532   }
3533   if (opcode[i]==0x39) { // SWC1 (get float address)
3534     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3535   }
3536   if (opcode[i]==0x3D) { // SDC1 (get double address)
3537     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3538   }
3539   // Generate address + offset
3540   if(!using_tlb) {
3541     if(!c)
3542       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3543   }
3544   else
3545   {
3546     map=get_reg(i_regs->regmap,TLREG);
3547     assert(map>=0);
3548     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3549       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3550     }
3551     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3552       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3553     }
3554   }
3555   if (opcode[i]==0x39) { // SWC1 (read float)
3556     emit_readword_indexed(0,tl,tl);
3557   }
3558   if (opcode[i]==0x3D) { // SDC1 (read double)
3559     emit_readword_indexed(4,tl,th);
3560     emit_readword_indexed(0,tl,tl);
3561   }
3562   if (opcode[i]==0x31) { // LWC1 (get target address)
3563     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3564   }
3565   if (opcode[i]==0x35) { // LDC1 (get target address)
3566     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3567   }
3568   if(!using_tlb) {
3569     if(!c) {
3570       jaddr2=(int)out;
3571       emit_jno(0);
3572     }
3573     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3574       jaddr2=(int)out;
3575       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3576     }
3577     #ifdef DESTRUCTIVE_SHIFT
3578     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3579       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3580     }
3581     #endif
3582   }else{
3583     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3584       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3585     }
3586     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3587       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3588     }
3589   }
3590   if (opcode[i]==0x31) { // LWC1
3591     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3592     //gen_tlb_addr_r(ar,map);
3593     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3594     #ifdef HOST_IMM_ADDR32
3595     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3596     else
3597     #endif
3598     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3599     type=LOADW_STUB;
3600   }
3601   if (opcode[i]==0x35) { // LDC1
3602     assert(th>=0);
3603     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3604     //gen_tlb_addr_r(ar,map);
3605     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3606     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3607     #ifdef HOST_IMM_ADDR32
3608     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3609     else
3610     #endif
3611     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3612     type=LOADD_STUB;
3613   }
3614   if (opcode[i]==0x39) { // SWC1
3615     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3616     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3617     type=STOREW_STUB;
3618   }
3619   if (opcode[i]==0x3D) { // SDC1
3620     assert(th>=0);
3621     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3622     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3623     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3624     type=STORED_STUB;
3625   }
3626   if(!using_tlb) {
3627     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3628       #ifndef DESTRUCTIVE_SHIFT
3629       temp=offset||c||s<0?ar:s;
3630       #endif
3631       #if defined(HOST_IMM8)
3632       int ir=get_reg(i_regs->regmap,INVCP);
3633       assert(ir>=0);
3634       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3635       #else
3636       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3637       #endif
3638       jaddr3=(int)out;
3639       emit_jne(0);
3640       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3641     }
3642   }
3643   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3644   if (opcode[i]==0x31) { // LWC1 (write float)
3645     emit_writeword_indexed(tl,0,temp);
3646   }
3647   if (opcode[i]==0x35) { // LDC1 (write double)
3648     emit_writeword_indexed(th,4,temp);
3649     emit_writeword_indexed(tl,0,temp);
3650   }
3651   //if(opcode[i]==0x39)
3652   /*if(opcode[i]==0x39||opcode[i]==0x31)
3653   {
3654     emit_pusha();
3655         emit_readword((int)&last_count,ECX);
3656         if(get_reg(i_regs->regmap,CCREG)<0)
3657           emit_loadreg(CCREG,HOST_CCREG);
3658         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3659         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3660         emit_writeword(HOST_CCREG,(int)&Count);
3661     emit_call((int)memdebug);
3662     emit_popa();
3663   }/**/
3664 #else
3665   cop1_unusable(i, i_regs);
3666 #endif
3667 }
3668
3669 void c2ls_assemble(int i,struct regstat *i_regs)
3670 {
3671   int s,tl;
3672   int ar;
3673   int offset;
3674   int memtarget=0,c=0;
3675   int jaddr,jaddr2=0,jaddr3,type;
3676   int agr=AGEN1+(i&1);
3677   u_int hr,reglist=0;
3678   u_int copr=(source[i]>>16)&0x1f;
3679   s=get_reg(i_regs->regmap,rs1[i]);
3680   tl=get_reg(i_regs->regmap,FTEMP);
3681   offset=imm[i];
3682   assert(rs1[i]>0);
3683   assert(tl>=0);
3684   assert(!using_tlb);
3685
3686   for(hr=0;hr<HOST_REGS;hr++) {
3687     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3688   }
3689   if(i_regs->regmap[HOST_CCREG]==CCREG)
3690     reglist&=~(1<<HOST_CCREG);
3691
3692   // get the address
3693   if (opcode[i]==0x3a) { // SWC2
3694     ar=get_reg(i_regs->regmap,agr);
3695     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3696     reglist|=1<<ar;
3697   } else { // LWC2
3698     ar=tl;
3699   }
3700   if(s>=0) c=(i_regs->wasconst>>s)&1;
3701   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3702   if (!offset&&!c&&s>=0) ar=s;
3703   assert(ar>=0);
3704
3705   if (opcode[i]==0x3a) { // SWC2
3706     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3707     type=STOREW_STUB;
3708   }
3709   else
3710     type=LOADW_STUB;
3711
3712   if(c&&!memtarget) {
3713     jaddr2=(int)out;
3714     emit_jmp(0); // inline_readstub/inline_writestub?
3715   }
3716   else {
3717     if(!c) {
3718       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3719       jaddr2=(int)out;
3720       emit_jno(0);
3721     }
3722     if (opcode[i]==0x32) { // LWC2
3723       #ifdef HOST_IMM_ADDR32
3724       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3725       else
3726       #endif
3727       emit_readword_indexed(0,ar,tl);
3728     }
3729     if (opcode[i]==0x3a) { // SWC2
3730       #ifdef DESTRUCTIVE_SHIFT
3731       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3732       #endif
3733       emit_writeword_indexed(tl,0,ar);
3734     }
3735   }
3736   if(jaddr2)
3737     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3738   if (opcode[i]==0x3a) { // SWC2
3739 #if defined(HOST_IMM8)
3740     int ir=get_reg(i_regs->regmap,INVCP);
3741     assert(ir>=0);
3742     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3743 #else
3744     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3745 #endif
3746     jaddr3=(int)out;
3747     emit_jne(0);
3748     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3749   }
3750   if (opcode[i]==0x32) { // LWC2
3751     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3752   }
3753 }
3754
3755 #ifndef multdiv_assemble
3756 void multdiv_assemble(int i,struct regstat *i_regs)
3757 {
3758   printf("Need multdiv_assemble for this architecture.\n");
3759   exit(1);
3760 }
3761 #endif
3762
3763 void mov_assemble(int i,struct regstat *i_regs)
3764 {
3765   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3766   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3767   if(rt1[i]) {
3768     signed char sh,sl,th,tl;
3769     th=get_reg(i_regs->regmap,rt1[i]|64);
3770     tl=get_reg(i_regs->regmap,rt1[i]);
3771     //assert(tl>=0);
3772     if(tl>=0) {
3773       sh=get_reg(i_regs->regmap,rs1[i]|64);
3774       sl=get_reg(i_regs->regmap,rs1[i]);
3775       if(sl>=0) emit_mov(sl,tl);
3776       else emit_loadreg(rs1[i],tl);
3777       if(th>=0) {
3778         if(sh>=0) emit_mov(sh,th);
3779         else emit_loadreg(rs1[i]|64,th);
3780       }
3781     }
3782   }
3783 }
3784
3785 #ifndef fconv_assemble
3786 void fconv_assemble(int i,struct regstat *i_regs)
3787 {
3788   printf("Need fconv_assemble for this architecture.\n");
3789   exit(1);
3790 }
3791 #endif
3792
3793 #if 0
3794 void float_assemble(int i,struct regstat *i_regs)
3795 {
3796   printf("Need float_assemble for this architecture.\n");
3797   exit(1);
3798 }
3799 #endif
3800
3801 void syscall_assemble(int i,struct regstat *i_regs)
3802 {
3803   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3804   assert(ccreg==HOST_CCREG);
3805   assert(!is_delayslot);
3806   emit_movimm(start+i*4,EAX); // Get PC
3807   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3808   emit_jmp((int)jump_syscall_hle); // XXX
3809 }
3810
3811 void hlecall_assemble(int i,struct regstat *i_regs)
3812 {
3813   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3814   assert(ccreg==HOST_CCREG);
3815   assert(!is_delayslot);
3816   emit_movimm(start+i*4+4,0); // Get PC
3817   emit_movimm((int)psxHLEt[source[i]&7],1);
3818   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3819   emit_jmp((int)jump_hlecall);
3820 }
3821
3822 void intcall_assemble(int i,struct regstat *i_regs)
3823 {
3824   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3825   assert(ccreg==HOST_CCREG);
3826   assert(!is_delayslot);
3827   emit_movimm(start+i*4,0); // Get PC
3828   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3829   emit_jmp((int)jump_intcall);
3830 }
3831
3832 void ds_assemble(int i,struct regstat *i_regs)
3833 {
3834   is_delayslot=1;
3835   switch(itype[i]) {
3836     case ALU:
3837       alu_assemble(i,i_regs);break;
3838     case IMM16:
3839       imm16_assemble(i,i_regs);break;
3840     case SHIFT:
3841       shift_assemble(i,i_regs);break;
3842     case SHIFTIMM:
3843       shiftimm_assemble(i,i_regs);break;
3844     case LOAD:
3845       load_assemble(i,i_regs);break;
3846     case LOADLR:
3847       loadlr_assemble(i,i_regs);break;
3848     case STORE:
3849       store_assemble(i,i_regs);break;
3850     case STORELR:
3851       storelr_assemble(i,i_regs);break;
3852     case COP0:
3853       cop0_assemble(i,i_regs);break;
3854     case COP1:
3855       cop1_assemble(i,i_regs);break;
3856     case C1LS:
3857       c1ls_assemble(i,i_regs);break;
3858     case COP2:
3859       cop2_assemble(i,i_regs);break;
3860     case C2LS:
3861       c2ls_assemble(i,i_regs);break;
3862     case C2OP:
3863       c2op_assemble(i,i_regs);break;
3864     case FCONV:
3865       fconv_assemble(i,i_regs);break;
3866     case FLOAT:
3867       float_assemble(i,i_regs);break;
3868     case FCOMP:
3869       fcomp_assemble(i,i_regs);break;
3870     case MULTDIV:
3871       multdiv_assemble(i,i_regs);break;
3872     case MOV:
3873       mov_assemble(i,i_regs);break;
3874     case SYSCALL:
3875     case HLECALL:
3876     case INTCALL:
3877     case SPAN:
3878     case UJUMP:
3879     case RJUMP:
3880     case CJUMP:
3881     case SJUMP:
3882     case FJUMP:
3883       printf("Jump in the delay slot.  This is probably a bug.\n");
3884   }
3885   is_delayslot=0;
3886 }
3887
3888 // Is the branch target a valid internal jump?
3889 int internal_branch(uint64_t i_is32,int addr)
3890 {
3891   if(addr&1) return 0; // Indirect (register) jump
3892   if(addr>=start && addr<start+slen*4-4)
3893   {
3894     int t=(addr-start)>>2;
3895     // Delay slots are not valid branch targets
3896     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3897     // 64 -> 32 bit transition requires a recompile
3898     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3899     {
3900       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3901       else printf("optimizable: yes\n");
3902     }*/
3903     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3904 #ifndef FORCE32
3905     if(requires_32bit[t]&~i_is32) return 0;
3906     else
3907 #endif
3908       return 1;
3909   }
3910   return 0;
3911 }
3912
3913 #ifndef wb_invalidate
3914 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3915   uint64_t u,uint64_t uu)
3916 {
3917   int hr;
3918   for(hr=0;hr<HOST_REGS;hr++) {
3919     if(hr!=EXCLUDE_REG) {
3920       if(pre[hr]!=entry[hr]) {
3921         if(pre[hr]>=0) {
3922           if((dirty>>hr)&1) {
3923             if(get_reg(entry,pre[hr])<0) {
3924               if(pre[hr]<64) {
3925                 if(!((u>>pre[hr])&1)) {
3926                   emit_storereg(pre[hr],hr);
3927                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3928                     emit_sarimm(hr,31,hr);
3929                     emit_storereg(pre[hr]|64,hr);
3930                   }
3931                 }
3932               }else{
3933                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3934                   emit_storereg(pre[hr],hr);
3935                 }
3936               }
3937             }
3938           }
3939         }
3940       }
3941     }
3942   }
3943   // Move from one register to another (no writeback)
3944   for(hr=0;hr<HOST_REGS;hr++) {
3945     if(hr!=EXCLUDE_REG) {
3946       if(pre[hr]!=entry[hr]) {
3947         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3948           int nr;
3949           if((nr=get_reg(entry,pre[hr]))>=0) {
3950             emit_mov(hr,nr);
3951           }
3952         }
3953       }
3954     }
3955   }
3956 }
3957 #endif
3958
3959 // Load the specified registers
3960 // This only loads the registers given as arguments because
3961 // we don't want to load things that will be overwritten
3962 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3963 {
3964   int hr;
3965   // Load 32-bit regs
3966   for(hr=0;hr<HOST_REGS;hr++) {
3967     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3968       if(entry[hr]!=regmap[hr]) {
3969         if(regmap[hr]==rs1||regmap[hr]==rs2)
3970         {
3971           if(regmap[hr]==0) {
3972             emit_zeroreg(hr);
3973           }
3974           else
3975           {
3976             emit_loadreg(regmap[hr],hr);
3977           }
3978         }
3979       }
3980     }
3981   }
3982   //Load 64-bit regs
3983   for(hr=0;hr<HOST_REGS;hr++) {
3984     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3985       if(entry[hr]!=regmap[hr]) {
3986         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3987         {
3988           assert(regmap[hr]!=64);
3989           if((is32>>(regmap[hr]&63))&1) {
3990             int lr=get_reg(regmap,regmap[hr]-64);
3991             if(lr>=0)
3992               emit_sarimm(lr,31,hr);
3993             else
3994               emit_loadreg(regmap[hr],hr);
3995           }
3996           else
3997           {
3998             emit_loadreg(regmap[hr],hr);
3999           }
4000         }
4001       }
4002     }
4003   }
4004 }
4005
4006 // Load registers prior to the start of a loop
4007 // so that they are not loaded within the loop
4008 static void loop_preload(signed char pre[],signed char entry[])
4009 {
4010   int hr;
4011   for(hr=0;hr<HOST_REGS;hr++) {
4012     if(hr!=EXCLUDE_REG) {
4013       if(pre[hr]!=entry[hr]) {
4014         if(entry[hr]>=0) {
4015           if(get_reg(pre,entry[hr])<0) {
4016             assem_debug("loop preload:\n");
4017             //printf("loop preload: %d\n",hr);
4018             if(entry[hr]==0) {
4019               emit_zeroreg(hr);
4020             }
4021             else if(entry[hr]<TEMPREG)
4022             {
4023               emit_loadreg(entry[hr],hr);
4024             }
4025             else if(entry[hr]-64<TEMPREG)
4026             {
4027               emit_loadreg(entry[hr],hr);
4028             }
4029           }
4030         }
4031       }
4032     }
4033   }
4034 }
4035
4036 // Generate address for load/store instruction
4037 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4038 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4039 {
4040   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4041     int ra;
4042     int agr=AGEN1+(i&1);
4043     int mgr=MGEN1+(i&1);
4044     if(itype[i]==LOAD) {
4045       ra=get_reg(i_regs->regmap,rt1[i]);
4046       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4047       assert(ra>=0);
4048     }
4049     if(itype[i]==LOADLR) {
4050       ra=get_reg(i_regs->regmap,FTEMP);
4051     }
4052     if(itype[i]==STORE||itype[i]==STORELR) {
4053       ra=get_reg(i_regs->regmap,agr);
4054       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4055     }
4056     if(itype[i]==C1LS||itype[i]==C2LS) {
4057       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4058         ra=get_reg(i_regs->regmap,FTEMP);
4059       else { // SWC1/SDC1/SWC2/SDC2
4060         ra=get_reg(i_regs->regmap,agr);
4061         if(ra<0) ra=get_reg(i_regs->regmap,-1);
4062       }
4063     }
4064     int rs=get_reg(i_regs->regmap,rs1[i]);
4065     int rm=get_reg(i_regs->regmap,TLREG);
4066     if(ra>=0) {
4067       int offset=imm[i];
4068       int c=(i_regs->wasconst>>rs)&1;
4069       if(rs1[i]==0) {
4070         // Using r0 as a base address
4071         /*if(rm>=0) {
4072           if(!entry||entry[rm]!=mgr) {
4073             generate_map_const(offset,rm);
4074           } // else did it in the previous cycle
4075         }*/
4076         if(!entry||entry[ra]!=agr) {
4077           if (opcode[i]==0x22||opcode[i]==0x26) {
4078             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4079           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4080             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4081           }else{
4082             emit_movimm(offset,ra);
4083           }
4084         } // else did it in the previous cycle
4085       }
4086       else if(rs<0) {
4087         if(!entry||entry[ra]!=rs1[i])
4088           emit_loadreg(rs1[i],ra);
4089         //if(!entry||entry[ra]!=rs1[i])
4090         //  printf("poor load scheduling!\n");
4091       }
4092       else if(c) {
4093         if(rm>=0) {
4094           if(!entry||entry[rm]!=mgr) {
4095             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4096               // Stores to memory go thru the mapper to detect self-modifying
4097               // code, loads don't.
4098               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4099                  (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4100                 generate_map_const(constmap[i][rs]+offset,rm);
4101             }else{
4102               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4103                 generate_map_const(constmap[i][rs]+offset,rm);
4104             }
4105           }
4106         }
4107         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4108           if(!entry||entry[ra]!=agr) {
4109             if (opcode[i]==0x22||opcode[i]==0x26) {
4110               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4111             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4112               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4113             }else{
4114               #ifdef HOST_IMM_ADDR32
4115               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4116                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4117               #endif
4118               emit_movimm(constmap[i][rs]+offset,ra);
4119             }
4120           } // else did it in the previous cycle
4121         } // else load_consts already did it
4122       }
4123       if(offset&&!c&&rs1[i]) {
4124         if(rs>=0) {
4125           emit_addimm(rs,offset,ra);
4126         }else{
4127           emit_addimm(ra,offset,ra);
4128         }
4129       }
4130     }
4131   }
4132   // Preload constants for next instruction
4133   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4134     int agr,ra;
4135     #ifndef HOST_IMM_ADDR32
4136     // Mapper entry
4137     agr=MGEN1+((i+1)&1);
4138     ra=get_reg(i_regs->regmap,agr);
4139     if(ra>=0) {
4140       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4141       int offset=imm[i+1];
4142       int c=(regs[i+1].wasconst>>rs)&1;
4143       if(c) {
4144         if(itype[i+1]==STORE||itype[i+1]==STORELR
4145            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4146           // Stores to memory go thru the mapper to detect self-modifying
4147           // code, loads don't.
4148           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4149              (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4150             generate_map_const(constmap[i+1][rs]+offset,ra);
4151         }else{
4152           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4153             generate_map_const(constmap[i+1][rs]+offset,ra);
4154         }
4155       }
4156       /*else if(rs1[i]==0) {
4157         generate_map_const(offset,ra);
4158       }*/
4159     }
4160     #endif
4161     // Actual address
4162     agr=AGEN1+((i+1)&1);
4163     ra=get_reg(i_regs->regmap,agr);
4164     if(ra>=0) {
4165       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4166       int offset=imm[i+1];
4167       int c=(regs[i+1].wasconst>>rs)&1;
4168       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4169         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4170           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4171         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4172           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4173         }else{
4174           #ifdef HOST_IMM_ADDR32
4175           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4176              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4177           #endif
4178           emit_movimm(constmap[i+1][rs]+offset,ra);
4179         }
4180       }
4181       else if(rs1[i+1]==0) {
4182         // Using r0 as a base address
4183         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4184           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4185         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4186           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4187         }else{
4188           emit_movimm(offset,ra);
4189         }
4190       }
4191     }
4192   }
4193 }
4194
4195 int get_final_value(int hr, int i, int *value)
4196 {
4197   int reg=regs[i].regmap[hr];
4198   while(i<slen-1) {
4199     if(regs[i+1].regmap[hr]!=reg) break;
4200     if(!((regs[i+1].isconst>>hr)&1)) break;
4201     if(bt[i+1]) break;
4202     i++;
4203   }
4204   if(i<slen-1) {
4205     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4206       *value=constmap[i][hr];
4207       return 1;
4208     }
4209     if(!bt[i+1]) {
4210       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4211         // Load in delay slot, out-of-order execution
4212         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4213         {
4214           #ifdef HOST_IMM_ADDR32
4215           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4216           #endif
4217           // Precompute load address
4218           *value=constmap[i][hr]+imm[i+2];
4219           return 1;
4220         }
4221       }
4222       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4223       {
4224         #ifdef HOST_IMM_ADDR32
4225         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4226         #endif
4227         // Precompute load address
4228         *value=constmap[i][hr]+imm[i+1];
4229         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4230         return 1;
4231       }
4232     }
4233   }
4234   *value=constmap[i][hr];
4235   //printf("c=%x\n",(int)constmap[i][hr]);
4236   if(i==slen-1) return 1;
4237   if(reg<64) {
4238     return !((unneeded_reg[i+1]>>reg)&1);
4239   }else{
4240     return !((unneeded_reg_upper[i+1]>>reg)&1);
4241   }
4242 }
4243
4244 // Load registers with known constants
4245 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4246 {
4247   int hr;
4248   // Load 32-bit regs
4249   for(hr=0;hr<HOST_REGS;hr++) {
4250     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4251       //if(entry[hr]!=regmap[hr]) {
4252       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4253         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4254           int value;
4255           if(get_final_value(hr,i,&value)) {
4256             if(value==0) {
4257               emit_zeroreg(hr);
4258             }
4259             else {
4260               emit_movimm(value,hr);
4261             }
4262           }
4263         }
4264       }
4265     }
4266   }
4267   // Load 64-bit regs
4268   for(hr=0;hr<HOST_REGS;hr++) {
4269     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4270       //if(entry[hr]!=regmap[hr]) {
4271       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4272         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4273           if((is32>>(regmap[hr]&63))&1) {
4274             int lr=get_reg(regmap,regmap[hr]-64);
4275             assert(lr>=0);
4276             emit_sarimm(lr,31,hr);
4277           }
4278           else
4279           {
4280             int value;
4281             if(get_final_value(hr,i,&value)) {
4282               if(value==0) {
4283                 emit_zeroreg(hr);
4284               }
4285               else {
4286                 emit_movimm(value,hr);
4287               }
4288             }
4289           }
4290         }
4291       }
4292     }
4293   }
4294 }
4295 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4296 {
4297   int hr;
4298   // Load 32-bit regs
4299   for(hr=0;hr<HOST_REGS;hr++) {
4300     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4301       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4302         int value=constmap[i][hr];
4303         if(value==0) {
4304           emit_zeroreg(hr);
4305         }
4306         else {
4307           emit_movimm(value,hr);
4308         }
4309       }
4310     }
4311   }
4312   // Load 64-bit regs
4313   for(hr=0;hr<HOST_REGS;hr++) {
4314     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4315       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4316         if((is32>>(regmap[hr]&63))&1) {
4317           int lr=get_reg(regmap,regmap[hr]-64);
4318           assert(lr>=0);
4319           emit_sarimm(lr,31,hr);
4320         }
4321         else
4322         {
4323           int value=constmap[i][hr];
4324           if(value==0) {
4325             emit_zeroreg(hr);
4326           }
4327           else {
4328             emit_movimm(value,hr);
4329           }
4330         }
4331       }
4332     }
4333   }
4334 }
4335
4336 // Write out all dirty registers (except cycle count)
4337 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4338 {
4339   int hr;
4340   for(hr=0;hr<HOST_REGS;hr++) {
4341     if(hr!=EXCLUDE_REG) {
4342       if(i_regmap[hr]>0) {
4343         if(i_regmap[hr]!=CCREG) {
4344           if((i_dirty>>hr)&1) {
4345             if(i_regmap[hr]<64) {
4346               emit_storereg(i_regmap[hr],hr);
4347 #ifndef FORCE32
4348               if( ((i_is32>>i_regmap[hr])&1) ) {
4349                 #ifdef DESTRUCTIVE_WRITEBACK
4350                 emit_sarimm(hr,31,hr);
4351                 emit_storereg(i_regmap[hr]|64,hr);
4352                 #else
4353                 emit_sarimm(hr,31,HOST_TEMPREG);
4354                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4355                 #endif
4356               }
4357 #endif
4358             }else{
4359               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4360                 emit_storereg(i_regmap[hr],hr);
4361               }
4362             }
4363           }
4364         }
4365       }
4366     }
4367   }
4368 }
4369 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4370 // This writes the registers not written by store_regs_bt
4371 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4372 {
4373   int hr;
4374   int t=(addr-start)>>2;
4375   for(hr=0;hr<HOST_REGS;hr++) {
4376     if(hr!=EXCLUDE_REG) {
4377       if(i_regmap[hr]>0) {
4378         if(i_regmap[hr]!=CCREG) {
4379           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4380             if((i_dirty>>hr)&1) {
4381               if(i_regmap[hr]<64) {
4382                 emit_storereg(i_regmap[hr],hr);
4383 #ifndef FORCE32
4384                 if( ((i_is32>>i_regmap[hr])&1) ) {
4385                   #ifdef DESTRUCTIVE_WRITEBACK
4386                   emit_sarimm(hr,31,hr);
4387                   emit_storereg(i_regmap[hr]|64,hr);
4388                   #else
4389                   emit_sarimm(hr,31,HOST_TEMPREG);
4390                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4391                   #endif
4392                 }
4393 #endif
4394               }else{
4395                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4396                   emit_storereg(i_regmap[hr],hr);
4397                 }
4398               }
4399             }
4400           }
4401         }
4402       }
4403     }
4404   }
4405 }
4406
4407 // Load all registers (except cycle count)
4408 void load_all_regs(signed char i_regmap[])
4409 {
4410   int hr;
4411   for(hr=0;hr<HOST_REGS;hr++) {
4412     if(hr!=EXCLUDE_REG) {
4413       if(i_regmap[hr]==0) {
4414         emit_zeroreg(hr);
4415       }
4416       else
4417       if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4418       {
4419         emit_loadreg(i_regmap[hr],hr);
4420       }
4421     }
4422   }
4423 }
4424
4425 // Load all current registers also needed by next instruction
4426 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4427 {
4428   int hr;
4429   for(hr=0;hr<HOST_REGS;hr++) {
4430     if(hr!=EXCLUDE_REG) {
4431       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4432         if(i_regmap[hr]==0) {
4433           emit_zeroreg(hr);
4434         }
4435         else
4436         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4437         {
4438           emit_loadreg(i_regmap[hr],hr);
4439         }
4440       }
4441     }
4442   }
4443 }
4444
4445 // Load all regs, storing cycle count if necessary
4446 void load_regs_entry(int t)
4447 {
4448   int hr;
4449   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4450   else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4451   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4452     emit_storereg(CCREG,HOST_CCREG);
4453   }
4454   // Load 32-bit regs
4455   for(hr=0;hr<HOST_REGS;hr++) {
4456     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4457       if(regs[t].regmap_entry[hr]==0) {
4458         emit_zeroreg(hr);
4459       }
4460       else if(regs[t].regmap_entry[hr]!=CCREG)
4461       {
4462         emit_loadreg(regs[t].regmap_entry[hr],hr);
4463       }
4464     }
4465   }
4466   // Load 64-bit regs
4467   for(hr=0;hr<HOST_REGS;hr++) {
4468     if(regs[t].regmap_entry[hr]>=64) {
4469       assert(regs[t].regmap_entry[hr]!=64);
4470       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4471         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4472         if(lr<0) {
4473           emit_loadreg(regs[t].regmap_entry[hr],hr);
4474         }
4475         else
4476         {
4477           emit_sarimm(lr,31,hr);
4478         }
4479       }
4480       else
4481       {
4482         emit_loadreg(regs[t].regmap_entry[hr],hr);
4483       }
4484     }
4485   }
4486 }
4487
4488 // Store dirty registers prior to branch
4489 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4490 {
4491   if(internal_branch(i_is32,addr))
4492   {
4493     int t=(addr-start)>>2;
4494     int hr;
4495     for(hr=0;hr<HOST_REGS;hr++) {
4496       if(hr!=EXCLUDE_REG) {
4497         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4498           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4499             if((i_dirty>>hr)&1) {
4500               if(i_regmap[hr]<64) {
4501                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4502                   emit_storereg(i_regmap[hr],hr);
4503                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4504                     #ifdef DESTRUCTIVE_WRITEBACK
4505                     emit_sarimm(hr,31,hr);
4506                     emit_storereg(i_regmap[hr]|64,hr);
4507                     #else
4508                     emit_sarimm(hr,31,HOST_TEMPREG);
4509                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4510                     #endif
4511                   }
4512                 }
4513               }else{
4514                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4515                   emit_storereg(i_regmap[hr],hr);
4516                 }
4517               }
4518             }
4519           }
4520         }
4521       }
4522     }
4523   }
4524   else
4525   {
4526     // Branch out of this block, write out all dirty regs
4527     wb_dirtys(i_regmap,i_is32,i_dirty);
4528   }
4529 }
4530
4531 // Load all needed registers for branch target
4532 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4533 {
4534   //if(addr>=start && addr<(start+slen*4))
4535   if(internal_branch(i_is32,addr))
4536   {
4537     int t=(addr-start)>>2;
4538     int hr;
4539     // Store the cycle count before loading something else
4540     if(i_regmap[HOST_CCREG]!=CCREG) {
4541       assert(i_regmap[HOST_CCREG]==-1);
4542     }
4543     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4544       emit_storereg(CCREG,HOST_CCREG);
4545     }
4546     // Load 32-bit regs
4547     for(hr=0;hr<HOST_REGS;hr++) {
4548       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4549         #ifdef DESTRUCTIVE_WRITEBACK
4550         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4551         #else
4552         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4553         #endif
4554           if(regs[t].regmap_entry[hr]==0) {
4555             emit_zeroreg(hr);
4556           }
4557           else if(regs[t].regmap_entry[hr]!=CCREG)
4558           {
4559             emit_loadreg(regs[t].regmap_entry[hr],hr);
4560           }
4561         }
4562       }
4563     }
4564     //Load 64-bit regs
4565     for(hr=0;hr<HOST_REGS;hr++) {
4566       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64) {
4567         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4568           assert(regs[t].regmap_entry[hr]!=64);
4569           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4570             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4571             if(lr<0) {
4572               emit_loadreg(regs[t].regmap_entry[hr],hr);
4573             }
4574             else
4575             {
4576               emit_sarimm(lr,31,hr);
4577             }
4578           }
4579           else
4580           {
4581             emit_loadreg(regs[t].regmap_entry[hr],hr);
4582           }
4583         }
4584         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4585           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4586           assert(lr>=0);
4587           emit_sarimm(lr,31,hr);
4588         }
4589       }
4590     }
4591   }
4592 }
4593
4594 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4595 {
4596   if(addr>=start && addr<start+slen*4-4)
4597   {
4598     int t=(addr-start)>>2;
4599     int hr;
4600     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4601     for(hr=0;hr<HOST_REGS;hr++)
4602     {
4603       if(hr!=EXCLUDE_REG)
4604       {
4605         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4606         {
4607           if(regs[t].regmap_entry[hr]!=-1)
4608           {
4609             return 0;
4610           }
4611           else
4612           if((i_dirty>>hr)&1)
4613           {
4614             if(i_regmap[hr]<64)
4615             {
4616               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4617                 return 0;
4618             }
4619             else
4620             {
4621               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4622                 return 0;
4623             }
4624           }
4625         }
4626         else // Same register but is it 32-bit or dirty?
4627         if(i_regmap[hr]>=0)
4628         {
4629           if(!((regs[t].dirty>>hr)&1))
4630           {
4631             if((i_dirty>>hr)&1)
4632             {
4633               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4634               {
4635                 //printf("%x: dirty no match\n",addr);
4636                 return 0;
4637               }
4638             }
4639           }
4640           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4641           {
4642             //printf("%x: is32 no match\n",addr);
4643             return 0;
4644           }
4645         }
4646       }
4647     }
4648     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4649 #ifndef FORCE32
4650     if(requires_32bit[t]&~i_is32) return 0;
4651 #endif
4652     // Delay slots are not valid branch targets
4653     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4654     // Delay slots require additional processing, so do not match
4655     if(is_ds[t]) return 0;
4656   }
4657   else
4658   {
4659     int hr;
4660     for(hr=0;hr<HOST_REGS;hr++)
4661     {
4662       if(hr!=EXCLUDE_REG)
4663       {
4664         if(i_regmap[hr]>=0)
4665         {
4666           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4667           {
4668             if((i_dirty>>hr)&1)
4669             {
4670               return 0;
4671             }
4672           }
4673         }
4674       }
4675     }
4676   }
4677   return 1;
4678 }
4679
4680 // Used when a branch jumps into the delay slot of another branch
4681 void ds_assemble_entry(int i)
4682 {
4683   int t=(ba[i]-start)>>2;
4684   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4685   assem_debug("Assemble delay slot at %x\n",ba[i]);
4686   assem_debug("<->\n");
4687   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4688     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4689   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4690   address_generation(t,&regs[t],regs[t].regmap_entry);
4691   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4692     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4693   cop1_usable=0;
4694   is_delayslot=0;
4695   switch(itype[t]) {
4696     case ALU:
4697       alu_assemble(t,&regs[t]);break;
4698     case IMM16:
4699       imm16_assemble(t,&regs[t]);break;
4700     case SHIFT:
4701       shift_assemble(t,&regs[t]);break;
4702     case SHIFTIMM:
4703       shiftimm_assemble(t,&regs[t]);break;
4704     case LOAD:
4705       load_assemble(t,&regs[t]);break;
4706     case LOADLR:
4707       loadlr_assemble(t,&regs[t]);break;
4708     case STORE:
4709       store_assemble(t,&regs[t]);break;
4710     case STORELR:
4711       storelr_assemble(t,&regs[t]);break;
4712     case COP0:
4713       cop0_assemble(t,&regs[t]);break;
4714     case COP1:
4715       cop1_assemble(t,&regs[t]);break;
4716     case C1LS:
4717       c1ls_assemble(t,&regs[t]);break;
4718     case COP2:
4719       cop2_assemble(t,&regs[t]);break;
4720     case C2LS:
4721       c2ls_assemble(t,&regs[t]);break;
4722     case C2OP:
4723       c2op_assemble(t,&regs[t]);break;
4724     case FCONV:
4725       fconv_assemble(t,&regs[t]);break;
4726     case FLOAT:
4727       float_assemble(t,&regs[t]);break;
4728     case FCOMP:
4729       fcomp_assemble(t,&regs[t]);break;
4730     case MULTDIV:
4731       multdiv_assemble(t,&regs[t]);break;
4732     case MOV:
4733       mov_assemble(t,&regs[t]);break;
4734     case SYSCALL:
4735     case HLECALL:
4736     case INTCALL:
4737     case SPAN:
4738     case UJUMP:
4739     case RJUMP:
4740     case CJUMP:
4741     case SJUMP:
4742     case FJUMP:
4743       printf("Jump in the delay slot.  This is probably a bug.\n");
4744   }
4745   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4746   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4747   if(internal_branch(regs[t].is32,ba[i]+4))
4748     assem_debug("branch: internal\n");
4749   else
4750     assem_debug("branch: external\n");
4751   assert(internal_branch(regs[t].is32,ba[i]+4));
4752   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4753   emit_jmp(0);
4754 }
4755
4756 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4757 {
4758   int count;
4759   int jaddr;
4760   int idle=0;
4761   if(itype[i]==RJUMP)
4762   {
4763     *adj=0;
4764   }
4765   //if(ba[i]>=start && ba[i]<(start+slen*4))
4766   if(internal_branch(branch_regs[i].is32,ba[i]))
4767   {
4768     int t=(ba[i]-start)>>2;
4769     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4770     else *adj=ccadj[t];
4771   }
4772   else
4773   {
4774     *adj=0;
4775   }
4776   count=ccadj[i];
4777   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4778     // Idle loop
4779     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4780     idle=(int)out;
4781     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4782     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4783     jaddr=(int)out;
4784     emit_jmp(0);
4785   }
4786   else if(*adj==0||invert) {
4787     emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4788     jaddr=(int)out;
4789     emit_jns(0);
4790   }
4791   else
4792   {
4793     emit_cmpimm(HOST_CCREG,-2*(count+2));
4794     jaddr=(int)out;
4795     emit_jns(0);
4796   }
4797   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4798 }
4799
4800 void do_ccstub(int n)
4801 {
4802   literal_pool(256);
4803   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4804   set_jump_target(stubs[n][1],(int)out);
4805   int i=stubs[n][4];
4806   if(stubs[n][6]==NULLDS) {
4807     // Delay slot instruction is nullified ("likely" branch)
4808     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4809   }
4810   else if(stubs[n][6]!=TAKEN) {
4811     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4812   }
4813   else {
4814     if(internal_branch(branch_regs[i].is32,ba[i]))
4815       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4816   }
4817   if(stubs[n][5]!=-1)
4818   {
4819     // Save PC as return address
4820     emit_movimm(stubs[n][5],EAX);
4821     emit_writeword(EAX,(int)&pcaddr);
4822   }
4823   else
4824   {
4825     // Return address depends on which way the branch goes
4826     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4827     {
4828       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4829       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4830       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4831       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4832       if(rs1[i]==0)
4833       {
4834         s1l=s2l;s1h=s2h;
4835         s2l=s2h=-1;
4836       }
4837       else if(rs2[i]==0)
4838       {
4839         s2l=s2h=-1;
4840       }
4841       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4842         s1h=s2h=-1;
4843       }
4844       assert(s1l>=0);
4845       #ifdef DESTRUCTIVE_WRITEBACK
4846       if(rs1[i]) {
4847         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4848           emit_loadreg(rs1[i],s1l);
4849       }
4850       else {
4851         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4852           emit_loadreg(rs2[i],s1l);
4853       }
4854       if(s2l>=0)
4855         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4856           emit_loadreg(rs2[i],s2l);
4857       #endif
4858       int hr=0;
4859       int addr,alt,ntaddr;
4860       while(hr<HOST_REGS)
4861       {
4862         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4863            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4864            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4865         {
4866           addr=hr++;break;
4867         }
4868         hr++;
4869       }
4870       while(hr<HOST_REGS)
4871       {
4872         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4873            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4874            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4875         {
4876           alt=hr++;break;
4877         }
4878         hr++;
4879       }
4880       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4881       {
4882         while(hr<HOST_REGS)
4883         {
4884           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4885              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4886              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4887           {
4888             ntaddr=hr;break;
4889           }
4890           hr++;
4891         }
4892         assert(hr<HOST_REGS);
4893       }
4894       if((opcode[i]&0x2f)==4) // BEQ
4895       {
4896         #ifdef HAVE_CMOV_IMM
4897         if(s1h<0) {
4898           if(s2l>=0) emit_cmp(s1l,s2l);
4899           else emit_test(s1l,s1l);
4900           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4901         }
4902         else
4903         #endif
4904         {
4905           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4906           if(s1h>=0) {
4907             if(s2h>=0) emit_cmp(s1h,s2h);
4908             else emit_test(s1h,s1h);
4909             emit_cmovne_reg(alt,addr);
4910           }
4911           if(s2l>=0) emit_cmp(s1l,s2l);
4912           else emit_test(s1l,s1l);
4913           emit_cmovne_reg(alt,addr);
4914         }
4915       }
4916       if((opcode[i]&0x2f)==5) // BNE
4917       {
4918         #ifdef HAVE_CMOV_IMM
4919         if(s1h<0) {
4920           if(s2l>=0) emit_cmp(s1l,s2l);
4921           else emit_test(s1l,s1l);
4922           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4923         }
4924         else
4925         #endif
4926         {
4927           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4928           if(s1h>=0) {
4929             if(s2h>=0) emit_cmp(s1h,s2h);
4930             else emit_test(s1h,s1h);
4931             emit_cmovne_reg(alt,addr);
4932           }
4933           if(s2l>=0) emit_cmp(s1l,s2l);
4934           else emit_test(s1l,s1l);
4935           emit_cmovne_reg(alt,addr);
4936         }
4937       }
4938       if((opcode[i]&0x2f)==6) // BLEZ
4939       {
4940         //emit_movimm(ba[i],alt);
4941         //emit_movimm(start+i*4+8,addr);
4942         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4943         emit_cmpimm(s1l,1);
4944         if(s1h>=0) emit_mov(addr,ntaddr);
4945         emit_cmovl_reg(alt,addr);
4946         if(s1h>=0) {
4947           emit_test(s1h,s1h);
4948           emit_cmovne_reg(ntaddr,addr);
4949           emit_cmovs_reg(alt,addr);
4950         }
4951       }
4952       if((opcode[i]&0x2f)==7) // BGTZ
4953       {
4954         //emit_movimm(ba[i],addr);
4955         //emit_movimm(start+i*4+8,ntaddr);
4956         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4957         emit_cmpimm(s1l,1);
4958         if(s1h>=0) emit_mov(addr,alt);
4959         emit_cmovl_reg(ntaddr,addr);
4960         if(s1h>=0) {
4961           emit_test(s1h,s1h);
4962           emit_cmovne_reg(alt,addr);
4963           emit_cmovs_reg(ntaddr,addr);
4964         }
4965       }
4966       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4967       {
4968         //emit_movimm(ba[i],alt);
4969         //emit_movimm(start+i*4+8,addr);
4970         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4971         if(s1h>=0) emit_test(s1h,s1h);
4972         else emit_test(s1l,s1l);
4973         emit_cmovs_reg(alt,addr);
4974       }
4975       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4976       {
4977         //emit_movimm(ba[i],addr);
4978         //emit_movimm(start+i*4+8,alt);
4979         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4980         if(s1h>=0) emit_test(s1h,s1h);
4981         else emit_test(s1l,s1l);
4982         emit_cmovs_reg(alt,addr);
4983       }
4984       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4985         if(source[i]&0x10000) // BC1T
4986         {
4987           //emit_movimm(ba[i],alt);
4988           //emit_movimm(start+i*4+8,addr);
4989           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4990           emit_testimm(s1l,0x800000);
4991           emit_cmovne_reg(alt,addr);
4992         }
4993         else // BC1F
4994         {
4995           //emit_movimm(ba[i],addr);
4996           //emit_movimm(start+i*4+8,alt);
4997           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4998           emit_testimm(s1l,0x800000);
4999           emit_cmovne_reg(alt,addr);
5000         }
5001       }
5002       emit_writeword(addr,(int)&pcaddr);
5003     }
5004     else
5005     if(itype[i]==RJUMP)
5006     {
5007       int r=get_reg(branch_regs[i].regmap,rs1[i]);
5008       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5009         r=get_reg(branch_regs[i].regmap,RTEMP);
5010       }
5011       emit_writeword(r,(int)&pcaddr);
5012     }
5013     else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5014   }
5015   // Update cycle count
5016   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5017   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5018   emit_call((int)cc_interrupt);
5019   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5020   if(stubs[n][6]==TAKEN) {
5021     if(internal_branch(branch_regs[i].is32,ba[i]))
5022       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5023     else if(itype[i]==RJUMP) {
5024       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5025         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5026       else
5027         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5028     }
5029   }else if(stubs[n][6]==NOTTAKEN) {
5030     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5031     else load_all_regs(branch_regs[i].regmap);
5032   }else if(stubs[n][6]==NULLDS) {
5033     // Delay slot instruction is nullified ("likely" branch)
5034     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5035     else load_all_regs(regs[i].regmap);
5036   }else{
5037     load_all_regs(branch_regs[i].regmap);
5038   }
5039   emit_jmp(stubs[n][2]); // return address
5040
5041   /* This works but uses a lot of memory...
5042   emit_readword((int)&last_count,ECX);
5043   emit_add(HOST_CCREG,ECX,EAX);
5044   emit_writeword(EAX,(int)&Count);
5045   emit_call((int)gen_interupt);
5046   emit_readword((int)&Count,HOST_CCREG);
5047   emit_readword((int)&next_interupt,EAX);
5048   emit_readword((int)&pending_exception,EBX);
5049   emit_writeword(EAX,(int)&last_count);
5050   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5051   emit_test(EBX,EBX);
5052   int jne_instr=(int)out;
5053   emit_jne(0);
5054   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5055   load_all_regs(branch_regs[i].regmap);
5056   emit_jmp(stubs[n][2]); // return address
5057   set_jump_target(jne_instr,(int)out);
5058   emit_readword((int)&pcaddr,EAX);
5059   // Call get_addr_ht instead of doing the hash table here.
5060   // This code is executed infrequently and takes up a lot of space
5061   // so smaller is better.
5062   emit_storereg(CCREG,HOST_CCREG);
5063   emit_pushreg(EAX);
5064   emit_call((int)get_addr_ht);
5065   emit_loadreg(CCREG,HOST_CCREG);
5066   emit_addimm(ESP,4,ESP);
5067   emit_jmpreg(EAX);*/
5068 }
5069
5070 add_to_linker(int addr,int target,int ext)
5071 {
5072   link_addr[linkcount][0]=addr;
5073   link_addr[linkcount][1]=target;
5074   link_addr[linkcount][2]=ext;
5075   linkcount++;
5076 }
5077
5078 void ujump_assemble(int i,struct regstat *i_regs)
5079 {
5080   signed char *i_regmap=i_regs->regmap;
5081   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5082   address_generation(i+1,i_regs,regs[i].regmap_entry);
5083   #ifdef REG_PREFETCH
5084   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5085   if(rt1[i]==31&&temp>=0)
5086   {
5087     int return_address=start+i*4+8;
5088     if(get_reg(branch_regs[i].regmap,31)>0)
5089     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5090   }
5091   #endif
5092   ds_assemble(i+1,i_regs);
5093   uint64_t bc_unneeded=branch_regs[i].u;
5094   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5095   bc_unneeded|=1|(1LL<<rt1[i]);
5096   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5097   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5098                 bc_unneeded,bc_unneeded_upper);
5099   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5100   if(rt1[i]==31) {
5101     int rt;
5102     unsigned int return_address;
5103     assert(rt1[i+1]!=31);
5104     assert(rt2[i+1]!=31);
5105     rt=get_reg(branch_regs[i].regmap,31);
5106     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5107     //assert(rt>=0);
5108     return_address=start+i*4+8;
5109     if(rt>=0) {
5110       #ifdef USE_MINI_HT
5111       if(internal_branch(branch_regs[i].is32,return_address)) {
5112         int temp=rt+1;
5113         if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5114            branch_regs[i].regmap[temp]>=0)
5115         {
5116           temp=get_reg(branch_regs[i].regmap,-1);
5117         }
5118         #ifdef HOST_TEMPREG
5119         if(temp<0) temp=HOST_TEMPREG;
5120         #endif
5121         if(temp>=0) do_miniht_insert(return_address,rt,temp);
5122         else emit_movimm(return_address,rt);
5123       }
5124       else
5125       #endif
5126       {
5127         #ifdef REG_PREFETCH
5128         if(temp>=0)
5129         {
5130           if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5131         }
5132         #endif
5133         emit_movimm(return_address,rt); // PC into link register
5134         #ifdef IMM_PREFETCH
5135         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5136         #endif
5137       }
5138     }
5139   }
5140   int cc,adj;
5141   cc=get_reg(branch_regs[i].regmap,CCREG);
5142   assert(cc==HOST_CCREG);
5143   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5144   #ifdef REG_PREFETCH
5145   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5146   #endif
5147   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5148   if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5149   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5150   if(internal_branch(branch_regs[i].is32,ba[i]))
5151     assem_debug("branch: internal\n");
5152   else
5153     assem_debug("branch: external\n");
5154   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5155     ds_assemble_entry(i);
5156   }
5157   else {
5158     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5159     emit_jmp(0);
5160   }
5161 }
5162
5163 void rjump_assemble(int i,struct regstat *i_regs)
5164 {
5165   signed char *i_regmap=i_regs->regmap;
5166   int temp;
5167   int rs,cc,adj;
5168   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5169   assert(rs>=0);
5170   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5171     // Delay slot abuse, make a copy of the branch address register
5172     temp=get_reg(branch_regs[i].regmap,RTEMP);
5173     assert(temp>=0);
5174     assert(regs[i].regmap[temp]==RTEMP);
5175     emit_mov(rs,temp);
5176     rs=temp;
5177   }
5178   address_generation(i+1,i_regs,regs[i].regmap_entry);
5179   #ifdef REG_PREFETCH
5180   if(rt1[i]==31)
5181   {
5182     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5183       int return_address=start+i*4+8;
5184       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5185     }
5186   }
5187   #endif
5188   #ifdef USE_MINI_HT
5189   if(rs1[i]==31) {
5190     int rh=get_reg(regs[i].regmap,RHASH);
5191     if(rh>=0) do_preload_rhash(rh);
5192   }
5193   #endif
5194   ds_assemble(i+1,i_regs);
5195   uint64_t bc_unneeded=branch_regs[i].u;
5196   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5197   bc_unneeded|=1|(1LL<<rt1[i]);
5198   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5199   bc_unneeded&=~(1LL<<rs1[i]);
5200   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5201                 bc_unneeded,bc_unneeded_upper);
5202   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5203   if(rt1[i]!=0) {
5204     int rt,return_address;
5205     assert(rt1[i+1]!=rt1[i]);
5206     assert(rt2[i+1]!=rt1[i]);
5207     rt=get_reg(branch_regs[i].regmap,rt1[i]);
5208     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5209     assert(rt>=0);
5210     return_address=start+i*4+8;
5211     #ifdef REG_PREFETCH
5212     if(temp>=0)
5213     {
5214       if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5215     }
5216     #endif
5217     emit_movimm(return_address,rt); // PC into link register
5218     #ifdef IMM_PREFETCH
5219     emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5220     #endif
5221   }
5222   cc=get_reg(branch_regs[i].regmap,CCREG);
5223   assert(cc==HOST_CCREG);
5224   #ifdef USE_MINI_HT
5225   int rh=get_reg(branch_regs[i].regmap,RHASH);
5226   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5227   if(rs1[i]==31) {
5228     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5229     do_preload_rhtbl(ht);
5230     do_rhash(rs,rh);
5231   }
5232   #endif
5233   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5234   #ifdef DESTRUCTIVE_WRITEBACK
5235   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5236     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5237       emit_loadreg(rs1[i],rs);
5238     }
5239   }
5240   #endif
5241   #ifdef REG_PREFETCH
5242   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5243   #endif
5244   #ifdef USE_MINI_HT
5245   if(rs1[i]==31) {
5246     do_miniht_load(ht,rh);
5247   }
5248   #endif
5249   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5250   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5251   //assert(adj==0);
5252   emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5253   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5254   emit_jns(0);
5255   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5256   #ifdef USE_MINI_HT
5257   if(rs1[i]==31) {
5258     do_miniht_jump(rs,rh,ht);
5259   }
5260   else
5261   #endif
5262   {
5263     //if(rs!=EAX) emit_mov(rs,EAX);
5264     //emit_jmp((int)jump_vaddr_eax);
5265     emit_jmp(jump_vaddr_reg[rs]);
5266   }
5267   /* Check hash table
5268   temp=!rs;
5269   emit_mov(rs,temp);
5270   emit_shrimm(rs,16,rs);
5271   emit_xor(temp,rs,rs);
5272   emit_movzwl_reg(rs,rs);
5273   emit_shlimm(rs,4,rs);
5274   emit_cmpmem_indexed((int)hash_table,rs,temp);
5275   emit_jne((int)out+14);
5276   emit_readword_indexed((int)hash_table+4,rs,rs);
5277   emit_jmpreg(rs);
5278   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5279   emit_addimm_no_flags(8,rs);
5280   emit_jeq((int)out-17);
5281   // No hit on hash table, call compiler
5282   emit_pushreg(temp);
5283 //DEBUG >
5284 #ifdef DEBUG_CYCLE_COUNT
5285   emit_readword((int)&last_count,ECX);
5286   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5287   emit_readword((int)&next_interupt,ECX);
5288   emit_writeword(HOST_CCREG,(int)&Count);
5289   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5290   emit_writeword(ECX,(int)&last_count);
5291 #endif
5292 //DEBUG <
5293   emit_storereg(CCREG,HOST_CCREG);
5294   emit_call((int)get_addr);
5295   emit_loadreg(CCREG,HOST_CCREG);
5296   emit_addimm(ESP,4,ESP);
5297   emit_jmpreg(EAX);*/
5298   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5299   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5300   #endif
5301 }
5302
5303 void cjump_assemble(int i,struct regstat *i_regs)
5304 {
5305   signed char *i_regmap=i_regs->regmap;
5306   int cc;
5307   int match;
5308   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5309   assem_debug("match=%d\n",match);
5310   int s1h,s1l,s2h,s2l;
5311   int prev_cop1_usable=cop1_usable;
5312   int unconditional=0,nop=0;
5313   int only32=0;
5314   int invert=0;
5315   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5316   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5317   if(!match) invert=1;
5318   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5319   if(i>(ba[i]-start)>>2) invert=1;
5320   #endif
5321
5322   if(ooo[i]) {
5323     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5324     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5325     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5326     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5327   }
5328   else {
5329     s1l=get_reg(i_regmap,rs1[i]);
5330     s1h=get_reg(i_regmap,rs1[i]|64);
5331     s2l=get_reg(i_regmap,rs2[i]);
5332     s2h=get_reg(i_regmap,rs2[i]|64);
5333   }
5334   if(rs1[i]==0&&rs2[i]==0)
5335   {
5336     if(opcode[i]&1) nop=1;
5337     else unconditional=1;
5338     //assert(opcode[i]!=5);
5339     //assert(opcode[i]!=7);
5340     //assert(opcode[i]!=0x15);
5341     //assert(opcode[i]!=0x17);
5342   }
5343   else if(rs1[i]==0)
5344   {
5345     s1l=s2l;s1h=s2h;
5346     s2l=s2h=-1;
5347     only32=(regs[i].was32>>rs2[i])&1;
5348   }
5349   else if(rs2[i]==0)
5350   {
5351     s2l=s2h=-1;
5352     only32=(regs[i].was32>>rs1[i])&1;
5353   }
5354   else {
5355     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5356   }
5357
5358   if(ooo[i]) {
5359     // Out of order execution (delay slot first)
5360     //printf("OOOE\n");
5361     address_generation(i+1,i_regs,regs[i].regmap_entry);
5362     ds_assemble(i+1,i_regs);
5363     int adj;
5364     uint64_t bc_unneeded=branch_regs[i].u;
5365     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5366     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5367     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5368     bc_unneeded|=1;
5369     bc_unneeded_upper|=1;
5370     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5371                   bc_unneeded,bc_unneeded_upper);
5372     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5373     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5374     cc=get_reg(branch_regs[i].regmap,CCREG);
5375     assert(cc==HOST_CCREG);
5376     if(unconditional)
5377       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5378     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5379     //assem_debug("cycle count (adj)\n");
5380     if(unconditional) {
5381       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5382       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5383         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5384         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5385         if(internal)
5386           assem_debug("branch: internal\n");
5387         else
5388           assem_debug("branch: external\n");
5389         if(internal&&is_ds[(ba[i]-start)>>2]) {
5390           ds_assemble_entry(i);
5391         }
5392         else {
5393           add_to_linker((int)out,ba[i],internal);
5394           emit_jmp(0);
5395         }
5396         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5397         if(((u_int)out)&7) emit_addnop(0);
5398         #endif
5399       }
5400     }
5401     else if(nop) {
5402       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5403       int jaddr=(int)out;
5404       emit_jns(0);
5405       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5406     }
5407     else {
5408       int taken=0,nottaken=0,nottaken1=0;
5409       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5410       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5411       if(!only32)
5412       {
5413         assert(s1h>=0);
5414         if(opcode[i]==4) // BEQ
5415         {
5416           if(s2h>=0) emit_cmp(s1h,s2h);
5417           else emit_test(s1h,s1h);
5418           nottaken1=(int)out;
5419           emit_jne(1);
5420         }
5421         if(opcode[i]==5) // BNE
5422         {
5423           if(s2h>=0) emit_cmp(s1h,s2h);
5424           else emit_test(s1h,s1h);
5425           if(invert) taken=(int)out;
5426           else add_to_linker((int)out,ba[i],internal);
5427           emit_jne(0);
5428         }
5429         if(opcode[i]==6) // BLEZ
5430         {
5431           emit_test(s1h,s1h);
5432           if(invert) taken=(int)out;
5433           else add_to_linker((int)out,ba[i],internal);
5434           emit_js(0);
5435           nottaken1=(int)out;
5436           emit_jne(1);
5437         }
5438         if(opcode[i]==7) // BGTZ
5439         {
5440           emit_test(s1h,s1h);
5441           nottaken1=(int)out;
5442           emit_js(1);
5443           if(invert) taken=(int)out;
5444           else add_to_linker((int)out,ba[i],internal);
5445           emit_jne(0);
5446         }
5447       } // if(!only32)
5448
5449       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5450       assert(s1l>=0);
5451       if(opcode[i]==4) // BEQ
5452       {
5453         if(s2l>=0) emit_cmp(s1l,s2l);
5454         else emit_test(s1l,s1l);
5455         if(invert){
5456           nottaken=(int)out;
5457           emit_jne(1);
5458         }else{
5459           add_to_linker((int)out,ba[i],internal);
5460           emit_jeq(0);
5461         }
5462       }
5463       if(opcode[i]==5) // BNE
5464       {
5465         if(s2l>=0) emit_cmp(s1l,s2l);
5466         else emit_test(s1l,s1l);
5467         if(invert){
5468           nottaken=(int)out;
5469           emit_jeq(1);
5470         }else{
5471           add_to_linker((int)out,ba[i],internal);
5472           emit_jne(0);
5473         }
5474       }
5475       if(opcode[i]==6) // BLEZ
5476       {
5477         emit_cmpimm(s1l,1);
5478         if(invert){
5479           nottaken=(int)out;
5480           emit_jge(1);
5481         }else{
5482           add_to_linker((int)out,ba[i],internal);
5483           emit_jl(0);
5484         }
5485       }
5486       if(opcode[i]==7) // BGTZ
5487       {
5488         emit_cmpimm(s1l,1);
5489         if(invert){
5490           nottaken=(int)out;
5491           emit_jl(1);
5492         }else{
5493           add_to_linker((int)out,ba[i],internal);
5494           emit_jge(0);
5495         }
5496       }
5497       if(invert) {
5498         if(taken) set_jump_target(taken,(int)out);
5499         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5500         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5501           if(adj) {
5502             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5503             add_to_linker((int)out,ba[i],internal);
5504           }else{
5505             emit_addnop(13);
5506             add_to_linker((int)out,ba[i],internal*2);
5507           }
5508           emit_jmp(0);
5509         }else
5510         #endif
5511         {
5512           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5513           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5514           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5515           if(internal)
5516             assem_debug("branch: internal\n");
5517           else
5518             assem_debug("branch: external\n");
5519           if(internal&&is_ds[(ba[i]-start)>>2]) {
5520             ds_assemble_entry(i);
5521           }
5522           else {
5523             add_to_linker((int)out,ba[i],internal);
5524             emit_jmp(0);
5525           }
5526         }
5527         set_jump_target(nottaken,(int)out);
5528       }
5529
5530       if(nottaken1) set_jump_target(nottaken1,(int)out);
5531       if(adj) {
5532         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5533       }
5534     } // (!unconditional)
5535   } // if(ooo)
5536   else
5537   {
5538     // In-order execution (branch first)
5539     //if(likely[i]) printf("IOL\n");
5540     //else
5541     //printf("IOE\n");
5542     int taken=0,nottaken=0,nottaken1=0;
5543     if(!unconditional&&!nop) {
5544       if(!only32)
5545       {
5546         assert(s1h>=0);
5547         if((opcode[i]&0x2f)==4) // BEQ
5548         {
5549           if(s2h>=0) emit_cmp(s1h,s2h);
5550           else emit_test(s1h,s1h);
5551           nottaken1=(int)out;
5552           emit_jne(2);
5553         }
5554         if((opcode[i]&0x2f)==5) // BNE
5555         {
5556           if(s2h>=0) emit_cmp(s1h,s2h);
5557           else emit_test(s1h,s1h);
5558           taken=(int)out;
5559           emit_jne(1);
5560         }
5561         if((opcode[i]&0x2f)==6) // BLEZ
5562         {
5563           emit_test(s1h,s1h);
5564           taken=(int)out;
5565           emit_js(1);
5566           nottaken1=(int)out;
5567           emit_jne(2);
5568         }
5569         if((opcode[i]&0x2f)==7) // BGTZ
5570         {
5571           emit_test(s1h,s1h);
5572           nottaken1=(int)out;
5573           emit_js(2);
5574           taken=(int)out;
5575           emit_jne(1);
5576         }
5577       } // if(!only32)
5578
5579       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5580       assert(s1l>=0);
5581       if((opcode[i]&0x2f)==4) // BEQ
5582       {
5583         if(s2l>=0) emit_cmp(s1l,s2l);
5584         else emit_test(s1l,s1l);
5585         nottaken=(int)out;
5586         emit_jne(2);
5587       }
5588       if((opcode[i]&0x2f)==5) // BNE
5589       {
5590         if(s2l>=0) emit_cmp(s1l,s2l);
5591         else emit_test(s1l,s1l);
5592         nottaken=(int)out;
5593         emit_jeq(2);
5594       }
5595       if((opcode[i]&0x2f)==6) // BLEZ
5596       {
5597         emit_cmpimm(s1l,1);
5598         nottaken=(int)out;
5599         emit_jge(2);
5600       }
5601       if((opcode[i]&0x2f)==7) // BGTZ
5602       {
5603         emit_cmpimm(s1l,1);
5604         nottaken=(int)out;
5605         emit_jl(2);
5606       }
5607     } // if(!unconditional)
5608     int adj;
5609     uint64_t ds_unneeded=branch_regs[i].u;
5610     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5611     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5612     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5613     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5614     ds_unneeded|=1;
5615     ds_unneeded_upper|=1;
5616     // branch taken
5617     if(!nop) {
5618       if(taken) set_jump_target(taken,(int)out);
5619       assem_debug("1:\n");
5620       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5621                     ds_unneeded,ds_unneeded_upper);
5622       // load regs
5623       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5624       address_generation(i+1,&branch_regs[i],0);
5625       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5626       ds_assemble(i+1,&branch_regs[i]);
5627       cc=get_reg(branch_regs[i].regmap,CCREG);
5628       if(cc==-1) {
5629         emit_loadreg(CCREG,cc=HOST_CCREG);
5630         // CHECK: Is the following instruction (fall thru) allocated ok?
5631       }
5632       assert(cc==HOST_CCREG);
5633       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5634       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5635       assem_debug("cycle count (adj)\n");
5636       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5637       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5638       if(internal)
5639         assem_debug("branch: internal\n");
5640       else
5641         assem_debug("branch: external\n");
5642       if(internal&&is_ds[(ba[i]-start)>>2]) {
5643         ds_assemble_entry(i);
5644       }
5645       else {
5646         add_to_linker((int)out,ba[i],internal);
5647         emit_jmp(0);
5648       }
5649     }
5650     // branch not taken
5651     cop1_usable=prev_cop1_usable;
5652     if(!unconditional) {
5653       if(nottaken1) set_jump_target(nottaken1,(int)out);
5654       set_jump_target(nottaken,(int)out);
5655       assem_debug("2:\n");
5656       if(!likely[i]) {
5657         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5658                       ds_unneeded,ds_unneeded_upper);
5659         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5660         address_generation(i+1,&branch_regs[i],0);
5661         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5662         ds_assemble(i+1,&branch_regs[i]);
5663       }
5664       cc=get_reg(branch_regs[i].regmap,CCREG);
5665       if(cc==-1&&!likely[i]) {
5666         // Cycle count isn't in a register, temporarily load it then write it out
5667         emit_loadreg(CCREG,HOST_CCREG);
5668         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5669         int jaddr=(int)out;
5670         emit_jns(0);
5671         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5672         emit_storereg(CCREG,HOST_CCREG);
5673       }
5674       else{
5675         cc=get_reg(i_regmap,CCREG);
5676         assert(cc==HOST_CCREG);
5677         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5678         int jaddr=(int)out;
5679         emit_jns(0);
5680         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5681       }
5682     }
5683   }
5684 }
5685
5686 void sjump_assemble(int i,struct regstat *i_regs)
5687 {
5688   signed char *i_regmap=i_regs->regmap;
5689   int cc;
5690   int match;
5691   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5692   assem_debug("smatch=%d\n",match);
5693   int s1h,s1l;
5694   int prev_cop1_usable=cop1_usable;
5695   int unconditional=0,nevertaken=0;
5696   int only32=0;
5697   int invert=0;
5698   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5699   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5700   if(!match) invert=1;
5701   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5702   if(i>(ba[i]-start)>>2) invert=1;
5703   #endif
5704
5705   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5706   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5707
5708   if(ooo[i]) {
5709     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5710     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5711   }
5712   else {
5713     s1l=get_reg(i_regmap,rs1[i]);
5714     s1h=get_reg(i_regmap,rs1[i]|64);
5715   }
5716   if(rs1[i]==0)
5717   {
5718     if(opcode2[i]&1) unconditional=1;
5719     else nevertaken=1;
5720     // These are never taken (r0 is never less than zero)
5721     //assert(opcode2[i]!=0);
5722     //assert(opcode2[i]!=2);
5723     //assert(opcode2[i]!=0x10);
5724     //assert(opcode2[i]!=0x12);
5725   }
5726   else {
5727     only32=(regs[i].was32>>rs1[i])&1;
5728   }
5729
5730   if(ooo[i]) {
5731     // Out of order execution (delay slot first)
5732     //printf("OOOE\n");
5733     address_generation(i+1,i_regs,regs[i].regmap_entry);
5734     ds_assemble(i+1,i_regs);
5735     int adj;
5736     uint64_t bc_unneeded=branch_regs[i].u;
5737     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5738     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5739     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5740     bc_unneeded|=1;
5741     bc_unneeded_upper|=1;
5742     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5743                   bc_unneeded,bc_unneeded_upper);
5744     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5745     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5746     if(rt1[i]==31) {
5747       int rt,return_address;
5748       rt=get_reg(branch_regs[i].regmap,31);
5749       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5750       if(rt>=0) {
5751         // Save the PC even if the branch is not taken
5752         return_address=start+i*4+8;
5753         emit_movimm(return_address,rt); // PC into link register
5754         #ifdef IMM_PREFETCH
5755         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5756         #endif
5757       }
5758     }
5759     cc=get_reg(branch_regs[i].regmap,CCREG);
5760     assert(cc==HOST_CCREG);
5761     if(unconditional)
5762       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5763     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5764     assem_debug("cycle count (adj)\n");
5765     if(unconditional) {
5766       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5767       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5768         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5769         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5770         if(internal)
5771           assem_debug("branch: internal\n");
5772         else
5773           assem_debug("branch: external\n");
5774         if(internal&&is_ds[(ba[i]-start)>>2]) {
5775           ds_assemble_entry(i);
5776         }
5777         else {
5778           add_to_linker((int)out,ba[i],internal);
5779           emit_jmp(0);
5780         }
5781         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5782         if(((u_int)out)&7) emit_addnop(0);
5783         #endif
5784       }
5785     }
5786     else if(nevertaken) {
5787       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5788       int jaddr=(int)out;
5789       emit_jns(0);
5790       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5791     }
5792     else {
5793       int nottaken=0;
5794       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5795       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5796       if(!only32)
5797       {
5798         assert(s1h>=0);
5799         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5800         {
5801           emit_test(s1h,s1h);
5802           if(invert){
5803             nottaken=(int)out;
5804             emit_jns(1);
5805           }else{
5806             add_to_linker((int)out,ba[i],internal);
5807             emit_js(0);
5808           }
5809         }
5810         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5811         {
5812           emit_test(s1h,s1h);
5813           if(invert){
5814             nottaken=(int)out;
5815             emit_js(1);
5816           }else{
5817             add_to_linker((int)out,ba[i],internal);
5818             emit_jns(0);
5819           }
5820         }
5821       } // if(!only32)
5822       else
5823       {
5824         assert(s1l>=0);
5825         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5826         {
5827           emit_test(s1l,s1l);
5828           if(invert){
5829             nottaken=(int)out;
5830             emit_jns(1);
5831           }else{
5832             add_to_linker((int)out,ba[i],internal);
5833             emit_js(0);
5834           }
5835         }
5836         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5837         {
5838           emit_test(s1l,s1l);
5839           if(invert){
5840             nottaken=(int)out;
5841             emit_js(1);
5842           }else{
5843             add_to_linker((int)out,ba[i],internal);
5844             emit_jns(0);
5845           }
5846         }
5847       } // if(!only32)
5848
5849       if(invert) {
5850         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5851         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5852           if(adj) {
5853             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5854             add_to_linker((int)out,ba[i],internal);
5855           }else{
5856             emit_addnop(13);
5857             add_to_linker((int)out,ba[i],internal*2);
5858           }
5859           emit_jmp(0);
5860         }else
5861         #endif
5862         {
5863           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5864           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5865           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5866           if(internal)
5867             assem_debug("branch: internal\n");
5868           else
5869             assem_debug("branch: external\n");
5870           if(internal&&is_ds[(ba[i]-start)>>2]) {
5871             ds_assemble_entry(i);
5872           }
5873           else {
5874             add_to_linker((int)out,ba[i],internal);
5875             emit_jmp(0);
5876           }
5877         }
5878         set_jump_target(nottaken,(int)out);
5879       }
5880
5881       if(adj) {
5882         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5883       }
5884     } // (!unconditional)
5885   } // if(ooo)
5886   else
5887   {
5888     // In-order execution (branch first)
5889     //printf("IOE\n");
5890     int nottaken=0;
5891     if(rt1[i]==31) {
5892       int rt,return_address;
5893       rt=get_reg(branch_regs[i].regmap,31);
5894       if(rt>=0) {
5895         // Save the PC even if the branch is not taken
5896         return_address=start+i*4+8;
5897         emit_movimm(return_address,rt); // PC into link register
5898         #ifdef IMM_PREFETCH
5899         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5900         #endif
5901       }
5902     }
5903     if(!unconditional) {
5904       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5905       if(!only32)
5906       {
5907         assert(s1h>=0);
5908         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5909         {
5910           emit_test(s1h,s1h);
5911           nottaken=(int)out;
5912           emit_jns(1);
5913         }
5914         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5915         {
5916           emit_test(s1h,s1h);
5917           nottaken=(int)out;
5918           emit_js(1);
5919         }
5920       } // if(!only32)
5921       else
5922       {
5923         assert(s1l>=0);
5924         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5925         {
5926           emit_test(s1l,s1l);
5927           nottaken=(int)out;
5928           emit_jns(1);
5929         }
5930         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5931         {
5932           emit_test(s1l,s1l);
5933           nottaken=(int)out;
5934           emit_js(1);
5935         }
5936       }
5937     } // if(!unconditional)
5938     int adj;
5939     uint64_t ds_unneeded=branch_regs[i].u;
5940     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5941     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5942     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5943     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5944     ds_unneeded|=1;
5945     ds_unneeded_upper|=1;
5946     // branch taken
5947     if(!nevertaken) {
5948       //assem_debug("1:\n");
5949       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5950                     ds_unneeded,ds_unneeded_upper);
5951       // load regs
5952       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5953       address_generation(i+1,&branch_regs[i],0);
5954       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5955       ds_assemble(i+1,&branch_regs[i]);
5956       cc=get_reg(branch_regs[i].regmap,CCREG);
5957       if(cc==-1) {
5958         emit_loadreg(CCREG,cc=HOST_CCREG);
5959         // CHECK: Is the following instruction (fall thru) allocated ok?
5960       }
5961       assert(cc==HOST_CCREG);
5962       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5963       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5964       assem_debug("cycle count (adj)\n");
5965       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5966       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5967       if(internal)
5968         assem_debug("branch: internal\n");
5969       else
5970         assem_debug("branch: external\n");
5971       if(internal&&is_ds[(ba[i]-start)>>2]) {
5972         ds_assemble_entry(i);
5973       }
5974       else {
5975         add_to_linker((int)out,ba[i],internal);
5976         emit_jmp(0);
5977       }
5978     }
5979     // branch not taken
5980     cop1_usable=prev_cop1_usable;
5981     if(!unconditional) {
5982       set_jump_target(nottaken,(int)out);
5983       assem_debug("1:\n");
5984       if(!likely[i]) {
5985         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5986                       ds_unneeded,ds_unneeded_upper);
5987         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5988         address_generation(i+1,&branch_regs[i],0);
5989         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5990         ds_assemble(i+1,&branch_regs[i]);
5991       }
5992       cc=get_reg(branch_regs[i].regmap,CCREG);
5993       if(cc==-1&&!likely[i]) {
5994         // Cycle count isn't in a register, temporarily load it then write it out
5995         emit_loadreg(CCREG,HOST_CCREG);
5996         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5997         int jaddr=(int)out;
5998         emit_jns(0);
5999         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6000         emit_storereg(CCREG,HOST_CCREG);
6001       }
6002       else{
6003         cc=get_reg(i_regmap,CCREG);
6004         assert(cc==HOST_CCREG);
6005         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6006         int jaddr=(int)out;
6007         emit_jns(0);
6008         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6009       }
6010     }
6011   }
6012 }
6013
6014 void fjump_assemble(int i,struct regstat *i_regs)
6015 {
6016   signed char *i_regmap=i_regs->regmap;
6017   int cc;
6018   int match;
6019   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6020   assem_debug("fmatch=%d\n",match);
6021   int fs,cs;
6022   int eaddr;
6023   int invert=0;
6024   int internal=internal_branch(branch_regs[i].is32,ba[i]);
6025   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6026   if(!match) invert=1;
6027   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6028   if(i>(ba[i]-start)>>2) invert=1;
6029   #endif
6030
6031   if(ooo[i]) {
6032     fs=get_reg(branch_regs[i].regmap,FSREG);
6033     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6034   }
6035   else {
6036     fs=get_reg(i_regmap,FSREG);
6037   }
6038
6039   // Check cop1 unusable
6040   if(!cop1_usable) {
6041     cs=get_reg(i_regmap,CSREG);
6042     assert(cs>=0);
6043     emit_testimm(cs,0x20000000);
6044     eaddr=(int)out;
6045     emit_jeq(0);
6046     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6047     cop1_usable=1;
6048   }
6049
6050   if(ooo[i]) {
6051     // Out of order execution (delay slot first)
6052     //printf("OOOE\n");
6053     ds_assemble(i+1,i_regs);
6054     int adj;
6055     uint64_t bc_unneeded=branch_regs[i].u;
6056     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6057     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6058     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6059     bc_unneeded|=1;
6060     bc_unneeded_upper|=1;
6061     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6062                   bc_unneeded,bc_unneeded_upper);
6063     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6064     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6065     cc=get_reg(branch_regs[i].regmap,CCREG);
6066     assert(cc==HOST_CCREG);
6067     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6068     assem_debug("cycle count (adj)\n");
6069     if(1) {
6070       int nottaken=0;
6071       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6072       if(1) {
6073         assert(fs>=0);
6074         emit_testimm(fs,0x800000);
6075         if(source[i]&0x10000) // BC1T
6076         {
6077           if(invert){
6078             nottaken=(int)out;
6079             emit_jeq(1);
6080           }else{
6081             add_to_linker((int)out,ba[i],internal);
6082             emit_jne(0);
6083           }
6084         }
6085         else // BC1F
6086           if(invert){
6087             nottaken=(int)out;
6088             emit_jne(1);
6089           }else{
6090             add_to_linker((int)out,ba[i],internal);
6091             emit_jeq(0);
6092           }
6093         {
6094         }
6095       } // if(!only32)
6096
6097       if(invert) {
6098         if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6099         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6100         else if(match) emit_addnop(13);
6101         #endif
6102         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6103         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6104         if(internal)
6105           assem_debug("branch: internal\n");
6106         else
6107           assem_debug("branch: external\n");
6108         if(internal&&is_ds[(ba[i]-start)>>2]) {
6109           ds_assemble_entry(i);
6110         }
6111         else {
6112           add_to_linker((int)out,ba[i],internal);
6113           emit_jmp(0);
6114         }
6115         set_jump_target(nottaken,(int)out);
6116       }
6117
6118       if(adj) {
6119         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6120       }
6121     } // (!unconditional)
6122   } // if(ooo)
6123   else
6124   {
6125     // In-order execution (branch first)
6126     //printf("IOE\n");
6127     int nottaken=0;
6128     if(1) {
6129       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6130       if(1) {
6131         assert(fs>=0);
6132         emit_testimm(fs,0x800000);
6133         if(source[i]&0x10000) // BC1T
6134         {
6135           nottaken=(int)out;
6136           emit_jeq(1);
6137         }
6138         else // BC1F
6139         {
6140           nottaken=(int)out;
6141           emit_jne(1);
6142         }
6143       }
6144     } // if(!unconditional)
6145     int adj;
6146     uint64_t ds_unneeded=branch_regs[i].u;
6147     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6148     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6149     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6150     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6151     ds_unneeded|=1;
6152     ds_unneeded_upper|=1;
6153     // branch taken
6154     //assem_debug("1:\n");
6155     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6156                   ds_unneeded,ds_unneeded_upper);
6157     // load regs
6158     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6159     address_generation(i+1,&branch_regs[i],0);
6160     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6161     ds_assemble(i+1,&branch_regs[i]);
6162     cc=get_reg(branch_regs[i].regmap,CCREG);
6163     if(cc==-1) {
6164       emit_loadreg(CCREG,cc=HOST_CCREG);
6165       // CHECK: Is the following instruction (fall thru) allocated ok?
6166     }
6167     assert(cc==HOST_CCREG);
6168     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6169     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6170     assem_debug("cycle count (adj)\n");
6171     if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6172     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6173     if(internal)
6174       assem_debug("branch: internal\n");
6175     else
6176       assem_debug("branch: external\n");
6177     if(internal&&is_ds[(ba[i]-start)>>2]) {
6178       ds_assemble_entry(i);
6179     }
6180     else {
6181       add_to_linker((int)out,ba[i],internal);
6182       emit_jmp(0);
6183     }
6184
6185     // branch not taken
6186     if(1) { // <- FIXME (don't need this)
6187       set_jump_target(nottaken,(int)out);
6188       assem_debug("1:\n");
6189       if(!likely[i]) {
6190         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6191                       ds_unneeded,ds_unneeded_upper);
6192         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6193         address_generation(i+1,&branch_regs[i],0);
6194         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6195         ds_assemble(i+1,&branch_regs[i]);
6196       }
6197       cc=get_reg(branch_regs[i].regmap,CCREG);
6198       if(cc==-1&&!likely[i]) {
6199         // Cycle count isn't in a register, temporarily load it then write it out
6200         emit_loadreg(CCREG,HOST_CCREG);
6201         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6202         int jaddr=(int)out;
6203         emit_jns(0);
6204         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6205         emit_storereg(CCREG,HOST_CCREG);
6206       }
6207       else{
6208         cc=get_reg(i_regmap,CCREG);
6209         assert(cc==HOST_CCREG);
6210         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6211         int jaddr=(int)out;
6212         emit_jns(0);
6213         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6214       }
6215     }
6216   }
6217 }
6218
6219 static void pagespan_assemble(int i,struct regstat *i_regs)
6220 {
6221   int s1l=get_reg(i_regs->regmap,rs1[i]);
6222   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6223   int s2l=get_reg(i_regs->regmap,rs2[i]);
6224   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6225   void *nt_branch=NULL;
6226   int taken=0;
6227   int nottaken=0;
6228   int unconditional=0;
6229   if(rs1[i]==0)
6230   {
6231     s1l=s2l;s1h=s2h;
6232     s2l=s2h=-1;
6233   }
6234   else if(rs2[i]==0)
6235   {
6236     s2l=s2h=-1;
6237   }
6238   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6239     s1h=s2h=-1;
6240   }
6241   int hr=0;
6242   int addr,alt,ntaddr;
6243   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6244   else {
6245     while(hr<HOST_REGS)
6246     {
6247       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6248          (i_regs->regmap[hr]&63)!=rs1[i] &&
6249          (i_regs->regmap[hr]&63)!=rs2[i] )
6250       {
6251         addr=hr++;break;
6252       }
6253       hr++;
6254     }
6255   }
6256   while(hr<HOST_REGS)
6257   {
6258     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6259        (i_regs->regmap[hr]&63)!=rs1[i] &&
6260        (i_regs->regmap[hr]&63)!=rs2[i] )
6261     {
6262       alt=hr++;break;
6263     }
6264     hr++;
6265   }
6266   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6267   {
6268     while(hr<HOST_REGS)
6269     {
6270       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6271          (i_regs->regmap[hr]&63)!=rs1[i] &&
6272          (i_regs->regmap[hr]&63)!=rs2[i] )
6273       {
6274         ntaddr=hr;break;
6275       }
6276       hr++;
6277     }
6278   }
6279   assert(hr<HOST_REGS);
6280   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6281     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6282   }
6283   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6284   if(opcode[i]==2) // J
6285   {
6286     unconditional=1;
6287   }
6288   if(opcode[i]==3) // JAL
6289   {
6290     // TODO: mini_ht
6291     int rt=get_reg(i_regs->regmap,31);
6292     emit_movimm(start+i*4+8,rt);
6293     unconditional=1;
6294   }
6295   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6296   {
6297     emit_mov(s1l,addr);
6298     if(opcode2[i]==9) // JALR
6299     {
6300       int rt=get_reg(i_regs->regmap,rt1[i]);
6301       emit_movimm(start+i*4+8,rt);
6302     }
6303   }
6304   if((opcode[i]&0x3f)==4) // BEQ
6305   {
6306     if(rs1[i]==rs2[i])
6307     {
6308       unconditional=1;
6309     }
6310     else
6311     #ifdef HAVE_CMOV_IMM
6312     if(s1h<0) {
6313       if(s2l>=0) emit_cmp(s1l,s2l);
6314       else emit_test(s1l,s1l);
6315       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6316     }
6317     else
6318     #endif
6319     {
6320       assert(s1l>=0);
6321       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6322       if(s1h>=0) {
6323         if(s2h>=0) emit_cmp(s1h,s2h);
6324         else emit_test(s1h,s1h);
6325         emit_cmovne_reg(alt,addr);
6326       }
6327       if(s2l>=0) emit_cmp(s1l,s2l);
6328       else emit_test(s1l,s1l);
6329       emit_cmovne_reg(alt,addr);
6330     }
6331   }
6332   if((opcode[i]&0x3f)==5) // BNE
6333   {
6334     #ifdef HAVE_CMOV_IMM
6335     if(s1h<0) {
6336       if(s2l>=0) emit_cmp(s1l,s2l);
6337       else emit_test(s1l,s1l);
6338       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6339     }
6340     else
6341     #endif
6342     {
6343       assert(s1l>=0);
6344       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6345       if(s1h>=0) {
6346         if(s2h>=0) emit_cmp(s1h,s2h);
6347         else emit_test(s1h,s1h);
6348         emit_cmovne_reg(alt,addr);
6349       }
6350       if(s2l>=0) emit_cmp(s1l,s2l);
6351       else emit_test(s1l,s1l);
6352       emit_cmovne_reg(alt,addr);
6353     }
6354   }
6355   if((opcode[i]&0x3f)==0x14) // BEQL
6356   {
6357     if(s1h>=0) {
6358       if(s2h>=0) emit_cmp(s1h,s2h);
6359       else emit_test(s1h,s1h);
6360       nottaken=(int)out;
6361       emit_jne(0);
6362     }
6363     if(s2l>=0) emit_cmp(s1l,s2l);
6364     else emit_test(s1l,s1l);
6365     if(nottaken) set_jump_target(nottaken,(int)out);
6366     nottaken=(int)out;
6367     emit_jne(0);
6368   }
6369   if((opcode[i]&0x3f)==0x15) // BNEL
6370   {
6371     if(s1h>=0) {
6372       if(s2h>=0) emit_cmp(s1h,s2h);
6373       else emit_test(s1h,s1h);
6374       taken=(int)out;
6375       emit_jne(0);
6376     }
6377     if(s2l>=0) emit_cmp(s1l,s2l);
6378     else emit_test(s1l,s1l);
6379     nottaken=(int)out;
6380     emit_jeq(0);
6381     if(taken) set_jump_target(taken,(int)out);
6382   }
6383   if((opcode[i]&0x3f)==6) // BLEZ
6384   {
6385     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6386     emit_cmpimm(s1l,1);
6387     if(s1h>=0) emit_mov(addr,ntaddr);
6388     emit_cmovl_reg(alt,addr);
6389     if(s1h>=0) {
6390       emit_test(s1h,s1h);
6391       emit_cmovne_reg(ntaddr,addr);
6392       emit_cmovs_reg(alt,addr);
6393     }
6394   }
6395   if((opcode[i]&0x3f)==7) // BGTZ
6396   {
6397     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6398     emit_cmpimm(s1l,1);
6399     if(s1h>=0) emit_mov(addr,alt);
6400     emit_cmovl_reg(ntaddr,addr);
6401     if(s1h>=0) {
6402       emit_test(s1h,s1h);
6403       emit_cmovne_reg(alt,addr);
6404       emit_cmovs_reg(ntaddr,addr);
6405     }
6406   }
6407   if((opcode[i]&0x3f)==0x16) // BLEZL
6408   {
6409     assert((opcode[i]&0x3f)!=0x16);
6410   }
6411   if((opcode[i]&0x3f)==0x17) // BGTZL
6412   {
6413     assert((opcode[i]&0x3f)!=0x17);
6414   }
6415   assert(opcode[i]!=1); // BLTZ/BGEZ
6416
6417   //FIXME: Check CSREG
6418   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6419     if((source[i]&0x30000)==0) // BC1F
6420     {
6421       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6422       emit_testimm(s1l,0x800000);
6423       emit_cmovne_reg(alt,addr);
6424     }
6425     if((source[i]&0x30000)==0x10000) // BC1T
6426     {
6427       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6428       emit_testimm(s1l,0x800000);
6429       emit_cmovne_reg(alt,addr);
6430     }
6431     if((source[i]&0x30000)==0x20000) // BC1FL
6432     {
6433       emit_testimm(s1l,0x800000);
6434       nottaken=(int)out;
6435       emit_jne(0);
6436     }
6437     if((source[i]&0x30000)==0x30000) // BC1TL
6438     {
6439       emit_testimm(s1l,0x800000);
6440       nottaken=(int)out;
6441       emit_jeq(0);
6442     }
6443   }
6444
6445   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6446   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6447   if(likely[i]||unconditional)
6448   {
6449     emit_movimm(ba[i],HOST_BTREG);
6450   }
6451   else if(addr!=HOST_BTREG)
6452   {
6453     emit_mov(addr,HOST_BTREG);
6454   }
6455   void *branch_addr=out;
6456   emit_jmp(0);
6457   int target_addr=start+i*4+5;
6458   void *stub=out;
6459   void *compiled_target_addr=check_addr(target_addr);
6460   emit_extjump_ds((int)branch_addr,target_addr);
6461   if(compiled_target_addr) {
6462     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6463     add_link(target_addr,stub);
6464   }
6465   else set_jump_target((int)branch_addr,(int)stub);
6466   if(likely[i]) {
6467     // Not-taken path
6468     set_jump_target((int)nottaken,(int)out);
6469     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6470     void *branch_addr=out;
6471     emit_jmp(0);
6472     int target_addr=start+i*4+8;
6473     void *stub=out;
6474     void *compiled_target_addr=check_addr(target_addr);
6475     emit_extjump_ds((int)branch_addr,target_addr);
6476     if(compiled_target_addr) {
6477       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6478       add_link(target_addr,stub);
6479     }
6480     else set_jump_target((int)branch_addr,(int)stub);
6481   }
6482 }
6483
6484 // Assemble the delay slot for the above
6485 static void pagespan_ds()
6486 {
6487   assem_debug("initial delay slot:\n");
6488   u_int vaddr=start+1;
6489   u_int page=get_page(vaddr);
6490   u_int vpage=get_vpage(vaddr);
6491   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6492   do_dirty_stub_ds();
6493   ll_add(jump_in+page,vaddr,(void *)out);
6494   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6495   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6496     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6497   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6498     emit_writeword(HOST_BTREG,(int)&branch_target);
6499   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6500   address_generation(0,&regs[0],regs[0].regmap_entry);
6501   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6502     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6503   cop1_usable=0;
6504   is_delayslot=0;
6505   switch(itype[0]) {
6506     case ALU:
6507       alu_assemble(0,&regs[0]);break;
6508     case IMM16:
6509       imm16_assemble(0,&regs[0]);break;
6510     case SHIFT:
6511       shift_assemble(0,&regs[0]);break;
6512     case SHIFTIMM:
6513       shiftimm_assemble(0,&regs[0]);break;
6514     case LOAD:
6515       load_assemble(0,&regs[0]);break;
6516     case LOADLR:
6517       loadlr_assemble(0,&regs[0]);break;
6518     case STORE:
6519       store_assemble(0,&regs[0]);break;
6520     case STORELR:
6521       storelr_assemble(0,&regs[0]);break;
6522     case COP0:
6523       cop0_assemble(0,&regs[0]);break;
6524     case COP1:
6525       cop1_assemble(0,&regs[0]);break;
6526     case C1LS:
6527       c1ls_assemble(0,&regs[0]);break;
6528     case COP2:
6529       cop2_assemble(0,&regs[0]);break;
6530     case C2LS:
6531       c2ls_assemble(0,&regs[0]);break;
6532     case C2OP:
6533       c2op_assemble(0,&regs[0]);break;
6534     case FCONV:
6535       fconv_assemble(0,&regs[0]);break;
6536     case FLOAT:
6537       float_assemble(0,&regs[0]);break;
6538     case FCOMP:
6539       fcomp_assemble(0,&regs[0]);break;
6540     case MULTDIV:
6541       multdiv_assemble(0,&regs[0]);break;
6542     case MOV:
6543       mov_assemble(0,&regs[0]);break;
6544     case SYSCALL:
6545     case HLECALL:
6546     case INTCALL:
6547     case SPAN:
6548     case UJUMP:
6549     case RJUMP:
6550     case CJUMP:
6551     case SJUMP:
6552     case FJUMP:
6553       printf("Jump in the delay slot.  This is probably a bug.\n");
6554   }
6555   int btaddr=get_reg(regs[0].regmap,BTREG);
6556   if(btaddr<0) {
6557     btaddr=get_reg(regs[0].regmap,-1);
6558     emit_readword((int)&branch_target,btaddr);
6559   }
6560   assert(btaddr!=HOST_CCREG);
6561   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6562 #ifdef HOST_IMM8
6563   emit_movimm(start+4,HOST_TEMPREG);
6564   emit_cmp(btaddr,HOST_TEMPREG);
6565 #else
6566   emit_cmpimm(btaddr,start+4);
6567 #endif
6568   int branch=(int)out;
6569   emit_jeq(0);
6570   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6571   emit_jmp(jump_vaddr_reg[btaddr]);
6572   set_jump_target(branch,(int)out);
6573   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6574   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6575 }
6576
6577 // Basic liveness analysis for MIPS registers
6578 void unneeded_registers(int istart,int iend,int r)
6579 {
6580   int i;
6581   uint64_t u,uu,b,bu;
6582   uint64_t temp_u,temp_uu;
6583   uint64_t tdep;
6584   if(iend==slen-1) {
6585     u=1;uu=1;
6586   }else{
6587     u=unneeded_reg[iend+1];
6588     uu=unneeded_reg_upper[iend+1];
6589     u=1;uu=1;
6590   }
6591   for (i=iend;i>=istart;i--)
6592   {
6593     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6594     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6595     {
6596       // If subroutine call, flag return address as a possible branch target
6597       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6598
6599       if(ba[i]<start || ba[i]>=(start+slen*4))
6600       {
6601         // Branch out of this block, flush all regs
6602         u=1;
6603         uu=1;
6604         /* Hexagon hack
6605         if(itype[i]==UJUMP&&rt1[i]==31)
6606         {
6607           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6608         }
6609         if(itype[i]==RJUMP&&rs1[i]==31)
6610         {
6611           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6612         }
6613         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6614           if(itype[i]==UJUMP&&rt1[i]==31)
6615           {
6616             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6617             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6618           }
6619           if(itype[i]==RJUMP&&rs1[i]==31)
6620           {
6621             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6622             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6623           }
6624         }*/
6625         branch_unneeded_reg[i]=u;
6626         branch_unneeded_reg_upper[i]=uu;
6627         // Merge in delay slot
6628         tdep=(~uu>>rt1[i+1])&1;
6629         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6630         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6631         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6632         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6633         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6634         u|=1;uu|=1;
6635         // If branch is "likely" (and conditional)
6636         // then we skip the delay slot on the fall-thru path
6637         if(likely[i]) {
6638           if(i<slen-1) {
6639             u&=unneeded_reg[i+2];
6640             uu&=unneeded_reg_upper[i+2];
6641           }
6642           else
6643           {
6644             u=1;
6645             uu=1;
6646           }
6647         }
6648       }
6649       else
6650       {
6651         // Internal branch, flag target
6652         bt[(ba[i]-start)>>2]=1;
6653         if(ba[i]<=start+i*4) {
6654           // Backward branch
6655           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6656           {
6657             // Unconditional branch
6658             temp_u=1;temp_uu=1;
6659           } else {
6660             // Conditional branch (not taken case)
6661             temp_u=unneeded_reg[i+2];
6662             temp_uu=unneeded_reg_upper[i+2];
6663           }
6664           // Merge in delay slot
6665           tdep=(~temp_uu>>rt1[i+1])&1;
6666           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6667           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6668           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6669           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6670           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6671           temp_u|=1;temp_uu|=1;
6672           // If branch is "likely" (and conditional)
6673           // then we skip the delay slot on the fall-thru path
6674           if(likely[i]) {
6675             if(i<slen-1) {
6676               temp_u&=unneeded_reg[i+2];
6677               temp_uu&=unneeded_reg_upper[i+2];
6678             }
6679             else
6680             {
6681               temp_u=1;
6682               temp_uu=1;
6683             }
6684           }
6685           tdep=(~temp_uu>>rt1[i])&1;
6686           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6687           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6688           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6689           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6690           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6691           temp_u|=1;temp_uu|=1;
6692           unneeded_reg[i]=temp_u;
6693           unneeded_reg_upper[i]=temp_uu;
6694           // Only go three levels deep.  This recursion can take an
6695           // excessive amount of time if there are a lot of nested loops.
6696           if(r<2) {
6697             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6698           }else{
6699             unneeded_reg[(ba[i]-start)>>2]=1;
6700             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6701           }
6702         } /*else*/ if(1) {
6703           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6704           {
6705             // Unconditional branch
6706             u=unneeded_reg[(ba[i]-start)>>2];
6707             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6708             branch_unneeded_reg[i]=u;
6709             branch_unneeded_reg_upper[i]=uu;
6710         //u=1;
6711         //uu=1;
6712         //branch_unneeded_reg[i]=u;
6713         //branch_unneeded_reg_upper[i]=uu;
6714             // Merge in delay slot
6715             tdep=(~uu>>rt1[i+1])&1;
6716             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6717             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6718             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6719             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6720             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6721             u|=1;uu|=1;
6722           } else {
6723             // Conditional branch
6724             b=unneeded_reg[(ba[i]-start)>>2];
6725             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6726             branch_unneeded_reg[i]=b;
6727             branch_unneeded_reg_upper[i]=bu;
6728         //b=1;
6729         //bu=1;
6730         //branch_unneeded_reg[i]=b;
6731         //branch_unneeded_reg_upper[i]=bu;
6732             // Branch delay slot
6733             tdep=(~uu>>rt1[i+1])&1;
6734             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6735             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6736             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6737             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6738             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6739             b|=1;bu|=1;
6740             // If branch is "likely" then we skip the
6741             // delay slot on the fall-thru path
6742             if(likely[i]) {
6743               u=b;
6744               uu=bu;
6745               if(i<slen-1) {
6746                 u&=unneeded_reg[i+2];
6747                 uu&=unneeded_reg_upper[i+2];
6748         //u=1;
6749         //uu=1;
6750               }
6751             } else {
6752               u&=b;
6753               uu&=bu;
6754         //u=1;
6755         //uu=1;
6756             }
6757             if(i<slen-1) {
6758               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6759               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6760         //branch_unneeded_reg[i]=1;
6761         //branch_unneeded_reg_upper[i]=1;
6762             } else {
6763               branch_unneeded_reg[i]=1;
6764               branch_unneeded_reg_upper[i]=1;
6765             }
6766           }
6767         }
6768       }
6769     }
6770     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6771     {
6772       // SYSCALL instruction (software interrupt)
6773       u=1;
6774       uu=1;
6775     }
6776     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6777     {
6778       // ERET instruction (return from interrupt)
6779       u=1;
6780       uu=1;
6781     }
6782     //u=uu=1; // DEBUG
6783     tdep=(~uu>>rt1[i])&1;
6784     // Written registers are unneeded
6785     u|=1LL<<rt1[i];
6786     u|=1LL<<rt2[i];
6787     uu|=1LL<<rt1[i];
6788     uu|=1LL<<rt2[i];
6789     // Accessed registers are needed
6790     u&=~(1LL<<rs1[i]);
6791     u&=~(1LL<<rs2[i]);
6792     uu&=~(1LL<<us1[i]);
6793     uu&=~(1LL<<us2[i]);
6794     // Source-target dependencies
6795     uu&=~(tdep<<dep1[i]);
6796     uu&=~(tdep<<dep2[i]);
6797     // R0 is always unneeded
6798     u|=1;uu|=1;
6799     // Save it
6800     unneeded_reg[i]=u;
6801     unneeded_reg_upper[i]=uu;
6802     /*
6803     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6804     printf("U:");
6805     int r;
6806     for(r=1;r<=CCREG;r++) {
6807       if((unneeded_reg[i]>>r)&1) {
6808         if(r==HIREG) printf(" HI");
6809         else if(r==LOREG) printf(" LO");
6810         else printf(" r%d",r);
6811       }
6812     }
6813     printf(" UU:");
6814     for(r=1;r<=CCREG;r++) {
6815       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6816         if(r==HIREG) printf(" HI");
6817         else if(r==LOREG) printf(" LO");
6818         else printf(" r%d",r);
6819       }
6820     }
6821     printf("\n");*/
6822   }
6823 #ifdef FORCE32
6824   for (i=iend;i>=istart;i--)
6825   {
6826     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6827   }
6828 #endif
6829 }
6830
6831 // Identify registers which are likely to contain 32-bit values
6832 // This is used to predict whether any branches will jump to a
6833 // location with 64-bit values in registers.
6834 static void provisional_32bit()
6835 {
6836   int i,j;
6837   uint64_t is32=1;
6838   uint64_t lastbranch=1;
6839
6840   for(i=0;i<slen;i++)
6841   {
6842     if(i>0) {
6843       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6844         if(i>1) is32=lastbranch;
6845         else is32=1;
6846       }
6847     }
6848     if(i>1)
6849     {
6850       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6851         if(likely[i-2]) {
6852           if(i>2) is32=lastbranch;
6853           else is32=1;
6854         }
6855       }
6856       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6857       {
6858         if(rs1[i-2]==0||rs2[i-2]==0)
6859         {
6860           if(rs1[i-2]) {
6861             is32|=1LL<<rs1[i-2];
6862           }
6863           if(rs2[i-2]) {
6864             is32|=1LL<<rs2[i-2];
6865           }
6866         }
6867       }
6868     }
6869     // If something jumps here with 64-bit values
6870     // then promote those registers to 64 bits
6871     if(bt[i])
6872     {
6873       uint64_t temp_is32=is32;
6874       for(j=i-1;j>=0;j--)
6875       {
6876         if(ba[j]==start+i*4)
6877           //temp_is32&=branch_regs[j].is32;
6878           temp_is32&=p32[j];
6879       }
6880       for(j=i;j<slen;j++)
6881       {
6882         if(ba[j]==start+i*4)
6883           temp_is32=1;
6884       }
6885       is32=temp_is32;
6886     }
6887     int type=itype[i];
6888     int op=opcode[i];
6889     int op2=opcode2[i];
6890     int rt=rt1[i];
6891     int s1=rs1[i];
6892     int s2=rs2[i];
6893     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6894       // Branches don't write registers, consider the delay slot instead.
6895       type=itype[i+1];
6896       op=opcode[i+1];
6897       op2=opcode2[i+1];
6898       rt=rt1[i+1];
6899       s1=rs1[i+1];
6900       s2=rs2[i+1];
6901       lastbranch=is32;
6902     }
6903     switch(type) {
6904       case LOAD:
6905         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6906            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6907           is32&=~(1LL<<rt);
6908         else
6909           is32|=1LL<<rt;
6910         break;
6911       case STORE:
6912       case STORELR:
6913         break;
6914       case LOADLR:
6915         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6916         if(op==0x22) is32|=1LL<<rt; // LWL
6917         break;
6918       case IMM16:
6919         if (op==0x08||op==0x09|| // ADDI/ADDIU
6920             op==0x0a||op==0x0b|| // SLTI/SLTIU
6921             op==0x0c|| // ANDI
6922             op==0x0f)  // LUI
6923         {
6924           is32|=1LL<<rt;
6925         }
6926         if(op==0x18||op==0x19) { // DADDI/DADDIU
6927           is32&=~(1LL<<rt);
6928           //if(imm[i]==0)
6929           //  is32|=((is32>>s1)&1LL)<<rt;
6930         }
6931         if(op==0x0d||op==0x0e) { // ORI/XORI
6932           uint64_t sr=((is32>>s1)&1LL);
6933           is32&=~(1LL<<rt);
6934           is32|=sr<<rt;
6935         }
6936         break;
6937       case UJUMP:
6938         break;
6939       case RJUMP:
6940         break;
6941       case CJUMP:
6942         break;
6943       case SJUMP:
6944         break;
6945       case FJUMP:
6946         break;
6947       case ALU:
6948         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6949           is32|=1LL<<rt;
6950         }
6951         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6952           is32|=1LL<<rt;
6953         }
6954         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6955           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6956           is32&=~(1LL<<rt);
6957           is32|=sr<<rt;
6958         }
6959         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6960           if(s1==0&&s2==0) {
6961             is32|=1LL<<rt;
6962           }
6963           else if(s2==0) {
6964             uint64_t sr=((is32>>s1)&1LL);
6965             is32&=~(1LL<<rt);
6966             is32|=sr<<rt;
6967           }
6968           else if(s1==0) {
6969             uint64_t sr=((is32>>s2)&1LL);
6970             is32&=~(1LL<<rt);
6971             is32|=sr<<rt;
6972           }
6973           else {
6974             is32&=~(1LL<<rt);
6975           }
6976         }
6977         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6978           if(s1==0&&s2==0) {
6979             is32|=1LL<<rt;
6980           }
6981           else if(s2==0) {
6982             uint64_t sr=((is32>>s1)&1LL);
6983             is32&=~(1LL<<rt);
6984             is32|=sr<<rt;
6985           }
6986           else {
6987             is32&=~(1LL<<rt);
6988           }
6989         }
6990         break;
6991       case MULTDIV:
6992         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
6993           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
6994         }
6995         else {
6996           is32|=(1LL<<HIREG)|(1LL<<LOREG);
6997         }
6998         break;
6999       case MOV:
7000         {
7001           uint64_t sr=((is32>>s1)&1LL);
7002           is32&=~(1LL<<rt);
7003           is32|=sr<<rt;
7004         }
7005         break;
7006       case SHIFT:
7007         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7008         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7009         break;
7010       case SHIFTIMM:
7011         is32|=1LL<<rt;
7012         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7013         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7014         break;
7015       case COP0:
7016         if(op2==0) is32|=1LL<<rt; // MFC0
7017         break;
7018       case COP1:
7019       case COP2:
7020         if(op2==0) is32|=1LL<<rt; // MFC1
7021         if(op2==1) is32&=~(1LL<<rt); // DMFC1
7022         if(op2==2) is32|=1LL<<rt; // CFC1
7023         break;
7024       case C1LS:
7025       case C2LS:
7026         break;
7027       case FLOAT:
7028       case FCONV:
7029         break;
7030       case FCOMP:
7031         break;
7032       case C2OP:
7033       case SYSCALL:
7034       case HLECALL:
7035         break;
7036       default:
7037         break;
7038     }
7039     is32|=1;
7040     p32[i]=is32;
7041
7042     if(i>0)
7043     {
7044       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7045       {
7046         if(rt1[i-1]==31) // JAL/JALR
7047         {
7048           // Subroutine call will return here, don't alloc any registers
7049           is32=1;
7050         }
7051         else if(i+1<slen)
7052         {
7053           // Internal branch will jump here, match registers to caller
7054           is32=0x3FFFFFFFFLL;
7055         }
7056       }
7057     }
7058   }
7059 }
7060
7061 // Identify registers which may be assumed to contain 32-bit values
7062 // and where optimizations will rely on this.
7063 // This is used to determine whether backward branches can safely
7064 // jump to a location with 64-bit values in registers.
7065 static void provisional_r32()
7066 {
7067   u_int r32=0;
7068   int i;
7069
7070   for (i=slen-1;i>=0;i--)
7071   {
7072     int hr;
7073     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7074     {
7075       if(ba[i]<start || ba[i]>=(start+slen*4))
7076       {
7077         // Branch out of this block, don't need anything
7078         r32=0;
7079       }
7080       else
7081       {
7082         // Internal branch
7083         // Need whatever matches the target
7084         // (and doesn't get overwritten by the delay slot instruction)
7085         r32=0;
7086         int t=(ba[i]-start)>>2;
7087         if(ba[i]>start+i*4) {
7088           // Forward branch
7089           //if(!(requires_32bit[t]&~regs[i].was32))
7090           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7091           if(!(pr32[t]&~regs[i].was32))
7092             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7093         }else{
7094           // Backward branch
7095           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7096             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7097         }
7098       }
7099       // Conditional branch may need registers for following instructions
7100       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7101       {
7102         if(i<slen-2) {
7103           //r32|=requires_32bit[i+2];
7104           r32|=pr32[i+2];
7105           r32&=regs[i].was32;
7106           // Mark this address as a branch target since it may be called
7107           // upon return from interrupt
7108           //bt[i+2]=1;
7109         }
7110       }
7111       // Merge in delay slot
7112       if(!likely[i]) {
7113         // These are overwritten unless the branch is "likely"
7114         // and the delay slot is nullified if not taken
7115         r32&=~(1LL<<rt1[i+1]);
7116         r32&=~(1LL<<rt2[i+1]);
7117       }
7118       // Assume these are needed (delay slot)
7119       if(us1[i+1]>0)
7120       {
7121         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7122       }
7123       if(us2[i+1]>0)
7124       {
7125         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7126       }
7127       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7128       {
7129         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7130       }
7131       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7132       {
7133         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7134       }
7135     }
7136     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7137     {
7138       // SYSCALL instruction (software interrupt)
7139       r32=0;
7140     }
7141     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7142     {
7143       // ERET instruction (return from interrupt)
7144       r32=0;
7145     }
7146     // Check 32 bits
7147     r32&=~(1LL<<rt1[i]);
7148     r32&=~(1LL<<rt2[i]);
7149     if(us1[i]>0)
7150     {
7151       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7152     }
7153     if(us2[i]>0)
7154     {
7155       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7156     }
7157     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7158     {
7159       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7160     }
7161     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7162     {
7163       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7164     }
7165     //requires_32bit[i]=r32;
7166     pr32[i]=r32;
7167
7168     // Dirty registers which are 32-bit, require 32-bit input
7169     // as they will be written as 32-bit values
7170     for(hr=0;hr<HOST_REGS;hr++)
7171     {
7172       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7173         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7174           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7175           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7176           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7177         }
7178       }
7179     }
7180   }
7181 }
7182
7183 // Write back dirty registers as soon as we will no longer modify them,
7184 // so that we don't end up with lots of writes at the branches.
7185 void clean_registers(int istart,int iend,int wr)
7186 {
7187   int i;
7188   int r;
7189   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7190   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7191   if(iend==slen-1) {
7192     will_dirty_i=will_dirty_next=0;
7193     wont_dirty_i=wont_dirty_next=0;
7194   }else{
7195     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7196     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7197   }
7198   for (i=iend;i>=istart;i--)
7199   {
7200     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7201     {
7202       if(ba[i]<start || ba[i]>=(start+slen*4))
7203       {
7204         // Branch out of this block, flush all regs
7205         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7206         {
7207           // Unconditional branch
7208           will_dirty_i=0;
7209           wont_dirty_i=0;
7210           // Merge in delay slot (will dirty)
7211           for(r=0;r<HOST_REGS;r++) {
7212             if(r!=EXCLUDE_REG) {
7213               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7214               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7215               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7216               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7217               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7218               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7219               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7220               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7221               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7222               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7223               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7224               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7225               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7226               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7227             }
7228           }
7229         }
7230         else
7231         {
7232           // Conditional branch
7233           will_dirty_i=0;
7234           wont_dirty_i=wont_dirty_next;
7235           // Merge in delay slot (will dirty)
7236           for(r=0;r<HOST_REGS;r++) {
7237             if(r!=EXCLUDE_REG) {
7238               if(!likely[i]) {
7239                 // Might not dirty if likely branch is not taken
7240                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7241                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7242                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7243                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7244                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7245                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7246                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7247                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7248                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7249                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7250                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7251                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7252                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7253                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7254               }
7255             }
7256           }
7257         }
7258         // Merge in delay slot (wont dirty)
7259         for(r=0;r<HOST_REGS;r++) {
7260           if(r!=EXCLUDE_REG) {
7261             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7262             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7263             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7264             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7265             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7266             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7267             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7268             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7269             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7270             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7271           }
7272         }
7273         if(wr) {
7274           #ifndef DESTRUCTIVE_WRITEBACK
7275           branch_regs[i].dirty&=wont_dirty_i;
7276           #endif
7277           branch_regs[i].dirty|=will_dirty_i;
7278         }
7279       }
7280       else
7281       {
7282         // Internal branch
7283         if(ba[i]<=start+i*4) {
7284           // Backward branch
7285           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7286           {
7287             // Unconditional branch
7288             temp_will_dirty=0;
7289             temp_wont_dirty=0;
7290             // Merge in delay slot (will dirty)
7291             for(r=0;r<HOST_REGS;r++) {
7292               if(r!=EXCLUDE_REG) {
7293                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7294                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7295                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7296                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7297                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7298                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7299                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7300                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7301                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7302                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7303                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7304                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7305                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7306                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7307               }
7308             }
7309           } else {
7310             // Conditional branch (not taken case)
7311             temp_will_dirty=will_dirty_next;
7312             temp_wont_dirty=wont_dirty_next;
7313             // Merge in delay slot (will dirty)
7314             for(r=0;r<HOST_REGS;r++) {
7315               if(r!=EXCLUDE_REG) {
7316                 if(!likely[i]) {
7317                   // Will not dirty if likely branch is not taken
7318                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7319                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7320                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7321                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7322                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7323                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7324                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7325                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7326                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7327                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7328                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7329                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7330                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7331                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7332                 }
7333               }
7334             }
7335           }
7336           // Merge in delay slot (wont dirty)
7337           for(r=0;r<HOST_REGS;r++) {
7338             if(r!=EXCLUDE_REG) {
7339               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7340               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7341               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7342               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7343               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7344               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7345               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7346               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7347               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7348               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7349             }
7350           }
7351           // Deal with changed mappings
7352           if(i<iend) {
7353             for(r=0;r<HOST_REGS;r++) {
7354               if(r!=EXCLUDE_REG) {
7355                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7356                   temp_will_dirty&=~(1<<r);
7357                   temp_wont_dirty&=~(1<<r);
7358                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7359                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7360                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7361                   } else {
7362                     temp_will_dirty|=1<<r;
7363                     temp_wont_dirty|=1<<r;
7364                   }
7365                 }
7366               }
7367             }
7368           }
7369           if(wr) {
7370             will_dirty[i]=temp_will_dirty;
7371             wont_dirty[i]=temp_wont_dirty;
7372             clean_registers((ba[i]-start)>>2,i-1,0);
7373           }else{
7374             // Limit recursion.  It can take an excessive amount
7375             // of time if there are a lot of nested loops.
7376             will_dirty[(ba[i]-start)>>2]=0;
7377             wont_dirty[(ba[i]-start)>>2]=-1;
7378           }
7379         }
7380         /*else*/ if(1)
7381         {
7382           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7383           {
7384             // Unconditional branch
7385             will_dirty_i=0;
7386             wont_dirty_i=0;
7387           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7388             for(r=0;r<HOST_REGS;r++) {
7389               if(r!=EXCLUDE_REG) {
7390                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7391                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7392                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7393                 }
7394               }
7395             }
7396           //}
7397             // Merge in delay slot
7398             for(r=0;r<HOST_REGS;r++) {
7399               if(r!=EXCLUDE_REG) {
7400                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7401                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7402                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7403                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7404                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7405                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7406                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7407                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7408                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7409                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7410                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7411                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7412                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7413                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7414               }
7415             }
7416           } else {
7417             // Conditional branch
7418             will_dirty_i=will_dirty_next;
7419             wont_dirty_i=wont_dirty_next;
7420           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7421             for(r=0;r<HOST_REGS;r++) {
7422               if(r!=EXCLUDE_REG) {
7423                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7424                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7425                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7426                 }
7427                 else
7428                 {
7429                   will_dirty_i&=~(1<<r);
7430                 }
7431                 // Treat delay slot as part of branch too
7432                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7433                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7434                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7435                 }
7436                 else
7437                 {
7438                   will_dirty[i+1]&=~(1<<r);
7439                 }*/
7440               }
7441             }
7442           //}
7443             // Merge in delay slot
7444             for(r=0;r<HOST_REGS;r++) {
7445               if(r!=EXCLUDE_REG) {
7446                 if(!likely[i]) {
7447                   // Might not dirty if likely branch is not taken
7448                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7449                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7450                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7451                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7452                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7453                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7454                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7455                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7456                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7457                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7458                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7459                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7460                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7461                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7462                 }
7463               }
7464             }
7465           }
7466           // Merge in delay slot
7467           for(r=0;r<HOST_REGS;r++) {
7468             if(r!=EXCLUDE_REG) {
7469               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7470               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7471               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7472               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7473               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7474               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7475               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7476               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7477               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7478               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7479             }
7480           }
7481           if(wr) {
7482             #ifndef DESTRUCTIVE_WRITEBACK
7483             branch_regs[i].dirty&=wont_dirty_i;
7484             #endif
7485             branch_regs[i].dirty|=will_dirty_i;
7486           }
7487         }
7488       }
7489     }
7490     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7491     {
7492       // SYSCALL instruction (software interrupt)
7493       will_dirty_i=0;
7494       wont_dirty_i=0;
7495     }
7496     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7497     {
7498       // ERET instruction (return from interrupt)
7499       will_dirty_i=0;
7500       wont_dirty_i=0;
7501     }
7502     will_dirty_next=will_dirty_i;
7503     wont_dirty_next=wont_dirty_i;
7504     for(r=0;r<HOST_REGS;r++) {
7505       if(r!=EXCLUDE_REG) {
7506         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7507         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7508         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7509         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7510         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7511         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7512         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7513         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7514         if(i>istart) {
7515           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7516           {
7517             // Don't store a register immediately after writing it,
7518             // may prevent dual-issue.
7519             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7520             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7521           }
7522         }
7523       }
7524     }
7525     // Save it
7526     will_dirty[i]=will_dirty_i;
7527     wont_dirty[i]=wont_dirty_i;
7528     // Mark registers that won't be dirtied as not dirty
7529     if(wr) {
7530       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7531       for(r=0;r<HOST_REGS;r++) {
7532         if((will_dirty_i>>r)&1) {
7533           printf(" r%d",r);
7534         }
7535       }
7536       printf("\n");*/
7537
7538       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7539         regs[i].dirty|=will_dirty_i;
7540         #ifndef DESTRUCTIVE_WRITEBACK
7541         regs[i].dirty&=wont_dirty_i;
7542         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7543         {
7544           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7545             for(r=0;r<HOST_REGS;r++) {
7546               if(r!=EXCLUDE_REG) {
7547                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7548                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7549                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7550               }
7551             }
7552           }
7553         }
7554         else
7555         {
7556           if(i<iend) {
7557             for(r=0;r<HOST_REGS;r++) {
7558               if(r!=EXCLUDE_REG) {
7559                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7560                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7561                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7562               }
7563             }
7564           }
7565         }
7566         #endif
7567       //}
7568     }
7569     // Deal with changed mappings
7570     temp_will_dirty=will_dirty_i;
7571     temp_wont_dirty=wont_dirty_i;
7572     for(r=0;r<HOST_REGS;r++) {
7573       if(r!=EXCLUDE_REG) {
7574         int nr;
7575         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7576           if(wr) {
7577             #ifndef DESTRUCTIVE_WRITEBACK
7578             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7579             #endif
7580             regs[i].wasdirty|=will_dirty_i&(1<<r);
7581           }
7582         }
7583         else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7584           // Register moved to a different register
7585           will_dirty_i&=~(1<<r);
7586           wont_dirty_i&=~(1<<r);
7587           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7588           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7589           if(wr) {
7590             #ifndef DESTRUCTIVE_WRITEBACK
7591             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7592             #endif
7593             regs[i].wasdirty|=will_dirty_i&(1<<r);
7594           }
7595         }
7596         else {
7597           will_dirty_i&=~(1<<r);
7598           wont_dirty_i&=~(1<<r);
7599           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7600             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7601             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7602           } else {
7603             wont_dirty_i|=1<<r;
7604             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7605           }
7606         }
7607       }
7608     }
7609   }
7610 }
7611
7612   /* disassembly */
7613 void disassemble_inst(int i)
7614 {
7615     if (bt[i]) printf("*"); else printf(" ");
7616     switch(itype[i]) {
7617       case UJUMP:
7618         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7619       case CJUMP:
7620         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7621       case SJUMP:
7622         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7623       case FJUMP:
7624         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7625       case RJUMP:
7626         if (opcode[i]==0x9&&rt1[i]!=31)
7627           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7628         else
7629           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7630         break;
7631       case SPAN:
7632         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7633       case IMM16:
7634         if(opcode[i]==0xf) //LUI
7635           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7636         else
7637           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7638         break;
7639       case LOAD:
7640       case LOADLR:
7641         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7642         break;
7643       case STORE:
7644       case STORELR:
7645         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7646         break;
7647       case ALU:
7648       case SHIFT:
7649         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7650         break;
7651       case MULTDIV:
7652         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7653         break;
7654       case SHIFTIMM:
7655         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7656         break;
7657       case MOV:
7658         if((opcode2[i]&0x1d)==0x10)
7659           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7660         else if((opcode2[i]&0x1d)==0x11)
7661           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7662         else
7663           printf (" %x: %s\n",start+i*4,insn[i]);
7664         break;
7665       case COP0:
7666         if(opcode2[i]==0)
7667           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7668         else if(opcode2[i]==4)
7669           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7670         else printf (" %x: %s\n",start+i*4,insn[i]);
7671         break;
7672       case COP1:
7673         if(opcode2[i]<3)
7674           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7675         else if(opcode2[i]>3)
7676           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7677         else printf (" %x: %s\n",start+i*4,insn[i]);
7678         break;
7679       case COP2:
7680         if(opcode2[i]<3)
7681           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7682         else if(opcode2[i]>3)
7683           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7684         else printf (" %x: %s\n",start+i*4,insn[i]);
7685         break;
7686       case C1LS:
7687         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7688         break;
7689       case C2LS:
7690         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7691         break;
7692       case INTCALL:
7693         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7694         break;
7695       default:
7696         //printf (" %s %8x\n",insn[i],source[i]);
7697         printf (" %x: %s\n",start+i*4,insn[i]);
7698     }
7699 }
7700
7701 void new_dynarec_init()
7702 {
7703   printf("Init new dynarec\n");
7704   out=(u_char *)BASE_ADDR;
7705   if (mmap (out, 1<<TARGET_SIZE_2,
7706             PROT_READ | PROT_WRITE | PROT_EXEC,
7707             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7708             -1, 0) <= 0) {printf("mmap() failed\n");}
7709 #ifdef MUPEN64
7710   rdword=&readmem_dword;
7711   fake_pc.f.r.rs=&readmem_dword;
7712   fake_pc.f.r.rt=&readmem_dword;
7713   fake_pc.f.r.rd=&readmem_dword;
7714 #endif
7715   int n;
7716   for(n=0x80000;n<0x80800;n++)
7717     invalid_code[n]=1;
7718   for(n=0;n<65536;n++)
7719     hash_table[n][0]=hash_table[n][2]=-1;
7720   memset(mini_ht,-1,sizeof(mini_ht));
7721   memset(restore_candidate,0,sizeof(restore_candidate));
7722   copy=shadow;
7723   expirep=16384; // Expiry pointer, +2 blocks
7724   pending_exception=0;
7725   literalcount=0;
7726 #ifdef HOST_IMM8
7727   // Copy this into local area so we don't have to put it in every literal pool
7728   invc_ptr=invalid_code;
7729 #endif
7730   stop_after_jal=0;
7731   // TLB
7732   using_tlb=0;
7733   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7734     memory_map[n]=-1;
7735   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7736     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7737   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7738     memory_map[n]=-1;
7739 #ifdef MUPEN64
7740   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7741     writemem[n] = write_nomem_new;
7742     writememb[n] = write_nomemb_new;
7743     writememh[n] = write_nomemh_new;
7744 #ifndef FORCE32
7745     writememd[n] = write_nomemd_new;
7746 #endif
7747     readmem[n] = read_nomem_new;
7748     readmemb[n] = read_nomemb_new;
7749     readmemh[n] = read_nomemh_new;
7750 #ifndef FORCE32
7751     readmemd[n] = read_nomemd_new;
7752 #endif
7753   }
7754   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7755     writemem[n] = write_rdram_new;
7756     writememb[n] = write_rdramb_new;
7757     writememh[n] = write_rdramh_new;
7758 #ifndef FORCE32
7759     writememd[n] = write_rdramd_new;
7760 #endif
7761   }
7762   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7763     writemem[n] = write_nomem_new;
7764     writememb[n] = write_nomemb_new;
7765     writememh[n] = write_nomemh_new;
7766 #ifndef FORCE32
7767     writememd[n] = write_nomemd_new;
7768 #endif
7769     readmem[n] = read_nomem_new;
7770     readmemb[n] = read_nomemb_new;
7771     readmemh[n] = read_nomemh_new;
7772 #ifndef FORCE32
7773     readmemd[n] = read_nomemd_new;
7774 #endif
7775   }
7776 #endif
7777   tlb_hacks();
7778   arch_init();
7779 }
7780
7781 void new_dynarec_cleanup()
7782 {
7783   int n;
7784   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7785   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7786   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7787   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7788   #ifdef ROM_COPY
7789   if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7790   #endif
7791 }
7792
7793 int new_recompile_block(int addr)
7794 {
7795 /*
7796   if(addr==0x800cd050) {
7797     int block;
7798     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7799     int n;
7800     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7801   }
7802 */
7803   //if(Count==365117028) tracedebug=1;
7804   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7805   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7806   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7807   //if(debug)
7808   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7809   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7810   /*if(Count>=312978186) {
7811     rlist();
7812   }*/
7813   //rlist();
7814   start = (u_int)addr&~3;
7815   //assert(((u_int)addr&1)==0);
7816 #ifdef PCSX
7817   if (Config.HLE && start == 0x80001000) // hlecall
7818   {
7819     // XXX: is this enough? Maybe check hleSoftCall?
7820     u_int beginning=(u_int)out;
7821     u_int page=get_page(start);
7822     invalid_code[start>>12]=0;
7823     emit_movimm(start,0);
7824     emit_writeword(0,(int)&pcaddr);
7825     emit_jmp((int)new_dyna_leave);
7826 #ifdef __arm__
7827     __clear_cache((void *)beginning,out);
7828 #endif
7829     ll_add(jump_in+page,start,(void *)beginning);
7830     return 0;
7831   }
7832   else if ((u_int)addr < 0x00200000 ||
7833     (0xa0000000 <= addr && addr < 0xa0200000)) {
7834     // used for BIOS calls mostly?
7835     source = (u_int *)((u_int)rdram+(start&0x1fffff));
7836     pagelimit = (addr&0xa0000000)|0x00200000;
7837   }
7838   else if (!Config.HLE && (
7839 /*    (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7840     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7841     // BIOS
7842     source = (u_int *)((u_int)psxR+(start&0x7ffff));
7843     pagelimit = (addr&0xfff00000)|0x80000;
7844   }
7845   else
7846 #endif
7847 #ifdef MUPEN64
7848   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7849     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7850     pagelimit = 0xa4001000;
7851   }
7852   else
7853 #endif
7854   if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
7855     source = (u_int *)((u_int)rdram+start-0x80000000);
7856     pagelimit = 0x80000000+RAM_SIZE;
7857   }
7858 #ifndef DISABLE_TLB
7859   else if ((signed int)addr >= (signed int)0xC0000000) {
7860     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7861     //if(tlb_LUT_r[start>>12])
7862       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7863     if((signed int)memory_map[start>>12]>=0) {
7864       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7865       pagelimit=(start+4096)&0xFFFFF000;
7866       int map=memory_map[start>>12];
7867       int i;
7868       for(i=0;i<5;i++) {
7869         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7870         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7871       }
7872       assem_debug("pagelimit=%x\n",pagelimit);
7873       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7874     }
7875     else {
7876       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7877       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7878       return -1; // Caller will invoke exception handler
7879     }
7880     //printf("source= %x\n",(int)source);
7881   }
7882 #endif
7883   else {
7884     printf("Compile at bogus memory address: %x \n", (int)addr);
7885     exit(1);
7886   }
7887
7888   /* Pass 1: disassemble */
7889   /* Pass 2: register dependencies, branch targets */
7890   /* Pass 3: register allocation */
7891   /* Pass 4: branch dependencies */
7892   /* Pass 5: pre-alloc */
7893   /* Pass 6: optimize clean/dirty state */
7894   /* Pass 7: flag 32-bit registers */
7895   /* Pass 8: assembly */
7896   /* Pass 9: linker */
7897   /* Pass 10: garbage collection / free memory */
7898
7899   int i,j;
7900   int done=0;
7901   unsigned int type,op,op2;
7902
7903   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7904
7905   /* Pass 1 disassembly */
7906
7907   for(i=0;!done;i++) {
7908     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7909     minimum_free_regs[i]=0;
7910     opcode[i]=op=source[i]>>26;
7911     switch(op)
7912     {
7913       case 0x00: strcpy(insn[i],"special"); type=NI;
7914         op2=source[i]&0x3f;
7915         switch(op2)
7916         {
7917           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7918           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7919           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7920           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7921           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7922           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7923           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7924           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7925           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7926           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7927           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7928           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7929           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7930           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7931           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7932           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7933           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7934           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7935           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7936           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7937           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7938           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7939           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7940           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7941           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7942           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7943           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7944           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7945           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7946           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7947           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7948           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7949           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7950           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7951           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7952           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7953           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7954           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7955           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7956           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7957           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7958           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7959           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7960           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7961           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7962           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7963           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7964           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7965           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7966           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7967           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7968           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7969         }
7970         break;
7971       case 0x01: strcpy(insn[i],"regimm"); type=NI;
7972         op2=(source[i]>>16)&0x1f;
7973         switch(op2)
7974         {
7975           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7976           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7977           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7978           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7979           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7980           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7981           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7982           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7983           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7984           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7985           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7986           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7987           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7988           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7989         }
7990         break;
7991       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7992       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7993       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7994       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7995       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7996       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7997       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7998       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7999       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8000       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8001       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8002       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8003       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8004       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8005       case 0x10: strcpy(insn[i],"cop0"); type=NI;
8006         op2=(source[i]>>21)&0x1f;
8007         switch(op2)
8008         {
8009           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8010           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8011           case 0x10: strcpy(insn[i],"tlb"); type=NI;
8012           switch(source[i]&0x3f)
8013           {
8014             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8015             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8016             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8017             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8018 #ifdef PCSX
8019             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8020 #else
8021             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8022 #endif
8023           }
8024         }
8025         break;
8026       case 0x11: strcpy(insn[i],"cop1"); type=NI;
8027         op2=(source[i]>>21)&0x1f;
8028         switch(op2)
8029         {
8030           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8031           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8032           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8033           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8034           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8035           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8036           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8037           switch((source[i]>>16)&0x3)
8038           {
8039             case 0x00: strcpy(insn[i],"BC1F"); break;
8040             case 0x01: strcpy(insn[i],"BC1T"); break;
8041             case 0x02: strcpy(insn[i],"BC1FL"); break;
8042             case 0x03: strcpy(insn[i],"BC1TL"); break;
8043           }
8044           break;
8045           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8046           switch(source[i]&0x3f)
8047           {
8048             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8049             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8050             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8051             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8052             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8053             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8054             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8055             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8056             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8057             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8058             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8059             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8060             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8061             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8062             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8063             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8064             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8065             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8066             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8067             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8068             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8069             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8070             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8071             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8072             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8073             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8074             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8075             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8076             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8077             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8078             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8079             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8080             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8081             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8082             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8083           }
8084           break;
8085           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8086           switch(source[i]&0x3f)
8087           {
8088             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8089             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8090             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8091             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8092             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8093             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8094             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8095             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8096             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8097             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8098             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8099             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8100             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8101             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8102             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8103             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8104             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8105             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8106             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8107             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8108             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8109             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8110             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8111             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8112             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8113             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8114             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8115             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8116             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8117             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8118             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8119             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8120             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8121             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8122             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8123           }
8124           break;
8125           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8126           switch(source[i]&0x3f)
8127           {
8128             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8129             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8130           }
8131           break;
8132           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8133           switch(source[i]&0x3f)
8134           {
8135             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8136             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8137           }
8138           break;
8139         }
8140         break;
8141 #ifndef FORCE32
8142       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8143       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8144       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8145       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8146       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8147       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8148       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8149       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8150 #endif
8151       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8152       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8153       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8154       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8155       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8156       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8157       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8158       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8159       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8160       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8161       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8162       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8163 #ifndef FORCE32
8164       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8165       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8166 #endif
8167       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8168       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8169       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8170       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8171 #ifndef FORCE32
8172       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8173       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8174       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8175 #endif
8176       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8177       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8178 #ifndef FORCE32
8179       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8180       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8181       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8182 #endif
8183 #ifdef PCSX
8184       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8185         // note: COP MIPS-1 encoding differs from MIPS32
8186         op2=(source[i]>>21)&0x1f;
8187         if (source[i]&0x3f) {
8188           if (gte_handlers[source[i]&0x3f]!=NULL) {
8189             snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8190             type=C2OP;
8191           }
8192         }
8193         else switch(op2)
8194         {
8195           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8196           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8197           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8198           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8199         }
8200         break;
8201       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8202       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8203       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8204 #endif
8205       default: strcpy(insn[i],"???"); type=NI;
8206         printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8207         break;
8208     }
8209 #ifdef PCSX
8210     /* detect branch in delay slot early */
8211     if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8212       opcode[i+1]=source[i+1]>>26;
8213       opcode2[i+1]=source[i+1]&0x3f;
8214       if((0<opcode[i+1]&&opcode[i+1]<8)||(opcode[i+1]==0&&(opcode2[i+1]==8||opcode2[i+1]==9))) {
8215         printf("branch in delay slot @%08x (%08x)\n", addr + i*4+4, addr);
8216         // don't handle first branch and call interpreter if it's hit
8217         type=INTCALL;
8218       }
8219     }
8220 #endif
8221     itype[i]=type;
8222     opcode2[i]=op2;
8223     /* Get registers/immediates */
8224     lt1[i]=0;
8225     us1[i]=0;
8226     us2[i]=0;
8227     dep1[i]=0;
8228     dep2[i]=0;
8229     switch(type) {
8230       case LOAD:
8231         rs1[i]=(source[i]>>21)&0x1f;
8232         rs2[i]=0;
8233         rt1[i]=(source[i]>>16)&0x1f;
8234         rt2[i]=0;
8235         imm[i]=(short)source[i];
8236         break;
8237       case STORE:
8238       case STORELR:
8239         rs1[i]=(source[i]>>21)&0x1f;
8240         rs2[i]=(source[i]>>16)&0x1f;
8241         rt1[i]=0;
8242         rt2[i]=0;
8243         imm[i]=(short)source[i];
8244         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8245         break;
8246       case LOADLR:
8247         // LWL/LWR only load part of the register,
8248         // therefore the target register must be treated as a source too
8249         rs1[i]=(source[i]>>21)&0x1f;
8250         rs2[i]=(source[i]>>16)&0x1f;
8251         rt1[i]=(source[i]>>16)&0x1f;
8252         rt2[i]=0;
8253         imm[i]=(short)source[i];
8254         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8255         if(op==0x26) dep1[i]=rt1[i]; // LWR
8256         break;
8257       case IMM16:
8258         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8259         else rs1[i]=(source[i]>>21)&0x1f;
8260         rs2[i]=0;
8261         rt1[i]=(source[i]>>16)&0x1f;
8262         rt2[i]=0;
8263         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8264           imm[i]=(unsigned short)source[i];
8265         }else{
8266           imm[i]=(short)source[i];
8267         }
8268         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8269         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8270         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8271         break;
8272       case UJUMP:
8273         rs1[i]=0;
8274         rs2[i]=0;
8275         rt1[i]=0;
8276         rt2[i]=0;
8277         // The JAL instruction writes to r31.
8278         if (op&1) {
8279           rt1[i]=31;
8280         }
8281         rs2[i]=CCREG;
8282         break;
8283       case RJUMP:
8284         rs1[i]=(source[i]>>21)&0x1f;
8285         rs2[i]=0;
8286         rt1[i]=0;
8287         rt2[i]=0;
8288         // The JALR instruction writes to rd.
8289         if (op2&1) {
8290           rt1[i]=(source[i]>>11)&0x1f;
8291         }
8292         rs2[i]=CCREG;
8293         break;
8294       case CJUMP:
8295         rs1[i]=(source[i]>>21)&0x1f;
8296         rs2[i]=(source[i]>>16)&0x1f;
8297         rt1[i]=0;
8298         rt2[i]=0;
8299         if(op&2) { // BGTZ/BLEZ
8300           rs2[i]=0;
8301         }
8302         us1[i]=rs1[i];
8303         us2[i]=rs2[i];
8304         likely[i]=op>>4;
8305         break;
8306       case SJUMP:
8307         rs1[i]=(source[i]>>21)&0x1f;
8308         rs2[i]=CCREG;
8309         rt1[i]=0;
8310         rt2[i]=0;
8311         us1[i]=rs1[i];
8312         if(op2&0x10) { // BxxAL
8313           rt1[i]=31;
8314           // NOTE: If the branch is not taken, r31 is still overwritten
8315         }
8316         likely[i]=(op2&2)>>1;
8317         break;
8318       case FJUMP:
8319         rs1[i]=FSREG;
8320         rs2[i]=CSREG;
8321         rt1[i]=0;
8322         rt2[i]=0;
8323         likely[i]=((source[i])>>17)&1;
8324         break;
8325       case ALU:
8326         rs1[i]=(source[i]>>21)&0x1f; // source
8327         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8328         rt1[i]=(source[i]>>11)&0x1f; // destination
8329         rt2[i]=0;
8330         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8331           us1[i]=rs1[i];us2[i]=rs2[i];
8332         }
8333         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8334           dep1[i]=rs1[i];dep2[i]=rs2[i];
8335         }
8336         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8337           dep1[i]=rs1[i];dep2[i]=rs2[i];
8338         }
8339         break;
8340       case MULTDIV:
8341         rs1[i]=(source[i]>>21)&0x1f; // source
8342         rs2[i]=(source[i]>>16)&0x1f; // divisor
8343         rt1[i]=HIREG;
8344         rt2[i]=LOREG;
8345         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8346           us1[i]=rs1[i];us2[i]=rs2[i];
8347         }
8348         break;
8349       case MOV:
8350         rs1[i]=0;
8351         rs2[i]=0;
8352         rt1[i]=0;
8353         rt2[i]=0;
8354         if(op2==0x10) rs1[i]=HIREG; // MFHI
8355         if(op2==0x11) rt1[i]=HIREG; // MTHI
8356         if(op2==0x12) rs1[i]=LOREG; // MFLO
8357         if(op2==0x13) rt1[i]=LOREG; // MTLO
8358         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8359         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8360         dep1[i]=rs1[i];
8361         break;
8362       case SHIFT:
8363         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8364         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8365         rt1[i]=(source[i]>>11)&0x1f; // destination
8366         rt2[i]=0;
8367         // DSLLV/DSRLV/DSRAV are 64-bit
8368         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8369         break;
8370       case SHIFTIMM:
8371         rs1[i]=(source[i]>>16)&0x1f;
8372         rs2[i]=0;
8373         rt1[i]=(source[i]>>11)&0x1f;
8374         rt2[i]=0;
8375         imm[i]=(source[i]>>6)&0x1f;
8376         // DSxx32 instructions
8377         if(op2>=0x3c) imm[i]|=0x20;
8378         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8379         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8380         break;
8381       case COP0:
8382         rs1[i]=0;
8383         rs2[i]=0;
8384         rt1[i]=0;
8385         rt2[i]=0;
8386         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8387         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8388         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8389         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8390         break;
8391       case COP1:
8392       case COP2:
8393         rs1[i]=0;
8394         rs2[i]=0;
8395         rt1[i]=0;
8396         rt2[i]=0;
8397         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8398         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8399         if(op2==5) us1[i]=rs1[i]; // DMTC1
8400         rs2[i]=CSREG;
8401         break;
8402       case C1LS:
8403         rs1[i]=(source[i]>>21)&0x1F;
8404         rs2[i]=CSREG;
8405         rt1[i]=0;
8406         rt2[i]=0;
8407         imm[i]=(short)source[i];
8408         break;
8409       case C2LS:
8410         rs1[i]=(source[i]>>21)&0x1F;
8411         rs2[i]=0;
8412         rt1[i]=0;
8413         rt2[i]=0;
8414         imm[i]=(short)source[i];
8415         break;
8416       case FLOAT:
8417       case FCONV:
8418         rs1[i]=0;
8419         rs2[i]=CSREG;
8420         rt1[i]=0;
8421         rt2[i]=0;
8422         break;
8423       case FCOMP:
8424         rs1[i]=FSREG;
8425         rs2[i]=CSREG;
8426         rt1[i]=FSREG;
8427         rt2[i]=0;
8428         break;
8429       case SYSCALL:
8430       case HLECALL:
8431       case INTCALL:
8432         rs1[i]=CCREG;
8433         rs2[i]=0;
8434         rt1[i]=0;
8435         rt2[i]=0;
8436         break;
8437       default:
8438         rs1[i]=0;
8439         rs2[i]=0;
8440         rt1[i]=0;
8441         rt2[i]=0;
8442     }
8443     /* Calculate branch target addresses */
8444     if(type==UJUMP)
8445       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8446     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8447       ba[i]=start+i*4+8; // Ignore never taken branch
8448     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8449       ba[i]=start+i*4+8; // Ignore never taken branch
8450     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8451       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8452     else ba[i]=-1;
8453     /* Is this the end of the block? */
8454     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8455 #ifdef PCSX
8456       // check for link register access in delay slot
8457       int rt1_=rt1[i-1];
8458       if(rt1_!=0&&(rs1[i]==rt1_||rs2[i]==rt1_||rt1[i]==rt1_||rt2[i]==rt1_)) {
8459         printf("link access in delay slot @%08x (%08x)\n", addr + i*4, addr);
8460         ba[i-1]=-1;
8461         itype[i-1]=INTCALL;
8462         done=2;
8463       }
8464       else
8465 #endif
8466       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8467         done=2;
8468       }
8469       else {
8470         if(stop_after_jal) done=1;
8471         // Stop on BREAK
8472         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8473       }
8474       // Don't recompile stuff that's already compiled
8475       if(check_addr(start+i*4+4)) done=1;
8476       // Don't get too close to the limit
8477       if(i>MAXBLOCK/2) done=1;
8478     }
8479     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8480     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8481     if(done==2) {
8482       // Does the block continue due to a branch?
8483       for(j=i-1;j>=0;j--)
8484       {
8485         if(ba[j]==start+i*4+4) done=j=0;
8486         if(ba[j]==start+i*4+8) done=j=0;
8487       }
8488     }
8489     //assert(i<MAXBLOCK-1);
8490     if(start+i*4==pagelimit-4) done=1;
8491     assert(start+i*4<pagelimit);
8492     if (i==MAXBLOCK-1) done=1;
8493     // Stop if we're compiling junk
8494     if(itype[i]==NI&&opcode[i]==0x11) {
8495       done=stop_after_jal=1;
8496       printf("Disabled speculative precompilation\n");
8497     }
8498   }
8499   slen=i;
8500   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8501     if(start+i*4==pagelimit) {
8502       itype[i-1]=SPAN;
8503     }
8504   }
8505   assert(slen>0);
8506
8507   /* Pass 2 - Register dependencies and branch targets */
8508
8509   unneeded_registers(0,slen-1,0);
8510
8511   /* Pass 3 - Register allocation */
8512
8513   struct regstat current; // Current register allocations/status
8514   current.is32=1;
8515   current.dirty=0;
8516   current.u=unneeded_reg[0];
8517   current.uu=unneeded_reg_upper[0];
8518   clear_all_regs(current.regmap);
8519   alloc_reg(&current,0,CCREG);
8520   dirty_reg(&current,CCREG);
8521   current.isconst=0;
8522   current.wasconst=0;
8523   int ds=0;
8524   int cc=0;
8525   int hr;
8526
8527 #ifndef FORCE32
8528   provisional_32bit();
8529 #endif
8530   if((u_int)addr&1) {
8531     // First instruction is delay slot
8532     cc=-1;
8533     bt[1]=1;
8534     ds=1;
8535     unneeded_reg[0]=1;
8536     unneeded_reg_upper[0]=1;
8537     current.regmap[HOST_BTREG]=BTREG;
8538   }
8539
8540   for(i=0;i<slen;i++)
8541   {
8542     if(bt[i])
8543     {
8544       int hr;
8545       for(hr=0;hr<HOST_REGS;hr++)
8546       {
8547         // Is this really necessary?
8548         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8549       }
8550       current.isconst=0;
8551     }
8552     if(i>1)
8553     {
8554       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8555       {
8556         if(rs1[i-2]==0||rs2[i-2]==0)
8557         {
8558           if(rs1[i-2]) {
8559             current.is32|=1LL<<rs1[i-2];
8560             int hr=get_reg(current.regmap,rs1[i-2]|64);
8561             if(hr>=0) current.regmap[hr]=-1;
8562           }
8563           if(rs2[i-2]) {
8564             current.is32|=1LL<<rs2[i-2];
8565             int hr=get_reg(current.regmap,rs2[i-2]|64);
8566             if(hr>=0) current.regmap[hr]=-1;
8567           }
8568         }
8569       }
8570     }
8571 #ifndef FORCE32
8572     // If something jumps here with 64-bit values
8573     // then promote those registers to 64 bits
8574     if(bt[i])
8575     {
8576       uint64_t temp_is32=current.is32;
8577       for(j=i-1;j>=0;j--)
8578       {
8579         if(ba[j]==start+i*4)
8580           temp_is32&=branch_regs[j].is32;
8581       }
8582       for(j=i;j<slen;j++)
8583       {
8584         if(ba[j]==start+i*4)
8585           //temp_is32=1;
8586           temp_is32&=p32[j];
8587       }
8588       if(temp_is32!=current.is32) {
8589         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8590         #ifdef DESTRUCTIVE_WRITEBACK
8591         for(hr=0;hr<HOST_REGS;hr++)
8592         {
8593           int r=current.regmap[hr];
8594           if(r>0&&r<64)
8595           {
8596             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8597               temp_is32|=1LL<<r;
8598               //printf("restore %d\n",r);
8599             }
8600           }
8601         }
8602         #endif
8603         current.is32=temp_is32;
8604       }
8605     }
8606 #else
8607     current.is32=-1LL;
8608 #endif
8609
8610     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8611     regs[i].wasconst=current.isconst;
8612     regs[i].was32=current.is32;
8613     regs[i].wasdirty=current.dirty;
8614     #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8615     // To change a dirty register from 32 to 64 bits, we must write
8616     // it out during the previous cycle (for branches, 2 cycles)
8617     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8618     {
8619       uint64_t temp_is32=current.is32;
8620       for(j=i-1;j>=0;j--)
8621       {
8622         if(ba[j]==start+i*4+4)
8623           temp_is32&=branch_regs[j].is32;
8624       }
8625       for(j=i;j<slen;j++)
8626       {
8627         if(ba[j]==start+i*4+4)
8628           //temp_is32=1;
8629           temp_is32&=p32[j];
8630       }
8631       if(temp_is32!=current.is32) {
8632         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8633         for(hr=0;hr<HOST_REGS;hr++)
8634         {
8635           int r=current.regmap[hr];
8636           if(r>0)
8637           {
8638             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8639               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8640               {
8641                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8642                 {
8643                   //printf("dump %d/r%d\n",hr,r);
8644                   current.regmap[hr]=-1;
8645                   if(get_reg(current.regmap,r|64)>=0)
8646                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8647                 }
8648               }
8649             }
8650           }
8651         }
8652       }
8653     }
8654     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8655     {
8656       uint64_t temp_is32=current.is32;
8657       for(j=i-1;j>=0;j--)
8658       {
8659         if(ba[j]==start+i*4+8)
8660           temp_is32&=branch_regs[j].is32;
8661       }
8662       for(j=i;j<slen;j++)
8663       {
8664         if(ba[j]==start+i*4+8)
8665           //temp_is32=1;
8666           temp_is32&=p32[j];
8667       }
8668       if(temp_is32!=current.is32) {
8669         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8670         for(hr=0;hr<HOST_REGS;hr++)
8671         {
8672           int r=current.regmap[hr];
8673           if(r>0)
8674           {
8675             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8676               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8677               {
8678                 //printf("dump %d/r%d\n",hr,r);
8679                 current.regmap[hr]=-1;
8680                 if(get_reg(current.regmap,r|64)>=0)
8681                   current.regmap[get_reg(current.regmap,r|64)]=-1;
8682               }
8683             }
8684           }
8685         }
8686       }
8687     }
8688     #endif
8689     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8690       if(i+1<slen) {
8691         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8692         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8693         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8694         current.u|=1;
8695         current.uu|=1;
8696       } else {
8697         current.u=1;
8698         current.uu=1;
8699       }
8700     } else {
8701       if(i+1<slen) {
8702         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8703         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8704         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8705         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8706         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8707         current.u|=1;
8708         current.uu|=1;
8709       } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8710     }
8711     is_ds[i]=ds;
8712     if(ds) {
8713       ds=0; // Skip delay slot, already allocated as part of branch
8714       // ...but we need to alloc it in case something jumps here
8715       if(i+1<slen) {
8716         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8717         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8718       }else{
8719         current.u=branch_unneeded_reg[i-1];
8720         current.uu=branch_unneeded_reg_upper[i-1];
8721       }
8722       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8723       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8724       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8725       current.u|=1;
8726       current.uu|=1;
8727       struct regstat temp;
8728       memcpy(&temp,&current,sizeof(current));
8729       temp.wasdirty=temp.dirty;
8730       temp.was32=temp.is32;
8731       // TODO: Take into account unconditional branches, as below
8732       delayslot_alloc(&temp,i);
8733       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8734       regs[i].wasdirty=temp.wasdirty;
8735       regs[i].was32=temp.was32;
8736       regs[i].dirty=temp.dirty;
8737       regs[i].is32=temp.is32;
8738       regs[i].isconst=0;
8739       regs[i].wasconst=0;
8740       current.isconst=0;
8741       // Create entry (branch target) regmap
8742       for(hr=0;hr<HOST_REGS;hr++)
8743       {
8744         int r=temp.regmap[hr];
8745         if(r>=0) {
8746           if(r!=regmap_pre[i][hr]) {
8747             regs[i].regmap_entry[hr]=-1;
8748           }
8749           else
8750           {
8751             if(r<64){
8752               if((current.u>>r)&1) {
8753                 regs[i].regmap_entry[hr]=-1;
8754                 regs[i].regmap[hr]=-1;
8755                 //Don't clear regs in the delay slot as the branch might need them
8756                 //current.regmap[hr]=-1;
8757               }else
8758                 regs[i].regmap_entry[hr]=r;
8759             }
8760             else {
8761               if((current.uu>>(r&63))&1) {
8762                 regs[i].regmap_entry[hr]=-1;
8763                 regs[i].regmap[hr]=-1;
8764                 //Don't clear regs in the delay slot as the branch might need them
8765                 //current.regmap[hr]=-1;
8766               }else
8767                 regs[i].regmap_entry[hr]=r;
8768             }
8769           }
8770         } else {
8771           // First instruction expects CCREG to be allocated
8772           if(i==0&&hr==HOST_CCREG)
8773             regs[i].regmap_entry[hr]=CCREG;
8774           else
8775             regs[i].regmap_entry[hr]=-1;
8776         }
8777       }
8778     }
8779     else { // Not delay slot
8780       switch(itype[i]) {
8781         case UJUMP:
8782           //current.isconst=0; // DEBUG
8783           //current.wasconst=0; // DEBUG
8784           //regs[i].wasconst=0; // DEBUG
8785           clear_const(&current,rt1[i]);
8786           alloc_cc(&current,i);
8787           dirty_reg(&current,CCREG);
8788           if (rt1[i]==31) {
8789             alloc_reg(&current,i,31);
8790             dirty_reg(&current,31);
8791             assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8792             assert(rt1[i+1]!=rt1[i]);
8793             #ifdef REG_PREFETCH
8794             alloc_reg(&current,i,PTEMP);
8795             #endif
8796             //current.is32|=1LL<<rt1[i];
8797           }
8798           ooo[i]=1;
8799           delayslot_alloc(&current,i+1);
8800           //current.isconst=0; // DEBUG
8801           ds=1;
8802           //printf("i=%d, isconst=%x\n",i,current.isconst);
8803           break;
8804         case RJUMP:
8805           //current.isconst=0;
8806           //current.wasconst=0;
8807           //regs[i].wasconst=0;
8808           clear_const(&current,rs1[i]);
8809           clear_const(&current,rt1[i]);
8810           alloc_cc(&current,i);
8811           dirty_reg(&current,CCREG);
8812           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8813             alloc_reg(&current,i,rs1[i]);
8814             if (rt1[i]!=0) {
8815               alloc_reg(&current,i,rt1[i]);
8816               dirty_reg(&current,rt1[i]);
8817               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
8818               assert(rt1[i+1]!=rt1[i]);
8819               #ifdef REG_PREFETCH
8820               alloc_reg(&current,i,PTEMP);
8821               #endif
8822             }
8823             #ifdef USE_MINI_HT
8824             if(rs1[i]==31) { // JALR
8825               alloc_reg(&current,i,RHASH);
8826               #ifndef HOST_IMM_ADDR32
8827               alloc_reg(&current,i,RHTBL);
8828               #endif
8829             }
8830             #endif
8831             delayslot_alloc(&current,i+1);
8832           } else {
8833             // The delay slot overwrites our source register,
8834             // allocate a temporary register to hold the old value.
8835             current.isconst=0;
8836             current.wasconst=0;
8837             regs[i].wasconst=0;
8838             delayslot_alloc(&current,i+1);
8839             current.isconst=0;
8840             alloc_reg(&current,i,RTEMP);
8841           }
8842           //current.isconst=0; // DEBUG
8843           ooo[i]=1;
8844           ds=1;
8845           break;
8846         case CJUMP:
8847           //current.isconst=0;
8848           //current.wasconst=0;
8849           //regs[i].wasconst=0;
8850           clear_const(&current,rs1[i]);
8851           clear_const(&current,rs2[i]);
8852           if((opcode[i]&0x3E)==4) // BEQ/BNE
8853           {
8854             alloc_cc(&current,i);
8855             dirty_reg(&current,CCREG);
8856             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8857             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8858             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8859             {
8860               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8861               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8862             }
8863             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8864                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8865               // The delay slot overwrites one of our conditions.
8866               // Allocate the branch condition registers instead.
8867               current.isconst=0;
8868               current.wasconst=0;
8869               regs[i].wasconst=0;
8870               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8871               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8872               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8873               {
8874                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8875                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8876               }
8877             }
8878             else
8879             {
8880               ooo[i]=1;
8881               delayslot_alloc(&current,i+1);
8882             }
8883           }
8884           else
8885           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8886           {
8887             alloc_cc(&current,i);
8888             dirty_reg(&current,CCREG);
8889             alloc_reg(&current,i,rs1[i]);
8890             if(!(current.is32>>rs1[i]&1))
8891             {
8892               alloc_reg64(&current,i,rs1[i]);
8893             }
8894             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8895               // The delay slot overwrites one of our conditions.
8896               // Allocate the branch condition registers instead.
8897               current.isconst=0;
8898               current.wasconst=0;
8899               regs[i].wasconst=0;
8900               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8901               if(!((current.is32>>rs1[i])&1))
8902               {
8903                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8904               }
8905             }
8906             else
8907             {
8908               ooo[i]=1;
8909               delayslot_alloc(&current,i+1);
8910             }
8911           }
8912           else
8913           // Don't alloc the delay slot yet because we might not execute it
8914           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8915           {
8916             current.isconst=0;
8917             current.wasconst=0;
8918             regs[i].wasconst=0;
8919             alloc_cc(&current,i);
8920             dirty_reg(&current,CCREG);
8921             alloc_reg(&current,i,rs1[i]);
8922             alloc_reg(&current,i,rs2[i]);
8923             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8924             {
8925               alloc_reg64(&current,i,rs1[i]);
8926               alloc_reg64(&current,i,rs2[i]);
8927             }
8928           }
8929           else
8930           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8931           {
8932             current.isconst=0;
8933             current.wasconst=0;
8934             regs[i].wasconst=0;
8935             alloc_cc(&current,i);
8936             dirty_reg(&current,CCREG);
8937             alloc_reg(&current,i,rs1[i]);
8938             if(!(current.is32>>rs1[i]&1))
8939             {
8940               alloc_reg64(&current,i,rs1[i]);
8941             }
8942           }
8943           ds=1;
8944           //current.isconst=0;
8945           break;
8946         case SJUMP:
8947           //current.isconst=0;
8948           //current.wasconst=0;
8949           //regs[i].wasconst=0;
8950           clear_const(&current,rs1[i]);
8951           clear_const(&current,rt1[i]);
8952           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8953           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8954           {
8955             alloc_cc(&current,i);
8956             dirty_reg(&current,CCREG);
8957             alloc_reg(&current,i,rs1[i]);
8958             if(!(current.is32>>rs1[i]&1))
8959             {
8960               alloc_reg64(&current,i,rs1[i]);
8961             }
8962             if (rt1[i]==31) { // BLTZAL/BGEZAL
8963               alloc_reg(&current,i,31);
8964               dirty_reg(&current,31);
8965               //#ifdef REG_PREFETCH
8966               //alloc_reg(&current,i,PTEMP);
8967               //#endif
8968               //current.is32|=1LL<<rt1[i];
8969             }
8970             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
8971                ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
8972               // Allocate the branch condition registers instead.
8973               current.isconst=0;
8974               current.wasconst=0;
8975               regs[i].wasconst=0;
8976               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8977               if(!((current.is32>>rs1[i])&1))
8978               {
8979                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8980               }
8981             }
8982             else
8983             {
8984               ooo[i]=1;
8985               delayslot_alloc(&current,i+1);
8986             }
8987           }
8988           else
8989           // Don't alloc the delay slot yet because we might not execute it
8990           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8991           {
8992             current.isconst=0;
8993             current.wasconst=0;
8994             regs[i].wasconst=0;
8995             alloc_cc(&current,i);
8996             dirty_reg(&current,CCREG);
8997             alloc_reg(&current,i,rs1[i]);
8998             if(!(current.is32>>rs1[i]&1))
8999             {
9000               alloc_reg64(&current,i,rs1[i]);
9001             }
9002           }
9003           ds=1;
9004           //current.isconst=0;
9005           break;
9006         case FJUMP:
9007           current.isconst=0;
9008           current.wasconst=0;
9009           regs[i].wasconst=0;
9010           if(likely[i]==0) // BC1F/BC1T
9011           {
9012             // TODO: Theoretically we can run out of registers here on x86.
9013             // The delay slot can allocate up to six, and we need to check
9014             // CSREG before executing the delay slot.  Possibly we can drop
9015             // the cycle count and then reload it after checking that the
9016             // FPU is in a usable state, or don't do out-of-order execution.
9017             alloc_cc(&current,i);
9018             dirty_reg(&current,CCREG);
9019             alloc_reg(&current,i,FSREG);
9020             alloc_reg(&current,i,CSREG);
9021             if(itype[i+1]==FCOMP) {
9022               // The delay slot overwrites the branch condition.
9023               // Allocate the branch condition registers instead.
9024               alloc_cc(&current,i);
9025               dirty_reg(&current,CCREG);
9026               alloc_reg(&current,i,CSREG);
9027               alloc_reg(&current,i,FSREG);
9028             }
9029             else {
9030               ooo[i]=1;
9031               delayslot_alloc(&current,i+1);
9032               alloc_reg(&current,i+1,CSREG);
9033             }
9034           }
9035           else
9036           // Don't alloc the delay slot yet because we might not execute it
9037           if(likely[i]) // BC1FL/BC1TL
9038           {
9039             alloc_cc(&current,i);
9040             dirty_reg(&current,CCREG);
9041             alloc_reg(&current,i,CSREG);
9042             alloc_reg(&current,i,FSREG);
9043           }
9044           ds=1;
9045           current.isconst=0;
9046           break;
9047         case IMM16:
9048           imm16_alloc(&current,i);
9049           break;
9050         case LOAD:
9051         case LOADLR:
9052           load_alloc(&current,i);
9053           break;
9054         case STORE:
9055         case STORELR:
9056           store_alloc(&current,i);
9057           break;
9058         case ALU:
9059           alu_alloc(&current,i);
9060           break;
9061         case SHIFT:
9062           shift_alloc(&current,i);
9063           break;
9064         case MULTDIV:
9065           multdiv_alloc(&current,i);
9066           break;
9067         case SHIFTIMM:
9068           shiftimm_alloc(&current,i);
9069           break;
9070         case MOV:
9071           mov_alloc(&current,i);
9072           break;
9073         case COP0:
9074           cop0_alloc(&current,i);
9075           break;
9076         case COP1:
9077         case COP2:
9078           cop1_alloc(&current,i);
9079           break;
9080         case C1LS:
9081           c1ls_alloc(&current,i);
9082           break;
9083         case C2LS:
9084           c2ls_alloc(&current,i);
9085           break;
9086         case C2OP:
9087           c2op_alloc(&current,i);
9088           break;
9089         case FCONV:
9090           fconv_alloc(&current,i);
9091           break;
9092         case FLOAT:
9093           float_alloc(&current,i);
9094           break;
9095         case FCOMP:
9096           fcomp_alloc(&current,i);
9097           break;
9098         case SYSCALL:
9099         case HLECALL:
9100         case INTCALL:
9101           syscall_alloc(&current,i);
9102           break;
9103         case SPAN:
9104           pagespan_alloc(&current,i);
9105           break;
9106       }
9107
9108       // Drop the upper half of registers that have become 32-bit
9109       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9110       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9111         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9112         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9113         current.uu|=1;
9114       } else {
9115         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9116         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9117         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9118         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9119         current.uu|=1;
9120       }
9121
9122       // Create entry (branch target) regmap
9123       for(hr=0;hr<HOST_REGS;hr++)
9124       {
9125         int r,or,er;
9126         r=current.regmap[hr];
9127         if(r>=0) {
9128           if(r!=regmap_pre[i][hr]) {
9129             // TODO: delay slot (?)
9130             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9131             if(or<0||(r&63)>=TEMPREG){
9132               regs[i].regmap_entry[hr]=-1;
9133             }
9134             else
9135             {
9136               // Just move it to a different register
9137               regs[i].regmap_entry[hr]=r;
9138               // If it was dirty before, it's still dirty
9139               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9140             }
9141           }
9142           else
9143           {
9144             // Unneeded
9145             if(r==0){
9146               regs[i].regmap_entry[hr]=0;
9147             }
9148             else
9149             if(r<64){
9150               if((current.u>>r)&1) {
9151                 regs[i].regmap_entry[hr]=-1;
9152                 //regs[i].regmap[hr]=-1;
9153                 current.regmap[hr]=-1;
9154               }else
9155                 regs[i].regmap_entry[hr]=r;
9156             }
9157             else {
9158               if((current.uu>>(r&63))&1) {
9159                 regs[i].regmap_entry[hr]=-1;
9160                 //regs[i].regmap[hr]=-1;
9161                 current.regmap[hr]=-1;
9162               }else
9163                 regs[i].regmap_entry[hr]=r;
9164             }
9165           }
9166         } else {
9167           // Branches expect CCREG to be allocated at the target
9168           if(regmap_pre[i][hr]==CCREG)
9169             regs[i].regmap_entry[hr]=CCREG;
9170           else
9171             regs[i].regmap_entry[hr]=-1;
9172         }
9173       }
9174       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9175     }
9176     /* Branch post-alloc */
9177     if(i>0)
9178     {
9179       current.was32=current.is32;
9180       current.wasdirty=current.dirty;
9181       switch(itype[i-1]) {
9182         case UJUMP:
9183           memcpy(&branch_regs[i-1],&current,sizeof(current));
9184           branch_regs[i-1].isconst=0;
9185           branch_regs[i-1].wasconst=0;
9186           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9187           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9188           alloc_cc(&branch_regs[i-1],i-1);
9189           dirty_reg(&branch_regs[i-1],CCREG);
9190           if(rt1[i-1]==31) { // JAL
9191             alloc_reg(&branch_regs[i-1],i-1,31);
9192             dirty_reg(&branch_regs[i-1],31);
9193             branch_regs[i-1].is32|=1LL<<31;
9194           }
9195           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9196           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9197           break;
9198         case RJUMP:
9199           memcpy(&branch_regs[i-1],&current,sizeof(current));
9200           branch_regs[i-1].isconst=0;
9201           branch_regs[i-1].wasconst=0;
9202           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9203           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9204           alloc_cc(&branch_regs[i-1],i-1);
9205           dirty_reg(&branch_regs[i-1],CCREG);
9206           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9207           if(rt1[i-1]!=0) { // JALR
9208             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9209             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9210             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9211           }
9212           #ifdef USE_MINI_HT
9213           if(rs1[i-1]==31) { // JALR
9214             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9215             #ifndef HOST_IMM_ADDR32
9216             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9217             #endif
9218           }
9219           #endif
9220           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9221           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9222           break;
9223         case CJUMP:
9224           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9225           {
9226             alloc_cc(&current,i-1);
9227             dirty_reg(&current,CCREG);
9228             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9229                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9230               // The delay slot overwrote one of our conditions
9231               // Delay slot goes after the test (in order)
9232               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9233               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9234               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9235               current.u|=1;
9236               current.uu|=1;
9237               delayslot_alloc(&current,i);
9238               current.isconst=0;
9239             }
9240             else
9241             {
9242               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9243               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9244               // Alloc the branch condition registers
9245               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9246               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9247               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9248               {
9249                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9250                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9251               }
9252             }
9253             memcpy(&branch_regs[i-1],&current,sizeof(current));
9254             branch_regs[i-1].isconst=0;
9255             branch_regs[i-1].wasconst=0;
9256             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9257             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9258           }
9259           else
9260           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9261           {
9262             alloc_cc(&current,i-1);
9263             dirty_reg(&current,CCREG);
9264             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9265               // The delay slot overwrote the branch condition
9266               // Delay slot goes after the test (in order)
9267               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9268               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9269               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9270               current.u|=1;
9271               current.uu|=1;
9272               delayslot_alloc(&current,i);
9273               current.isconst=0;
9274             }
9275             else
9276             {
9277               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9278               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9279               // Alloc the branch condition register
9280               alloc_reg(&current,i-1,rs1[i-1]);
9281               if(!(current.is32>>rs1[i-1]&1))
9282               {
9283                 alloc_reg64(&current,i-1,rs1[i-1]);
9284               }
9285             }
9286             memcpy(&branch_regs[i-1],&current,sizeof(current));
9287             branch_regs[i-1].isconst=0;
9288             branch_regs[i-1].wasconst=0;
9289             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9290             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9291           }
9292           else
9293           // Alloc the delay slot in case the branch is taken
9294           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9295           {
9296             memcpy(&branch_regs[i-1],&current,sizeof(current));
9297             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9298             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9299             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9300             alloc_cc(&branch_regs[i-1],i);
9301             dirty_reg(&branch_regs[i-1],CCREG);
9302             delayslot_alloc(&branch_regs[i-1],i);
9303             branch_regs[i-1].isconst=0;
9304             alloc_reg(&current,i,CCREG); // Not taken path
9305             dirty_reg(&current,CCREG);
9306             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9307           }
9308           else
9309           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9310           {
9311             memcpy(&branch_regs[i-1],&current,sizeof(current));
9312             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9313             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9314             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9315             alloc_cc(&branch_regs[i-1],i);
9316             dirty_reg(&branch_regs[i-1],CCREG);
9317             delayslot_alloc(&branch_regs[i-1],i);
9318             branch_regs[i-1].isconst=0;
9319             alloc_reg(&current,i,CCREG); // Not taken path
9320             dirty_reg(&current,CCREG);
9321             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9322           }
9323           break;
9324         case SJUMP:
9325           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9326           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9327           {
9328             alloc_cc(&current,i-1);
9329             dirty_reg(&current,CCREG);
9330             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9331               // The delay slot overwrote the branch condition
9332               // Delay slot goes after the test (in order)
9333               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9334               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9335               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9336               current.u|=1;
9337               current.uu|=1;
9338               delayslot_alloc(&current,i);
9339               current.isconst=0;
9340             }
9341             else
9342             {
9343               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9344               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9345               // Alloc the branch condition register
9346               alloc_reg(&current,i-1,rs1[i-1]);
9347               if(!(current.is32>>rs1[i-1]&1))
9348               {
9349                 alloc_reg64(&current,i-1,rs1[i-1]);
9350               }
9351             }
9352             memcpy(&branch_regs[i-1],&current,sizeof(current));
9353             branch_regs[i-1].isconst=0;
9354             branch_regs[i-1].wasconst=0;
9355             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9356             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9357           }
9358           else
9359           // Alloc the delay slot in case the branch is taken
9360           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9361           {
9362             memcpy(&branch_regs[i-1],&current,sizeof(current));
9363             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9364             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9365             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9366             alloc_cc(&branch_regs[i-1],i);
9367             dirty_reg(&branch_regs[i-1],CCREG);
9368             delayslot_alloc(&branch_regs[i-1],i);
9369             branch_regs[i-1].isconst=0;
9370             alloc_reg(&current,i,CCREG); // Not taken path
9371             dirty_reg(&current,CCREG);
9372             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9373           }
9374           // FIXME: BLTZAL/BGEZAL
9375           if(opcode2[i-1]&0x10) { // BxxZAL
9376             alloc_reg(&branch_regs[i-1],i-1,31);
9377             dirty_reg(&branch_regs[i-1],31);
9378             branch_regs[i-1].is32|=1LL<<31;
9379           }
9380           break;
9381         case FJUMP:
9382           if(likely[i-1]==0) // BC1F/BC1T
9383           {
9384             alloc_cc(&current,i-1);
9385             dirty_reg(&current,CCREG);
9386             if(itype[i]==FCOMP) {
9387               // The delay slot overwrote the branch condition
9388               // Delay slot goes after the test (in order)
9389               delayslot_alloc(&current,i);
9390               current.isconst=0;
9391             }
9392             else
9393             {
9394               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9395               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9396               // Alloc the branch condition register
9397               alloc_reg(&current,i-1,FSREG);
9398             }
9399             memcpy(&branch_regs[i-1],&current,sizeof(current));
9400             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9401           }
9402           else // BC1FL/BC1TL
9403           {
9404             // Alloc the delay slot in case the branch is taken
9405             memcpy(&branch_regs[i-1],&current,sizeof(current));
9406             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9407             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9408             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9409             alloc_cc(&branch_regs[i-1],i);
9410             dirty_reg(&branch_regs[i-1],CCREG);
9411             delayslot_alloc(&branch_regs[i-1],i);
9412             branch_regs[i-1].isconst=0;
9413             alloc_reg(&current,i,CCREG); // Not taken path
9414             dirty_reg(&current,CCREG);
9415             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9416           }
9417           break;
9418       }
9419
9420       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9421       {
9422         if(rt1[i-1]==31) // JAL/JALR
9423         {
9424           // Subroutine call will return here, don't alloc any registers
9425           current.is32=1;
9426           current.dirty=0;
9427           clear_all_regs(current.regmap);
9428           alloc_reg(&current,i,CCREG);
9429           dirty_reg(&current,CCREG);
9430         }
9431         else if(i+1<slen)
9432         {
9433           // Internal branch will jump here, match registers to caller
9434           current.is32=0x3FFFFFFFFLL;
9435           current.dirty=0;
9436           clear_all_regs(current.regmap);
9437           alloc_reg(&current,i,CCREG);
9438           dirty_reg(&current,CCREG);
9439           for(j=i-1;j>=0;j--)
9440           {
9441             if(ba[j]==start+i*4+4) {
9442               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9443               current.is32=branch_regs[j].is32;
9444               current.dirty=branch_regs[j].dirty;
9445               break;
9446             }
9447           }
9448           while(j>=0) {
9449             if(ba[j]==start+i*4+4) {
9450               for(hr=0;hr<HOST_REGS;hr++) {
9451                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9452                   current.regmap[hr]=-1;
9453                 }
9454                 current.is32&=branch_regs[j].is32;
9455                 current.dirty&=branch_regs[j].dirty;
9456               }
9457             }
9458             j--;
9459           }
9460         }
9461       }
9462     }
9463
9464     // Count cycles in between branches
9465     ccadj[i]=cc;
9466     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9467     {
9468       cc=0;
9469     }
9470     else
9471     {
9472       cc++;
9473     }
9474
9475     flush_dirty_uppers(&current);
9476     if(!is_ds[i]) {
9477       regs[i].is32=current.is32;
9478       regs[i].dirty=current.dirty;
9479       regs[i].isconst=current.isconst;
9480       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9481     }
9482     for(hr=0;hr<HOST_REGS;hr++) {
9483       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9484         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9485           regs[i].wasconst&=~(1<<hr);
9486         }
9487       }
9488     }
9489     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9490   }
9491
9492   /* Pass 4 - Cull unused host registers */
9493
9494   uint64_t nr=0;
9495
9496   for (i=slen-1;i>=0;i--)
9497   {
9498     int hr;
9499     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9500     {
9501       if(ba[i]<start || ba[i]>=(start+slen*4))
9502       {
9503         // Branch out of this block, don't need anything
9504         nr=0;
9505       }
9506       else
9507       {
9508         // Internal branch
9509         // Need whatever matches the target
9510         nr=0;
9511         int t=(ba[i]-start)>>2;
9512         for(hr=0;hr<HOST_REGS;hr++)
9513         {
9514           if(regs[i].regmap_entry[hr]>=0) {
9515             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9516           }
9517         }
9518       }
9519       // Conditional branch may need registers for following instructions
9520       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9521       {
9522         if(i<slen-2) {
9523           nr|=needed_reg[i+2];
9524           for(hr=0;hr<HOST_REGS;hr++)
9525           {
9526             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9527             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9528           }
9529         }
9530       }
9531       // Don't need stuff which is overwritten
9532       if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9533       if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9534       // Merge in delay slot
9535       for(hr=0;hr<HOST_REGS;hr++)
9536       {
9537         if(!likely[i]) {
9538           // These are overwritten unless the branch is "likely"
9539           // and the delay slot is nullified if not taken
9540           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9541           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9542         }
9543         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9544         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9545         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9546         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9547         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9548         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9549         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9550         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9551         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9552           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9553           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9554         }
9555         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9556           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9557           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9558         }
9559         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9560           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9561           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9562         }
9563       }
9564     }
9565     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9566     {
9567       // SYSCALL instruction (software interrupt)
9568       nr=0;
9569     }
9570     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9571     {
9572       // ERET instruction (return from interrupt)
9573       nr=0;
9574     }
9575     else // Non-branch
9576     {
9577       if(i<slen-1) {
9578         for(hr=0;hr<HOST_REGS;hr++) {
9579           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9580           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9581           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9582           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9583         }
9584       }
9585     }
9586     for(hr=0;hr<HOST_REGS;hr++)
9587     {
9588       // Overwritten registers are not needed
9589       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9590       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9591       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9592       // Source registers are needed
9593       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9594       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9595       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9596       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9597       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9598       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9599       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9600       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9601       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9602         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9603         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9604       }
9605       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9606         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9607         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9608       }
9609       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9610         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9611         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9612       }
9613       // Don't store a register immediately after writing it,
9614       // may prevent dual-issue.
9615       // But do so if this is a branch target, otherwise we
9616       // might have to load the register before the branch.
9617       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9618         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9619            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9620           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9621           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9622         }
9623         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9624            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9625           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9626           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9627         }
9628       }
9629     }
9630     // Cycle count is needed at branches.  Assume it is needed at the target too.
9631     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9632       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9633       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9634     }
9635     // Save it
9636     needed_reg[i]=nr;
9637
9638     // Deallocate unneeded registers
9639     for(hr=0;hr<HOST_REGS;hr++)
9640     {
9641       if(!((nr>>hr)&1)) {
9642         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9643         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9644            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9645            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9646         {
9647           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9648           {
9649             if(likely[i]) {
9650               regs[i].regmap[hr]=-1;
9651               regs[i].isconst&=~(1<<hr);
9652               if(i<slen-2) regmap_pre[i+2][hr]=-1;
9653             }
9654           }
9655         }
9656         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9657         {
9658           int d1=0,d2=0,map=0,temp=0;
9659           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9660           {
9661             d1=dep1[i+1];
9662             d2=dep2[i+1];
9663           }
9664           if(using_tlb) {
9665             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9666                itype[i+1]==STORE || itype[i+1]==STORELR ||
9667                itype[i+1]==C1LS || itype[i+1]==C2LS)
9668             map=TLREG;
9669           } else
9670           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9671              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9672             map=INVCP;
9673           }
9674           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9675              itype[i+1]==C1LS || itype[i+1]==C2LS)
9676             temp=FTEMP;
9677           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9678              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9679              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9680              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9681              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9682              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9683              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9684              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9685              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9686              regs[i].regmap[hr]!=map )
9687           {
9688             regs[i].regmap[hr]=-1;
9689             regs[i].isconst&=~(1<<hr);
9690             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9691                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9692                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9693                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9694                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9695                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9696                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9697                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9698                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9699                branch_regs[i].regmap[hr]!=map)
9700             {
9701               branch_regs[i].regmap[hr]=-1;
9702               branch_regs[i].regmap_entry[hr]=-1;
9703               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9704               {
9705                 if(!likely[i]&&i<slen-2) {
9706                   regmap_pre[i+2][hr]=-1;
9707                 }
9708               }
9709             }
9710           }
9711         }
9712         else
9713         {
9714           // Non-branch
9715           if(i>0)
9716           {
9717             int d1=0,d2=0,map=-1,temp=-1;
9718             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9719             {
9720               d1=dep1[i];
9721               d2=dep2[i];
9722             }
9723             if(using_tlb) {
9724               if(itype[i]==LOAD || itype[i]==LOADLR ||
9725                  itype[i]==STORE || itype[i]==STORELR ||
9726                  itype[i]==C1LS || itype[i]==C2LS)
9727               map=TLREG;
9728             } else if(itype[i]==STORE || itype[i]==STORELR ||
9729                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9730               map=INVCP;
9731             }
9732             if(itype[i]==LOADLR || itype[i]==STORELR ||
9733                itype[i]==C1LS || itype[i]==C2LS)
9734               temp=FTEMP;
9735             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9736                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9737                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9738                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9739                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9740                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9741             {
9742               if(i<slen-1&&!is_ds[i]) {
9743                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9744                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9745                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9746                 {
9747                   printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9748                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9749                 }
9750                 regmap_pre[i+1][hr]=-1;
9751                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9752               }
9753               regs[i].regmap[hr]=-1;
9754               regs[i].isconst&=~(1<<hr);
9755             }
9756           }
9757         }
9758       }
9759     }
9760   }
9761
9762   /* Pass 5 - Pre-allocate registers */
9763
9764   // If a register is allocated during a loop, try to allocate it for the
9765   // entire loop, if possible.  This avoids loading/storing registers
9766   // inside of the loop.
9767
9768   signed char f_regmap[HOST_REGS];
9769   clear_all_regs(f_regmap);
9770   for(i=0;i<slen-1;i++)
9771   {
9772     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9773     {
9774       if(ba[i]>=start && ba[i]<(start+i*4))
9775       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9776       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9777       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9778       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9779       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9780       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9781       {
9782         int t=(ba[i]-start)>>2;
9783         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9784         if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9785         for(hr=0;hr<HOST_REGS;hr++)
9786         {
9787           if(regs[i].regmap[hr]>64) {
9788             if(!((regs[i].dirty>>hr)&1))
9789               f_regmap[hr]=regs[i].regmap[hr];
9790             else f_regmap[hr]=-1;
9791           }
9792           else if(regs[i].regmap[hr]>=0) {
9793             if(f_regmap[hr]!=regs[i].regmap[hr]) {
9794               // dealloc old register
9795               int n;
9796               for(n=0;n<HOST_REGS;n++)
9797               {
9798                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9799               }
9800               // and alloc new one
9801               f_regmap[hr]=regs[i].regmap[hr];
9802             }
9803           }
9804           if(branch_regs[i].regmap[hr]>64) {
9805             if(!((branch_regs[i].dirty>>hr)&1))
9806               f_regmap[hr]=branch_regs[i].regmap[hr];
9807             else f_regmap[hr]=-1;
9808           }
9809           else if(branch_regs[i].regmap[hr]>=0) {
9810             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9811               // dealloc old register
9812               int n;
9813               for(n=0;n<HOST_REGS;n++)
9814               {
9815                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9816               }
9817               // and alloc new one
9818               f_regmap[hr]=branch_regs[i].regmap[hr];
9819             }
9820           }
9821           if(ooo[i]) {
9822             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9823               f_regmap[hr]=branch_regs[i].regmap[hr];
9824           }else{
9825             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
9826               f_regmap[hr]=branch_regs[i].regmap[hr];
9827           }
9828           // Avoid dirty->clean transition
9829           #ifdef DESTRUCTIVE_WRITEBACK
9830           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9831           #endif
9832           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9833           // case above, however it's always a good idea.  We can't hoist the
9834           // load if the register was already allocated, so there's no point
9835           // wasting time analyzing most of these cases.  It only "succeeds"
9836           // when the mapping was different and the load can be replaced with
9837           // a mov, which is of negligible benefit.  So such cases are
9838           // skipped below.
9839           if(f_regmap[hr]>0) {
9840             if(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0) {
9841               int r=f_regmap[hr];
9842               for(j=t;j<=i;j++)
9843               {
9844                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9845                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9846                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9847                 if(r>63) {
9848                   // NB This can exclude the case where the upper-half
9849                   // register is lower numbered than the lower-half
9850                   // register.  Not sure if it's worth fixing...
9851                   if(get_reg(regs[j].regmap,r&63)<0) break;
9852                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
9853                   if(regs[j].is32&(1LL<<(r&63))) break;
9854                 }
9855                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9856                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9857                   int k;
9858                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9859                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9860                     if(r>63) {
9861                       if(get_reg(regs[i].regmap,r&63)<0) break;
9862                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9863                     }
9864                     k=i;
9865                     while(k>1&&regs[k-1].regmap[hr]==-1) {
9866                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9867                         //printf("no free regs for store %x\n",start+(k-1)*4);
9868                         break;
9869                       }
9870                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9871                         //printf("no-match due to different register\n");
9872                         break;
9873                       }
9874                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9875                         //printf("no-match due to branch\n");
9876                         break;
9877                       }
9878                       // call/ret fast path assumes no registers allocated
9879                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9880                         break;
9881                       }
9882                       if(r>63) {
9883                         // NB This can exclude the case where the upper-half
9884                         // register is lower numbered than the lower-half
9885                         // register.  Not sure if it's worth fixing...
9886                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
9887                         if(regs[k-1].is32&(1LL<<(r&63))) break;
9888                       }
9889                       k--;
9890                     }
9891                     if(i<slen-1) {
9892                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9893                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9894                         //printf("bad match after branch\n");
9895                         break;
9896                       }
9897                     }
9898                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9899                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
9900                       while(k<i) {
9901                         regs[k].regmap_entry[hr]=f_regmap[hr];
9902                         regs[k].regmap[hr]=f_regmap[hr];
9903                         regmap_pre[k+1][hr]=f_regmap[hr];
9904                         regs[k].wasdirty&=~(1<<hr);
9905                         regs[k].dirty&=~(1<<hr);
9906                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9907                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9908                         regs[k].wasconst&=~(1<<hr);
9909                         regs[k].isconst&=~(1<<hr);
9910                         k++;
9911                       }
9912                     }
9913                     else {
9914                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9915                       break;
9916                     }
9917                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9918                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9919                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
9920                       regs[i].regmap_entry[hr]=f_regmap[hr];
9921                       regs[i].regmap[hr]=f_regmap[hr];
9922                       regs[i].wasdirty&=~(1<<hr);
9923                       regs[i].dirty&=~(1<<hr);
9924                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9925                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9926                       regs[i].wasconst&=~(1<<hr);
9927                       regs[i].isconst&=~(1<<hr);
9928                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9929                       branch_regs[i].wasdirty&=~(1<<hr);
9930                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9931                       branch_regs[i].regmap[hr]=f_regmap[hr];
9932                       branch_regs[i].dirty&=~(1<<hr);
9933                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9934                       branch_regs[i].wasconst&=~(1<<hr);
9935                       branch_regs[i].isconst&=~(1<<hr);
9936                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9937                         regmap_pre[i+2][hr]=f_regmap[hr];
9938                         regs[i+2].wasdirty&=~(1<<hr);
9939                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9940                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9941                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
9942                       }
9943                     }
9944                   }
9945                   for(k=t;k<j;k++) {
9946                     // Alloc register clean at beginning of loop,
9947                     // but may dirty it in pass 6
9948                     regs[k].regmap_entry[hr]=f_regmap[hr];
9949                     regs[k].regmap[hr]=f_regmap[hr];
9950                     regs[k].dirty&=~(1<<hr);
9951                     regs[k].wasconst&=~(1<<hr);
9952                     regs[k].isconst&=~(1<<hr);
9953                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
9954                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
9955                       branch_regs[k].regmap[hr]=f_regmap[hr];
9956                       branch_regs[k].dirty&=~(1<<hr);
9957                       branch_regs[k].wasconst&=~(1<<hr);
9958                       branch_regs[k].isconst&=~(1<<hr);
9959                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
9960                         regmap_pre[k+2][hr]=f_regmap[hr];
9961                         regs[k+2].wasdirty&=~(1<<hr);
9962                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
9963                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
9964                       }
9965                     }
9966                     else
9967                     {
9968                       regmap_pre[k+1][hr]=f_regmap[hr];
9969                       regs[k+1].wasdirty&=~(1<<hr);
9970                     }
9971                   }
9972                   if(regs[j].regmap[hr]==f_regmap[hr])
9973                     regs[j].regmap_entry[hr]=f_regmap[hr];
9974                   break;
9975                 }
9976                 if(j==i) break;
9977                 if(regs[j].regmap[hr]>=0)
9978                   break;
9979                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9980                   //printf("no-match due to different register\n");
9981                   break;
9982                 }
9983                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9984                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9985                   break;
9986                 }
9987                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
9988                 {
9989                   // Stop on unconditional branch
9990                   break;
9991                 }
9992                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
9993                 {
9994                   if(ooo[j]) {
9995                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
9996                       break;
9997                   }else{
9998                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
9999                       break;
10000                   }
10001                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10002                     //printf("no-match due to different register (branch)\n");
10003                     break;
10004                   }
10005                 }
10006                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10007                   //printf("No free regs for store %x\n",start+j*4);
10008                   break;
10009                 }
10010                 if(f_regmap[hr]>=64) {
10011                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10012                     break;
10013                   }
10014                   else
10015                   {
10016                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10017                       break;
10018                     }
10019                   }
10020                 }
10021               }
10022             }
10023           }
10024         }
10025       }
10026     }else{
10027       int count=0;
10028       for(hr=0;hr<HOST_REGS;hr++)
10029       {
10030         if(hr!=EXCLUDE_REG) {
10031           if(regs[i].regmap[hr]>64) {
10032             if(!((regs[i].dirty>>hr)&1))
10033               f_regmap[hr]=regs[i].regmap[hr];
10034           }
10035           else if(regs[i].regmap[hr]>=0) {
10036             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10037               // dealloc old register
10038               int n;
10039               for(n=0;n<HOST_REGS;n++)
10040               {
10041                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10042               }
10043               // and alloc new one
10044               f_regmap[hr]=regs[i].regmap[hr];
10045             }
10046           }
10047           else if(regs[i].regmap[hr]<0) count++;
10048         }
10049       }
10050       // Try to restore cycle count at branch targets
10051       if(bt[i]) {
10052         for(j=i;j<slen-1;j++) {
10053           if(regs[j].regmap[HOST_CCREG]!=-1) break;
10054           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10055             //printf("no free regs for store %x\n",start+j*4);
10056             break;
10057           }
10058         }
10059         if(regs[j].regmap[HOST_CCREG]==CCREG) {
10060           int k=i;
10061           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10062           while(k<j) {
10063             regs[k].regmap_entry[HOST_CCREG]=CCREG;
10064             regs[k].regmap[HOST_CCREG]=CCREG;
10065             regmap_pre[k+1][HOST_CCREG]=CCREG;
10066             regs[k+1].wasdirty|=1<<HOST_CCREG;
10067             regs[k].dirty|=1<<HOST_CCREG;
10068             regs[k].wasconst&=~(1<<HOST_CCREG);
10069             regs[k].isconst&=~(1<<HOST_CCREG);
10070             k++;
10071           }
10072           regs[j].regmap_entry[HOST_CCREG]=CCREG;
10073         }
10074         // Work backwards from the branch target
10075         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10076         {
10077           //printf("Extend backwards\n");
10078           int k;
10079           k=i;
10080           while(regs[k-1].regmap[HOST_CCREG]==-1) {
10081             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10082               //printf("no free regs for store %x\n",start+(k-1)*4);
10083               break;
10084             }
10085             k--;
10086           }
10087           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10088             //printf("Extend CC, %x ->\n",start+k*4);
10089             while(k<=i) {
10090               regs[k].regmap_entry[HOST_CCREG]=CCREG;
10091               regs[k].regmap[HOST_CCREG]=CCREG;
10092               regmap_pre[k+1][HOST_CCREG]=CCREG;
10093               regs[k+1].wasdirty|=1<<HOST_CCREG;
10094               regs[k].dirty|=1<<HOST_CCREG;
10095               regs[k].wasconst&=~(1<<HOST_CCREG);
10096               regs[k].isconst&=~(1<<HOST_CCREG);
10097               k++;
10098             }
10099           }
10100           else {
10101             //printf("Fail Extend CC, %x ->\n",start+k*4);
10102           }
10103         }
10104       }
10105       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10106          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10107          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10108          itype[i]!=FCONV&&itype[i]!=FCOMP)
10109       {
10110         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10111       }
10112     }
10113   }
10114
10115   // This allocates registers (if possible) one instruction prior
10116   // to use, which can avoid a load-use penalty on certain CPUs.
10117   for(i=0;i<slen-1;i++)
10118   {
10119     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10120     {
10121       if(!bt[i+1])
10122       {
10123         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10124            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10125         {
10126           if(rs1[i+1]) {
10127             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10128             {
10129               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10130               {
10131                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10132                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10133                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10134                 regs[i].isconst&=~(1<<hr);
10135                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10136                 constmap[i][hr]=constmap[i+1][hr];
10137                 regs[i+1].wasdirty&=~(1<<hr);
10138                 regs[i].dirty&=~(1<<hr);
10139               }
10140             }
10141           }
10142           if(rs2[i+1]) {
10143             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10144             {
10145               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10146               {
10147                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10148                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10149                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10150                 regs[i].isconst&=~(1<<hr);
10151                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10152                 constmap[i][hr]=constmap[i+1][hr];
10153                 regs[i+1].wasdirty&=~(1<<hr);
10154                 regs[i].dirty&=~(1<<hr);
10155               }
10156             }
10157           }
10158           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10159             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10160             {
10161               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10162               {
10163                 regs[i].regmap[hr]=rs1[i+1];
10164                 regmap_pre[i+1][hr]=rs1[i+1];
10165                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10166                 regs[i].isconst&=~(1<<hr);
10167                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10168                 constmap[i][hr]=constmap[i+1][hr];
10169                 regs[i+1].wasdirty&=~(1<<hr);
10170                 regs[i].dirty&=~(1<<hr);
10171               }
10172             }
10173           }
10174           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10175             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10176             {
10177               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10178               {
10179                 regs[i].regmap[hr]=rs1[i+1];
10180                 regmap_pre[i+1][hr]=rs1[i+1];
10181                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10182                 regs[i].isconst&=~(1<<hr);
10183                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10184                 constmap[i][hr]=constmap[i+1][hr];
10185                 regs[i+1].wasdirty&=~(1<<hr);
10186                 regs[i].dirty&=~(1<<hr);
10187               }
10188             }
10189           }
10190           #ifndef HOST_IMM_ADDR32
10191           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10192             hr=get_reg(regs[i+1].regmap,TLREG);
10193             if(hr>=0) {
10194               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10195               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10196                 int nr;
10197                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10198                 {
10199                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10200                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10201                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10202                   regs[i].isconst&=~(1<<hr);
10203                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10204                   constmap[i][hr]=constmap[i+1][hr];
10205                   regs[i+1].wasdirty&=~(1<<hr);
10206                   regs[i].dirty&=~(1<<hr);
10207                 }
10208                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10209                 {
10210                   // move it to another register
10211                   regs[i+1].regmap[hr]=-1;
10212                   regmap_pre[i+2][hr]=-1;
10213                   regs[i+1].regmap[nr]=TLREG;
10214                   regmap_pre[i+2][nr]=TLREG;
10215                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10216                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10217                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10218                   regs[i].isconst&=~(1<<nr);
10219                   regs[i+1].isconst&=~(1<<nr);
10220                   regs[i].dirty&=~(1<<nr);
10221                   regs[i+1].wasdirty&=~(1<<nr);
10222                   regs[i+1].dirty&=~(1<<nr);
10223                   regs[i+2].wasdirty&=~(1<<nr);
10224                 }
10225               }
10226             }
10227           }
10228           #endif
10229           if(itype[i+1]==STORE||itype[i+1]==STORELR
10230              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10231             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10232               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10233               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10234               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10235               assert(hr>=0);
10236               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10237               {
10238                 regs[i].regmap[hr]=rs1[i+1];
10239                 regmap_pre[i+1][hr]=rs1[i+1];
10240                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10241                 regs[i].isconst&=~(1<<hr);
10242                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10243                 constmap[i][hr]=constmap[i+1][hr];
10244                 regs[i+1].wasdirty&=~(1<<hr);
10245                 regs[i].dirty&=~(1<<hr);
10246               }
10247             }
10248           }
10249           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10250             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10251               int nr;
10252               hr=get_reg(regs[i+1].regmap,FTEMP);
10253               assert(hr>=0);
10254               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10255               {
10256                 regs[i].regmap[hr]=rs1[i+1];
10257                 regmap_pre[i+1][hr]=rs1[i+1];
10258                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10259                 regs[i].isconst&=~(1<<hr);
10260                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10261                 constmap[i][hr]=constmap[i+1][hr];
10262                 regs[i+1].wasdirty&=~(1<<hr);
10263                 regs[i].dirty&=~(1<<hr);
10264               }
10265               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10266               {
10267                 // move it to another register
10268                 regs[i+1].regmap[hr]=-1;
10269                 regmap_pre[i+2][hr]=-1;
10270                 regs[i+1].regmap[nr]=FTEMP;
10271                 regmap_pre[i+2][nr]=FTEMP;
10272                 regs[i].regmap[nr]=rs1[i+1];
10273                 regmap_pre[i+1][nr]=rs1[i+1];
10274                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10275                 regs[i].isconst&=~(1<<nr);
10276                 regs[i+1].isconst&=~(1<<nr);
10277                 regs[i].dirty&=~(1<<nr);
10278                 regs[i+1].wasdirty&=~(1<<nr);
10279                 regs[i+1].dirty&=~(1<<nr);
10280                 regs[i+2].wasdirty&=~(1<<nr);
10281               }
10282             }
10283           }
10284           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10285             if(itype[i+1]==LOAD)
10286               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10287             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10288               hr=get_reg(regs[i+1].regmap,FTEMP);
10289             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10290               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10291               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10292             }
10293             if(hr>=0&&regs[i].regmap[hr]<0) {
10294               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10295               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10296                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10297                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10298                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10299                 regs[i].isconst&=~(1<<hr);
10300                 regs[i+1].wasdirty&=~(1<<hr);
10301                 regs[i].dirty&=~(1<<hr);
10302               }
10303             }
10304           }
10305         }
10306       }
10307     }
10308   }
10309
10310   /* Pass 6 - Optimize clean/dirty state */
10311   clean_registers(0,slen-1,1);
10312
10313   /* Pass 7 - Identify 32-bit registers */
10314 #ifndef FORCE32
10315   provisional_r32();
10316
10317   u_int r32=0;
10318
10319   for (i=slen-1;i>=0;i--)
10320   {
10321     int hr;
10322     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10323     {
10324       if(ba[i]<start || ba[i]>=(start+slen*4))
10325       {
10326         // Branch out of this block, don't need anything
10327         r32=0;
10328       }
10329       else
10330       {
10331         // Internal branch
10332         // Need whatever matches the target
10333         // (and doesn't get overwritten by the delay slot instruction)
10334         r32=0;
10335         int t=(ba[i]-start)>>2;
10336         if(ba[i]>start+i*4) {
10337           // Forward branch
10338           if(!(requires_32bit[t]&~regs[i].was32))
10339             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10340         }else{
10341           // Backward branch
10342           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10343           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10344           if(!(pr32[t]&~regs[i].was32))
10345             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10346         }
10347       }
10348       // Conditional branch may need registers for following instructions
10349       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10350       {
10351         if(i<slen-2) {
10352           r32|=requires_32bit[i+2];
10353           r32&=regs[i].was32;
10354           // Mark this address as a branch target since it may be called
10355           // upon return from interrupt
10356           bt[i+2]=1;
10357         }
10358       }
10359       // Merge in delay slot
10360       if(!likely[i]) {
10361         // These are overwritten unless the branch is "likely"
10362         // and the delay slot is nullified if not taken
10363         r32&=~(1LL<<rt1[i+1]);
10364         r32&=~(1LL<<rt2[i+1]);
10365       }
10366       // Assume these are needed (delay slot)
10367       if(us1[i+1]>0)
10368       {
10369         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10370       }
10371       if(us2[i+1]>0)
10372       {
10373         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10374       }
10375       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10376       {
10377         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10378       }
10379       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10380       {
10381         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10382       }
10383     }
10384     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10385     {
10386       // SYSCALL instruction (software interrupt)
10387       r32=0;
10388     }
10389     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10390     {
10391       // ERET instruction (return from interrupt)
10392       r32=0;
10393     }
10394     // Check 32 bits
10395     r32&=~(1LL<<rt1[i]);
10396     r32&=~(1LL<<rt2[i]);
10397     if(us1[i]>0)
10398     {
10399       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10400     }
10401     if(us2[i]>0)
10402     {
10403       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10404     }
10405     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10406     {
10407       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10408     }
10409     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10410     {
10411       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10412     }
10413     requires_32bit[i]=r32;
10414
10415     // Dirty registers which are 32-bit, require 32-bit input
10416     // as they will be written as 32-bit values
10417     for(hr=0;hr<HOST_REGS;hr++)
10418     {
10419       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10420         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10421           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10422           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10423         }
10424       }
10425     }
10426     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10427   }
10428 #endif
10429
10430   if(itype[slen-1]==SPAN) {
10431     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10432   }
10433
10434   /* Debug/disassembly */
10435   if((void*)assem_debug==(void*)printf)
10436   for(i=0;i<slen;i++)
10437   {
10438     printf("U:");
10439     int r;
10440     for(r=1;r<=CCREG;r++) {
10441       if((unneeded_reg[i]>>r)&1) {
10442         if(r==HIREG) printf(" HI");
10443         else if(r==LOREG) printf(" LO");
10444         else printf(" r%d",r);
10445       }
10446     }
10447 #ifndef FORCE32
10448     printf(" UU:");
10449     for(r=1;r<=CCREG;r++) {
10450       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10451         if(r==HIREG) printf(" HI");
10452         else if(r==LOREG) printf(" LO");
10453         else printf(" r%d",r);
10454       }
10455     }
10456     printf(" 32:");
10457     for(r=0;r<=CCREG;r++) {
10458       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10459       if((regs[i].was32>>r)&1) {
10460         if(r==CCREG) printf(" CC");
10461         else if(r==HIREG) printf(" HI");
10462         else if(r==LOREG) printf(" LO");
10463         else printf(" r%d",r);
10464       }
10465     }
10466 #endif
10467     printf("\n");
10468     #if defined(__i386__) || defined(__x86_64__)
10469     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10470     #endif
10471     #ifdef __arm__
10472     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10473     #endif
10474     printf("needs: ");
10475     if(needed_reg[i]&1) printf("eax ");
10476     if((needed_reg[i]>>1)&1) printf("ecx ");
10477     if((needed_reg[i]>>2)&1) printf("edx ");
10478     if((needed_reg[i]>>3)&1) printf("ebx ");
10479     if((needed_reg[i]>>5)&1) printf("ebp ");
10480     if((needed_reg[i]>>6)&1) printf("esi ");
10481     if((needed_reg[i]>>7)&1) printf("edi ");
10482     printf("r:");
10483     for(r=0;r<=CCREG;r++) {
10484       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10485       if((requires_32bit[i]>>r)&1) {
10486         if(r==CCREG) printf(" CC");
10487         else if(r==HIREG) printf(" HI");
10488         else if(r==LOREG) printf(" LO");
10489         else printf(" r%d",r);
10490       }
10491     }
10492     printf("\n");
10493     /*printf("pr:");
10494     for(r=0;r<=CCREG;r++) {
10495       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10496       if((pr32[i]>>r)&1) {
10497         if(r==CCREG) printf(" CC");
10498         else if(r==HIREG) printf(" HI");
10499         else if(r==LOREG) printf(" LO");
10500         else printf(" r%d",r);
10501       }
10502     }
10503     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10504     printf("\n");*/
10505     #if defined(__i386__) || defined(__x86_64__)
10506     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10507     printf("dirty: ");
10508     if(regs[i].wasdirty&1) printf("eax ");
10509     if((regs[i].wasdirty>>1)&1) printf("ecx ");
10510     if((regs[i].wasdirty>>2)&1) printf("edx ");
10511     if((regs[i].wasdirty>>3)&1) printf("ebx ");
10512     if((regs[i].wasdirty>>5)&1) printf("ebp ");
10513     if((regs[i].wasdirty>>6)&1) printf("esi ");
10514     if((regs[i].wasdirty>>7)&1) printf("edi ");
10515     #endif
10516     #ifdef __arm__
10517     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10518     printf("dirty: ");
10519     if(regs[i].wasdirty&1) printf("r0 ");
10520     if((regs[i].wasdirty>>1)&1) printf("r1 ");
10521     if((regs[i].wasdirty>>2)&1) printf("r2 ");
10522     if((regs[i].wasdirty>>3)&1) printf("r3 ");
10523     if((regs[i].wasdirty>>4)&1) printf("r4 ");
10524     if((regs[i].wasdirty>>5)&1) printf("r5 ");
10525     if((regs[i].wasdirty>>6)&1) printf("r6 ");
10526     if((regs[i].wasdirty>>7)&1) printf("r7 ");
10527     if((regs[i].wasdirty>>8)&1) printf("r8 ");
10528     if((regs[i].wasdirty>>9)&1) printf("r9 ");
10529     if((regs[i].wasdirty>>10)&1) printf("r10 ");
10530     if((regs[i].wasdirty>>12)&1) printf("r12 ");
10531     #endif
10532     printf("\n");
10533     disassemble_inst(i);
10534     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10535     #if defined(__i386__) || defined(__x86_64__)
10536     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10537     if(regs[i].dirty&1) printf("eax ");
10538     if((regs[i].dirty>>1)&1) printf("ecx ");
10539     if((regs[i].dirty>>2)&1) printf("edx ");
10540     if((regs[i].dirty>>3)&1) printf("ebx ");
10541     if((regs[i].dirty>>5)&1) printf("ebp ");
10542     if((regs[i].dirty>>6)&1) printf("esi ");
10543     if((regs[i].dirty>>7)&1) printf("edi ");
10544     #endif
10545     #ifdef __arm__
10546     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10547     if(regs[i].dirty&1) printf("r0 ");
10548     if((regs[i].dirty>>1)&1) printf("r1 ");
10549     if((regs[i].dirty>>2)&1) printf("r2 ");
10550     if((regs[i].dirty>>3)&1) printf("r3 ");
10551     if((regs[i].dirty>>4)&1) printf("r4 ");
10552     if((regs[i].dirty>>5)&1) printf("r5 ");
10553     if((regs[i].dirty>>6)&1) printf("r6 ");
10554     if((regs[i].dirty>>7)&1) printf("r7 ");
10555     if((regs[i].dirty>>8)&1) printf("r8 ");
10556     if((regs[i].dirty>>9)&1) printf("r9 ");
10557     if((regs[i].dirty>>10)&1) printf("r10 ");
10558     if((regs[i].dirty>>12)&1) printf("r12 ");
10559     #endif
10560     printf("\n");
10561     if(regs[i].isconst) {
10562       printf("constants: ");
10563       #if defined(__i386__) || defined(__x86_64__)
10564       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10565       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10566       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10567       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10568       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10569       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10570       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10571       #endif
10572       #ifdef __arm__
10573       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10574       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10575       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10576       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10577       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10578       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10579       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10580       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10581       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10582       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10583       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10584       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10585       #endif
10586       printf("\n");
10587     }
10588 #ifndef FORCE32
10589     printf(" 32:");
10590     for(r=0;r<=CCREG;r++) {
10591       if((regs[i].is32>>r)&1) {
10592         if(r==CCREG) printf(" CC");
10593         else if(r==HIREG) printf(" HI");
10594         else if(r==LOREG) printf(" LO");
10595         else printf(" r%d",r);
10596       }
10597     }
10598     printf("\n");
10599 #endif
10600     /*printf(" p32:");
10601     for(r=0;r<=CCREG;r++) {
10602       if((p32[i]>>r)&1) {
10603         if(r==CCREG) printf(" CC");
10604         else if(r==HIREG) printf(" HI");
10605         else if(r==LOREG) printf(" LO");
10606         else printf(" r%d",r);
10607       }
10608     }
10609     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10610     else printf("\n");*/
10611     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10612       #if defined(__i386__) || defined(__x86_64__)
10613       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10614       if(branch_regs[i].dirty&1) printf("eax ");
10615       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10616       if((branch_regs[i].dirty>>2)&1) printf("edx ");
10617       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10618       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10619       if((branch_regs[i].dirty>>6)&1) printf("esi ");
10620       if((branch_regs[i].dirty>>7)&1) printf("edi ");
10621       #endif
10622       #ifdef __arm__
10623       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10624       if(branch_regs[i].dirty&1) printf("r0 ");
10625       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10626       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10627       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10628       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10629       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10630       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10631       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10632       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10633       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10634       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10635       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10636       #endif
10637 #ifndef FORCE32
10638       printf(" 32:");
10639       for(r=0;r<=CCREG;r++) {
10640         if((branch_regs[i].is32>>r)&1) {
10641           if(r==CCREG) printf(" CC");
10642           else if(r==HIREG) printf(" HI");
10643           else if(r==LOREG) printf(" LO");
10644           else printf(" r%d",r);
10645         }
10646       }
10647       printf("\n");
10648 #endif
10649     }
10650   }
10651
10652   /* Pass 8 - Assembly */
10653   linkcount=0;stubcount=0;
10654   ds=0;is_delayslot=0;
10655   cop1_usable=0;
10656   uint64_t is32_pre=0;
10657   u_int dirty_pre=0;
10658   u_int beginning=(u_int)out;
10659   if((u_int)addr&1) {
10660     ds=1;
10661     pagespan_ds();
10662   }
10663   u_int instr_addr0_override=0;
10664
10665 #ifdef PCSX
10666   if (start == 0x80030000) {
10667     // nasty hack for fastbios thing
10668     instr_addr0_override=(u_int)out;
10669     emit_movimm(start,0);
10670     emit_readword((int)&pcaddr,1);
10671     emit_writeword(0,(int)&pcaddr);
10672     emit_cmp(0,1);
10673     emit_jne((int)new_dyna_leave);
10674   }
10675 #endif
10676   for(i=0;i<slen;i++)
10677   {
10678     //if(ds) printf("ds: ");
10679     if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10680     if(ds) {
10681       ds=0; // Skip delay slot
10682       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10683       instr_addr[i]=0;
10684     } else {
10685       #ifndef DESTRUCTIVE_WRITEBACK
10686       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10687       {
10688         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10689               unneeded_reg[i],unneeded_reg_upper[i]);
10690         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10691               unneeded_reg[i],unneeded_reg_upper[i]);
10692       }
10693       is32_pre=regs[i].is32;
10694       dirty_pre=regs[i].dirty;
10695       #endif
10696       // write back
10697       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10698       {
10699         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10700                       unneeded_reg[i],unneeded_reg_upper[i]);
10701         loop_preload(regmap_pre[i],regs[i].regmap_entry);
10702       }
10703       // branch target entry point
10704       instr_addr[i]=(u_int)out;
10705       assem_debug("<->\n");
10706       // load regs
10707       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10708         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10709       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10710       address_generation(i,&regs[i],regs[i].regmap_entry);
10711       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10712       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10713       {
10714         // Load the delay slot registers if necessary
10715         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10716           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10717         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10718           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10719         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
10720           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10721       }
10722       else if(i+1<slen)
10723       {
10724         // Preload registers for following instruction
10725         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10726           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10727             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10728         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10729           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10730             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10731       }
10732       // TODO: if(is_ooo(i)) address_generation(i+1);
10733       if(itype[i]==CJUMP||itype[i]==FJUMP)
10734         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10735       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
10736         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10737       if(bt[i]) cop1_usable=0;
10738       // assemble
10739       switch(itype[i]) {
10740         case ALU:
10741           alu_assemble(i,&regs[i]);break;
10742         case IMM16:
10743           imm16_assemble(i,&regs[i]);break;
10744         case SHIFT:
10745           shift_assemble(i,&regs[i]);break;
10746         case SHIFTIMM:
10747           shiftimm_assemble(i,&regs[i]);break;
10748         case LOAD:
10749           load_assemble(i,&regs[i]);break;
10750         case LOADLR:
10751           loadlr_assemble(i,&regs[i]);break;
10752         case STORE:
10753           store_assemble(i,&regs[i]);break;
10754         case STORELR:
10755           storelr_assemble(i,&regs[i]);break;
10756         case COP0:
10757           cop0_assemble(i,&regs[i]);break;
10758         case COP1:
10759           cop1_assemble(i,&regs[i]);break;
10760         case C1LS:
10761           c1ls_assemble(i,&regs[i]);break;
10762         case COP2:
10763           cop2_assemble(i,&regs[i]);break;
10764         case C2LS:
10765           c2ls_assemble(i,&regs[i]);break;
10766         case C2OP:
10767           c2op_assemble(i,&regs[i]);break;
10768         case FCONV:
10769           fconv_assemble(i,&regs[i]);break;
10770         case FLOAT:
10771           float_assemble(i,&regs[i]);break;
10772         case FCOMP:
10773           fcomp_assemble(i,&regs[i]);break;
10774         case MULTDIV:
10775           multdiv_assemble(i,&regs[i]);break;
10776         case MOV:
10777           mov_assemble(i,&regs[i]);break;
10778         case SYSCALL:
10779           syscall_assemble(i,&regs[i]);break;
10780         case HLECALL:
10781           hlecall_assemble(i,&regs[i]);break;
10782         case INTCALL:
10783           intcall_assemble(i,&regs[i]);break;
10784         case UJUMP:
10785           ujump_assemble(i,&regs[i]);ds=1;break;
10786         case RJUMP:
10787           rjump_assemble(i,&regs[i]);ds=1;break;
10788         case CJUMP:
10789           cjump_assemble(i,&regs[i]);ds=1;break;
10790         case SJUMP:
10791           sjump_assemble(i,&regs[i]);ds=1;break;
10792         case FJUMP:
10793           fjump_assemble(i,&regs[i]);ds=1;break;
10794         case SPAN:
10795           pagespan_assemble(i,&regs[i]);break;
10796       }
10797       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10798         literal_pool(1024);
10799       else
10800         literal_pool_jumpover(256);
10801     }
10802   }
10803   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10804   // If the block did not end with an unconditional branch,
10805   // add a jump to the next instruction.
10806   if(i>1) {
10807     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10808       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10809       assert(i==slen);
10810       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10811         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10812         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10813           emit_loadreg(CCREG,HOST_CCREG);
10814         emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10815       }
10816       else if(!likely[i-2])
10817       {
10818         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10819         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10820       }
10821       else
10822       {
10823         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10824         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10825       }
10826       add_to_linker((int)out,start+i*4,0);
10827       emit_jmp(0);
10828     }
10829   }
10830   else
10831   {
10832     assert(i>0);
10833     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10834     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10835     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10836       emit_loadreg(CCREG,HOST_CCREG);
10837     emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10838     add_to_linker((int)out,start+i*4,0);
10839     emit_jmp(0);
10840   }
10841
10842   // TODO: delay slot stubs?
10843   // Stubs
10844   for(i=0;i<stubcount;i++)
10845   {
10846     switch(stubs[i][0])
10847     {
10848       case LOADB_STUB:
10849       case LOADH_STUB:
10850       case LOADW_STUB:
10851       case LOADD_STUB:
10852       case LOADBU_STUB:
10853       case LOADHU_STUB:
10854         do_readstub(i);break;
10855       case STOREB_STUB:
10856       case STOREH_STUB:
10857       case STOREW_STUB:
10858       case STORED_STUB:
10859         do_writestub(i);break;
10860       case CC_STUB:
10861         do_ccstub(i);break;
10862       case INVCODE_STUB:
10863         do_invstub(i);break;
10864       case FP_STUB:
10865         do_cop1stub(i);break;
10866       case STORELR_STUB:
10867         do_unalignedwritestub(i);break;
10868     }
10869   }
10870
10871   if (instr_addr0_override)
10872     instr_addr[0] = instr_addr0_override;
10873
10874   /* Pass 9 - Linker */
10875   for(i=0;i<linkcount;i++)
10876   {
10877     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10878     literal_pool(64);
10879     if(!link_addr[i][2])
10880     {
10881       void *stub=out;
10882       void *addr=check_addr(link_addr[i][1]);
10883       emit_extjump(link_addr[i][0],link_addr[i][1]);
10884       if(addr) {
10885         set_jump_target(link_addr[i][0],(int)addr);
10886         add_link(link_addr[i][1],stub);
10887       }
10888       else set_jump_target(link_addr[i][0],(int)stub);
10889     }
10890     else
10891     {
10892       // Internal branch
10893       int target=(link_addr[i][1]-start)>>2;
10894       assert(target>=0&&target<slen);
10895       assert(instr_addr[target]);
10896       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10897       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10898       //#else
10899       set_jump_target(link_addr[i][0],instr_addr[target]);
10900       //#endif
10901     }
10902   }
10903   // External Branch Targets (jump_in)
10904   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10905   for(i=0;i<slen;i++)
10906   {
10907     if(bt[i]||i==0)
10908     {
10909       if(instr_addr[i]) // TODO - delay slots (=null)
10910       {
10911         u_int vaddr=start+i*4;
10912         u_int page=get_page(vaddr);
10913         u_int vpage=get_vpage(vaddr);
10914         literal_pool(256);
10915         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10916 #ifndef FORCE32
10917         if(!requires_32bit[i])
10918 #else
10919         if(1)
10920 #endif
10921         {
10922           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10923           assem_debug("jump_in: %x\n",start+i*4);
10924           ll_add(jump_dirty+vpage,vaddr,(void *)out);
10925           int entry_point=do_dirty_stub(i);
10926           ll_add(jump_in+page,vaddr,(void *)entry_point);
10927           // If there was an existing entry in the hash table,
10928           // replace it with the new address.
10929           // Don't add new entries.  We'll insert the
10930           // ones that actually get used in check_addr().
10931           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10932           if(ht_bin[0]==vaddr) {
10933             ht_bin[1]=entry_point;
10934           }
10935           if(ht_bin[2]==vaddr) {
10936             ht_bin[3]=entry_point;
10937           }
10938         }
10939         else
10940         {
10941           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10942           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10943           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10944           //int entry_point=(int)out;
10945           ////assem_debug("entry_point: %x\n",entry_point);
10946           //load_regs_entry(i);
10947           //if(entry_point==(int)out)
10948           //  entry_point=instr_addr[i];
10949           //else
10950           //  emit_jmp(instr_addr[i]);
10951           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10952           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10953           int entry_point=do_dirty_stub(i);
10954           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10955         }
10956       }
10957     }
10958   }
10959   // Write out the literal pool if necessary
10960   literal_pool(0);
10961   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10962   // Align code
10963   if(((u_int)out)&7) emit_addnop(13);
10964   #endif
10965   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10966   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10967   memcpy(copy,source,slen*4);
10968   copy+=slen*4;
10969
10970   #ifdef __arm__
10971   __clear_cache((void *)beginning,out);
10972   #endif
10973
10974   // If we're within 256K of the end of the buffer,
10975   // start over from the beginning. (Is 256K enough?)
10976   if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10977
10978   // Trap writes to any of the pages we compiled
10979   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10980     invalid_code[i]=0;
10981 #ifndef DISABLE_TLB
10982     memory_map[i]|=0x40000000;
10983     if((signed int)start>=(signed int)0xC0000000) {
10984       assert(using_tlb);
10985       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10986       invalid_code[j]=0;
10987       memory_map[j]|=0x40000000;
10988       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
10989     }
10990 #endif
10991   }
10992
10993   /* Pass 10 - Free memory by expiring oldest blocks */
10994
10995   int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
10996   while(expirep!=end)
10997   {
10998     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10999     int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11000     inv_debug("EXP: Phase %d\n",expirep);
11001     switch((expirep>>11)&3)
11002     {
11003       case 0:
11004         // Clear jump_in and jump_dirty
11005         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11006         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11007         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11008         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11009         break;
11010       case 1:
11011         // Clear pointers
11012         ll_kill_pointers(jump_out[expirep&2047],base,shift);
11013         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11014         break;
11015       case 2:
11016         // Clear hash table
11017         for(i=0;i<32;i++) {
11018           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11019           if((ht_bin[3]>>shift)==(base>>shift) ||
11020              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11021             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11022             ht_bin[2]=ht_bin[3]=-1;
11023           }
11024           if((ht_bin[1]>>shift)==(base>>shift) ||
11025              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11026             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11027             ht_bin[0]=ht_bin[2];
11028             ht_bin[1]=ht_bin[3];
11029             ht_bin[2]=ht_bin[3]=-1;
11030           }
11031         }
11032         break;
11033       case 3:
11034         // Clear jump_out
11035         #ifdef __arm__
11036         if((expirep&2047)==0)
11037           do_clear_cache();
11038         #endif
11039         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11040         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11041         break;
11042     }
11043     expirep=(expirep+1)&65535;
11044   }
11045   return 0;
11046 }
11047
11048 // vim:shiftwidth=2:expandtab