1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
25 #include "emu_if.h" //emulator interface
30 #include "assem_x86.h"
33 #include "assem_x64.h"
36 #include "assem_arm.h"
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
55 uint64_t constmap[HOST_REGS];
63 struct ll_entry *next;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
85 char likely[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
110 u_int stubs[MAXBLOCK*3][8];
112 u_int literals[1024][2];
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
129 /* registers that may be allocated */
131 #define HIREG 32 // hi
132 #define LOREG 33 // lo
133 #define FSREG 34 // FPU status (FCSR)
134 #define CSREG 35 // Coprocessor status
135 #define CCREG 36 // Cycle count
136 #define INVCP 37 // Pointer to invalid_code
138 #define FTEMP 38 // FPU/LDL/LDR temporary register
139 #define PTEMP 39 // Prefetch temporary register
140 #define TLREG 40 // TLB mapping offset
141 #define RHASH 41 // Return address hash
142 #define RHTBL 42 // Return address hash table address
143 #define RTEMP 43 // JR/JALR address register
145 #define AGEN1 44 // Address generation temporary register
146 #define AGEN2 45 // Address generation temporary register
147 #define MGEN1 46 // Maptable address generation temporary register
148 #define MGEN2 47 // Maptable address generation temporary register
149 #define BTREG 48 // Branch target temporary register
151 /* instruction types */
152 #define NOP 0 // No operation
153 #define LOAD 1 // Load
154 #define STORE 2 // Store
155 #define LOADLR 3 // Unaligned load
156 #define STORELR 4 // Unaligned store
157 #define MOV 5 // Move
158 #define ALU 6 // Arithmetic/logic
159 #define MULTDIV 7 // Multiply/divide
160 #define SHIFT 8 // Shift by register
161 #define SHIFTIMM 9// Shift by immediate
162 #define IMM16 10 // 16-bit immediate
163 #define RJUMP 11 // Unconditional jump to register
164 #define UJUMP 12 // Unconditional jump
165 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166 #define SJUMP 14 // Conditional branch (regimm format)
167 #define COP0 15 // Coprocessor 0
168 #define COP1 16 // Coprocessor 1
169 #define C1LS 17 // Coprocessor 1 load/store
170 #define FJUMP 18 // Conditional branch (floating point)
171 #define FLOAT 19 // Floating point unit
172 #define FCONV 20 // Convert integer to float
173 #define FCOMP 21 // Floating point compare (sets FSREG)
174 #define SYSCALL 22// SYSCALL
175 #define OTHER 23 // Other
176 #define SPAN 24 // Branch/delay slot spans 2 pages
177 #define NI 25 // Not implemented
178 #define HLECALL 26// PCSX fake opcodes for HLE
179 #define COP2 27 // Coprocessor 2 move
180 #define C2LS 28 // Coprocessor 2 load/store
181 #define C2OP 29 // Coprocessor 2 operation
190 #define LOADBU_STUB 7
191 #define LOADHU_STUB 8
192 #define STOREB_STUB 9
193 #define STOREH_STUB 10
194 #define STOREW_STUB 11
195 #define STORED_STUB 12
196 #define STORELR_STUB 13
197 #define INVCODE_STUB 14
205 int new_recompile_block(int addr);
206 void *get_addr_ht(u_int vaddr);
207 void invalidate_block(u_int block);
208 void invalidate_addr(u_int addr);
209 void remove_hash(int vaddr);
212 void dyna_linker_ds();
214 void verify_code_vm();
215 void verify_code_ds();
218 void fp_exception_ds();
220 void jump_syscall_hle();
223 void new_dyna_leave();
228 void read_nomem_new();
229 void read_nomemb_new();
230 void read_nomemh_new();
231 void read_nomemd_new();
232 void write_nomem_new();
233 void write_nomemb_new();
234 void write_nomemh_new();
235 void write_nomemd_new();
236 void write_rdram_new();
237 void write_rdramb_new();
238 void write_rdramh_new();
239 void write_rdramd_new();
240 extern u_int memory_map[1048576];
242 // Needed by assembler
243 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
244 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
245 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
246 void load_all_regs(signed char i_regmap[]);
247 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
248 void load_regs_entry(int t);
249 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
253 //#define DEBUG_CYCLE_COUNT 1
256 //#define assem_debug printf
257 //#define inv_debug printf
258 #define assem_debug nullf
259 #define inv_debug nullf
261 static void tlb_hacks()
265 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
269 switch (ROM_HEADER->Country_code&0xFF)
281 // Unknown country code
285 u_int rom_addr=(u_int)rom;
287 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
288 // in the lower 4G of memory to use this hack. Copy it if necessary.
289 if((void *)rom>(void *)0xffffffff) {
290 munmap(ROM_COPY, 67108864);
291 if(mmap(ROM_COPY, 12582912,
292 PROT_READ | PROT_WRITE,
293 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
294 -1, 0) <= 0) {printf("mmap() failed\n");}
295 memcpy(ROM_COPY,rom,12582912);
296 rom_addr=(u_int)ROM_COPY;
300 for(n=0x7F000;n<0x80000;n++) {
301 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
308 static u_int get_page(u_int vaddr)
310 u_int page=(vaddr^0x80000000)>>12;
312 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
314 if(page>2048) page=2048+(page&2047);
318 static u_int get_vpage(u_int vaddr)
320 u_int vpage=(vaddr^0x80000000)>>12;
322 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
324 if(vpage>2048) vpage=2048+(vpage&2047);
328 // Get address from virtual address
329 // This is called from the recompiled JR/JALR instructions
330 void *get_addr(u_int vaddr)
332 u_int page=get_page(vaddr);
333 u_int vpage=get_vpage(vaddr);
334 struct ll_entry *head;
335 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
338 if(head->vaddr==vaddr&&head->reg32==0) {
339 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
340 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
343 ht_bin[1]=(int)head->addr;
349 head=jump_dirty[vpage];
351 if(head->vaddr==vaddr&&head->reg32==0) {
352 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
353 // Don't restore blocks which are about to expire from the cache
354 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
355 if(verify_dirty(head->addr)) {
356 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
357 invalid_code[vaddr>>12]=0;
358 memory_map[vaddr>>12]|=0x40000000;
361 if(tlb_LUT_r[vaddr>>12]) {
362 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
363 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
366 restore_candidate[vpage>>3]|=1<<(vpage&7);
368 else restore_candidate[page>>3]|=1<<(page&7);
369 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
370 if(ht_bin[0]==vaddr) {
371 ht_bin[1]=(int)head->addr; // Replace existing entry
377 ht_bin[1]=(int)head->addr;
385 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
386 int r=new_recompile_block(vaddr);
387 if(r==0) return get_addr(vaddr);
388 // Execute in unmapped page, generate pagefault execption
390 Cause=(vaddr<<31)|0x8;
391 EPC=(vaddr&1)?vaddr-5:vaddr;
393 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
394 EntryHi=BadVAddr&0xFFFFE000;
395 return get_addr_ht(0x80000000);
397 // Look up address in hash table first
398 void *get_addr_ht(u_int vaddr)
400 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
401 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
402 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
403 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
404 return get_addr(vaddr);
407 void *get_addr_32(u_int vaddr,u_int flags)
410 return get_addr(vaddr);
412 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
413 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
414 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
415 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
416 u_int page=get_page(vaddr);
417 u_int vpage=get_vpage(vaddr);
418 struct ll_entry *head;
421 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
422 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
424 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
426 ht_bin[1]=(int)head->addr;
428 }else if(ht_bin[2]==-1) {
429 ht_bin[3]=(int)head->addr;
432 //ht_bin[3]=ht_bin[1];
433 //ht_bin[2]=ht_bin[0];
434 //ht_bin[1]=(int)head->addr;
441 head=jump_dirty[vpage];
443 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
444 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
445 // Don't restore blocks which are about to expire from the cache
446 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
447 if(verify_dirty(head->addr)) {
448 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
449 invalid_code[vaddr>>12]=0;
450 memory_map[vaddr>>12]|=0x40000000;
453 if(tlb_LUT_r[vaddr>>12]) {
454 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
455 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
458 restore_candidate[vpage>>3]|=1<<(vpage&7);
460 else restore_candidate[page>>3]|=1<<(page&7);
462 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
464 ht_bin[1]=(int)head->addr;
466 }else if(ht_bin[2]==-1) {
467 ht_bin[3]=(int)head->addr;
470 //ht_bin[3]=ht_bin[1];
471 //ht_bin[2]=ht_bin[0];
472 //ht_bin[1]=(int)head->addr;
480 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
481 int r=new_recompile_block(vaddr);
482 if(r==0) return get_addr(vaddr);
483 // Execute in unmapped page, generate pagefault execption
485 Cause=(vaddr<<31)|0x8;
486 EPC=(vaddr&1)?vaddr-5:vaddr;
488 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
489 EntryHi=BadVAddr&0xFFFFE000;
490 return get_addr_ht(0x80000000);
493 void clear_all_regs(signed char regmap[])
496 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
499 signed char get_reg(signed char regmap[],int r)
502 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
506 // Find a register that is available for two consecutive cycles
507 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
510 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
514 int count_free_regs(signed char regmap[])
518 for(hr=0;hr<HOST_REGS;hr++)
520 if(hr!=EXCLUDE_REG) {
521 if(regmap[hr]<0) count++;
527 void dirty_reg(struct regstat *cur,signed char reg)
531 for (hr=0;hr<HOST_REGS;hr++) {
532 if((cur->regmap[hr]&63)==reg) {
538 // If we dirty the lower half of a 64 bit register which is now being
539 // sign-extended, we need to dump the upper half.
540 // Note: Do this only after completion of the instruction, because
541 // some instructions may need to read the full 64-bit value even if
542 // overwriting it (eg SLTI, DSRA32).
543 static void flush_dirty_uppers(struct regstat *cur)
546 for (hr=0;hr<HOST_REGS;hr++) {
547 if((cur->dirty>>hr)&1) {
550 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
555 void set_const(struct regstat *cur,signed char reg,uint64_t value)
559 for (hr=0;hr<HOST_REGS;hr++) {
560 if(cur->regmap[hr]==reg) {
562 cur->constmap[hr]=value;
564 else if((cur->regmap[hr]^64)==reg) {
566 cur->constmap[hr]=value>>32;
571 void clear_const(struct regstat *cur,signed char reg)
575 for (hr=0;hr<HOST_REGS;hr++) {
576 if((cur->regmap[hr]&63)==reg) {
577 cur->isconst&=~(1<<hr);
582 int is_const(struct regstat *cur,signed char reg)
586 for (hr=0;hr<HOST_REGS;hr++) {
587 if((cur->regmap[hr]&63)==reg) {
588 return (cur->isconst>>hr)&1;
593 uint64_t get_const(struct regstat *cur,signed char reg)
597 for (hr=0;hr<HOST_REGS;hr++) {
598 if(cur->regmap[hr]==reg) {
599 return cur->constmap[hr];
602 printf("Unknown constant in r%d\n",reg);
606 // Least soon needed registers
607 // Look at the next ten instructions and see which registers
608 // will be used. Try not to reallocate these.
609 void lsn(u_char hsn[], int i, int *preferred_reg)
619 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
621 // Don't go past an unconditonal jump
628 if(rs1[i+j]) hsn[rs1[i+j]]=j;
629 if(rs2[i+j]) hsn[rs2[i+j]]=j;
630 if(rt1[i+j]) hsn[rt1[i+j]]=j;
631 if(rt2[i+j]) hsn[rt2[i+j]]=j;
632 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
633 // Stores can allocate zero
637 // On some architectures stores need invc_ptr
638 #if defined(HOST_IMM8)
639 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
643 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
651 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
653 // Follow first branch
654 int t=(ba[i+b]-start)>>2;
655 j=7-b;if(t+j>=slen) j=slen-t-1;
658 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
659 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
660 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
661 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
664 // TODO: preferred register based on backward branch
666 // Delay slot should preferably not overwrite branch conditions or cycle count
667 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
668 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
669 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
675 // Coprocessor load/store needs FTEMP, even if not declared
676 if(itype[i]==C1LS||itype[i]==C2LS) {
679 // Load L/R also uses FTEMP as a temporary register
680 if(itype[i]==LOADLR) {
683 // Also 64-bit SDL/SDR
684 if(opcode[i]==0x2c||opcode[i]==0x2d) {
687 // Don't remove the TLB registers either
688 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
691 // Don't remove the miniht registers
692 if(itype[i]==UJUMP||itype[i]==RJUMP)
699 // We only want to allocate registers if we're going to use them again soon
700 int needed_again(int r, int i)
706 u_char hsn[MAXREG+1];
709 memset(hsn,10,sizeof(hsn));
710 lsn(hsn,i,&preferred_reg);
712 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
714 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
715 return 0; // Don't need any registers if exiting the block
723 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
725 // Don't go past an unconditonal jump
729 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||((source[i+j]&0xfc00003f)==0x0d))
736 if(rs1[i+j]==r) rn=j;
737 if(rs2[i+j]==r) rn=j;
738 if((unneeded_reg[i+j]>>r)&1) rn=10;
739 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
747 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
749 // Follow first branch
751 int t=(ba[i+b]-start)>>2;
752 j=7-b;if(t+j>=slen) j=slen-t-1;
755 if(!((unneeded_reg[t+j]>>r)&1)) {
756 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
757 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
763 for(hr=0;hr<HOST_REGS;hr++) {
764 if(hr!=EXCLUDE_REG) {
765 if(rn<hsn[hr]) return 1;
771 // Try to match register allocations at the end of a loop with those
773 int loop_reg(int i, int r, int hr)
782 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
784 // Don't go past an unconditonal jump
791 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
796 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
797 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
798 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
800 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
802 int t=(ba[i+k]-start)>>2;
803 int reg=get_reg(regs[t].regmap_entry,r);
804 if(reg>=0) return reg;
805 //reg=get_reg(regs[t+1].regmap_entry,r);
806 //if(reg>=0) return reg;
814 // Allocate every register, preserving source/target regs
815 void alloc_all(struct regstat *cur,int i)
819 for(hr=0;hr<HOST_REGS;hr++) {
820 if(hr!=EXCLUDE_REG) {
821 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
822 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
825 cur->dirty&=~(1<<hr);
828 if((cur->regmap[hr]&63)==0)
831 cur->dirty&=~(1<<hr);
838 void div64(int64_t dividend,int64_t divisor)
842 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
843 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
845 void divu64(uint64_t dividend,uint64_t divisor)
849 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
850 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
853 void mult64(uint64_t m1,uint64_t m2)
855 unsigned long long int op1, op2, op3, op4;
856 unsigned long long int result1, result2, result3, result4;
857 unsigned long long int temp1, temp2, temp3, temp4;
873 op1 = op2 & 0xFFFFFFFF;
874 op2 = (op2 >> 32) & 0xFFFFFFFF;
875 op3 = op4 & 0xFFFFFFFF;
876 op4 = (op4 >> 32) & 0xFFFFFFFF;
879 temp2 = (temp1 >> 32) + op1 * op4;
881 temp4 = (temp3 >> 32) + op2 * op4;
883 result1 = temp1 & 0xFFFFFFFF;
884 result2 = temp2 + (temp3 & 0xFFFFFFFF);
885 result3 = (result2 >> 32) + temp4;
886 result4 = (result3 >> 32);
888 lo = result1 | (result2 << 32);
889 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
898 void multu64(uint64_t m1,uint64_t m2)
900 unsigned long long int op1, op2, op3, op4;
901 unsigned long long int result1, result2, result3, result4;
902 unsigned long long int temp1, temp2, temp3, temp4;
904 op1 = m1 & 0xFFFFFFFF;
905 op2 = (m1 >> 32) & 0xFFFFFFFF;
906 op3 = m2 & 0xFFFFFFFF;
907 op4 = (m2 >> 32) & 0xFFFFFFFF;
910 temp2 = (temp1 >> 32) + op1 * op4;
912 temp4 = (temp3 >> 32) + op2 * op4;
914 result1 = temp1 & 0xFFFFFFFF;
915 result2 = temp2 + (temp3 & 0xFFFFFFFF);
916 result3 = (result2 >> 32) + temp4;
917 result4 = (result3 >> 32);
919 lo = result1 | (result2 << 32);
920 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
922 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
923 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
926 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
934 else original=loaded;
937 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
940 original>>=64-(bits^56);
941 original<<=64-(bits^56);
945 else original=loaded;
950 #include "assem_x86.c"
953 #include "assem_x64.c"
956 #include "assem_arm.c"
959 // Add virtual address mapping to linked list
960 void ll_add(struct ll_entry **head,int vaddr,void *addr)
962 struct ll_entry *new_entry;
963 new_entry=malloc(sizeof(struct ll_entry));
964 assert(new_entry!=NULL);
965 new_entry->vaddr=vaddr;
967 new_entry->addr=addr;
968 new_entry->next=*head;
972 // Add virtual address mapping for 32-bit compiled block
973 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
975 ll_add(head,vaddr,addr);
977 (*head)->reg32=reg32;
981 // Check if an address is already compiled
982 // but don't return addresses which are about to expire from the cache
983 void *check_addr(u_int vaddr)
985 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
986 if(ht_bin[0]==vaddr) {
987 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
988 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
990 if(ht_bin[2]==vaddr) {
991 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
992 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
994 u_int page=get_page(vaddr);
995 struct ll_entry *head;
998 if(head->vaddr==vaddr&&head->reg32==0) {
999 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1000 // Update existing entry with current address
1001 if(ht_bin[0]==vaddr) {
1002 ht_bin[1]=(int)head->addr;
1005 if(ht_bin[2]==vaddr) {
1006 ht_bin[3]=(int)head->addr;
1009 // Insert into hash table with low priority.
1010 // Don't evict existing entries, as they are probably
1011 // addresses that are being accessed frequently.
1013 ht_bin[1]=(int)head->addr;
1015 }else if(ht_bin[2]==-1) {
1016 ht_bin[3]=(int)head->addr;
1027 void remove_hash(int vaddr)
1029 //printf("remove hash: %x\n",vaddr);
1030 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1031 if(ht_bin[2]==vaddr) {
1032 ht_bin[2]=ht_bin[3]=-1;
1034 if(ht_bin[0]==vaddr) {
1035 ht_bin[0]=ht_bin[2];
1036 ht_bin[1]=ht_bin[3];
1037 ht_bin[2]=ht_bin[3]=-1;
1041 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1043 struct ll_entry *next;
1045 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1046 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1048 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1049 remove_hash((*head)->vaddr);
1056 head=&((*head)->next);
1061 // Remove all entries from linked list
1062 void ll_clear(struct ll_entry **head)
1064 struct ll_entry *cur;
1065 struct ll_entry *next;
1076 // Dereference the pointers and remove if it matches
1077 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1080 int ptr=get_pointer(head->addr);
1081 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1082 if(((ptr>>shift)==(addr>>shift)) ||
1083 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1085 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1086 kill_pointer(head->addr);
1092 // This is called when we write to a compiled block (see do_invstub)
1093 int invalidate_page(u_int page)
1096 struct ll_entry *head;
1097 struct ll_entry *next;
1101 inv_debug("INVALIDATE: %x\n",head->vaddr);
1102 remove_hash(head->vaddr);
1107 head=jump_out[page];
1110 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1111 kill_pointer(head->addr);
1119 void invalidate_block(u_int block)
1122 u_int page=get_page(block<<12);
1123 u_int vpage=get_vpage(block<<12);
1124 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1125 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1128 struct ll_entry *head;
1129 head=jump_dirty[vpage];
1130 //printf("page=%d vpage=%d\n",page,vpage);
1133 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1134 get_bounds((int)head->addr,&start,&end);
1135 //printf("start: %x end: %x\n",start,end);
1136 if(page<2048&&start>=0x80000000&&end<0x80800000) {
1137 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1138 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1139 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1143 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1144 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1145 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1146 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1153 //printf("first=%d last=%d\n",first,last);
1154 modified=invalidate_page(page);
1155 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1156 assert(last<page+5);
1157 // Invalidate the adjacent pages if a block crosses a 4K boundary
1159 invalidate_page(first);
1162 for(first=page+1;first<last;first++) {
1163 invalidate_page(first);
1166 // Don't trap writes
1167 invalid_code[block]=1;
1169 // If there is a valid TLB entry for this page, remove write protect
1170 if(tlb_LUT_w[block]) {
1171 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1172 // CHECK: Is this right?
1173 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1174 u_int real_block=tlb_LUT_w[block]>>12;
1175 invalid_code[real_block]=1;
1176 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1178 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1182 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1185 memset(mini_ht,-1,sizeof(mini_ht));
1188 void invalidate_addr(u_int addr)
1190 invalidate_block(addr>>12);
1192 void invalidate_all_pages()
1195 for(page=0;page<4096;page++)
1196 invalidate_page(page);
1197 for(page=0;page<1048576;page++)
1198 if(!invalid_code[page]) {
1199 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1200 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1203 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1206 memset(mini_ht,-1,sizeof(mini_ht));
1210 for(page=0;page<0x100000;page++) {
1211 if(tlb_LUT_r[page]) {
1212 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1213 if(!tlb_LUT_w[page]||!invalid_code[page])
1214 memory_map[page]|=0x40000000; // Write protect
1216 else memory_map[page]=-1;
1217 if(page==0x80000) page=0xC0000;
1223 // Add an entry to jump_out after making a link
1224 void add_link(u_int vaddr,void *src)
1226 u_int page=get_page(vaddr);
1227 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1228 ll_add(jump_out+page,vaddr,src);
1229 //int ptr=get_pointer(src);
1230 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1233 // If a code block was found to be unmodified (bit was set in
1234 // restore_candidate) and it remains unmodified (bit is clear
1235 // in invalid_code) then move the entries for that 4K page from
1236 // the dirty list to the clean list.
1237 void clean_blocks(u_int page)
1239 struct ll_entry *head;
1240 inv_debug("INV: clean_blocks page=%d\n",page);
1241 head=jump_dirty[page];
1243 if(!invalid_code[head->vaddr>>12]) {
1244 // Don't restore blocks which are about to expire from the cache
1245 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1247 if(verify_dirty((int)head->addr)) {
1248 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1251 get_bounds((int)head->addr,&start,&end);
1252 if(start-(u_int)rdram<0x800000) {
1253 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1254 inv|=invalid_code[i];
1257 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1258 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1259 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1260 if(addr<start||addr>=end) inv=1;
1262 else if((signed int)head->vaddr>=(signed int)0x80800000) {
1266 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1267 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1270 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1272 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1273 //printf("page=%x, addr=%x\n",page,head->vaddr);
1274 //assert(head->vaddr>>12==(page|0x80000));
1275 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1276 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1278 if(ht_bin[0]==head->vaddr) {
1279 ht_bin[1]=(int)clean_addr; // Replace existing entry
1281 if(ht_bin[2]==head->vaddr) {
1282 ht_bin[3]=(int)clean_addr; // Replace existing entry
1295 void mov_alloc(struct regstat *current,int i)
1297 // Note: Don't need to actually alloc the source registers
1298 if((~current->is32>>rs1[i])&1) {
1299 //alloc_reg64(current,i,rs1[i]);
1300 alloc_reg64(current,i,rt1[i]);
1301 current->is32&=~(1LL<<rt1[i]);
1303 //alloc_reg(current,i,rs1[i]);
1304 alloc_reg(current,i,rt1[i]);
1305 current->is32|=(1LL<<rt1[i]);
1307 clear_const(current,rs1[i]);
1308 clear_const(current,rt1[i]);
1309 dirty_reg(current,rt1[i]);
1312 void shiftimm_alloc(struct regstat *current,int i)
1314 clear_const(current,rs1[i]);
1315 clear_const(current,rt1[i]);
1316 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1319 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1321 alloc_reg(current,i,rt1[i]);
1322 current->is32|=1LL<<rt1[i];
1323 dirty_reg(current,rt1[i]);
1326 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1329 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1330 alloc_reg64(current,i,rt1[i]);
1331 current->is32&=~(1LL<<rt1[i]);
1332 dirty_reg(current,rt1[i]);
1335 if(opcode2[i]==0x3c) // DSLL32
1338 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1339 alloc_reg64(current,i,rt1[i]);
1340 current->is32&=~(1LL<<rt1[i]);
1341 dirty_reg(current,rt1[i]);
1344 if(opcode2[i]==0x3e) // DSRL32
1347 alloc_reg64(current,i,rs1[i]);
1349 alloc_reg64(current,i,rt1[i]);
1350 current->is32&=~(1LL<<rt1[i]);
1352 alloc_reg(current,i,rt1[i]);
1353 current->is32|=1LL<<rt1[i];
1355 dirty_reg(current,rt1[i]);
1358 if(opcode2[i]==0x3f) // DSRA32
1361 alloc_reg64(current,i,rs1[i]);
1362 alloc_reg(current,i,rt1[i]);
1363 current->is32|=1LL<<rt1[i];
1364 dirty_reg(current,rt1[i]);
1369 void shift_alloc(struct regstat *current,int i)
1372 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1374 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1375 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1376 alloc_reg(current,i,rt1[i]);
1377 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1378 current->is32|=1LL<<rt1[i];
1379 } else { // DSLLV/DSRLV/DSRAV
1380 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1381 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1382 alloc_reg64(current,i,rt1[i]);
1383 current->is32&=~(1LL<<rt1[i]);
1384 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1385 alloc_reg_temp(current,i,-1);
1387 clear_const(current,rs1[i]);
1388 clear_const(current,rs2[i]);
1389 clear_const(current,rt1[i]);
1390 dirty_reg(current,rt1[i]);
1394 void alu_alloc(struct regstat *current,int i)
1396 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1398 if(rs1[i]&&rs2[i]) {
1399 alloc_reg(current,i,rs1[i]);
1400 alloc_reg(current,i,rs2[i]);
1403 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1404 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1406 alloc_reg(current,i,rt1[i]);
1408 current->is32|=1LL<<rt1[i];
1410 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1412 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1414 alloc_reg64(current,i,rs1[i]);
1415 alloc_reg64(current,i,rs2[i]);
1416 alloc_reg(current,i,rt1[i]);
1418 alloc_reg(current,i,rs1[i]);
1419 alloc_reg(current,i,rs2[i]);
1420 alloc_reg(current,i,rt1[i]);
1423 current->is32|=1LL<<rt1[i];
1425 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1427 if(rs1[i]&&rs2[i]) {
1428 alloc_reg(current,i,rs1[i]);
1429 alloc_reg(current,i,rs2[i]);
1433 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1434 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1436 alloc_reg(current,i,rt1[i]);
1437 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1439 if(!((current->uu>>rt1[i])&1)) {
1440 alloc_reg64(current,i,rt1[i]);
1442 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1443 if(rs1[i]&&rs2[i]) {
1444 alloc_reg64(current,i,rs1[i]);
1445 alloc_reg64(current,i,rs2[i]);
1449 // Is is really worth it to keep 64-bit values in registers?
1451 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1452 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1456 current->is32&=~(1LL<<rt1[i]);
1458 current->is32|=1LL<<rt1[i];
1462 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1464 if(rs1[i]&&rs2[i]) {
1465 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1466 alloc_reg64(current,i,rs1[i]);
1467 alloc_reg64(current,i,rs2[i]);
1468 alloc_reg64(current,i,rt1[i]);
1470 alloc_reg(current,i,rs1[i]);
1471 alloc_reg(current,i,rs2[i]);
1472 alloc_reg(current,i,rt1[i]);
1476 alloc_reg(current,i,rt1[i]);
1477 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1478 // DADD used as move, or zeroing
1479 // If we have a 64-bit source, then make the target 64 bits too
1480 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1481 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1482 alloc_reg64(current,i,rt1[i]);
1483 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1484 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1485 alloc_reg64(current,i,rt1[i]);
1487 if(opcode2[i]>=0x2e&&rs2[i]) {
1488 // DSUB used as negation - 64-bit result
1489 // If we have a 32-bit register, extend it to 64 bits
1490 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1491 alloc_reg64(current,i,rt1[i]);
1495 if(rs1[i]&&rs2[i]) {
1496 current->is32&=~(1LL<<rt1[i]);
1498 current->is32&=~(1LL<<rt1[i]);
1499 if((current->is32>>rs1[i])&1)
1500 current->is32|=1LL<<rt1[i];
1502 current->is32&=~(1LL<<rt1[i]);
1503 if((current->is32>>rs2[i])&1)
1504 current->is32|=1LL<<rt1[i];
1506 current->is32|=1LL<<rt1[i];
1510 clear_const(current,rs1[i]);
1511 clear_const(current,rs2[i]);
1512 clear_const(current,rt1[i]);
1513 dirty_reg(current,rt1[i]);
1516 void imm16_alloc(struct regstat *current,int i)
1518 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1520 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1521 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1522 current->is32&=~(1LL<<rt1[i]);
1523 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1524 // TODO: Could preserve the 32-bit flag if the immediate is zero
1525 alloc_reg64(current,i,rt1[i]);
1526 alloc_reg64(current,i,rs1[i]);
1528 clear_const(current,rs1[i]);
1529 clear_const(current,rt1[i]);
1531 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1532 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1533 current->is32|=1LL<<rt1[i];
1534 clear_const(current,rs1[i]);
1535 clear_const(current,rt1[i]);
1537 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1538 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1539 if(rs1[i]!=rt1[i]) {
1540 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1541 alloc_reg64(current,i,rt1[i]);
1542 current->is32&=~(1LL<<rt1[i]);
1545 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1546 if(is_const(current,rs1[i])) {
1547 int v=get_const(current,rs1[i]);
1548 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1549 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1550 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1552 else clear_const(current,rt1[i]);
1554 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1555 if(is_const(current,rs1[i])) {
1556 int v=get_const(current,rs1[i]);
1557 set_const(current,rt1[i],v+imm[i]);
1559 else clear_const(current,rt1[i]);
1560 current->is32|=1LL<<rt1[i];
1563 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1564 current->is32|=1LL<<rt1[i];
1566 dirty_reg(current,rt1[i]);
1569 void load_alloc(struct regstat *current,int i)
1571 clear_const(current,rt1[i]);
1572 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1573 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1574 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1576 alloc_reg(current,i,rt1[i]);
1577 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1579 current->is32&=~(1LL<<rt1[i]);
1580 alloc_reg64(current,i,rt1[i]);
1582 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1584 current->is32&=~(1LL<<rt1[i]);
1585 alloc_reg64(current,i,rt1[i]);
1586 alloc_all(current,i);
1587 alloc_reg64(current,i,FTEMP);
1589 else current->is32|=1LL<<rt1[i];
1590 dirty_reg(current,rt1[i]);
1591 // If using TLB, need a register for pointer to the mapping table
1592 if(using_tlb) alloc_reg(current,i,TLREG);
1593 // LWL/LWR need a temporary register for the old value
1594 if(opcode[i]==0x22||opcode[i]==0x26)
1596 alloc_reg(current,i,FTEMP);
1597 alloc_reg_temp(current,i,-1);
1602 // Load to r0 (dummy load)
1603 // but we still need a register to calculate the address
1604 alloc_reg_temp(current,i,-1);
1608 void store_alloc(struct regstat *current,int i)
1610 clear_const(current,rs2[i]);
1611 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1612 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1613 alloc_reg(current,i,rs2[i]);
1614 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1615 alloc_reg64(current,i,rs2[i]);
1616 if(rs2[i]) alloc_reg(current,i,FTEMP);
1618 // If using TLB, need a register for pointer to the mapping table
1619 if(using_tlb) alloc_reg(current,i,TLREG);
1620 #if defined(HOST_IMM8)
1621 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1622 else alloc_reg(current,i,INVCP);
1624 if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR
1625 alloc_reg(current,i,FTEMP);
1627 // We need a temporary register for address generation
1628 alloc_reg_temp(current,i,-1);
1631 void c1ls_alloc(struct regstat *current,int i)
1633 //clear_const(current,rs1[i]); // FIXME
1634 clear_const(current,rt1[i]);
1635 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1636 alloc_reg(current,i,CSREG); // Status
1637 alloc_reg(current,i,FTEMP);
1638 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1639 alloc_reg64(current,i,FTEMP);
1641 // If using TLB, need a register for pointer to the mapping table
1642 if(using_tlb) alloc_reg(current,i,TLREG);
1643 #if defined(HOST_IMM8)
1644 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1645 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1646 alloc_reg(current,i,INVCP);
1648 // We need a temporary register for address generation
1649 alloc_reg_temp(current,i,-1);
1652 void c2ls_alloc(struct regstat *current,int i)
1654 clear_const(current,rt1[i]);
1655 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1656 alloc_reg(current,i,FTEMP);
1657 // If using TLB, need a register for pointer to the mapping table
1658 if(using_tlb) alloc_reg(current,i,TLREG);
1659 #if defined(HOST_IMM8)
1660 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1661 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1662 alloc_reg(current,i,INVCP);
1664 // We need a temporary register for address generation
1665 alloc_reg_temp(current,i,-1);
1668 #ifndef multdiv_alloc
1669 void multdiv_alloc(struct regstat *current,int i)
1676 // case 0x1D: DMULTU
1679 clear_const(current,rs1[i]);
1680 clear_const(current,rs2[i]);
1683 if((opcode2[i]&4)==0) // 32-bit
1685 current->u&=~(1LL<<HIREG);
1686 current->u&=~(1LL<<LOREG);
1687 alloc_reg(current,i,HIREG);
1688 alloc_reg(current,i,LOREG);
1689 alloc_reg(current,i,rs1[i]);
1690 alloc_reg(current,i,rs2[i]);
1691 current->is32|=1LL<<HIREG;
1692 current->is32|=1LL<<LOREG;
1693 dirty_reg(current,HIREG);
1694 dirty_reg(current,LOREG);
1698 current->u&=~(1LL<<HIREG);
1699 current->u&=~(1LL<<LOREG);
1700 current->uu&=~(1LL<<HIREG);
1701 current->uu&=~(1LL<<LOREG);
1702 alloc_reg64(current,i,HIREG);
1703 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1704 alloc_reg64(current,i,rs1[i]);
1705 alloc_reg64(current,i,rs2[i]);
1706 alloc_all(current,i);
1707 current->is32&=~(1LL<<HIREG);
1708 current->is32&=~(1LL<<LOREG);
1709 dirty_reg(current,HIREG);
1710 dirty_reg(current,LOREG);
1715 // Multiply by zero is zero.
1716 // MIPS does not have a divide by zero exception.
1717 // The result is undefined, we return zero.
1718 alloc_reg(current,i,HIREG);
1719 alloc_reg(current,i,LOREG);
1720 current->is32|=1LL<<HIREG;
1721 current->is32|=1LL<<LOREG;
1722 dirty_reg(current,HIREG);
1723 dirty_reg(current,LOREG);
1728 void cop0_alloc(struct regstat *current,int i)
1730 if(opcode2[i]==0) // MFC0
1733 clear_const(current,rt1[i]);
1734 alloc_all(current,i);
1735 alloc_reg(current,i,rt1[i]);
1736 current->is32|=1LL<<rt1[i];
1737 dirty_reg(current,rt1[i]);
1740 else if(opcode2[i]==4) // MTC0
1743 clear_const(current,rs1[i]);
1744 alloc_reg(current,i,rs1[i]);
1745 alloc_all(current,i);
1748 alloc_all(current,i); // FIXME: Keep r0
1750 alloc_reg(current,i,0);
1755 // TLBR/TLBWI/TLBWR/TLBP/ERET
1756 assert(opcode2[i]==0x10);
1757 alloc_all(current,i);
1761 void cop1_alloc(struct regstat *current,int i)
1763 alloc_reg(current,i,CSREG); // Load status
1764 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1767 clear_const(current,rt1[i]);
1769 alloc_reg64(current,i,rt1[i]); // DMFC1
1770 current->is32&=~(1LL<<rt1[i]);
1772 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1773 current->is32|=1LL<<rt1[i];
1775 dirty_reg(current,rt1[i]);
1776 alloc_reg_temp(current,i,-1);
1778 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1781 clear_const(current,rs1[i]);
1783 alloc_reg64(current,i,rs1[i]); // DMTC1
1785 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1786 alloc_reg_temp(current,i,-1);
1790 alloc_reg(current,i,0);
1791 alloc_reg_temp(current,i,-1);
1795 void fconv_alloc(struct regstat *current,int i)
1797 alloc_reg(current,i,CSREG); // Load status
1798 alloc_reg_temp(current,i,-1);
1800 void float_alloc(struct regstat *current,int i)
1802 alloc_reg(current,i,CSREG); // Load status
1803 alloc_reg_temp(current,i,-1);
1805 void c2op_alloc(struct regstat *current,int i)
1807 alloc_reg_temp(current,i,-1);
1809 void fcomp_alloc(struct regstat *current,int i)
1811 alloc_reg(current,i,CSREG); // Load status
1812 alloc_reg(current,i,FSREG); // Load flags
1813 dirty_reg(current,FSREG); // Flag will be modified
1814 alloc_reg_temp(current,i,-1);
1817 void syscall_alloc(struct regstat *current,int i)
1819 alloc_cc(current,i);
1820 dirty_reg(current,CCREG);
1821 alloc_all(current,i);
1825 void delayslot_alloc(struct regstat *current,int i)
1836 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1837 printf("Disabled speculative precompilation\n");
1841 imm16_alloc(current,i);
1845 load_alloc(current,i);
1849 store_alloc(current,i);
1852 alu_alloc(current,i);
1855 shift_alloc(current,i);
1858 multdiv_alloc(current,i);
1861 shiftimm_alloc(current,i);
1864 mov_alloc(current,i);
1867 cop0_alloc(current,i);
1871 cop1_alloc(current,i);
1874 c1ls_alloc(current,i);
1877 c2ls_alloc(current,i);
1880 fconv_alloc(current,i);
1883 float_alloc(current,i);
1886 fcomp_alloc(current,i);
1889 c2op_alloc(current,i);
1894 // Special case where a branch and delay slot span two pages in virtual memory
1895 static void pagespan_alloc(struct regstat *current,int i)
1898 current->wasconst=0;
1900 alloc_all(current,i);
1901 alloc_cc(current,i);
1902 dirty_reg(current,CCREG);
1903 if(opcode[i]==3) // JAL
1905 alloc_reg(current,i,31);
1906 dirty_reg(current,31);
1908 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1910 alloc_reg(current,i,rs1[i]);
1912 alloc_reg(current,i,31);
1913 dirty_reg(current,31);
1916 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1918 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1919 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1920 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1922 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1923 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1927 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1929 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1930 if(!((current->is32>>rs1[i])&1))
1932 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1936 if(opcode[i]==0x11) // BC1
1938 alloc_reg(current,i,FSREG);
1939 alloc_reg(current,i,CSREG);
1944 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1946 stubs[stubcount][0]=type;
1947 stubs[stubcount][1]=addr;
1948 stubs[stubcount][2]=retaddr;
1949 stubs[stubcount][3]=a;
1950 stubs[stubcount][4]=b;
1951 stubs[stubcount][5]=c;
1952 stubs[stubcount][6]=d;
1953 stubs[stubcount][7]=e;
1957 // Write out a single register
1958 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1961 for(hr=0;hr<HOST_REGS;hr++) {
1962 if(hr!=EXCLUDE_REG) {
1963 if((regmap[hr]&63)==r) {
1966 emit_storereg(r,hr);
1968 if((is32>>regmap[hr])&1) {
1969 emit_sarimm(hr,31,hr);
1970 emit_storereg(r|64,hr);
1974 emit_storereg(r|64,hr);
1984 //if(!tracedebug) return 0;
1987 for(i=0;i<2097152;i++) {
1988 unsigned int temp=sum;
1991 sum^=((u_int *)rdram)[i];
2000 sum^=((u_int *)reg)[i];
2008 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2010 #ifndef DISABLE_COP1
2013 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2023 void memdebug(int i)
2025 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2026 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2029 //if(Count>=-2084597794) {
2030 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2032 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2033 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2034 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2037 printf("TRACE: %x\n",(&i)[-1]);
2041 printf("TRACE: %x \n",(&j)[10]);
2042 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2046 //printf("TRACE: %x\n",(&i)[-1]);
2049 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2051 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2054 void alu_assemble(int i,struct regstat *i_regs)
2056 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2058 signed char s1,s2,t;
2059 t=get_reg(i_regs->regmap,rt1[i]);
2061 s1=get_reg(i_regs->regmap,rs1[i]);
2062 s2=get_reg(i_regs->regmap,rs2[i]);
2063 if(rs1[i]&&rs2[i]) {
2066 if(opcode2[i]&2) emit_sub(s1,s2,t);
2067 else emit_add(s1,s2,t);
2070 if(s1>=0) emit_mov(s1,t);
2071 else emit_loadreg(rs1[i],t);
2075 if(opcode2[i]&2) emit_neg(s2,t);
2076 else emit_mov(s2,t);
2079 emit_loadreg(rs2[i],t);
2080 if(opcode2[i]&2) emit_neg(t,t);
2083 else emit_zeroreg(t);
2087 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2089 signed char s1l,s2l,s1h,s2h,tl,th;
2090 tl=get_reg(i_regs->regmap,rt1[i]);
2091 th=get_reg(i_regs->regmap,rt1[i]|64);
2093 s1l=get_reg(i_regs->regmap,rs1[i]);
2094 s2l=get_reg(i_regs->regmap,rs2[i]);
2095 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2096 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2097 if(rs1[i]&&rs2[i]) {
2100 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2101 else emit_adds(s1l,s2l,tl);
2103 #ifdef INVERTED_CARRY
2104 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2106 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2108 else emit_add(s1h,s2h,th);
2112 if(s1l>=0) emit_mov(s1l,tl);
2113 else emit_loadreg(rs1[i],tl);
2115 if(s1h>=0) emit_mov(s1h,th);
2116 else emit_loadreg(rs1[i]|64,th);
2121 if(opcode2[i]&2) emit_negs(s2l,tl);
2122 else emit_mov(s2l,tl);
2125 emit_loadreg(rs2[i],tl);
2126 if(opcode2[i]&2) emit_negs(tl,tl);
2129 #ifdef INVERTED_CARRY
2130 if(s2h>=0) emit_mov(s2h,th);
2131 else emit_loadreg(rs2[i]|64,th);
2133 emit_adcimm(-1,th); // x86 has inverted carry flag
2138 if(s2h>=0) emit_rscimm(s2h,0,th);
2140 emit_loadreg(rs2[i]|64,th);
2141 emit_rscimm(th,0,th);
2144 if(s2h>=0) emit_mov(s2h,th);
2145 else emit_loadreg(rs2[i]|64,th);
2152 if(th>=0) emit_zeroreg(th);
2157 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2159 signed char s1l,s1h,s2l,s2h,t;
2160 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2162 t=get_reg(i_regs->regmap,rt1[i]);
2165 s1l=get_reg(i_regs->regmap,rs1[i]);
2166 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2167 s2l=get_reg(i_regs->regmap,rs2[i]);
2168 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2169 if(rs2[i]==0) // rx<r0
2172 if(opcode2[i]==0x2a) // SLT
2173 emit_shrimm(s1h,31,t);
2174 else // SLTU (unsigned can not be less than zero)
2177 else if(rs1[i]==0) // r0<rx
2180 if(opcode2[i]==0x2a) // SLT
2181 emit_set_gz64_32(s2h,s2l,t);
2182 else // SLTU (set if not zero)
2183 emit_set_nz64_32(s2h,s2l,t);
2186 assert(s1l>=0);assert(s1h>=0);
2187 assert(s2l>=0);assert(s2h>=0);
2188 if(opcode2[i]==0x2a) // SLT
2189 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2191 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2195 t=get_reg(i_regs->regmap,rt1[i]);
2198 s1l=get_reg(i_regs->regmap,rs1[i]);
2199 s2l=get_reg(i_regs->regmap,rs2[i]);
2200 if(rs2[i]==0) // rx<r0
2203 if(opcode2[i]==0x2a) // SLT
2204 emit_shrimm(s1l,31,t);
2205 else // SLTU (unsigned can not be less than zero)
2208 else if(rs1[i]==0) // r0<rx
2211 if(opcode2[i]==0x2a) // SLT
2212 emit_set_gz32(s2l,t);
2213 else // SLTU (set if not zero)
2214 emit_set_nz32(s2l,t);
2217 assert(s1l>=0);assert(s2l>=0);
2218 if(opcode2[i]==0x2a) // SLT
2219 emit_set_if_less32(s1l,s2l,t);
2221 emit_set_if_carry32(s1l,s2l,t);
2227 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2229 signed char s1l,s1h,s2l,s2h,th,tl;
2230 tl=get_reg(i_regs->regmap,rt1[i]);
2231 th=get_reg(i_regs->regmap,rt1[i]|64);
2232 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2236 s1l=get_reg(i_regs->regmap,rs1[i]);
2237 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2238 s2l=get_reg(i_regs->regmap,rs2[i]);
2239 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2240 if(rs1[i]&&rs2[i]) {
2241 assert(s1l>=0);assert(s1h>=0);
2242 assert(s2l>=0);assert(s2h>=0);
2243 if(opcode2[i]==0x24) { // AND
2244 emit_and(s1l,s2l,tl);
2245 emit_and(s1h,s2h,th);
2247 if(opcode2[i]==0x25) { // OR
2248 emit_or(s1l,s2l,tl);
2249 emit_or(s1h,s2h,th);
2251 if(opcode2[i]==0x26) { // XOR
2252 emit_xor(s1l,s2l,tl);
2253 emit_xor(s1h,s2h,th);
2255 if(opcode2[i]==0x27) { // NOR
2256 emit_or(s1l,s2l,tl);
2257 emit_or(s1h,s2h,th);
2264 if(opcode2[i]==0x24) { // AND
2268 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2270 if(s1l>=0) emit_mov(s1l,tl);
2271 else emit_loadreg(rs1[i],tl);
2272 if(s1h>=0) emit_mov(s1h,th);
2273 else emit_loadreg(rs1[i]|64,th);
2277 if(s2l>=0) emit_mov(s2l,tl);
2278 else emit_loadreg(rs2[i],tl);
2279 if(s2h>=0) emit_mov(s2h,th);
2280 else emit_loadreg(rs2[i]|64,th);
2287 if(opcode2[i]==0x27) { // NOR
2289 if(s1l>=0) emit_not(s1l,tl);
2291 emit_loadreg(rs1[i],tl);
2294 if(s1h>=0) emit_not(s1h,th);
2296 emit_loadreg(rs1[i]|64,th);
2302 if(s2l>=0) emit_not(s2l,tl);
2304 emit_loadreg(rs2[i],tl);
2307 if(s2h>=0) emit_not(s2h,th);
2309 emit_loadreg(rs2[i]|64,th);
2325 s1l=get_reg(i_regs->regmap,rs1[i]);
2326 s2l=get_reg(i_regs->regmap,rs2[i]);
2327 if(rs1[i]&&rs2[i]) {
2330 if(opcode2[i]==0x24) { // AND
2331 emit_and(s1l,s2l,tl);
2333 if(opcode2[i]==0x25) { // OR
2334 emit_or(s1l,s2l,tl);
2336 if(opcode2[i]==0x26) { // XOR
2337 emit_xor(s1l,s2l,tl);
2339 if(opcode2[i]==0x27) { // NOR
2340 emit_or(s1l,s2l,tl);
2346 if(opcode2[i]==0x24) { // AND
2349 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2351 if(s1l>=0) emit_mov(s1l,tl);
2352 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2356 if(s2l>=0) emit_mov(s2l,tl);
2357 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2359 else emit_zeroreg(tl);
2361 if(opcode2[i]==0x27) { // NOR
2363 if(s1l>=0) emit_not(s1l,tl);
2365 emit_loadreg(rs1[i],tl);
2371 if(s2l>=0) emit_not(s2l,tl);
2373 emit_loadreg(rs2[i],tl);
2377 else emit_movimm(-1,tl);
2386 void imm16_assemble(int i,struct regstat *i_regs)
2388 if (opcode[i]==0x0f) { // LUI
2391 t=get_reg(i_regs->regmap,rt1[i]);
2394 if(!((i_regs->isconst>>t)&1))
2395 emit_movimm(imm[i]<<16,t);
2399 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2402 t=get_reg(i_regs->regmap,rt1[i]);
2403 s=get_reg(i_regs->regmap,rs1[i]);
2408 if(!((i_regs->isconst>>t)&1)) {
2410 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2411 emit_addimm(t,imm[i],t);
2413 if(!((i_regs->wasconst>>s)&1))
2414 emit_addimm(s,imm[i],t);
2416 emit_movimm(constmap[i][s]+imm[i],t);
2422 if(!((i_regs->isconst>>t)&1))
2423 emit_movimm(imm[i],t);
2428 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2430 signed char sh,sl,th,tl;
2431 th=get_reg(i_regs->regmap,rt1[i]|64);
2432 tl=get_reg(i_regs->regmap,rt1[i]);
2433 sh=get_reg(i_regs->regmap,rs1[i]|64);
2434 sl=get_reg(i_regs->regmap,rs1[i]);
2440 emit_addimm64_32(sh,sl,imm[i],th,tl);
2443 emit_addimm(sl,imm[i],tl);
2446 emit_movimm(imm[i],tl);
2447 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2452 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2454 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2455 signed char sh,sl,t;
2456 t=get_reg(i_regs->regmap,rt1[i]);
2457 sh=get_reg(i_regs->regmap,rs1[i]|64);
2458 sl=get_reg(i_regs->regmap,rs1[i]);
2462 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2463 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2464 if(opcode[i]==0x0a) { // SLTI
2466 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2467 emit_slti32(t,imm[i],t);
2469 emit_slti32(sl,imm[i],t);
2474 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2475 emit_sltiu32(t,imm[i],t);
2477 emit_sltiu32(sl,imm[i],t);
2482 if(opcode[i]==0x0a) // SLTI
2483 emit_slti64_32(sh,sl,imm[i],t);
2485 emit_sltiu64_32(sh,sl,imm[i],t);
2488 // SLTI(U) with r0 is just stupid,
2489 // nonetheless examples can be found
2490 if(opcode[i]==0x0a) // SLTI
2491 if(0<imm[i]) emit_movimm(1,t);
2492 else emit_zeroreg(t);
2495 if(imm[i]) emit_movimm(1,t);
2496 else emit_zeroreg(t);
2502 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2504 signed char sh,sl,th,tl;
2505 th=get_reg(i_regs->regmap,rt1[i]|64);
2506 tl=get_reg(i_regs->regmap,rt1[i]);
2507 sh=get_reg(i_regs->regmap,rs1[i]|64);
2508 sl=get_reg(i_regs->regmap,rs1[i]);
2509 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2510 if(opcode[i]==0x0c) //ANDI
2514 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2515 emit_andimm(tl,imm[i],tl);
2517 if(!((i_regs->wasconst>>sl)&1))
2518 emit_andimm(sl,imm[i],tl);
2520 emit_movimm(constmap[i][sl]&imm[i],tl);
2525 if(th>=0) emit_zeroreg(th);
2531 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2535 emit_loadreg(rs1[i]|64,th);
2540 if(opcode[i]==0x0d) //ORI
2542 emit_orimm(tl,imm[i],tl);
2544 if(!((i_regs->wasconst>>sl)&1))
2545 emit_orimm(sl,imm[i],tl);
2547 emit_movimm(constmap[i][sl]|imm[i],tl);
2549 if(opcode[i]==0x0e) //XORI
2551 emit_xorimm(tl,imm[i],tl);
2553 if(!((i_regs->wasconst>>sl)&1))
2554 emit_xorimm(sl,imm[i],tl);
2556 emit_movimm(constmap[i][sl]^imm[i],tl);
2560 emit_movimm(imm[i],tl);
2561 if(th>=0) emit_zeroreg(th);
2569 void shiftimm_assemble(int i,struct regstat *i_regs)
2571 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2575 t=get_reg(i_regs->regmap,rt1[i]);
2576 s=get_reg(i_regs->regmap,rs1[i]);
2585 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2587 if(opcode2[i]==0) // SLL
2589 emit_shlimm(s<0?t:s,imm[i],t);
2591 if(opcode2[i]==2) // SRL
2593 emit_shrimm(s<0?t:s,imm[i],t);
2595 if(opcode2[i]==3) // SRA
2597 emit_sarimm(s<0?t:s,imm[i],t);
2601 if(s>=0 && s!=t) emit_mov(s,t);
2605 //emit_storereg(rt1[i],t); //DEBUG
2608 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2611 signed char sh,sl,th,tl;
2612 th=get_reg(i_regs->regmap,rt1[i]|64);
2613 tl=get_reg(i_regs->regmap,rt1[i]);
2614 sh=get_reg(i_regs->regmap,rs1[i]|64);
2615 sl=get_reg(i_regs->regmap,rs1[i]);
2620 if(th>=0) emit_zeroreg(th);
2627 if(opcode2[i]==0x38) // DSLL
2629 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2630 emit_shlimm(sl,imm[i],tl);
2632 if(opcode2[i]==0x3a) // DSRL
2634 emit_shrdimm(sl,sh,imm[i],tl);
2635 if(th>=0) emit_shrimm(sh,imm[i],th);
2637 if(opcode2[i]==0x3b) // DSRA
2639 emit_shrdimm(sl,sh,imm[i],tl);
2640 if(th>=0) emit_sarimm(sh,imm[i],th);
2644 if(sl!=tl) emit_mov(sl,tl);
2645 if(th>=0&&sh!=th) emit_mov(sh,th);
2651 if(opcode2[i]==0x3c) // DSLL32
2654 signed char sl,tl,th;
2655 tl=get_reg(i_regs->regmap,rt1[i]);
2656 th=get_reg(i_regs->regmap,rt1[i]|64);
2657 sl=get_reg(i_regs->regmap,rs1[i]);
2666 emit_shlimm(th,imm[i]&31,th);
2671 if(opcode2[i]==0x3e) // DSRL32
2674 signed char sh,tl,th;
2675 tl=get_reg(i_regs->regmap,rt1[i]);
2676 th=get_reg(i_regs->regmap,rt1[i]|64);
2677 sh=get_reg(i_regs->regmap,rs1[i]|64);
2681 if(th>=0) emit_zeroreg(th);
2684 emit_shrimm(tl,imm[i]&31,tl);
2689 if(opcode2[i]==0x3f) // DSRA32
2693 tl=get_reg(i_regs->regmap,rt1[i]);
2694 sh=get_reg(i_regs->regmap,rs1[i]|64);
2700 emit_sarimm(tl,imm[i]&31,tl);
2707 #ifndef shift_assemble
2708 void shift_assemble(int i,struct regstat *i_regs)
2710 printf("Need shift_assemble for this architecture.\n");
2715 void load_assemble(int i,struct regstat *i_regs)
2717 int s,th,tl,addr,map=-1;
2722 th=get_reg(i_regs->regmap,rt1[i]|64);
2723 tl=get_reg(i_regs->regmap,rt1[i]);
2724 s=get_reg(i_regs->regmap,rs1[i]);
2726 for(hr=0;hr<HOST_REGS;hr++) {
2727 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2729 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2731 c=(i_regs->wasconst>>s)&1;
2732 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2733 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2735 if(offset||s<0||c) addr=tl;
2737 //printf("load_assemble: c=%d\n",c);
2738 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2739 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2744 if(th>=0) reglist&=~(1<<th);
2747 //#define R29_HACK 1
2749 // Strmnnrmn's speed hack
2750 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2753 emit_cmpimm(addr,0x800000);
2755 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2756 // Hint to branch predictor that the branch is unlikely to be taken
2758 emit_jno_unlikely(0);
2766 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2767 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2768 map=get_reg(i_regs->regmap,TLREG);
2770 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2771 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2773 if (opcode[i]==0x20) { // LB
2775 #ifdef HOST_IMM_ADDR32
2777 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2781 //emit_xorimm(addr,3,tl);
2782 //gen_tlb_addr_r(tl,map);
2783 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2785 #ifdef BIG_ENDIAN_MIPS
2786 if(!c) emit_xorimm(addr,3,tl);
2787 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2789 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2790 else if (tl!=addr) emit_mov(addr,tl);
2792 emit_movsbl_indexed_tlb(x,tl,map,tl);
2795 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2798 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2800 if (opcode[i]==0x21) { // LH
2802 #ifdef HOST_IMM_ADDR32
2804 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2809 #ifdef BIG_ENDIAN_MIPS
2810 if(!c) emit_xorimm(addr,2,tl);
2811 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2813 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2814 else if (tl!=addr) emit_mov(addr,tl);
2817 //emit_movswl_indexed_tlb(x,tl,map,tl);
2820 gen_tlb_addr_r(tl,map);
2821 emit_movswl_indexed(x,tl,tl);
2823 emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2826 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2829 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2831 if (opcode[i]==0x23) { // LW
2833 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2834 #ifdef HOST_IMM_ADDR32
2836 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2839 emit_readword_indexed_tlb(0,addr,map,tl);
2841 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2844 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2846 if (opcode[i]==0x24) { // LBU
2848 #ifdef HOST_IMM_ADDR32
2850 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2854 //emit_xorimm(addr,3,tl);
2855 //gen_tlb_addr_r(tl,map);
2856 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2858 #ifdef BIG_ENDIAN_MIPS
2859 if(!c) emit_xorimm(addr,3,tl);
2860 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2862 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2863 else if (tl!=addr) emit_mov(addr,tl);
2865 emit_movzbl_indexed_tlb(x,tl,map,tl);
2868 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2871 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2873 if (opcode[i]==0x25) { // LHU
2875 #ifdef HOST_IMM_ADDR32
2877 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2882 #ifdef BIG_ENDIAN_MIPS
2883 if(!c) emit_xorimm(addr,2,tl);
2884 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2886 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2887 else if (tl!=addr) emit_mov(addr,tl);
2890 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2893 gen_tlb_addr_r(tl,map);
2894 emit_movzwl_indexed(x,tl,tl);
2896 emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2898 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2902 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2904 if (opcode[i]==0x27) { // LWU
2907 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2908 #ifdef HOST_IMM_ADDR32
2910 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2913 emit_readword_indexed_tlb(0,addr,map,tl);
2915 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2918 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2922 if (opcode[i]==0x37) { // LD
2924 //gen_tlb_addr_r(tl,map);
2925 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2926 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2927 #ifdef HOST_IMM_ADDR32
2929 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2932 emit_readdword_indexed_tlb(0,addr,map,th,tl);
2934 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2937 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2939 //emit_storereg(rt1[i],tl); // DEBUG
2941 //if(opcode[i]==0x23)
2942 //if(opcode[i]==0x24)
2943 //if(opcode[i]==0x23||opcode[i]==0x24)
2944 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2948 emit_readword((int)&last_count,ECX);
2950 if(get_reg(i_regs->regmap,CCREG)<0)
2951 emit_loadreg(CCREG,HOST_CCREG);
2952 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2953 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2954 emit_writeword(HOST_CCREG,(int)&Count);
2957 if(get_reg(i_regs->regmap,CCREG)<0)
2958 emit_loadreg(CCREG,0);
2960 emit_mov(HOST_CCREG,0);
2962 emit_addimm(0,2*ccadj[i],0);
2963 emit_writeword(0,(int)&Count);
2965 emit_call((int)memdebug);
2967 restore_regs(0x100f);
2971 #ifndef loadlr_assemble
2972 void loadlr_assemble(int i,struct regstat *i_regs)
2974 printf("Need loadlr_assemble for this architecture.\n");
2979 void store_assemble(int i,struct regstat *i_regs)
2984 int jaddr=0,jaddr2,type;
2985 int memtarget=0,c=0;
2986 int agr=AGEN1+(i&1);
2988 th=get_reg(i_regs->regmap,rs2[i]|64);
2989 tl=get_reg(i_regs->regmap,rs2[i]);
2990 s=get_reg(i_regs->regmap,rs1[i]);
2991 temp=get_reg(i_regs->regmap,agr);
2992 if(temp<0) temp=get_reg(i_regs->regmap,-1);
2995 c=(i_regs->wasconst>>s)&1;
2996 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2997 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3001 for(hr=0;hr<HOST_REGS;hr++) {
3002 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3004 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3005 if(offset||s<0||c) addr=temp;
3010 // Strmnnrmn's speed hack
3012 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3014 emit_cmpimm(addr,0x800000);
3015 #ifdef DESTRUCTIVE_SHIFT
3016 if(s==addr) emit_mov(s,temp);
3019 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3023 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3024 // Hint to branch predictor that the branch is unlikely to be taken
3026 emit_jno_unlikely(0);
3034 if (opcode[i]==0x28) x=3; // SB
3035 if (opcode[i]==0x29) x=2; // SH
3036 map=get_reg(i_regs->regmap,TLREG);
3038 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3039 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3042 if (opcode[i]==0x28) { // SB
3045 #ifdef BIG_ENDIAN_MIPS
3046 if(!c) emit_xorimm(addr,3,temp);
3047 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3049 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3050 else if (addr!=temp) emit_mov(addr,temp);
3052 //gen_tlb_addr_w(temp,map);
3053 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3054 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3058 if (opcode[i]==0x29) { // SH
3061 #ifdef BIG_ENDIAN_MIPS
3062 if(!c) emit_xorimm(addr,2,temp);
3063 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3065 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3066 else if (addr!=temp) emit_mov(addr,temp);
3069 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3072 gen_tlb_addr_w(temp,map);
3073 emit_writehword_indexed(tl,x,temp);
3075 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3079 if (opcode[i]==0x2B) { // SW
3081 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3082 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3085 if (opcode[i]==0x3F) { // SD
3089 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3090 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3091 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3094 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3095 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3096 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3101 if(!using_tlb&&(!c||memtarget))
3102 // addr could be a temp, make sure it survives STORE*_STUB
3105 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3106 } else if(!memtarget) {
3107 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3111 #ifdef DESTRUCTIVE_SHIFT
3112 // The x86 shift operation is 'destructive'; it overwrites the
3113 // source register, so we need to make a copy first and use that.
3116 #if defined(HOST_IMM8)
3117 int ir=get_reg(i_regs->regmap,INVCP);
3119 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3121 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3125 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3128 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3129 //if(opcode[i]==0x2B || opcode[i]==0x28)
3130 //if(opcode[i]==0x2B || opcode[i]==0x29)
3131 //if(opcode[i]==0x2B)
3132 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3136 emit_readword((int)&last_count,ECX);
3138 if(get_reg(i_regs->regmap,CCREG)<0)
3139 emit_loadreg(CCREG,HOST_CCREG);
3140 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3141 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3142 emit_writeword(HOST_CCREG,(int)&Count);
3145 if(get_reg(i_regs->regmap,CCREG)<0)
3146 emit_loadreg(CCREG,0);
3148 emit_mov(HOST_CCREG,0);
3150 emit_addimm(0,2*ccadj[i],0);
3151 emit_writeword(0,(int)&Count);
3153 emit_call((int)memdebug);
3155 restore_regs(0x100f);
3159 void storelr_assemble(int i,struct regstat *i_regs)
3166 int case1,case2,case3;
3167 int done0,done1,done2;
3170 th=get_reg(i_regs->regmap,rs2[i]|64);
3171 tl=get_reg(i_regs->regmap,rs2[i]);
3172 s=get_reg(i_regs->regmap,rs1[i]);
3173 temp=get_reg(i_regs->regmap,-1);
3176 c=(i_regs->isconst>>s)&1;
3177 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3178 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3181 for(hr=0;hr<HOST_REGS;hr++) {
3182 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3188 emit_cmpimm(s<0||offset?temp:s,0x800000);
3189 if(!offset&&s!=temp) emit_mov(s,temp);
3195 if(!memtarget||!rs1[i]) {
3200 if((u_int)rdram!=0x80000000)
3201 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3203 int map=get_reg(i_regs->regmap,TLREG);
3205 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3206 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3207 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3208 if(!jaddr&&!memtarget) {
3212 gen_tlb_addr_w(temp,map);
3215 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3216 temp2=get_reg(i_regs->regmap,FTEMP);
3217 if(!rs2[i]) temp2=th=tl;
3220 #ifndef BIG_ENDIAN_MIPS
3221 emit_xorimm(temp,3,temp);
3223 emit_testimm(temp,2);
3226 emit_testimm(temp,1);
3230 if (opcode[i]==0x2A) { // SWL
3231 emit_writeword_indexed(tl,0,temp);
3233 if (opcode[i]==0x2E) { // SWR
3234 emit_writebyte_indexed(tl,3,temp);
3236 if (opcode[i]==0x2C) { // SDL
3237 emit_writeword_indexed(th,0,temp);
3238 if(rs2[i]) emit_mov(tl,temp2);
3240 if (opcode[i]==0x2D) { // SDR
3241 emit_writebyte_indexed(tl,3,temp);
3242 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3247 set_jump_target(case1,(int)out);
3248 if (opcode[i]==0x2A) { // SWL
3249 // Write 3 msb into three least significant bytes
3250 if(rs2[i]) emit_rorimm(tl,8,tl);
3251 emit_writehword_indexed(tl,-1,temp);
3252 if(rs2[i]) emit_rorimm(tl,16,tl);
3253 emit_writebyte_indexed(tl,1,temp);
3254 if(rs2[i]) emit_rorimm(tl,8,tl);
3256 if (opcode[i]==0x2E) { // SWR
3257 // Write two lsb into two most significant bytes
3258 emit_writehword_indexed(tl,1,temp);
3260 if (opcode[i]==0x2C) { // SDL
3261 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3262 // Write 3 msb into three least significant bytes
3263 if(rs2[i]) emit_rorimm(th,8,th);
3264 emit_writehword_indexed(th,-1,temp);
3265 if(rs2[i]) emit_rorimm(th,16,th);
3266 emit_writebyte_indexed(th,1,temp);
3267 if(rs2[i]) emit_rorimm(th,8,th);
3269 if (opcode[i]==0x2D) { // SDR
3270 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3271 // Write two lsb into two most significant bytes
3272 emit_writehword_indexed(tl,1,temp);
3277 set_jump_target(case2,(int)out);
3278 emit_testimm(temp,1);
3281 if (opcode[i]==0x2A) { // SWL
3282 // Write two msb into two least significant bytes
3283 if(rs2[i]) emit_rorimm(tl,16,tl);
3284 emit_writehword_indexed(tl,-2,temp);
3285 if(rs2[i]) emit_rorimm(tl,16,tl);
3287 if (opcode[i]==0x2E) { // SWR
3288 // Write 3 lsb into three most significant bytes
3289 emit_writebyte_indexed(tl,-1,temp);
3290 if(rs2[i]) emit_rorimm(tl,8,tl);
3291 emit_writehword_indexed(tl,0,temp);
3292 if(rs2[i]) emit_rorimm(tl,24,tl);
3294 if (opcode[i]==0x2C) { // SDL
3295 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3296 // Write two msb into two least significant bytes
3297 if(rs2[i]) emit_rorimm(th,16,th);
3298 emit_writehword_indexed(th,-2,temp);
3299 if(rs2[i]) emit_rorimm(th,16,th);
3301 if (opcode[i]==0x2D) { // SDR
3302 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3303 // Write 3 lsb into three most significant bytes
3304 emit_writebyte_indexed(tl,-1,temp);
3305 if(rs2[i]) emit_rorimm(tl,8,tl);
3306 emit_writehword_indexed(tl,0,temp);
3307 if(rs2[i]) emit_rorimm(tl,24,tl);
3312 set_jump_target(case3,(int)out);
3313 if (opcode[i]==0x2A) { // SWL
3314 // Write msb into least significant byte
3315 if(rs2[i]) emit_rorimm(tl,24,tl);
3316 emit_writebyte_indexed(tl,-3,temp);
3317 if(rs2[i]) emit_rorimm(tl,8,tl);
3319 if (opcode[i]==0x2E) { // SWR
3320 // Write entire word
3321 emit_writeword_indexed(tl,-3,temp);
3323 if (opcode[i]==0x2C) { // SDL
3324 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3325 // Write msb into least significant byte
3326 if(rs2[i]) emit_rorimm(th,24,th);
3327 emit_writebyte_indexed(th,-3,temp);
3328 if(rs2[i]) emit_rorimm(th,8,th);
3330 if (opcode[i]==0x2D) { // SDR
3331 if(rs2[i]) emit_mov(th,temp2);
3332 // Write entire word
3333 emit_writeword_indexed(tl,-3,temp);
3335 set_jump_target(done0,(int)out);
3336 set_jump_target(done1,(int)out);
3337 set_jump_target(done2,(int)out);
3338 if (opcode[i]==0x2C) { // SDL
3339 emit_testimm(temp,4);
3342 emit_andimm(temp,~3,temp);
3343 emit_writeword_indexed(temp2,4,temp);
3344 set_jump_target(done0,(int)out);
3346 if (opcode[i]==0x2D) { // SDR
3347 emit_testimm(temp,4);
3350 emit_andimm(temp,~3,temp);
3351 emit_writeword_indexed(temp2,-4,temp);
3352 set_jump_target(done0,(int)out);
3355 add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist);
3358 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3359 #if defined(HOST_IMM8)
3360 int ir=get_reg(i_regs->regmap,INVCP);
3362 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3364 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3368 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3372 //save_regs(0x100f);