drc: merge Ari64's patch: 10_unnecessary_invalidate
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2  *   Mupen64plus - new_dynarec.c                                           *
3  *   Copyright (C) 2009-2010 Ari64                                         *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21 #include <stdlib.h>
22 #include <stdint.h> //include for uint64_t
23 #include <assert.h>
24
25 #include "emu_if.h" //emulator interface
26
27 #include <sys/mman.h>
28
29 #ifdef __i386__
30 #include "assem_x86.h"
31 #endif
32 #ifdef __x86_64__
33 #include "assem_x64.h"
34 #endif
35 #ifdef __arm__
36 #include "assem_arm.h"
37 #endif
38
39 #define MAXBLOCK 4096
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
42
43 struct regstat
44 {
45   signed char regmap_entry[HOST_REGS];
46   signed char regmap[HOST_REGS];
47   uint64_t was32;
48   uint64_t is32;
49   uint64_t wasdirty;
50   uint64_t dirty;
51   uint64_t u;
52   uint64_t uu;
53   u_int wasconst;
54   u_int isconst;
55   uint64_t constmap[HOST_REGS];
56 };
57
58 struct ll_entry
59 {
60   u_int vaddr;
61   u_int reg32;
62   void *addr;
63   struct ll_entry *next;
64 };
65
66   u_int start;
67   u_int *source;
68   u_int pagelimit;
69   char insn[MAXBLOCK][10];
70   u_char itype[MAXBLOCK];
71   u_char opcode[MAXBLOCK];
72   u_char opcode2[MAXBLOCK];
73   u_char bt[MAXBLOCK];
74   u_char rs1[MAXBLOCK];
75   u_char rs2[MAXBLOCK];
76   u_char rt1[MAXBLOCK];
77   u_char rt2[MAXBLOCK];
78   u_char us1[MAXBLOCK];
79   u_char us2[MAXBLOCK];
80   u_char dep1[MAXBLOCK];
81   u_char dep2[MAXBLOCK];
82   u_char lt1[MAXBLOCK];
83   int imm[MAXBLOCK];
84   u_int ba[MAXBLOCK];
85   char likely[MAXBLOCK];
86   char is_ds[MAXBLOCK];
87   char ooo[MAXBLOCK];
88   uint64_t unneeded_reg[MAXBLOCK];
89   uint64_t unneeded_reg_upper[MAXBLOCK];
90   uint64_t branch_unneeded_reg[MAXBLOCK];
91   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92   uint64_t p32[MAXBLOCK];
93   uint64_t pr32[MAXBLOCK];
94   signed char regmap_pre[MAXBLOCK][HOST_REGS];
95   signed char regmap[MAXBLOCK][HOST_REGS];
96   signed char regmap_entry[MAXBLOCK][HOST_REGS];
97   uint64_t constmap[MAXBLOCK][HOST_REGS];
98   struct regstat regs[MAXBLOCK];
99   struct regstat branch_regs[MAXBLOCK];
100   signed char minimum_free_regs[MAXBLOCK];
101   u_int needed_reg[MAXBLOCK];
102   uint64_t requires_32bit[MAXBLOCK];
103   u_int wont_dirty[MAXBLOCK];
104   u_int will_dirty[MAXBLOCK];
105   int ccadj[MAXBLOCK];
106   int slen;
107   u_int instr_addr[MAXBLOCK];
108   u_int link_addr[MAXBLOCK][3];
109   int linkcount;
110   u_int stubs[MAXBLOCK*3][8];
111   int stubcount;
112   u_int literals[1024][2];
113   int literalcount;
114   int is_delayslot;
115   int cop1_usable;
116   u_char *out;
117   struct ll_entry *jump_in[4096];
118   struct ll_entry *jump_out[4096];
119   struct ll_entry *jump_dirty[4096];
120   u_int hash_table[65536][4]  __attribute__((aligned(16)));
121   char shadow[1048576]  __attribute__((aligned(16)));
122   void *copy;
123   int expirep;
124   u_int using_tlb;
125   u_int stop_after_jal;
126   extern u_char restore_candidate[512];
127   extern int cycle_count;
128
129   /* registers that may be allocated */
130   /* 1-31 gpr */
131 #define HIREG 32 // hi
132 #define LOREG 33 // lo
133 #define FSREG 34 // FPU status (FCSR)
134 #define CSREG 35 // Coprocessor status
135 #define CCREG 36 // Cycle count
136 #define INVCP 37 // Pointer to invalid_code
137 #define TEMPREG 38
138 #define FTEMP 38 // FPU/LDL/LDR temporary register
139 #define PTEMP 39 // Prefetch temporary register
140 #define TLREG 40 // TLB mapping offset
141 #define RHASH 41 // Return address hash
142 #define RHTBL 42 // Return address hash table address
143 #define RTEMP 43 // JR/JALR address register
144 #define MAXREG 43
145 #define AGEN1 44 // Address generation temporary register
146 #define AGEN2 45 // Address generation temporary register
147 #define MGEN1 46 // Maptable address generation temporary register
148 #define MGEN2 47 // Maptable address generation temporary register
149 #define BTREG 48 // Branch target temporary register
150
151   /* instruction types */
152 #define NOP 0     // No operation
153 #define LOAD 1    // Load
154 #define STORE 2   // Store
155 #define LOADLR 3  // Unaligned load
156 #define STORELR 4 // Unaligned store
157 #define MOV 5     // Move 
158 #define ALU 6     // Arithmetic/logic
159 #define MULTDIV 7 // Multiply/divide
160 #define SHIFT 8   // Shift by register
161 #define SHIFTIMM 9// Shift by immediate
162 #define IMM16 10  // 16-bit immediate
163 #define RJUMP 11  // Unconditional jump to register
164 #define UJUMP 12  // Unconditional jump
165 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166 #define SJUMP 14  // Conditional branch (regimm format)
167 #define COP0 15   // Coprocessor 0
168 #define COP1 16   // Coprocessor 1
169 #define C1LS 17   // Coprocessor 1 load/store
170 #define FJUMP 18  // Conditional branch (floating point)
171 #define FLOAT 19  // Floating point unit
172 #define FCONV 20  // Convert integer to float
173 #define FCOMP 21  // Floating point compare (sets FSREG)
174 #define SYSCALL 22// SYSCALL
175 #define OTHER 23  // Other
176 #define SPAN 24   // Branch/delay slot spans 2 pages
177 #define NI 25     // Not implemented
178 #define HLECALL 26// PCSX fake opcodes for HLE
179 #define COP2 27   // Coprocessor 2 move
180 #define C2LS 28   // Coprocessor 2 load/store
181 #define C2OP 29   // Coprocessor 2 operation
182 #define INTCALL 30// Call interpreter to handle rare corner cases
183
184   /* stubs */
185 #define CC_STUB 1
186 #define FP_STUB 2
187 #define LOADB_STUB 3
188 #define LOADH_STUB 4
189 #define LOADW_STUB 5
190 #define LOADD_STUB 6
191 #define LOADBU_STUB 7
192 #define LOADHU_STUB 8
193 #define STOREB_STUB 9
194 #define STOREH_STUB 10
195 #define STOREW_STUB 11
196 #define STORED_STUB 12
197 #define STORELR_STUB 13
198 #define INVCODE_STUB 14
199
200   /* branch codes */
201 #define TAKEN 1
202 #define NOTTAKEN 2
203 #define NULLDS 3
204
205 // asm linkage
206 int new_recompile_block(int addr);
207 void *get_addr_ht(u_int vaddr);
208 void invalidate_block(u_int block);
209 void invalidate_addr(u_int addr);
210 void remove_hash(int vaddr);
211 void jump_vaddr();
212 void dyna_linker();
213 void dyna_linker_ds();
214 void verify_code();
215 void verify_code_vm();
216 void verify_code_ds();
217 void cc_interrupt();
218 void fp_exception();
219 void fp_exception_ds();
220 void jump_syscall();
221 void jump_syscall_hle();
222 void jump_eret();
223 void jump_hlecall();
224 void jump_intcall();
225 void new_dyna_leave();
226
227 // TLB
228 void TLBWI_new();
229 void TLBWR_new();
230 void read_nomem_new();
231 void read_nomemb_new();
232 void read_nomemh_new();
233 void read_nomemd_new();
234 void write_nomem_new();
235 void write_nomemb_new();
236 void write_nomemh_new();
237 void write_nomemd_new();
238 void write_rdram_new();
239 void write_rdramb_new();
240 void write_rdramh_new();
241 void write_rdramd_new();
242 extern u_int memory_map[1048576];
243
244 // Needed by assembler
245 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
246 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
247 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
248 void load_all_regs(signed char i_regmap[]);
249 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
250 void load_regs_entry(int t);
251 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
252
253 int tracedebug=0;
254
255 //#define DEBUG_CYCLE_COUNT 1
256
257 void nullf() {}
258 //#define assem_debug printf
259 //#define inv_debug printf
260 #define assem_debug nullf
261 #define inv_debug nullf
262
263 static void tlb_hacks()
264 {
265 #ifndef DISABLE_TLB
266   // Goldeneye hack
267   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
268   {
269     u_int addr;
270     int n;
271     switch (ROM_HEADER->Country_code&0xFF) 
272     {
273       case 0x45: // U
274         addr=0x34b30;
275         break;                   
276       case 0x4A: // J 
277         addr=0x34b70;    
278         break;    
279       case 0x50: // E 
280         addr=0x329f0;
281         break;                        
282       default: 
283         // Unknown country code
284         addr=0;
285         break;
286     }
287     u_int rom_addr=(u_int)rom;
288     #ifdef ROM_COPY
289     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
290     // in the lower 4G of memory to use this hack.  Copy it if necessary.
291     if((void *)rom>(void *)0xffffffff) {
292       munmap(ROM_COPY, 67108864);
293       if(mmap(ROM_COPY, 12582912,
294               PROT_READ | PROT_WRITE,
295               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
296               -1, 0) <= 0) {printf("mmap() failed\n");}
297       memcpy(ROM_COPY,rom,12582912);
298       rom_addr=(u_int)ROM_COPY;
299     }
300     #endif
301     if(addr) {
302       for(n=0x7F000;n<0x80000;n++) {
303         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
304       }
305     }
306   }
307 #endif
308 }
309
310 static u_int get_page(u_int vaddr)
311 {
312 #ifndef PCSX
313   u_int page=(vaddr^0x80000000)>>12;
314 #else
315   u_int page=vaddr&~0xe0000000;
316   if (page < 0x1000000)
317     page &= ~0x0e00000; // RAM mirrors
318   page>>=12;
319 #endif
320 #ifndef DISABLE_TLB
321   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
322 #endif
323   if(page>2048) page=2048+(page&2047);
324   return page;
325 }
326
327 static u_int get_vpage(u_int vaddr)
328 {
329   u_int vpage=(vaddr^0x80000000)>>12;
330 #ifndef DISABLE_TLB
331   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
332 #endif
333   if(vpage>2048) vpage=2048+(vpage&2047);
334   return vpage;
335 }
336
337 // Get address from virtual address
338 // This is called from the recompiled JR/JALR instructions
339 void *get_addr(u_int vaddr)
340 {
341   u_int page=get_page(vaddr);
342   u_int vpage=get_vpage(vaddr);
343   struct ll_entry *head;
344   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
345   head=jump_in[page];
346   while(head!=NULL) {
347     if(head->vaddr==vaddr&&head->reg32==0) {
348   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
349       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
350       ht_bin[3]=ht_bin[1];
351       ht_bin[2]=ht_bin[0];
352       ht_bin[1]=(int)head->addr;
353       ht_bin[0]=vaddr;
354       return head->addr;
355     }
356     head=head->next;
357   }
358   head=jump_dirty[vpage];
359   while(head!=NULL) {
360     if(head->vaddr==vaddr&&head->reg32==0) {
361       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
362       // Don't restore blocks which are about to expire from the cache
363       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
364       if(verify_dirty(head->addr)) {
365         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
366         invalid_code[vaddr>>12]=0;
367         memory_map[vaddr>>12]|=0x40000000;
368         if(vpage<2048) {
369 #ifndef DISABLE_TLB
370           if(tlb_LUT_r[vaddr>>12]) {
371             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
372             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
373           }
374 #endif
375           restore_candidate[vpage>>3]|=1<<(vpage&7);
376         }
377         else restore_candidate[page>>3]|=1<<(page&7);
378         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
379         if(ht_bin[0]==vaddr) {
380           ht_bin[1]=(int)head->addr; // Replace existing entry
381         }
382         else
383         {
384           ht_bin[3]=ht_bin[1];
385           ht_bin[2]=ht_bin[0];
386           ht_bin[1]=(int)head->addr;
387           ht_bin[0]=vaddr;
388         }
389         return head->addr;
390       }
391     }
392     head=head->next;
393   }
394   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
395   int r=new_recompile_block(vaddr);
396   if(r==0) return get_addr(vaddr);
397   // Execute in unmapped page, generate pagefault execption
398   Status|=2;
399   Cause=(vaddr<<31)|0x8;
400   EPC=(vaddr&1)?vaddr-5:vaddr;
401   BadVAddr=(vaddr&~1);
402   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
403   EntryHi=BadVAddr&0xFFFFE000;
404   return get_addr_ht(0x80000000);
405 }
406 // Look up address in hash table first
407 void *get_addr_ht(u_int vaddr)
408 {
409   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
410   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
411   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
412   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
413   return get_addr(vaddr);
414 }
415
416 void *get_addr_32(u_int vaddr,u_int flags)
417 {
418 #ifdef FORCE32
419   return get_addr(vaddr);
420 #else
421   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
422   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
423   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
424   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
425   u_int page=get_page(vaddr);
426   u_int vpage=get_vpage(vaddr);
427   struct ll_entry *head;
428   head=jump_in[page];
429   while(head!=NULL) {
430     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
431       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
432       if(head->reg32==0) {
433         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
434         if(ht_bin[0]==-1) {
435           ht_bin[1]=(int)head->addr;
436           ht_bin[0]=vaddr;
437         }else if(ht_bin[2]==-1) {
438           ht_bin[3]=(int)head->addr;
439           ht_bin[2]=vaddr;
440         }
441         //ht_bin[3]=ht_bin[1];
442         //ht_bin[2]=ht_bin[0];
443         //ht_bin[1]=(int)head->addr;
444         //ht_bin[0]=vaddr;
445       }
446       return head->addr;
447     }
448     head=head->next;
449   }
450   head=jump_dirty[vpage];
451   while(head!=NULL) {
452     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
453       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
454       // Don't restore blocks which are about to expire from the cache
455       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
456       if(verify_dirty(head->addr)) {
457         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
458         invalid_code[vaddr>>12]=0;
459         memory_map[vaddr>>12]|=0x40000000;
460         if(vpage<2048) {
461 #ifndef DISABLE_TLB
462           if(tlb_LUT_r[vaddr>>12]) {
463             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
464             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
465           }
466 #endif
467           restore_candidate[vpage>>3]|=1<<(vpage&7);
468         }
469         else restore_candidate[page>>3]|=1<<(page&7);
470         if(head->reg32==0) {
471           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
472           if(ht_bin[0]==-1) {
473             ht_bin[1]=(int)head->addr;
474             ht_bin[0]=vaddr;
475           }else if(ht_bin[2]==-1) {
476             ht_bin[3]=(int)head->addr;
477             ht_bin[2]=vaddr;
478           }
479           //ht_bin[3]=ht_bin[1];
480           //ht_bin[2]=ht_bin[0];
481           //ht_bin[1]=(int)head->addr;
482           //ht_bin[0]=vaddr;
483         }
484         return head->addr;
485       }
486     }
487     head=head->next;
488   }
489   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
490   int r=new_recompile_block(vaddr);
491   if(r==0) return get_addr(vaddr);
492   // Execute in unmapped page, generate pagefault execption
493   Status|=2;
494   Cause=(vaddr<<31)|0x8;
495   EPC=(vaddr&1)?vaddr-5:vaddr;
496   BadVAddr=(vaddr&~1);
497   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
498   EntryHi=BadVAddr&0xFFFFE000;
499   return get_addr_ht(0x80000000);
500 #endif
501 }
502
503 void clear_all_regs(signed char regmap[])
504 {
505   int hr;
506   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
507 }
508
509 signed char get_reg(signed char regmap[],int r)
510 {
511   int hr;
512   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
513   return -1;
514 }
515
516 // Find a register that is available for two consecutive cycles
517 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
518 {
519   int hr;
520   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
521   return -1;
522 }
523
524 int count_free_regs(signed char regmap[])
525 {
526   int count=0;
527   int hr;
528   for(hr=0;hr<HOST_REGS;hr++)
529   {
530     if(hr!=EXCLUDE_REG) {
531       if(regmap[hr]<0) count++;
532     }
533   }
534   return count;
535 }
536
537 void dirty_reg(struct regstat *cur,signed char reg)
538 {
539   int hr;
540   if(!reg) return;
541   for (hr=0;hr<HOST_REGS;hr++) {
542     if((cur->regmap[hr]&63)==reg) {
543       cur->dirty|=1<<hr;
544     }
545   }
546 }
547
548 // If we dirty the lower half of a 64 bit register which is now being
549 // sign-extended, we need to dump the upper half.
550 // Note: Do this only after completion of the instruction, because
551 // some instructions may need to read the full 64-bit value even if
552 // overwriting it (eg SLTI, DSRA32).
553 static void flush_dirty_uppers(struct regstat *cur)
554 {
555   int hr,reg;
556   for (hr=0;hr<HOST_REGS;hr++) {
557     if((cur->dirty>>hr)&1) {
558       reg=cur->regmap[hr];
559       if(reg>=64) 
560         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
561     }
562   }
563 }
564
565 void set_const(struct regstat *cur,signed char reg,uint64_t value)
566 {
567   int hr;
568   if(!reg) return;
569   for (hr=0;hr<HOST_REGS;hr++) {
570     if(cur->regmap[hr]==reg) {
571       cur->isconst|=1<<hr;
572       cur->constmap[hr]=value;
573     }
574     else if((cur->regmap[hr]^64)==reg) {
575       cur->isconst|=1<<hr;
576       cur->constmap[hr]=value>>32;
577     }
578   }
579 }
580
581 void clear_const(struct regstat *cur,signed char reg)
582 {
583   int hr;
584   if(!reg) return;
585   for (hr=0;hr<HOST_REGS;hr++) {
586     if((cur->regmap[hr]&63)==reg) {
587       cur->isconst&=~(1<<hr);
588     }
589   }
590 }
591
592 int is_const(struct regstat *cur,signed char reg)
593 {
594   int hr;
595   if(!reg) return 1;
596   for (hr=0;hr<HOST_REGS;hr++) {
597     if((cur->regmap[hr]&63)==reg) {
598       return (cur->isconst>>hr)&1;
599     }
600   }
601   return 0;
602 }
603 uint64_t get_const(struct regstat *cur,signed char reg)
604 {
605   int hr;
606   if(!reg) return 0;
607   for (hr=0;hr<HOST_REGS;hr++) {
608     if(cur->regmap[hr]==reg) {
609       return cur->constmap[hr];
610     }
611   }
612   printf("Unknown constant in r%d\n",reg);
613   exit(1);
614 }
615
616 // Least soon needed registers
617 // Look at the next ten instructions and see which registers
618 // will be used.  Try not to reallocate these.
619 void lsn(u_char hsn[], int i, int *preferred_reg)
620 {
621   int j;
622   int b=-1;
623   for(j=0;j<9;j++)
624   {
625     if(i+j>=slen) {
626       j=slen-i-1;
627       break;
628     }
629     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
630     {
631       // Don't go past an unconditonal jump
632       j++;
633       break;
634     }
635   }
636   for(;j>=0;j--)
637   {
638     if(rs1[i+j]) hsn[rs1[i+j]]=j;
639     if(rs2[i+j]) hsn[rs2[i+j]]=j;
640     if(rt1[i+j]) hsn[rt1[i+j]]=j;
641     if(rt2[i+j]) hsn[rt2[i+j]]=j;
642     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
643       // Stores can allocate zero
644       hsn[rs1[i+j]]=j;
645       hsn[rs2[i+j]]=j;
646     }
647     // On some architectures stores need invc_ptr
648     #if defined(HOST_IMM8)
649     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
650       hsn[INVCP]=j;
651     }
652     #endif
653     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
654     {
655       hsn[CCREG]=j;
656       b=j;
657     }
658   }
659   if(b>=0)
660   {
661     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
662     {
663       // Follow first branch
664       int t=(ba[i+b]-start)>>2;
665       j=7-b;if(t+j>=slen) j=slen-t-1;
666       for(;j>=0;j--)
667       {
668         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
669         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
670         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
671         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
672       }
673     }
674     // TODO: preferred register based on backward branch
675   }
676   // Delay slot should preferably not overwrite branch conditions or cycle count
677   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
678     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
679     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
680     hsn[CCREG]=1;
681     // ...or hash tables
682     hsn[RHASH]=1;
683     hsn[RHTBL]=1;
684   }
685   // Coprocessor load/store needs FTEMP, even if not declared
686   if(itype[i]==C1LS||itype[i]==C2LS) {
687     hsn[FTEMP]=0;
688   }
689   // Load L/R also uses FTEMP as a temporary register
690   if(itype[i]==LOADLR) {
691     hsn[FTEMP]=0;
692   }
693   // Also SWL/SWR/SDL/SDR
694   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
695     hsn[FTEMP]=0;
696   }
697   // Don't remove the TLB registers either
698   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
699     hsn[TLREG]=0;
700   }
701   // Don't remove the miniht registers
702   if(itype[i]==UJUMP||itype[i]==RJUMP)
703   {
704     hsn[RHASH]=0;
705     hsn[RHTBL]=0;
706   }
707 }
708
709 // We only want to allocate registers if we're going to use them again soon
710 int needed_again(int r, int i)
711 {
712   int j;
713   int b=-1;
714   int rn=10;
715   int hr;
716   u_char hsn[MAXREG+1];
717   int preferred_reg;
718   
719   memset(hsn,10,sizeof(hsn));
720   lsn(hsn,i,&preferred_reg);
721   
722   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
723   {
724     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
725       return 0; // Don't need any registers if exiting the block
726   }
727   for(j=0;j<9;j++)
728   {
729     if(i+j>=slen) {
730       j=slen-i-1;
731       break;
732     }
733     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
734     {
735       // Don't go past an unconditonal jump
736       j++;
737       break;
738     }
739     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
740     {
741       break;
742     }
743   }
744   for(;j>=1;j--)
745   {
746     if(rs1[i+j]==r) rn=j;
747     if(rs2[i+j]==r) rn=j;
748     if((unneeded_reg[i+j]>>r)&1) rn=10;
749     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
750     {
751       b=j;
752     }
753   }
754   /*
755   if(b>=0)
756   {
757     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
758     {
759       // Follow first branch
760       int o=rn;
761       int t=(ba[i+b]-start)>>2;
762       j=7-b;if(t+j>=slen) j=slen-t-1;
763       for(;j>=0;j--)
764       {
765         if(!((unneeded_reg[t+j]>>r)&1)) {
766           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
767           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
768         }
769         else rn=o;
770       }
771     }
772   }*/
773   for(hr=0;hr<HOST_REGS;hr++) {
774     if(hr!=EXCLUDE_REG) {
775       if(rn<hsn[hr]) return 1;
776     }
777   }
778   return 0;
779 }
780
781 // Try to match register allocations at the end of a loop with those
782 // at the beginning
783 int loop_reg(int i, int r, int hr)
784 {
785   int j,k;
786   for(j=0;j<9;j++)
787   {
788     if(i+j>=slen) {
789       j=slen-i-1;
790       break;
791     }
792     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
793     {
794       // Don't go past an unconditonal jump
795       j++;
796       break;
797     }
798   }
799   k=0;
800   if(i>0){
801     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
802       k--;
803   }
804   for(;k<j;k++)
805   {
806     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
807     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
808     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
809     {
810       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
811       {
812         int t=(ba[i+k]-start)>>2;
813         int reg=get_reg(regs[t].regmap_entry,r);
814         if(reg>=0) return reg;
815         //reg=get_reg(regs[t+1].regmap_entry,r);
816         //if(reg>=0) return reg;
817       }
818     }
819   }
820   return hr;
821 }
822
823
824 // Allocate every register, preserving source/target regs
825 void alloc_all(struct regstat *cur,int i)
826 {
827   int hr;
828   
829   for(hr=0;hr<HOST_REGS;hr++) {
830     if(hr!=EXCLUDE_REG) {
831       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
832          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
833       {
834         cur->regmap[hr]=-1;
835         cur->dirty&=~(1<<hr);
836       }
837       // Don't need zeros
838       if((cur->regmap[hr]&63)==0)
839       {
840         cur->regmap[hr]=-1;
841         cur->dirty&=~(1<<hr);
842       }
843     }
844   }
845 }
846
847
848 void div64(int64_t dividend,int64_t divisor)
849 {
850   lo=dividend/divisor;
851   hi=dividend%divisor;
852   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
853   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
854 }
855 void divu64(uint64_t dividend,uint64_t divisor)
856 {
857   lo=dividend/divisor;
858   hi=dividend%divisor;
859   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
860   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
861 }
862
863 void mult64(uint64_t m1,uint64_t m2)
864 {
865    unsigned long long int op1, op2, op3, op4;
866    unsigned long long int result1, result2, result3, result4;
867    unsigned long long int temp1, temp2, temp3, temp4;
868    int sign = 0;
869    
870    if (m1 < 0)
871      {
872     op2 = -m1;
873     sign = 1 - sign;
874      }
875    else op2 = m1;
876    if (m2 < 0)
877      {
878     op4 = -m2;
879     sign = 1 - sign;
880      }
881    else op4 = m2;
882    
883    op1 = op2 & 0xFFFFFFFF;
884    op2 = (op2 >> 32) & 0xFFFFFFFF;
885    op3 = op4 & 0xFFFFFFFF;
886    op4 = (op4 >> 32) & 0xFFFFFFFF;
887    
888    temp1 = op1 * op3;
889    temp2 = (temp1 >> 32) + op1 * op4;
890    temp3 = op2 * op3;
891    temp4 = (temp3 >> 32) + op2 * op4;
892    
893    result1 = temp1 & 0xFFFFFFFF;
894    result2 = temp2 + (temp3 & 0xFFFFFFFF);
895    result3 = (result2 >> 32) + temp4;
896    result4 = (result3 >> 32);
897    
898    lo = result1 | (result2 << 32);
899    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
900    if (sign)
901      {
902     hi = ~hi;
903     if (!lo) hi++;
904     else lo = ~lo + 1;
905      }
906 }
907
908 void multu64(uint64_t m1,uint64_t m2)
909 {
910    unsigned long long int op1, op2, op3, op4;
911    unsigned long long int result1, result2, result3, result4;
912    unsigned long long int temp1, temp2, temp3, temp4;
913    
914    op1 = m1 & 0xFFFFFFFF;
915    op2 = (m1 >> 32) & 0xFFFFFFFF;
916    op3 = m2 & 0xFFFFFFFF;
917    op4 = (m2 >> 32) & 0xFFFFFFFF;
918    
919    temp1 = op1 * op3;
920    temp2 = (temp1 >> 32) + op1 * op4;
921    temp3 = op2 * op3;
922    temp4 = (temp3 >> 32) + op2 * op4;
923    
924    result1 = temp1 & 0xFFFFFFFF;
925    result2 = temp2 + (temp3 & 0xFFFFFFFF);
926    result3 = (result2 >> 32) + temp4;
927    result4 = (result3 >> 32);
928    
929    lo = result1 | (result2 << 32);
930    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
931    
932   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
933   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
934 }
935
936 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
937 {
938   if(bits) {
939     original<<=64-bits;
940     original>>=64-bits;
941     loaded<<=bits;
942     original|=loaded;
943   }
944   else original=loaded;
945   return original;
946 }
947 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
948 {
949   if(bits^56) {
950     original>>=64-(bits^56);
951     original<<=64-(bits^56);
952     loaded>>=bits^56;
953     original|=loaded;
954   }
955   else original=loaded;
956   return original;
957 }
958
959 #ifdef __i386__
960 #include "assem_x86.c"
961 #endif
962 #ifdef __x86_64__
963 #include "assem_x64.c"
964 #endif
965 #ifdef __arm__
966 #include "assem_arm.c"
967 #endif
968
969 // Add virtual address mapping to linked list
970 void ll_add(struct ll_entry **head,int vaddr,void *addr)
971 {
972   struct ll_entry *new_entry;
973   new_entry=malloc(sizeof(struct ll_entry));
974   assert(new_entry!=NULL);
975   new_entry->vaddr=vaddr;
976   new_entry->reg32=0;
977   new_entry->addr=addr;
978   new_entry->next=*head;
979   *head=new_entry;
980 }
981
982 // Add virtual address mapping for 32-bit compiled block
983 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
984 {
985   ll_add(head,vaddr,addr);
986 #ifndef FORCE32
987   (*head)->reg32=reg32;
988 #endif
989 }
990
991 // Check if an address is already compiled
992 // but don't return addresses which are about to expire from the cache
993 void *check_addr(u_int vaddr)
994 {
995   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
996   if(ht_bin[0]==vaddr) {
997     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
998       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
999   }
1000   if(ht_bin[2]==vaddr) {
1001     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1002       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1003   }
1004   u_int page=get_page(vaddr);
1005   struct ll_entry *head;
1006   head=jump_in[page];
1007   while(head!=NULL) {
1008     if(head->vaddr==vaddr&&head->reg32==0) {
1009       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1010         // Update existing entry with current address
1011         if(ht_bin[0]==vaddr) {
1012           ht_bin[1]=(int)head->addr;
1013           return head->addr;
1014         }
1015         if(ht_bin[2]==vaddr) {
1016           ht_bin[3]=(int)head->addr;
1017           return head->addr;
1018         }
1019         // Insert into hash table with low priority.
1020         // Don't evict existing entries, as they are probably
1021         // addresses that are being accessed frequently.
1022         if(ht_bin[0]==-1) {
1023           ht_bin[1]=(int)head->addr;
1024           ht_bin[0]=vaddr;
1025         }else if(ht_bin[2]==-1) {
1026           ht_bin[3]=(int)head->addr;
1027           ht_bin[2]=vaddr;
1028         }
1029         return head->addr;
1030       }
1031     }
1032     head=head->next;
1033   }
1034   return 0;
1035 }
1036
1037 void remove_hash(int vaddr)
1038 {
1039   //printf("remove hash: %x\n",vaddr);
1040   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1041   if(ht_bin[2]==vaddr) {
1042     ht_bin[2]=ht_bin[3]=-1;
1043   }
1044   if(ht_bin[0]==vaddr) {
1045     ht_bin[0]=ht_bin[2];
1046     ht_bin[1]=ht_bin[3];
1047     ht_bin[2]=ht_bin[3]=-1;
1048   }
1049 }
1050
1051 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1052 {
1053   struct ll_entry *next;
1054   while(*head) {
1055     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) || 
1056        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1057     {
1058       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1059       remove_hash((*head)->vaddr);
1060       next=(*head)->next;
1061       free(*head);
1062       *head=next;
1063     }
1064     else
1065     {
1066       head=&((*head)->next);
1067     }
1068   }
1069 }
1070
1071 // Remove all entries from linked list
1072 void ll_clear(struct ll_entry **head)
1073 {
1074   struct ll_entry *cur;
1075   struct ll_entry *next;
1076   if(cur=*head) {
1077     *head=0;
1078     while(cur) {
1079       next=cur->next;
1080       free(cur);
1081       cur=next;
1082     }
1083   }
1084 }
1085
1086 // Dereference the pointers and remove if it matches
1087 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1088 {
1089   while(head) {
1090     int ptr=get_pointer(head->addr);
1091     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1092     if(((ptr>>shift)==(addr>>shift)) ||
1093        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1094     {
1095       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1096       u_int host_addr=(u_int)kill_pointer(head->addr);
1097       #ifdef __arm__
1098         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1099       #endif
1100     }
1101     head=head->next;
1102   }
1103 }
1104
1105 // This is called when we write to a compiled block (see do_invstub)
1106 void invalidate_page(u_int page)
1107 {
1108   struct ll_entry *head;
1109   struct ll_entry *next;
1110   head=jump_in[page];
1111   jump_in[page]=0;
1112   while(head!=NULL) {
1113     inv_debug("INVALIDATE: %x\n",head->vaddr);
1114     remove_hash(head->vaddr);
1115     next=head->next;
1116     free(head);
1117     head=next;
1118   }
1119   head=jump_out[page];
1120   jump_out[page]=0;
1121   while(head!=NULL) {
1122     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1123     u_int host_addr=(u_int)kill_pointer(head->addr);
1124     #ifdef __arm__
1125       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1126     #endif
1127     next=head->next;
1128     free(head);
1129     head=next;
1130   }
1131 }
1132 void invalidate_block(u_int block)
1133 {
1134   u_int page=get_page(block<<12);
1135   u_int vpage=get_vpage(block<<12);
1136   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1137   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1138   u_int first,last;
1139   first=last=page;
1140   struct ll_entry *head;
1141   head=jump_dirty[vpage];
1142   //printf("page=%d vpage=%d\n",page,vpage);
1143   while(head!=NULL) {
1144     u_int start,end;
1145     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1146       get_bounds((int)head->addr,&start,&end);
1147       //printf("start: %x end: %x\n",start,end);
1148       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1149         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1150           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1151           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1152         }
1153       }
1154 #ifndef DISABLE_TLB
1155       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1156         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1157           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1158           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1159         }
1160       }
1161 #endif
1162     }
1163     head=head->next;
1164   }
1165   //printf("first=%d last=%d\n",first,last);
1166   invalidate_page(page);
1167   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1168   assert(last<page+5);
1169   // Invalidate the adjacent pages if a block crosses a 4K boundary
1170   while(first<page) {
1171     invalidate_page(first);
1172     first++;
1173   }
1174   for(first=page+1;first<last;first++) {
1175     invalidate_page(first);
1176   }
1177   #ifdef __arm__
1178     do_clear_cache();
1179   #endif
1180   
1181   // Don't trap writes
1182   invalid_code[block]=1;
1183 #ifndef DISABLE_TLB
1184   // If there is a valid TLB entry for this page, remove write protect
1185   if(tlb_LUT_w[block]) {
1186     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1187     // CHECK: Is this right?
1188     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1189     u_int real_block=tlb_LUT_w[block]>>12;
1190     invalid_code[real_block]=1;
1191     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1192   }
1193   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1194 #endif
1195
1196   #ifdef USE_MINI_HT
1197   memset(mini_ht,-1,sizeof(mini_ht));
1198   #endif
1199 }
1200 void invalidate_addr(u_int addr)
1201 {
1202   invalidate_block(addr>>12);
1203 }
1204 // This is called when loading a save state.
1205 // Anything could have changed, so invalidate everything.
1206 void invalidate_all_pages()
1207 {
1208   u_int page,n;
1209   for(page=0;page<4096;page++)
1210     invalidate_page(page);
1211   for(page=0;page<1048576;page++)
1212     if(!invalid_code[page]) {
1213       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1214       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1215     }
1216   #ifdef __arm__
1217   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1218   #endif
1219   #ifdef USE_MINI_HT
1220   memset(mini_ht,-1,sizeof(mini_ht));
1221   #endif
1222   #ifndef DISABLE_TLB
1223   // TLB
1224   for(page=0;page<0x100000;page++) {
1225     if(tlb_LUT_r[page]) {
1226       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1227       if(!tlb_LUT_w[page]||!invalid_code[page])
1228         memory_map[page]|=0x40000000; // Write protect
1229     }
1230     else memory_map[page]=-1;
1231     if(page==0x80000) page=0xC0000;
1232   }
1233   tlb_hacks();
1234   #endif
1235 }
1236
1237 // Add an entry to jump_out after making a link
1238 void add_link(u_int vaddr,void *src)
1239 {
1240   u_int page=get_page(vaddr);
1241   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1242   ll_add(jump_out+page,vaddr,src);
1243   //int ptr=get_pointer(src);
1244   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1245 }
1246
1247 // If a code block was found to be unmodified (bit was set in
1248 // restore_candidate) and it remains unmodified (bit is clear
1249 // in invalid_code) then move the entries for that 4K page from
1250 // the dirty list to the clean list.
1251 void clean_blocks(u_int page)
1252 {
1253   struct ll_entry *head;
1254   inv_debug("INV: clean_blocks page=%d\n",page);
1255   head=jump_dirty[page];
1256   while(head!=NULL) {
1257     if(!invalid_code[head->vaddr>>12]) {
1258       // Don't restore blocks which are about to expire from the cache
1259       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1260         u_int start,end;
1261         if(verify_dirty((int)head->addr)) {
1262           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1263           u_int i;
1264           u_int inv=0;
1265           get_bounds((int)head->addr,&start,&end);
1266           if(start-(u_int)rdram<RAM_SIZE) {
1267             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1268               inv|=invalid_code[i];
1269             }
1270           }
1271           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1272             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1273             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1274             if(addr<start||addr>=end) inv=1;
1275           }
1276           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1277             inv=1;
1278           }
1279           if(!inv) {
1280             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1281             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1282               u_int ppage=page;
1283 #ifndef DISABLE_TLB
1284               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1285 #endif
1286               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1287               //printf("page=%x, addr=%x\n",page,head->vaddr);
1288               //assert(head->vaddr>>12==(page|0x80000));
1289               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1290               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1291               if(!head->reg32) {
1292                 if(ht_bin[0]==head->vaddr) {
1293                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1294                 }
1295                 if(ht_bin[2]==head->vaddr) {
1296                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1297                 }
1298               }
1299             }
1300           }
1301         }
1302       }
1303     }
1304     head=head->next;
1305   }
1306 }
1307
1308
1309 void mov_alloc(struct regstat *current,int i)
1310 {
1311   // Note: Don't need to actually alloc the source registers
1312   if((~current->is32>>rs1[i])&1) {
1313     //alloc_reg64(current,i,rs1[i]);
1314     alloc_reg64(current,i,rt1[i]);
1315     current->is32&=~(1LL<<rt1[i]);
1316   } else {
1317     //alloc_reg(current,i,rs1[i]);
1318     alloc_reg(current,i,rt1[i]);
1319     current->is32|=(1LL<<rt1[i]);
1320   }
1321   clear_const(current,rs1[i]);
1322   clear_const(current,rt1[i]);
1323   dirty_reg(current,rt1[i]);
1324 }
1325
1326 void shiftimm_alloc(struct regstat *current,int i)
1327 {
1328   clear_const(current,rs1[i]);
1329   clear_const(current,rt1[i]);
1330   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1331   {
1332     if(rt1[i]) {
1333       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1334       else lt1[i]=rs1[i];
1335       alloc_reg(current,i,rt1[i]);
1336       current->is32|=1LL<<rt1[i];
1337       dirty_reg(current,rt1[i]);
1338     }
1339   }
1340   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1341   {
1342     if(rt1[i]) {
1343       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1344       alloc_reg64(current,i,rt1[i]);
1345       current->is32&=~(1LL<<rt1[i]);
1346       dirty_reg(current,rt1[i]);
1347     }
1348   }
1349   if(opcode2[i]==0x3c) // DSLL32
1350   {
1351     if(rt1[i]) {
1352       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1353       alloc_reg64(current,i,rt1[i]);
1354       current->is32&=~(1LL<<rt1[i]);
1355       dirty_reg(current,rt1[i]);
1356     }
1357   }
1358   if(opcode2[i]==0x3e) // DSRL32
1359   {
1360     if(rt1[i]) {
1361       alloc_reg64(current,i,rs1[i]);
1362       if(imm[i]==32) {
1363         alloc_reg64(current,i,rt1[i]);
1364         current->is32&=~(1LL<<rt1[i]);
1365       } else {
1366         alloc_reg(current,i,rt1[i]);
1367         current->is32|=1LL<<rt1[i];
1368       }
1369       dirty_reg(current,rt1[i]);
1370     }
1371   }
1372   if(opcode2[i]==0x3f) // DSRA32
1373   {
1374     if(rt1[i]) {
1375       alloc_reg64(current,i,rs1[i]);
1376       alloc_reg(current,i,rt1[i]);
1377       current->is32|=1LL<<rt1[i];
1378       dirty_reg(current,rt1[i]);
1379     }
1380   }
1381 }
1382
1383 void shift_alloc(struct regstat *current,int i)
1384 {
1385   if(rt1[i]) {
1386     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1387     {
1388       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1389       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1390       alloc_reg(current,i,rt1[i]);
1391       if(rt1[i]==rs2[i]) {
1392         alloc_reg_temp(current,i,-1);
1393         minimum_free_regs[i]=1;
1394       }
1395       current->is32|=1LL<<rt1[i];
1396     } else { // DSLLV/DSRLV/DSRAV
1397       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1398       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1399       alloc_reg64(current,i,rt1[i]);
1400       current->is32&=~(1LL<<rt1[i]);
1401       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1402       {
1403         alloc_reg_temp(current,i,-1);
1404         minimum_free_regs[i]=1;
1405       }
1406     }
1407     clear_const(current,rs1[i]);
1408     clear_const(current,rs2[i]);
1409     clear_const(current,rt1[i]);
1410     dirty_reg(current,rt1[i]);
1411   }
1412 }
1413
1414 void alu_alloc(struct regstat *current,int i)
1415 {
1416   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1417     if(rt1[i]) {
1418       if(rs1[i]&&rs2[i]) {
1419         alloc_reg(current,i,rs1[i]);
1420         alloc_reg(current,i,rs2[i]);
1421       }
1422       else {
1423         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1424         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1425       }
1426       alloc_reg(current,i,rt1[i]);
1427     }
1428     current->is32|=1LL<<rt1[i];
1429   }
1430   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1431     if(rt1[i]) {
1432       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1433       {
1434         alloc_reg64(current,i,rs1[i]);
1435         alloc_reg64(current,i,rs2[i]);
1436         alloc_reg(current,i,rt1[i]);
1437       } else {
1438         alloc_reg(current,i,rs1[i]);
1439         alloc_reg(current,i,rs2[i]);
1440         alloc_reg(current,i,rt1[i]);
1441       }
1442     }
1443     current->is32|=1LL<<rt1[i];
1444   }
1445   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1446     if(rt1[i]) {
1447       if(rs1[i]&&rs2[i]) {
1448         alloc_reg(current,i,rs1[i]);
1449         alloc_reg(current,i,rs2[i]);
1450       }
1451       else
1452       {
1453         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1454         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1455       }
1456       alloc_reg(current,i,rt1[i]);
1457       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1458       {
1459         if(!((current->uu>>rt1[i])&1)) {
1460           alloc_reg64(current,i,rt1[i]);
1461         }
1462         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1463           if(rs1[i]&&rs2[i]) {
1464             alloc_reg64(current,i,rs1[i]);
1465             alloc_reg64(current,i,rs2[i]);
1466           }
1467           else
1468           {
1469             // Is is really worth it to keep 64-bit values in registers?
1470             #ifdef NATIVE_64BIT
1471             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1472             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1473             #endif
1474           }
1475         }
1476         current->is32&=~(1LL<<rt1[i]);
1477       } else {
1478         current->is32|=1LL<<rt1[i];
1479       }
1480     }
1481   }
1482   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1483     if(rt1[i]) {
1484       if(rs1[i]&&rs2[i]) {
1485         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1486           alloc_reg64(current,i,rs1[i]);
1487           alloc_reg64(current,i,rs2[i]);
1488           alloc_reg64(current,i,rt1[i]);
1489         } else {
1490           alloc_reg(current,i,rs1[i]);
1491           alloc_reg(current,i,rs2[i]);
1492           alloc_reg(current,i,rt1[i]);
1493         }
1494       }
1495       else {
1496         alloc_reg(current,i,rt1[i]);
1497         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1498           // DADD used as move, or zeroing
1499           // If we have a 64-bit source, then make the target 64 bits too
1500           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1501             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1502             alloc_reg64(current,i,rt1[i]);
1503           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1504             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1505             alloc_reg64(current,i,rt1[i]);
1506           }
1507           if(opcode2[i]>=0x2e&&rs2[i]) {
1508             // DSUB used as negation - 64-bit result
1509             // If we have a 32-bit register, extend it to 64 bits
1510             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1511             alloc_reg64(current,i,rt1[i]);
1512           }
1513         }
1514       }
1515       if(rs1[i]&&rs2[i]) {
1516         current->is32&=~(1LL<<rt1[i]);
1517       } else if(rs1[i]) {
1518         current->is32&=~(1LL<<rt1[i]);
1519         if((current->is32>>rs1[i])&1)
1520           current->is32|=1LL<<rt1[i];
1521       } else if(rs2[i]) {
1522         current->is32&=~(1LL<<rt1[i]);
1523         if((current->is32>>rs2[i])&1)
1524           current->is32|=1LL<<rt1[i];
1525       } else {
1526         current->is32|=1LL<<rt1[i];
1527       }
1528     }
1529   }
1530   clear_const(current,rs1[i]);
1531   clear_const(current,rs2[i]);
1532   clear_const(current,rt1[i]);
1533   dirty_reg(current,rt1[i]);
1534 }
1535
1536 void imm16_alloc(struct regstat *current,int i)
1537 {
1538   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1539   else lt1[i]=rs1[i];
1540   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1541   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1542     current->is32&=~(1LL<<rt1[i]);
1543     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1544       // TODO: Could preserve the 32-bit flag if the immediate is zero
1545       alloc_reg64(current,i,rt1[i]);
1546       alloc_reg64(current,i,rs1[i]);
1547     }
1548     clear_const(current,rs1[i]);
1549     clear_const(current,rt1[i]);
1550   }
1551   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1552     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1553     current->is32|=1LL<<rt1[i];
1554     clear_const(current,rs1[i]);
1555     clear_const(current,rt1[i]);
1556   }
1557   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1558     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1559       if(rs1[i]!=rt1[i]) {
1560         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1561         alloc_reg64(current,i,rt1[i]);
1562         current->is32&=~(1LL<<rt1[i]);
1563       }
1564     }
1565     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1566     if(is_const(current,rs1[i])) {
1567       int v=get_const(current,rs1[i]);
1568       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1569       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1570       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1571     }
1572     else clear_const(current,rt1[i]);
1573   }
1574   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1575     if(is_const(current,rs1[i])) {
1576       int v=get_const(current,rs1[i]);
1577       set_const(current,rt1[i],v+imm[i]);
1578     }
1579     else clear_const(current,rt1[i]);
1580     current->is32|=1LL<<rt1[i];
1581   }
1582   else {
1583     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1584     current->is32|=1LL<<rt1[i];
1585   }
1586   dirty_reg(current,rt1[i]);
1587 }
1588
1589 void load_alloc(struct regstat *current,int i)
1590 {
1591   clear_const(current,rt1[i]);
1592   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1593   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1594   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1595   if(rt1[i]) {
1596     alloc_reg(current,i,rt1[i]);
1597     if(get_reg(current->regmap,rt1[i])<0) {
1598       // dummy load, but we still need a register to calculate the address
1599       alloc_reg_temp(current,i,-1);
1600       minimum_free_regs[i]=1;
1601     }
1602     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1603     {
1604       current->is32&=~(1LL<<rt1[i]);
1605       alloc_reg64(current,i,rt1[i]);
1606     }
1607     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1608     {
1609       current->is32&=~(1LL<<rt1[i]);
1610       alloc_reg64(current,i,rt1[i]);
1611       alloc_all(current,i);
1612       alloc_reg64(current,i,FTEMP);
1613       minimum_free_regs[i]=HOST_REGS;
1614     }
1615     else current->is32|=1LL<<rt1[i];
1616     dirty_reg(current,rt1[i]);
1617     // If using TLB, need a register for pointer to the mapping table
1618     if(using_tlb) alloc_reg(current,i,TLREG);
1619     // LWL/LWR need a temporary register for the old value
1620     if(opcode[i]==0x22||opcode[i]==0x26)
1621     {
1622       alloc_reg(current,i,FTEMP);
1623       alloc_reg_temp(current,i,-1);
1624       minimum_free_regs[i]=1;
1625     }
1626   }
1627   else
1628   {
1629     // Load to r0 (dummy load)
1630     // but we still need a register to calculate the address
1631     if(opcode[i]==0x22||opcode[i]==0x26)
1632     {
1633       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1634     }
1635     alloc_reg_temp(current,i,-1);
1636     minimum_free_regs[i]=1;
1637     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1638     {
1639       alloc_all(current,i);
1640       alloc_reg64(current,i,FTEMP);
1641       minimum_free_regs[i]=HOST_REGS;
1642     }
1643   }
1644 }
1645
1646 void store_alloc(struct regstat *current,int i)
1647 {
1648   clear_const(current,rs2[i]);
1649   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1650   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1651   alloc_reg(current,i,rs2[i]);
1652   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1653     alloc_reg64(current,i,rs2[i]);
1654     if(rs2[i]) alloc_reg(current,i,FTEMP);
1655   }
1656   // If using TLB, need a register for pointer to the mapping table
1657   if(using_tlb) alloc_reg(current,i,TLREG);
1658   #if defined(HOST_IMM8)
1659   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1660   else alloc_reg(current,i,INVCP);
1661   #endif
1662   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1663     alloc_reg(current,i,FTEMP);
1664   }
1665   // We need a temporary register for address generation
1666   alloc_reg_temp(current,i,-1);
1667   minimum_free_regs[i]=1;
1668 }
1669
1670 void c1ls_alloc(struct regstat *current,int i)
1671 {
1672   //clear_const(current,rs1[i]); // FIXME
1673   clear_const(current,rt1[i]);
1674   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1675   alloc_reg(current,i,CSREG); // Status
1676   alloc_reg(current,i,FTEMP);
1677   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1678     alloc_reg64(current,i,FTEMP);
1679   }
1680   // If using TLB, need a register for pointer to the mapping table
1681   if(using_tlb) alloc_reg(current,i,TLREG);
1682   #if defined(HOST_IMM8)
1683   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1684   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1685     alloc_reg(current,i,INVCP);
1686   #endif
1687   // We need a temporary register for address generation
1688   alloc_reg_temp(current,i,-1);
1689 }
1690
1691 void c2ls_alloc(struct regstat *current,int i)
1692 {
1693   clear_const(current,rt1[i]);
1694   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1695   alloc_reg(current,i,FTEMP);
1696   // If using TLB, need a register for pointer to the mapping table
1697   if(using_tlb) alloc_reg(current,i,TLREG);
1698   #if defined(HOST_IMM8)
1699   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1700   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1701     alloc_reg(current,i,INVCP);
1702   #endif
1703   // We need a temporary register for address generation
1704   alloc_reg_temp(current,i,-1);
1705   minimum_free_regs[i]=1;
1706 }
1707
1708 #ifndef multdiv_alloc
1709 void multdiv_alloc(struct regstat *current,int i)
1710 {
1711   //  case 0x18: MULT
1712   //  case 0x19: MULTU
1713   //  case 0x1A: DIV
1714   //  case 0x1B: DIVU
1715   //  case 0x1C: DMULT
1716   //  case 0x1D: DMULTU
1717   //  case 0x1E: DDIV
1718   //  case 0x1F: DDIVU
1719   clear_const(current,rs1[i]);
1720   clear_const(current,rs2[i]);
1721   if(rs1[i]&&rs2[i])
1722   {
1723     if((opcode2[i]&4)==0) // 32-bit
1724     {
1725       current->u&=~(1LL<<HIREG);
1726       current->u&=~(1LL<<LOREG);
1727       alloc_reg(current,i,HIREG);
1728       alloc_reg(current,i,LOREG);
1729       alloc_reg(current,i,rs1[i]);
1730       alloc_reg(current,i,rs2[i]);
1731       current->is32|=1LL<<HIREG;
1732       current->is32|=1LL<<LOREG;
1733       dirty_reg(current,HIREG);
1734       dirty_reg(current,LOREG);
1735     }
1736     else // 64-bit
1737     {
1738       current->u&=~(1LL<<HIREG);
1739       current->u&=~(1LL<<LOREG);
1740       current->uu&=~(1LL<<HIREG);
1741       current->uu&=~(1LL<<LOREG);
1742       alloc_reg64(current,i,HIREG);
1743       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1744       alloc_reg64(current,i,rs1[i]);
1745       alloc_reg64(current,i,rs2[i]);
1746       alloc_all(current,i);
1747       current->is32&=~(1LL<<HIREG);
1748       current->is32&=~(1LL<<LOREG);
1749       dirty_reg(current,HIREG);
1750       dirty_reg(current,LOREG);
1751       minimum_free_regs[i]=HOST_REGS;
1752     }
1753   }
1754   else
1755   {
1756     // Multiply by zero is zero.
1757     // MIPS does not have a divide by zero exception.
1758     // The result is undefined, we return zero.
1759     alloc_reg(current,i,HIREG);
1760     alloc_reg(current,i,LOREG);
1761     current->is32|=1LL<<HIREG;
1762     current->is32|=1LL<<LOREG;
1763     dirty_reg(current,HIREG);
1764     dirty_reg(current,LOREG);
1765   }
1766 }
1767 #endif
1768
1769 void cop0_alloc(struct regstat *current,int i)
1770 {
1771   if(opcode2[i]==0) // MFC0
1772   {
1773     if(rt1[i]) {
1774       clear_const(current,rt1[i]);
1775       alloc_all(current,i);
1776       alloc_reg(current,i,rt1[i]);
1777       current->is32|=1LL<<rt1[i];
1778       dirty_reg(current,rt1[i]);
1779     }
1780   }
1781   else if(opcode2[i]==4) // MTC0
1782   {
1783     if(rs1[i]){
1784       clear_const(current,rs1[i]);
1785       alloc_reg(current,i,rs1[i]);
1786       alloc_all(current,i);
1787     }
1788     else {
1789       alloc_all(current,i); // FIXME: Keep r0
1790       current->u&=~1LL;
1791       alloc_reg(current,i,0);
1792     }
1793   }
1794   else
1795   {
1796     // TLBR/TLBWI/TLBWR/TLBP/ERET
1797     assert(opcode2[i]==0x10);
1798     alloc_all(current,i);
1799   }
1800   minimum_free_regs[i]=HOST_REGS;
1801 }
1802
1803 void cop1_alloc(struct regstat *current,int i)
1804 {
1805   alloc_reg(current,i,CSREG); // Load status
1806   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1807   {
1808     if(rt1[i]){
1809       clear_const(current,rt1[i]);
1810       if(opcode2[i]==1) {
1811         alloc_reg64(current,i,rt1[i]); // DMFC1
1812         current->is32&=~(1LL<<rt1[i]);
1813       }else{
1814         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1815         current->is32|=1LL<<rt1[i];
1816       }
1817       dirty_reg(current,rt1[i]);
1818     }
1819     alloc_reg_temp(current,i,-1);
1820   }
1821   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1822   {
1823     if(rs1[i]){
1824       clear_const(current,rs1[i]);
1825       if(opcode2[i]==5)
1826         alloc_reg64(current,i,rs1[i]); // DMTC1
1827       else
1828         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1829       alloc_reg_temp(current,i,-1);
1830     }
1831     else {
1832       current->u&=~1LL;
1833       alloc_reg(current,i,0);
1834       alloc_reg_temp(current,i,-1);
1835     }
1836   }
1837   minimum_free_regs[i]=1;
1838 }
1839 void fconv_alloc(struct regstat *current,int i)
1840 {
1841   alloc_reg(current,i,CSREG); // Load status
1842   alloc_reg_temp(current,i,-1);
1843   minimum_free_regs[i]=1;
1844 }
1845 void float_alloc(struct regstat *current,int i)
1846 {
1847   alloc_reg(current,i,CSREG); // Load status
1848   alloc_reg_temp(current,i,-1);
1849   minimum_free_regs[i]=1;
1850 }
1851 void c2op_alloc(struct regstat *current,int i)
1852 {
1853   alloc_reg_temp(current,i,-1);
1854 }
1855 void fcomp_alloc(struct regstat *current,int i)
1856 {
1857   alloc_reg(current,i,CSREG); // Load status
1858   alloc_reg(current,i,FSREG); // Load flags
1859   dirty_reg(current,FSREG); // Flag will be modified
1860   alloc_reg_temp(current,i,-1);
1861   minimum_free_regs[i]=1;
1862 }
1863
1864 void syscall_alloc(struct regstat *current,int i)
1865 {
1866   alloc_cc(current,i);
1867   dirty_reg(current,CCREG);
1868   alloc_all(current,i);
1869   minimum_free_regs[i]=HOST_REGS;
1870   current->isconst=0;
1871 }
1872
1873 void delayslot_alloc(struct regstat *current,int i)
1874 {
1875   switch(itype[i]) {
1876     case UJUMP:
1877     case CJUMP:
1878     case SJUMP:
1879     case RJUMP:
1880     case FJUMP:
1881     case SYSCALL:
1882     case HLECALL:
1883     case SPAN:
1884       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1885       printf("Disabled speculative precompilation\n");
1886       stop_after_jal=1;
1887       break;
1888     case IMM16:
1889       imm16_alloc(current,i);
1890       break;
1891     case LOAD:
1892     case LOADLR:
1893       load_alloc(current,i);
1894       break;
1895     case STORE:
1896     case STORELR:
1897       store_alloc(current,i);
1898       break;
1899     case ALU:
1900       alu_alloc(current,i);
1901       break;
1902     case SHIFT:
1903       shift_alloc(current,i);
1904       break;
1905     case MULTDIV:
1906       multdiv_alloc(current,i);
1907       break;
1908     case SHIFTIMM:
1909       shiftimm_alloc(current,i);
1910       break;
1911     case MOV:
1912       mov_alloc(current,i);
1913       break;
1914     case COP0:
1915       cop0_alloc(current,i);
1916       break;
1917     case COP1:
1918     case COP2:
1919       cop1_alloc(current,i);
1920       break;
1921     case C1LS:
1922       c1ls_alloc(current,i);
1923       break;
1924     case C2LS:
1925       c2ls_alloc(current,i);
1926       break;
1927     case FCONV:
1928       fconv_alloc(current,i);
1929       break;
1930     case FLOAT:
1931       float_alloc(current,i);
1932       break;
1933     case FCOMP:
1934       fcomp_alloc(current,i);
1935       break;
1936     case C2OP:
1937       c2op_alloc(current,i);
1938       break;
1939   }
1940 }
1941
1942 // Special case where a branch and delay slot span two pages in virtual memory
1943 static void pagespan_alloc(struct regstat *current,int i)
1944 {
1945   current->isconst=0;
1946   current->wasconst=0;
1947   regs[i].wasconst=0;
1948   minimum_free_regs[i]=HOST_REGS;
1949   alloc_all(current,i);
1950   alloc_cc(current,i);
1951   dirty_reg(current,CCREG);
1952   if(opcode[i]==3) // JAL
1953   {
1954     alloc_reg(current,i,31);
1955     dirty_reg(current,31);
1956   }
1957   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1958   {
1959     alloc_reg(current,i,rs1[i]);
1960     if (rt1[i]!=0) {
1961       alloc_reg(current,i,rt1[i]);
1962       dirty_reg(current,rt1[i]);
1963     }
1964   }
1965   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1966   {
1967     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1968     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1969     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1970     {
1971       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1972       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1973     }
1974   }
1975   else
1976   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1977   {
1978     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1979     if(!((current->is32>>rs1[i])&1))
1980     {
1981       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1982     }
1983   }
1984   else
1985   if(opcode[i]==0x11) // BC1
1986   {
1987     alloc_reg(current,i,FSREG);
1988     alloc_reg(current,i,CSREG);
1989   }
1990   //else ...
1991 }
1992
1993 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1994 {
1995   stubs[stubcount][0]=type;
1996   stubs[stubcount][1]=addr;
1997   stubs[stubcount][2]=retaddr;
1998   stubs[stubcount][3]=a;
1999   stubs[stubcount][4]=b;
2000   stubs[stubcount][5]=c;
2001   stubs[stubcount][6]=d;
2002   stubs[stubcount][7]=e;
2003   stubcount++;
2004 }
2005
2006 // Write out a single register
2007 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2008 {
2009   int hr;
2010   for(hr=0;hr<HOST_REGS;hr++) {
2011     if(hr!=EXCLUDE_REG) {
2012       if((regmap[hr]&63)==r) {
2013         if((dirty>>hr)&1) {
2014           if(regmap[hr]<64) {
2015             emit_storereg(r,hr);
2016 #ifndef FORCE32
2017             if((is32>>regmap[hr])&1) {
2018               emit_sarimm(hr,31,hr);
2019               emit_storereg(r|64,hr);
2020             }
2021 #endif
2022           }else{
2023             emit_storereg(r|64,hr);
2024           }
2025         }
2026       }
2027     }
2028   }
2029 }
2030
2031 int mchecksum()
2032 {
2033   //if(!tracedebug) return 0;
2034   int i;
2035   int sum=0;
2036   for(i=0;i<2097152;i++) {
2037     unsigned int temp=sum;
2038     sum<<=1;
2039     sum|=(~temp)>>31;
2040     sum^=((u_int *)rdram)[i];
2041   }
2042   return sum;
2043 }
2044 int rchecksum()
2045 {
2046   int i;
2047   int sum=0;
2048   for(i=0;i<64;i++)
2049     sum^=((u_int *)reg)[i];
2050   return sum;
2051 }
2052 void rlist()
2053 {
2054   int i;
2055   printf("TRACE: ");
2056   for(i=0;i<32;i++)
2057     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2058   printf("\n");
2059 #ifndef DISABLE_COP1
2060   printf("TRACE: ");
2061   for(i=0;i<32;i++)
2062     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2063   printf("\n");
2064 #endif
2065 }
2066
2067 void enabletrace()
2068 {
2069   tracedebug=1;
2070 }
2071
2072 void memdebug(int i)
2073 {
2074   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2075   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2076   //rlist();
2077   //if(tracedebug) {
2078   //if(Count>=-2084597794) {
2079   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2080   //if(0) {
2081     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2082     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2083     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2084     rlist();
2085     #ifdef __i386__
2086     printf("TRACE: %x\n",(&i)[-1]);
2087     #endif
2088     #ifdef __arm__
2089     int j;
2090     printf("TRACE: %x \n",(&j)[10]);
2091     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2092     #endif
2093     //fflush(stdout);
2094   }
2095   //printf("TRACE: %x\n",(&i)[-1]);
2096 }
2097
2098 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2099 {
2100   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2101 }
2102
2103 void alu_assemble(int i,struct regstat *i_regs)
2104 {
2105   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2106     if(rt1[i]) {
2107       signed char s1,s2,t;
2108       t=get_reg(i_regs->regmap,rt1[i]);
2109       if(t>=0) {
2110         s1=get_reg(i_regs->regmap,rs1[i]);
2111         s2=get_reg(i_regs->regmap,rs2[i]);
2112         if(rs1[i]&&rs2[i]) {
2113           assert(s1>=0);
2114           assert(s2>=0);
2115           if(opcode2[i]&2) emit_sub(s1,s2,t);
2116           else emit_add(s1,s2,t);
2117         }
2118         else if(rs1[i]) {
2119           if(s1>=0) emit_mov(s1,t);
2120           else emit_loadreg(rs1[i],t);
2121         }
2122         else if(rs2[i]) {
2123           if(s2>=0) {
2124             if(opcode2[i]&2) emit_neg(s2,t);
2125             else emit_mov(s2,t);
2126           }
2127           else {
2128             emit_loadreg(rs2[i],t);
2129             if(opcode2[i]&2) emit_neg(t,t);
2130           }
2131         }
2132         else emit_zeroreg(t);
2133       }
2134     }
2135   }
2136   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2137     if(rt1[i]) {
2138       signed char s1l,s2l,s1h,s2h,tl,th;
2139       tl=get_reg(i_regs->regmap,rt1[i]);
2140       th=get_reg(i_regs->regmap,rt1[i]|64);
2141       if(tl>=0) {
2142         s1l=get_reg(i_regs->regmap,rs1[i]);
2143         s2l=get_reg(i_regs->regmap,rs2[i]);
2144         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2145         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2146         if(rs1[i]&&rs2[i]) {
2147           assert(s1l>=0);
2148           assert(s2l>=0);
2149           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2150           else emit_adds(s1l,s2l,tl);
2151           if(th>=0) {
2152             #ifdef INVERTED_CARRY
2153             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2154             #else
2155             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2156             #endif
2157             else emit_add(s1h,s2h,th);
2158           }
2159         }
2160         else if(rs1[i]) {
2161           if(s1l>=0) emit_mov(s1l,tl);
2162           else emit_loadreg(rs1[i],tl);
2163           if(th>=0) {
2164             if(s1h>=0) emit_mov(s1h,th);
2165             else emit_loadreg(rs1[i]|64,th);
2166           }
2167         }
2168         else if(rs2[i]) {
2169           if(s2l>=0) {
2170             if(opcode2[i]&2) emit_negs(s2l,tl);
2171             else emit_mov(s2l,tl);
2172           }
2173           else {
2174             emit_loadreg(rs2[i],tl);
2175             if(opcode2[i]&2) emit_negs(tl,tl);
2176           }
2177           if(th>=0) {
2178             #ifdef INVERTED_CARRY
2179             if(s2h>=0) emit_mov(s2h,th);
2180             else emit_loadreg(rs2[i]|64,th);
2181             if(opcode2[i]&2) {
2182               emit_adcimm(-1,th); // x86 has inverted carry flag
2183               emit_not(th,th);
2184             }
2185             #else
2186             if(opcode2[i]&2) {
2187               if(s2h>=0) emit_rscimm(s2h,0,th);
2188               else {
2189                 emit_loadreg(rs2[i]|64,th);
2190                 emit_rscimm(th,0,th);
2191               }
2192             }else{
2193               if(s2h>=0) emit_mov(s2h,th);
2194               else emit_loadreg(rs2[i]|64,th);
2195             }
2196             #endif
2197           }
2198         }
2199         else {
2200           emit_zeroreg(tl);
2201           if(th>=0) emit_zeroreg(th);
2202         }
2203       }
2204     }
2205   }
2206   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2207     if(rt1[i]) {
2208       signed char s1l,s1h,s2l,s2h,t;
2209       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2210       {
2211         t=get_reg(i_regs->regmap,rt1[i]);
2212         //assert(t>=0);
2213         if(t>=0) {
2214           s1l=get_reg(i_regs->regmap,rs1[i]);
2215           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2216           s2l=get_reg(i_regs->regmap,rs2[i]);
2217           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2218           if(rs2[i]==0) // rx<r0
2219           {
2220             assert(s1h>=0);
2221             if(opcode2[i]==0x2a) // SLT
2222               emit_shrimm(s1h,31,t);
2223             else // SLTU (unsigned can not be less than zero)
2224               emit_zeroreg(t);
2225           }
2226           else if(rs1[i]==0) // r0<rx
2227           {
2228             assert(s2h>=0);
2229             if(opcode2[i]==0x2a) // SLT
2230               emit_set_gz64_32(s2h,s2l,t);
2231             else // SLTU (set if not zero)
2232               emit_set_nz64_32(s2h,s2l,t);
2233           }
2234           else {
2235             assert(s1l>=0);assert(s1h>=0);
2236             assert(s2l>=0);assert(s2h>=0);
2237             if(opcode2[i]==0x2a) // SLT
2238               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2239             else // SLTU
2240               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2241           }
2242         }
2243       } else {
2244         t=get_reg(i_regs->regmap,rt1[i]);
2245         //assert(t>=0);
2246         if(t>=0) {
2247           s1l=get_reg(i_regs->regmap,rs1[i]);
2248           s2l=get_reg(i_regs->regmap,rs2[i]);
2249           if(rs2[i]==0) // rx<r0
2250           {
2251             assert(s1l>=0);
2252             if(opcode2[i]==0x2a) // SLT
2253               emit_shrimm(s1l,31,t);
2254             else // SLTU (unsigned can not be less than zero)
2255               emit_zeroreg(t);
2256           }
2257           else if(rs1[i]==0) // r0<rx
2258           {
2259             assert(s2l>=0);
2260             if(opcode2[i]==0x2a) // SLT
2261               emit_set_gz32(s2l,t);
2262             else // SLTU (set if not zero)
2263               emit_set_nz32(s2l,t);
2264           }
2265           else{
2266             assert(s1l>=0);assert(s2l>=0);
2267             if(opcode2[i]==0x2a) // SLT
2268               emit_set_if_less32(s1l,s2l,t);
2269             else // SLTU
2270               emit_set_if_carry32(s1l,s2l,t);
2271           }
2272         }
2273       }
2274     }
2275   }
2276   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2277     if(rt1[i]) {
2278       signed char s1l,s1h,s2l,s2h,th,tl;
2279       tl=get_reg(i_regs->regmap,rt1[i]);
2280       th=get_reg(i_regs->regmap,rt1[i]|64);
2281       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2282       {
2283         assert(tl>=0);
2284         if(tl>=0) {
2285           s1l=get_reg(i_regs->regmap,rs1[i]);
2286           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2287           s2l=get_reg(i_regs->regmap,rs2[i]);
2288           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2289           if(rs1[i]&&rs2[i]) {
2290             assert(s1l>=0);assert(s1h>=0);
2291             assert(s2l>=0);assert(s2h>=0);
2292             if(opcode2[i]==0x24) { // AND
2293               emit_and(s1l,s2l,tl);
2294               emit_and(s1h,s2h,th);
2295             } else
2296             if(opcode2[i]==0x25) { // OR
2297               emit_or(s1l,s2l,tl);
2298               emit_or(s1h,s2h,th);
2299             } else
2300             if(opcode2[i]==0x26) { // XOR
2301               emit_xor(s1l,s2l,tl);
2302               emit_xor(s1h,s2h,th);
2303             } else
2304             if(opcode2[i]==0x27) { // NOR
2305               emit_or(s1l,s2l,tl);
2306               emit_or(s1h,s2h,th);
2307               emit_not(tl,tl);
2308               emit_not(th,th);
2309             }
2310           }
2311           else
2312           {
2313             if(opcode2[i]==0x24) { // AND
2314               emit_zeroreg(tl);
2315               emit_zeroreg(th);
2316             } else
2317             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2318               if(rs1[i]){
2319                 if(s1l>=0) emit_mov(s1l,tl);
2320                 else emit_loadreg(rs1[i],tl);
2321                 if(s1h>=0) emit_mov(s1h,th);
2322                 else emit_loadreg(rs1[i]|64,th);
2323               }
2324               else
2325               if(rs2[i]){
2326                 if(s2l>=0) emit_mov(s2l,tl);
2327                 else emit_loadreg(rs2[i],tl);
2328                 if(s2h>=0) emit_mov(s2h,th);
2329                 else emit_loadreg(rs2[i]|64,th);
2330               }
2331               else{
2332                 emit_zeroreg(tl);
2333                 emit_zeroreg(th);
2334               }
2335             } else
2336             if(opcode2[i]==0x27) { // NOR
2337               if(rs1[i]){
2338                 if(s1l>=0) emit_not(s1l,tl);
2339                 else{
2340                   emit_loadreg(rs1[i],tl);
2341                   emit_not(tl,tl);
2342                 }
2343                 if(s1h>=0) emit_not(s1h,th);
2344                 else{
2345                   emit_loadreg(rs1[i]|64,th);
2346                   emit_not(th,th);
2347                 }
2348               }
2349               else
2350               if(rs2[i]){
2351                 if(s2l>=0) emit_not(s2l,tl);
2352                 else{
2353                   emit_loadreg(rs2[i],tl);
2354                   emit_not(tl,tl);
2355                 }
2356                 if(s2h>=0) emit_not(s2h,th);
2357                 else{
2358                   emit_loadreg(rs2[i]|64,th);
2359                   emit_not(th,th);
2360                 }
2361               }
2362               else {
2363                 emit_movimm(-1,tl);
2364                 emit_movimm(-1,th);
2365               }
2366             }
2367           }
2368         }
2369       }
2370       else
2371       {
2372         // 32 bit
2373         if(tl>=0) {
2374           s1l=get_reg(i_regs->regmap,rs1[i]);
2375           s2l=get_reg(i_regs->regmap,rs2[i]);
2376           if(rs1[i]&&rs2[i]) {
2377             assert(s1l>=0);
2378             assert(s2l>=0);
2379             if(opcode2[i]==0x24) { // AND
2380               emit_and(s1l,s2l,tl);
2381             } else
2382             if(opcode2[i]==0x25) { // OR
2383               emit_or(s1l,s2l,tl);
2384             } else
2385             if(opcode2[i]==0x26) { // XOR
2386               emit_xor(s1l,s2l,tl);
2387             } else
2388             if(opcode2[i]==0x27) { // NOR
2389               emit_or(s1l,s2l,tl);
2390               emit_not(tl,tl);
2391             }
2392           }
2393           else
2394           {
2395             if(opcode2[i]==0x24) { // AND
2396               emit_zeroreg(tl);
2397             } else
2398             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2399               if(rs1[i]){
2400                 if(s1l>=0) emit_mov(s1l,tl);
2401                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2402               }
2403               else
2404               if(rs2[i]){
2405                 if(s2l>=0) emit_mov(s2l,tl);
2406                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2407               }
2408               else emit_zeroreg(tl);
2409             } else
2410             if(opcode2[i]==0x27) { // NOR
2411               if(rs1[i]){
2412                 if(s1l>=0) emit_not(s1l,tl);
2413                 else {
2414                   emit_loadreg(rs1[i],tl);
2415                   emit_not(tl,tl);
2416                 }
2417               }
2418               else
2419               if(rs2[i]){
2420                 if(s2l>=0) emit_not(s2l,tl);
2421                 else {
2422                   emit_loadreg(rs2[i],tl);
2423                   emit_not(tl,tl);
2424                 }
2425               }
2426               else emit_movimm(-1,tl);
2427             }
2428           }
2429         }
2430       }
2431     }
2432   }
2433 }
2434
2435 void imm16_assemble(int i,struct regstat *i_regs)
2436 {
2437   if (opcode[i]==0x0f) { // LUI
2438     if(rt1[i]) {
2439       signed char t;
2440       t=get_reg(i_regs->regmap,rt1[i]);
2441       //assert(t>=0);
2442       if(t>=0) {
2443         if(!((i_regs->isconst>>t)&1))
2444           emit_movimm(imm[i]<<16,t);
2445       }
2446     }
2447   }
2448   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2449     if(rt1[i]) {
2450       signed char s,t;
2451       t=get_reg(i_regs->regmap,rt1[i]);
2452       s=get_reg(i_regs->regmap,rs1[i]);
2453       if(rs1[i]) {
2454         //assert(t>=0);
2455         //assert(s>=0);
2456         if(t>=0) {
2457           if(!((i_regs->isconst>>t)&1)) {
2458             if(s<0) {
2459               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2460               emit_addimm(t,imm[i],t);
2461             }else{
2462               if(!((i_regs->wasconst>>s)&1))
2463                 emit_addimm(s,imm[i],t);
2464               else
2465                 emit_movimm(constmap[i][s]+imm[i],t);
2466             }
2467           }
2468         }
2469       } else {
2470         if(t>=0) {
2471           if(!((i_regs->isconst>>t)&1))
2472             emit_movimm(imm[i],t);
2473         }
2474       }
2475     }
2476   }
2477   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2478     if(rt1[i]) {
2479       signed char sh,sl,th,tl;
2480       th=get_reg(i_regs->regmap,rt1[i]|64);
2481       tl=get_reg(i_regs->regmap,rt1[i]);
2482       sh=get_reg(i_regs->regmap,rs1[i]|64);
2483       sl=get_reg(i_regs->regmap,rs1[i]);
2484       if(tl>=0) {
2485         if(rs1[i]) {
2486           assert(sh>=0);
2487           assert(sl>=0);
2488           if(th>=0) {
2489             emit_addimm64_32(sh,sl,imm[i],th,tl);
2490           }
2491           else {
2492             emit_addimm(sl,imm[i],tl);
2493           }
2494         } else {
2495           emit_movimm(imm[i],tl);
2496           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2497         }
2498       }
2499     }
2500   }
2501   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2502     if(rt1[i]) {
2503       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2504       signed char sh,sl,t;
2505       t=get_reg(i_regs->regmap,rt1[i]);
2506       sh=get_reg(i_regs->regmap,rs1[i]|64);
2507       sl=get_reg(i_regs->regmap,rs1[i]);
2508       //assert(t>=0);
2509       if(t>=0) {
2510         if(rs1[i]>0) {
2511           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2512           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2513             if(opcode[i]==0x0a) { // SLTI
2514               if(sl<0) {
2515                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2516                 emit_slti32(t,imm[i],t);
2517               }else{
2518                 emit_slti32(sl,imm[i],t);
2519               }
2520             }
2521             else { // SLTIU
2522               if(sl<0) {
2523                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2524                 emit_sltiu32(t,imm[i],t);
2525               }else{
2526                 emit_sltiu32(sl,imm[i],t);
2527               }
2528             }
2529           }else{ // 64-bit
2530             assert(sl>=0);
2531             if(opcode[i]==0x0a) // SLTI
2532               emit_slti64_32(sh,sl,imm[i],t);
2533             else // SLTIU
2534               emit_sltiu64_32(sh,sl,imm[i],t);
2535           }
2536         }else{
2537           // SLTI(U) with r0 is just stupid,
2538           // nonetheless examples can be found
2539           if(opcode[i]==0x0a) // SLTI
2540             if(0<imm[i]) emit_movimm(1,t);
2541             else emit_zeroreg(t);
2542           else // SLTIU
2543           {
2544             if(imm[i]) emit_movimm(1,t);
2545             else emit_zeroreg(t);
2546           }
2547         }
2548       }
2549     }
2550   }
2551   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2552     if(rt1[i]) {
2553       signed char sh,sl,th,tl;
2554       th=get_reg(i_regs->regmap,rt1[i]|64);
2555       tl=get_reg(i_regs->regmap,rt1[i]);
2556       sh=get_reg(i_regs->regmap,rs1[i]|64);
2557       sl=get_reg(i_regs->regmap,rs1[i]);
2558       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2559         if(opcode[i]==0x0c) //ANDI
2560         {
2561           if(rs1[i]) {
2562             if(sl<0) {
2563               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2564               emit_andimm(tl,imm[i],tl);
2565             }else{
2566               if(!((i_regs->wasconst>>sl)&1))
2567                 emit_andimm(sl,imm[i],tl);
2568               else
2569                 emit_movimm(constmap[i][sl]&imm[i],tl);
2570             }
2571           }
2572           else
2573             emit_zeroreg(tl);
2574           if(th>=0) emit_zeroreg(th);
2575         }
2576         else
2577         {
2578           if(rs1[i]) {
2579             if(sl<0) {
2580               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2581             }
2582             if(th>=0) {
2583               if(sh<0) {
2584                 emit_loadreg(rs1[i]|64,th);
2585               }else{
2586                 emit_mov(sh,th);
2587               }
2588             }
2589             if(opcode[i]==0x0d) //ORI
2590             if(sl<0) {
2591               emit_orimm(tl,imm[i],tl);
2592             }else{
2593               if(!((i_regs->wasconst>>sl)&1))
2594                 emit_orimm(sl,imm[i],tl);
2595               else
2596                 emit_movimm(constmap[i][sl]|imm[i],tl);
2597             }
2598             if(opcode[i]==0x0e) //XORI
2599             if(sl<0) {
2600               emit_xorimm(tl,imm[i],tl);
2601             }else{
2602               if(!((i_regs->wasconst>>sl)&1))
2603                 emit_xorimm(sl,imm[i],tl);
2604               else
2605                 emit_movimm(constmap[i][sl]^imm[i],tl);
2606             }
2607           }
2608           else {
2609             emit_movimm(imm[i],tl);
2610             if(th>=0) emit_zeroreg(th);
2611           }
2612         }
2613       }
2614     }
2615   }
2616 }
2617
2618 void shiftimm_assemble(int i,struct regstat *i_regs)
2619 {
2620   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2621   {
2622     if(rt1[i]) {
2623       signed char s,t;
2624       t=get_reg(i_regs->regmap,rt1[i]);
2625       s=get_reg(i_regs->regmap,rs1[i]);
2626       //assert(t>=0);
2627       if(t>=0){
2628         if(rs1[i]==0)
2629         {
2630           emit_zeroreg(t);
2631         }
2632         else
2633         {
2634           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2635           if(imm[i]) {
2636             if(opcode2[i]==0) // SLL
2637             {
2638               emit_shlimm(s<0?t:s,imm[i],t);
2639             }
2640             if(opcode2[i]==2) // SRL
2641             {
2642               emit_shrimm(s<0?t:s,imm[i],t);
2643             }
2644             if(opcode2[i]==3) // SRA
2645             {
2646               emit_sarimm(s<0?t:s,imm[i],t);
2647             }
2648           }else{
2649             // Shift by zero
2650             if(s>=0 && s!=t) emit_mov(s,t);
2651           }
2652         }
2653       }
2654       //emit_storereg(rt1[i],t); //DEBUG
2655     }
2656   }
2657   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2658   {
2659     if(rt1[i]) {
2660       signed char sh,sl,th,tl;
2661       th=get_reg(i_regs->regmap,rt1[i]|64);
2662       tl=get_reg(i_regs->regmap,rt1[i]);
2663       sh=get_reg(i_regs->regmap,rs1[i]|64);
2664       sl=get_reg(i_regs->regmap,rs1[i]);
2665       if(tl>=0) {
2666         if(rs1[i]==0)
2667         {
2668           emit_zeroreg(tl);
2669           if(th>=0) emit_zeroreg(th);
2670         }
2671         else
2672         {
2673           assert(sl>=0);
2674           assert(sh>=0);
2675           if(imm[i]) {
2676             if(opcode2[i]==0x38) // DSLL
2677             {
2678               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2679               emit_shlimm(sl,imm[i],tl);
2680             }
2681             if(opcode2[i]==0x3a) // DSRL
2682             {
2683               emit_shrdimm(sl,sh,imm[i],tl);
2684               if(th>=0) emit_shrimm(sh,imm[i],th);
2685             }
2686             if(opcode2[i]==0x3b) // DSRA
2687             {
2688               emit_shrdimm(sl,sh,imm[i],tl);
2689               if(th>=0) emit_sarimm(sh,imm[i],th);
2690             }
2691           }else{
2692             // Shift by zero
2693             if(sl!=tl) emit_mov(sl,tl);
2694             if(th>=0&&sh!=th) emit_mov(sh,th);
2695           }
2696         }
2697       }
2698     }
2699   }
2700   if(opcode2[i]==0x3c) // DSLL32
2701   {
2702     if(rt1[i]) {
2703       signed char sl,tl,th;
2704       tl=get_reg(i_regs->regmap,rt1[i]);
2705       th=get_reg(i_regs->regmap,rt1[i]|64);
2706       sl=get_reg(i_regs->regmap,rs1[i]);
2707       if(th>=0||tl>=0){
2708         assert(tl>=0);
2709         assert(th>=0);
2710         assert(sl>=0);
2711         emit_mov(sl,th);
2712         emit_zeroreg(tl);
2713         if(imm[i]>32)
2714         {
2715           emit_shlimm(th,imm[i]&31,th);
2716         }
2717       }
2718     }
2719   }
2720   if(opcode2[i]==0x3e) // DSRL32
2721   {
2722     if(rt1[i]) {
2723       signed char sh,tl,th;
2724       tl=get_reg(i_regs->regmap,rt1[i]);
2725       th=get_reg(i_regs->regmap,rt1[i]|64);
2726       sh=get_reg(i_regs->regmap,rs1[i]|64);
2727       if(tl>=0){
2728         assert(sh>=0);
2729         emit_mov(sh,tl);
2730         if(th>=0) emit_zeroreg(th);
2731         if(imm[i]>32)
2732         {
2733           emit_shrimm(tl,imm[i]&31,tl);
2734         }
2735       }
2736     }
2737   }
2738   if(opcode2[i]==0x3f) // DSRA32
2739   {
2740     if(rt1[i]) {
2741       signed char sh,tl;
2742       tl=get_reg(i_regs->regmap,rt1[i]);
2743       sh=get_reg(i_regs->regmap,rs1[i]|64);
2744       if(tl>=0){
2745         assert(sh>=0);
2746         emit_mov(sh,tl);
2747         if(imm[i]>32)
2748         {
2749           emit_sarimm(tl,imm[i]&31,tl);
2750         }
2751       }
2752     }
2753   }
2754 }
2755
2756 #ifndef shift_assemble
2757 void shift_assemble(int i,struct regstat *i_regs)
2758 {
2759   printf("Need shift_assemble for this architecture.\n");
2760   exit(1);
2761 }
2762 #endif
2763
2764 void load_assemble(int i,struct regstat *i_regs)
2765 {
2766   int s,th,tl,addr,map=-1;
2767   int offset;
2768   int jaddr=0;
2769   int memtarget=0,c=0;
2770   u_int hr,reglist=0;
2771   th=get_reg(i_regs->regmap,rt1[i]|64);
2772   tl=get_reg(i_regs->regmap,rt1[i]);
2773   s=get_reg(i_regs->regmap,rs1[i]);
2774   offset=imm[i];
2775   for(hr=0;hr<HOST_REGS;hr++) {
2776     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2777   }
2778   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2779   if(s>=0) {
2780     c=(i_regs->wasconst>>s)&1;
2781     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2782     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2783   }
2784   //printf("load_assemble: c=%d\n",c);
2785   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2786   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2787 #ifdef PCSX
2788   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2789     ||rt1[i]==0) {
2790       // could be FIFO, must perform the read
2791       // ||dummy read
2792       assem_debug("(forced read)\n");
2793       tl=get_reg(i_regs->regmap,-1);
2794       assert(tl>=0);
2795   }
2796 #endif
2797   if(offset||s<0||c) addr=tl;
2798   else addr=s;
2799   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2800  if(tl>=0) {
2801   //printf("load_assemble: c=%d\n",c);
2802   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2803   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2804   reglist&=~(1<<tl);
2805   if(th>=0) reglist&=~(1<<th);
2806   if(!using_tlb) {
2807     if(!c) {
2808       #ifdef RAM_OFFSET
2809       map=get_reg(i_regs->regmap,ROREG);
2810       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2811       #endif
2812 //#define R29_HACK 1
2813       #ifdef R29_HACK
2814       // Strmnnrmn's speed hack
2815       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2816       #endif
2817       {
2818         emit_cmpimm(addr,RAM_SIZE);
2819         jaddr=(int)out;
2820         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2821         // Hint to branch predictor that the branch is unlikely to be taken
2822         if(rs1[i]>=28)
2823           emit_jno_unlikely(0);
2824         else
2825         #endif
2826         emit_jno(0);
2827       }
2828     }
2829   }else{ // using tlb
2830     int x=0;
2831     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2832     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2833     map=get_reg(i_regs->regmap,TLREG);
2834     assert(map>=0);
2835     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2836     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2837   }
2838   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2839   if (opcode[i]==0x20) { // LB
2840     if(!c||memtarget) {
2841       if(!dummy) {
2842         #ifdef HOST_IMM_ADDR32
2843         if(c)
2844           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2845         else
2846         #endif
2847         {
2848           //emit_xorimm(addr,3,tl);
2849           //gen_tlb_addr_r(tl,map);
2850           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2851           int x=0,a=tl;
2852 #ifdef BIG_ENDIAN_MIPS
2853           if(!c) emit_xorimm(addr,3,tl);
2854           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2855 #else
2856           if(!c) a=addr;
2857 #endif
2858           emit_movsbl_indexed_tlb(x,a,map,tl);
2859         }
2860       }
2861       if(jaddr)
2862         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2863     }
2864     else
2865       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2866   }
2867   if (opcode[i]==0x21) { // LH
2868     if(!c||memtarget) {
2869       if(!dummy) {
2870         #ifdef HOST_IMM_ADDR32
2871         if(c)
2872           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2873         else
2874         #endif
2875         {
2876           int x=0,a=tl;
2877 #ifdef BIG_ENDIAN_MIPS
2878           if(!c) emit_xorimm(addr,2,tl);
2879           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2880 #else
2881           if(!c) a=addr;
2882 #endif
2883           //#ifdef
2884           //emit_movswl_indexed_tlb(x,tl,map,tl);
2885           //else
2886           if(map>=0) {
2887             gen_tlb_addr_r(a,map);
2888             emit_movswl_indexed(x,a,tl);
2889           }else{
2890             #ifdef RAM_OFFSET
2891             emit_movswl_indexed(x,a,tl);
2892             #else
2893             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2894             #endif
2895           }
2896         }
2897       }
2898       if(jaddr)
2899         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2900     }
2901     else
2902       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2903   }
2904   if (opcode[i]==0x23) { // LW
2905     if(!c||memtarget) {
2906       if(!dummy) {
2907         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2908         #ifdef HOST_IMM_ADDR32
2909         if(c)
2910           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2911         else
2912         #endif
2913         emit_readword_indexed_tlb(0,addr,map,tl);
2914       }
2915       if(jaddr)
2916         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2917     }
2918     else
2919       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2920   }
2921   if (opcode[i]==0x24) { // LBU
2922     if(!c||memtarget) {
2923       if(!dummy) {
2924         #ifdef HOST_IMM_ADDR32
2925         if(c)
2926           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2927         else
2928         #endif
2929         {
2930           //emit_xorimm(addr,3,tl);
2931           //gen_tlb_addr_r(tl,map);
2932           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2933           int x=0,a=tl;
2934 #ifdef BIG_ENDIAN_MIPS
2935           if(!c) emit_xorimm(addr,3,tl);
2936           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2937 #else
2938           if(!c) a=addr;
2939 #endif
2940           emit_movzbl_indexed_tlb(x,a,map,tl);
2941         }
2942       }
2943       if(jaddr)
2944         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2945     }
2946     else
2947       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2948   }
2949   if (opcode[i]==0x25) { // LHU
2950     if(!c||memtarget) {
2951       if(!dummy) {
2952         #ifdef HOST_IMM_ADDR32
2953         if(c)
2954           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2955         else
2956         #endif
2957         {
2958           int x=0,a=tl;
2959 #ifdef BIG_ENDIAN_MIPS
2960           if(!c) emit_xorimm(addr,2,tl);
2961           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2962 #else
2963           if(!c) a=addr;
2964 #endif
2965           //#ifdef
2966           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2967           //#else
2968           if(map>=0) {
2969             gen_tlb_addr_r(a,map);
2970             emit_movzwl_indexed(x,a,tl);
2971           }else{
2972             #ifdef RAM_OFFSET
2973             emit_movzwl_indexed(x,a,tl);
2974             #else
2975             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2976             #endif
2977           }
2978         }
2979       }
2980       if(jaddr)
2981         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2982     }
2983     else
2984       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2985   }
2986   if (opcode[i]==0x27) { // LWU
2987     assert(th>=0);
2988     if(!c||memtarget) {
2989       if(!dummy) {
2990         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2991         #ifdef HOST_IMM_ADDR32
2992         if(c)
2993           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2994         else
2995         #endif
2996         emit_readword_indexed_tlb(0,addr,map,tl);
2997       }
2998       if(jaddr)
2999         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3000     }
3001     else {
3002       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3003     }
3004     emit_zeroreg(th);
3005   }
3006   if (opcode[i]==0x37) { // LD
3007     if(!c||memtarget) {
3008       if(!dummy) {
3009         //gen_tlb_addr_r(tl,map);
3010         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3011         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3012         #ifdef HOST_IMM_ADDR32
3013         if(c)
3014           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3015         else
3016         #endif
3017         emit_readdword_indexed_tlb(0,addr,map,th,tl);
3018       }
3019       if(jaddr)
3020         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3021     }
3022     else
3023       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3024   }
3025  }
3026   //emit_storereg(rt1[i],tl); // DEBUG
3027   //if(opcode[i]==0x23)
3028   //if(opcode[i]==0x24)
3029   //if(opcode[i]==0x23||opcode[i]==0x24)
3030   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3031   {
3032     //emit_pusha();
3033     save_regs(0x100f);
3034         emit_readword((int)&last_count,ECX);
3035         #ifdef __i386__
3036         if(get_reg(i_regs->regmap,CCREG)<0)
3037           emit_loadreg(CCREG,HOST_CCREG);
3038         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3039         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3040         emit_writeword(HOST_CCREG,(int)&Count);
3041         #endif
3042         #ifdef __arm__
3043         if(get_reg(i_regs->regmap,CCREG)<0)
3044           emit_loadreg(CCREG,0);
3045         else
3046           emit_mov(HOST_CCREG,0);
3047         emit_add(0,ECX,0);
3048         emit_addimm(0,2*ccadj[i],0);
3049         emit_writeword(0,(int)&Count);
3050         #endif
3051     emit_call((int)memdebug);
3052     //emit_popa();
3053     restore_regs(0x100f);
3054   }/**/
3055 }
3056
3057 #ifndef loadlr_assemble
3058 void loadlr_assemble(int i,struct regstat *i_regs)
3059 {
3060   printf("Need loadlr_assemble for this architecture.\n");
3061   exit(1);
3062 }
3063 #endif
3064
3065 void store_assemble(int i,struct regstat *i_regs)
3066 {
3067   int s,th,tl,map=-1;
3068   int addr,temp;
3069   int offset;
3070   int jaddr=0,jaddr2,type;
3071   int memtarget=0,c=0;
3072   int agr=AGEN1+(i&1);
3073   u_int hr,reglist=0;
3074   th=get_reg(i_regs->regmap,rs2[i]|64);
3075   tl=get_reg(i_regs->regmap,rs2[i]);
3076   s=get_reg(i_regs->regmap,rs1[i]);
3077   temp=get_reg(i_regs->regmap,agr);
3078   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3079   offset=imm[i];
3080   if(s>=0) {
3081     c=(i_regs->wasconst>>s)&1;
3082     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3083     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3084   }
3085   assert(tl>=0);
3086   assert(temp>=0);
3087   for(hr=0;hr<HOST_REGS;hr++) {
3088     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3089   }
3090   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3091   if(offset||s<0||c) addr=temp;
3092   else addr=s;
3093   if(!using_tlb) {
3094     if(!c) {
3095       #ifdef R29_HACK
3096       // Strmnnrmn's speed hack
3097       memtarget=1;
3098       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3099       #endif
3100       emit_cmpimm(addr,RAM_SIZE);
3101       #ifdef DESTRUCTIVE_SHIFT
3102       if(s==addr) emit_mov(s,temp);
3103       #endif
3104       #ifdef R29_HACK
3105       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3106       #endif
3107       {
3108         jaddr=(int)out;
3109         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3110         // Hint to branch predictor that the branch is unlikely to be taken
3111         if(rs1[i]>=28)
3112           emit_jno_unlikely(0);
3113         else
3114         #endif
3115         emit_jno(0);
3116       }
3117     }
3118   }else{ // using tlb
3119     int x=0;
3120     if (opcode[i]==0x28) x=3; // SB
3121     if (opcode[i]==0x29) x=2; // SH
3122     map=get_reg(i_regs->regmap,TLREG);
3123     assert(map>=0);
3124     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3125     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3126   }
3127
3128   if (opcode[i]==0x28) { // SB
3129     if(!c||memtarget) {
3130       int x=0;
3131 #ifdef BIG_ENDIAN_MIPS
3132       if(!c) emit_xorimm(addr,3,temp);
3133       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3134 #else
3135       if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3136       else if (addr!=temp) emit_mov(addr,temp);
3137 #endif
3138       //gen_tlb_addr_w(temp,map);
3139       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3140       emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3141     }
3142     type=STOREB_STUB;
3143   }
3144   if (opcode[i]==0x29) { // SH
3145     if(!c||memtarget) {
3146       int x=0;
3147 #ifdef BIG_ENDIAN_MIPS
3148       if(!c) emit_xorimm(addr,2,temp);
3149       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3150 #else
3151       if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3152       else if (addr!=temp) emit_mov(addr,temp);
3153 #endif
3154       //#ifdef
3155       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3156       //#else
3157       if(map>=0) {
3158         gen_tlb_addr_w(temp,map);
3159         emit_writehword_indexed(tl,x,temp);
3160       }else
3161         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3162     }
3163     type=STOREH_STUB;
3164   }
3165   if (opcode[i]==0x2B) { // SW
3166     if(!c||memtarget)
3167       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3168       emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3169     type=STOREW_STUB;
3170   }
3171   if (opcode[i]==0x3F) { // SD
3172     if(!c||memtarget) {
3173       if(rs2[i]) {
3174         assert(th>=0);
3175         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3176         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3177         emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3178       }else{
3179         // Store zero
3180         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3181         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3182         emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3183       }
3184     }
3185     type=STORED_STUB;
3186   }
3187   if(!using_tlb) {
3188     if(!c||memtarget) {
3189       #ifdef DESTRUCTIVE_SHIFT
3190       // The x86 shift operation is 'destructive'; it overwrites the
3191       // source register, so we need to make a copy first and use that.
3192       addr=temp;
3193       #endif
3194       #if defined(HOST_IMM8)
3195       int ir=get_reg(i_regs->regmap,INVCP);
3196       assert(ir>=0);
3197       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3198       #else
3199       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3200       #endif
3201       jaddr2=(int)out;
3202       emit_jne(0);
3203       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3204     }
3205   }
3206   if(jaddr) {
3207     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3208   } else if(c&&!memtarget) {
3209     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3210   }
3211   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3212   //if(opcode[i]==0x2B || opcode[i]==0x28)
3213   //if(opcode[i]==0x2B || opcode[i]==0x29)
3214   //if(opcode[i]==0x2B)
3215   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3216   {
3217     //emit_pusha();
3218     save_regs(0x100f);
3219         emit_readword((int)&last_count,ECX);
3220         #ifdef __i386__
3221         if(get_reg(i_regs->regmap,CCREG)<0)
3222           emit_loadreg(CCREG,HOST_CCREG);
3223         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3224         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3225         emit_writeword(HOST_CCREG,(int)&Count);
3226         #endif
3227         #ifdef __arm__
3228         if(get_reg(i_regs->regmap,CCREG)<0)
3229           emit_loadreg(CCREG,0);
3230         else
3231           emit_mov(HOST_CCREG,0);
3232         emit_add(0,ECX,0);
3233         emit_addimm(0,2*ccadj[i],0);
3234         emit_writeword(0,(int)&Count);
3235         #endif
3236     emit_call((int)memdebug);
3237     //emit_popa();
3238     restore_regs(0x100f);
3239   }/**/
3240 }
3241
3242 void storelr_assemble(int i,struct regstat *i_regs)
3243 {
3244   int s,th,tl;
3245   int temp;
3246   int temp2;
3247   int offset;
3248   int jaddr=0,jaddr2;
3249   int case1,case2,case3;
3250   int done0,done1,done2;
3251   int memtarget,c=0;
3252   int agr=AGEN1+(i&1);
3253   u_int hr,reglist=0;
3254   th=get_reg(i_regs->regmap,rs2[i]|64);
3255   tl=get_reg(i_regs->regmap,rs2[i]);
3256   s=get_reg(i_regs->regmap,rs1[i]);
3257   temp=get_reg(i_regs->regmap,agr);
3258   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3259   offset=imm[i];
3260   if(s>=0) {
3261     c=(i_regs->isconst>>s)&1;
3262     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3263     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3264   }
3265   assert(tl>=0);
3266   for(hr=0;hr<HOST_REGS;hr++) {
3267     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3268   }
3269   assert(temp>=0);
3270   if(!using_tlb) {
3271     if(!c) {
3272       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3273       if(!offset&&s!=temp) emit_mov(s,temp);
3274       jaddr=(int)out;
3275       emit_jno(0);
3276     }
3277     else
3278     {
3279       if(!memtarget||!rs1[i]) {
3280         jaddr=(int)out;
3281         emit_jmp(0);
3282       }
3283     }
3284     #ifdef RAM_OFFSET
3285     int map=get_reg(i_regs->regmap,ROREG);
3286     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3287     gen_tlb_addr_w(temp,map);
3288     #else
3289     if((u_int)rdram!=0x80000000) 
3290       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3291     #endif
3292   }else{ // using tlb
3293     int map=get_reg(i_regs->regmap,TLREG);
3294     assert(map>=0);
3295     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3296     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3297     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3298     if(!jaddr&&!memtarget) {
3299       jaddr=(int)out;
3300       emit_jmp(0);
3301     }
3302     gen_tlb_addr_w(temp,map);
3303   }
3304
3305   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3306     temp2=get_reg(i_regs->regmap,FTEMP);
3307     if(!rs2[i]) temp2=th=tl;
3308   }
3309
3310 #ifndef BIG_ENDIAN_MIPS
3311     emit_xorimm(temp,3,temp);
3312 #endif
3313   emit_testimm(temp,2);
3314   case2=(int)out;
3315   emit_jne(0);
3316   emit_testimm(temp,1);
3317   case1=(int)out;
3318   emit_jne(0);
3319   // 0
3320   if (opcode[i]==0x2A) { // SWL
3321     emit_writeword_indexed(tl,0,temp);
3322   }
3323   if (opcode[i]==0x2E) { // SWR
3324     emit_writebyte_indexed(tl,3,temp);
3325   }
3326   if (opcode[i]==0x2C) { // SDL
3327     emit_writeword_indexed(th,0,temp);
3328     if(rs2[i]) emit_mov(tl,temp2);
3329   }
3330   if (opcode[i]==0x2D) { // SDR
3331     emit_writebyte_indexed(tl,3,temp);
3332     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3333   }
3334   done0=(int)out;
3335   emit_jmp(0);
3336   // 1
3337   set_jump_target(case1,(int)out);
3338   if (opcode[i]==0x2A) { // SWL
3339     // Write 3 msb into three least significant bytes
3340     if(rs2[i]) emit_rorimm(tl,8,tl);
3341     emit_writehword_indexed(tl,-1,temp);
3342     if(rs2[i]) emit_rorimm(tl,16,tl);
3343     emit_writebyte_indexed(tl,1,temp);
3344     if(rs2[i]) emit_rorimm(tl,8,tl);
3345   }
3346   if (opcode[i]==0x2E) { // SWR
3347     // Write two lsb into two most significant bytes
3348     emit_writehword_indexed(tl,1,temp);
3349   }
3350   if (opcode[i]==0x2C) { // SDL
3351     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3352     // Write 3 msb into three least significant bytes
3353     if(rs2[i]) emit_rorimm(th,8,th);
3354     emit_writehword_indexed(th,-1,temp);
3355     if(rs2[i]) emit_rorimm(th,16,th);
3356     emit_writebyte_indexed(th,1,temp);
3357     if(rs2[i]) emit_rorimm(th,8,th);
3358   }
3359   if (opcode[i]==0x2D) { // SDR
3360     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3361     // Write two lsb into two most significant bytes
3362     emit_writehword_indexed(tl,1,temp);
3363   }
3364   done1=(int)out;
3365   emit_jmp(0);
3366   // 2
3367   set_jump_target(case2,(int)out);
3368   emit_testimm(temp,1);
3369   case3=(int)out;
3370   emit_jne(0);
3371   if (opcode[i]==0x2A) { // SWL
3372     // Write two msb into two least significant bytes
3373     if(rs2[i]) emit_rorimm(tl,16,tl);
3374     emit_writehword_indexed(tl,-2,temp);
3375     if(rs2[i]) emit_rorimm(tl,16,tl);
3376   }
3377   if (opcode[i]==0x2E) { // SWR
3378     // Write 3 lsb into three most significant bytes
3379     emit_writebyte_indexed(tl,-1,temp);
3380     if(rs2[i]) emit_rorimm(tl,8,tl);