1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
25 #include "emu_if.h" //emulator interface
30 #include "assem_x86.h"
33 #include "assem_x64.h"
36 #include "assem_arm.h"
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
55 uint64_t constmap[HOST_REGS];
63 struct ll_entry *next;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
85 char likely[MAXBLOCK];
88 uint64_t unneeded_reg[MAXBLOCK];
89 uint64_t unneeded_reg_upper[MAXBLOCK];
90 uint64_t branch_unneeded_reg[MAXBLOCK];
91 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92 uint64_t p32[MAXBLOCK];
93 uint64_t pr32[MAXBLOCK];
94 signed char regmap_pre[MAXBLOCK][HOST_REGS];
95 signed char regmap[MAXBLOCK][HOST_REGS];
96 signed char regmap_entry[MAXBLOCK][HOST_REGS];
97 uint64_t constmap[MAXBLOCK][HOST_REGS];
98 struct regstat regs[MAXBLOCK];
99 struct regstat branch_regs[MAXBLOCK];
100 signed char minimum_free_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
110 u_int stubs[MAXBLOCK*3][8];
112 u_int literals[1024][2];
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
127 static const u_int using_tlb=0;
129 static u_int sp_in_mirror;
130 u_int stop_after_jal;
131 extern u_char restore_candidate[512];
132 extern int cycle_count;
134 /* registers that may be allocated */
136 #define HIREG 32 // hi
137 #define LOREG 33 // lo
138 #define FSREG 34 // FPU status (FCSR)
139 #define CSREG 35 // Coprocessor status
140 #define CCREG 36 // Cycle count
141 #define INVCP 37 // Pointer to invalid_code
142 #define MMREG 38 // Pointer to memory_map
143 #define ROREG 39 // ram offset (if rdram!=0x80000000)
145 #define FTEMP 40 // FPU temporary register
146 #define PTEMP 41 // Prefetch temporary register
147 #define TLREG 42 // TLB mapping offset
148 #define RHASH 43 // Return address hash
149 #define RHTBL 44 // Return address hash table address
150 #define RTEMP 45 // JR/JALR address register
152 #define AGEN1 46 // Address generation temporary register
153 #define AGEN2 47 // Address generation temporary register
154 #define MGEN1 48 // Maptable address generation temporary register
155 #define MGEN2 49 // Maptable address generation temporary register
156 #define BTREG 50 // Branch target temporary register
158 /* instruction types */
159 #define NOP 0 // No operation
160 #define LOAD 1 // Load
161 #define STORE 2 // Store
162 #define LOADLR 3 // Unaligned load
163 #define STORELR 4 // Unaligned store
164 #define MOV 5 // Move
165 #define ALU 6 // Arithmetic/logic
166 #define MULTDIV 7 // Multiply/divide
167 #define SHIFT 8 // Shift by register
168 #define SHIFTIMM 9// Shift by immediate
169 #define IMM16 10 // 16-bit immediate
170 #define RJUMP 11 // Unconditional jump to register
171 #define UJUMP 12 // Unconditional jump
172 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
173 #define SJUMP 14 // Conditional branch (regimm format)
174 #define COP0 15 // Coprocessor 0
175 #define COP1 16 // Coprocessor 1
176 #define C1LS 17 // Coprocessor 1 load/store
177 #define FJUMP 18 // Conditional branch (floating point)
178 #define FLOAT 19 // Floating point unit
179 #define FCONV 20 // Convert integer to float
180 #define FCOMP 21 // Floating point compare (sets FSREG)
181 #define SYSCALL 22// SYSCALL
182 #define OTHER 23 // Other
183 #define SPAN 24 // Branch/delay slot spans 2 pages
184 #define NI 25 // Not implemented
185 #define HLECALL 26// PCSX fake opcodes for HLE
186 #define COP2 27 // Coprocessor 2 move
187 #define C2LS 28 // Coprocessor 2 load/store
188 #define C2OP 29 // Coprocessor 2 operation
189 #define INTCALL 30// Call interpreter to handle rare corner cases
198 #define LOADBU_STUB 7
199 #define LOADHU_STUB 8
200 #define STOREB_STUB 9
201 #define STOREH_STUB 10
202 #define STOREW_STUB 11
203 #define STORED_STUB 12
204 #define STORELR_STUB 13
205 #define INVCODE_STUB 14
213 int new_recompile_block(int addr);
214 void *get_addr_ht(u_int vaddr);
215 void invalidate_block(u_int block);
216 void invalidate_addr(u_int addr);
217 void remove_hash(int vaddr);
220 void dyna_linker_ds();
222 void verify_code_vm();
223 void verify_code_ds();
226 void fp_exception_ds();
228 void jump_syscall_hle();
232 void new_dyna_leave();
237 void read_nomem_new();
238 void read_nomemb_new();
239 void read_nomemh_new();
240 void read_nomemd_new();
241 void write_nomem_new();
242 void write_nomemb_new();
243 void write_nomemh_new();
244 void write_nomemd_new();
245 void write_rdram_new();
246 void write_rdramb_new();
247 void write_rdramh_new();
248 void write_rdramd_new();
249 extern u_int memory_map[1048576];
251 // Needed by assembler
252 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
253 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
254 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
255 void load_all_regs(signed char i_regmap[]);
256 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
257 void load_regs_entry(int t);
258 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
262 //#define DEBUG_CYCLE_COUNT 1
265 //#define assem_debug printf
266 //#define inv_debug printf
267 #define assem_debug nullf
268 #define inv_debug nullf
270 static void tlb_hacks()
274 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
278 switch (ROM_HEADER->Country_code&0xFF)
290 // Unknown country code
294 u_int rom_addr=(u_int)rom;
296 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
297 // in the lower 4G of memory to use this hack. Copy it if necessary.
298 if((void *)rom>(void *)0xffffffff) {
299 munmap(ROM_COPY, 67108864);
300 if(mmap(ROM_COPY, 12582912,
301 PROT_READ | PROT_WRITE,
302 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
303 -1, 0) <= 0) {printf("mmap() failed\n");}
304 memcpy(ROM_COPY,rom,12582912);
305 rom_addr=(u_int)ROM_COPY;
309 for(n=0x7F000;n<0x80000;n++) {
310 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
317 static u_int get_page(u_int vaddr)
320 u_int page=(vaddr^0x80000000)>>12;
322 u_int page=vaddr&~0xe0000000;
323 if (page < 0x1000000)
324 page &= ~0x0e00000; // RAM mirrors
328 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
330 if(page>2048) page=2048+(page&2047);
334 static u_int get_vpage(u_int vaddr)
336 u_int vpage=(vaddr^0x80000000)>>12;
338 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
340 if(vpage>2048) vpage=2048+(vpage&2047);
344 // Get address from virtual address
345 // This is called from the recompiled JR/JALR instructions
346 void *get_addr(u_int vaddr)
348 u_int page=get_page(vaddr);
349 u_int vpage=get_vpage(vaddr);
350 struct ll_entry *head;
351 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
354 if(head->vaddr==vaddr&&head->reg32==0) {
355 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
356 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
359 ht_bin[1]=(int)head->addr;
365 head=jump_dirty[vpage];
367 if(head->vaddr==vaddr&&head->reg32==0) {
368 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
369 // Don't restore blocks which are about to expire from the cache
370 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
371 if(verify_dirty(head->addr)) {
372 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
373 invalid_code[vaddr>>12]=0;
374 memory_map[vaddr>>12]|=0x40000000;
377 if(tlb_LUT_r[vaddr>>12]) {
378 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
379 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
382 restore_candidate[vpage>>3]|=1<<(vpage&7);
384 else restore_candidate[page>>3]|=1<<(page&7);
385 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
386 if(ht_bin[0]==vaddr) {
387 ht_bin[1]=(int)head->addr; // Replace existing entry
393 ht_bin[1]=(int)head->addr;
401 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
402 int r=new_recompile_block(vaddr);
403 if(r==0) return get_addr(vaddr);
404 // Execute in unmapped page, generate pagefault execption
406 Cause=(vaddr<<31)|0x8;
407 EPC=(vaddr&1)?vaddr-5:vaddr;
409 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
410 EntryHi=BadVAddr&0xFFFFE000;
411 return get_addr_ht(0x80000000);
413 // Look up address in hash table first
414 void *get_addr_ht(u_int vaddr)
416 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
417 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
418 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
419 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
420 return get_addr(vaddr);
423 void *get_addr_32(u_int vaddr,u_int flags)
426 return get_addr(vaddr);
428 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
429 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
430 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
431 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
432 u_int page=get_page(vaddr);
433 u_int vpage=get_vpage(vaddr);
434 struct ll_entry *head;
437 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
438 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
440 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
442 ht_bin[1]=(int)head->addr;
444 }else if(ht_bin[2]==-1) {
445 ht_bin[3]=(int)head->addr;
448 //ht_bin[3]=ht_bin[1];
449 //ht_bin[2]=ht_bin[0];
450 //ht_bin[1]=(int)head->addr;
457 head=jump_dirty[vpage];
459 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
460 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
461 // Don't restore blocks which are about to expire from the cache
462 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
463 if(verify_dirty(head->addr)) {
464 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
465 invalid_code[vaddr>>12]=0;
466 memory_map[vaddr>>12]|=0x40000000;
469 if(tlb_LUT_r[vaddr>>12]) {
470 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
471 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
474 restore_candidate[vpage>>3]|=1<<(vpage&7);
476 else restore_candidate[page>>3]|=1<<(page&7);
478 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
480 ht_bin[1]=(int)head->addr;
482 }else if(ht_bin[2]==-1) {
483 ht_bin[3]=(int)head->addr;
486 //ht_bin[3]=ht_bin[1];
487 //ht_bin[2]=ht_bin[0];
488 //ht_bin[1]=(int)head->addr;
496 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
497 int r=new_recompile_block(vaddr);
498 if(r==0) return get_addr(vaddr);
499 // Execute in unmapped page, generate pagefault execption
501 Cause=(vaddr<<31)|0x8;
502 EPC=(vaddr&1)?vaddr-5:vaddr;
504 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
505 EntryHi=BadVAddr&0xFFFFE000;
506 return get_addr_ht(0x80000000);
510 void clear_all_regs(signed char regmap[])
513 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
516 signed char get_reg(signed char regmap[],int r)
519 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
523 // Find a register that is available for two consecutive cycles
524 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
527 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
531 int count_free_regs(signed char regmap[])
535 for(hr=0;hr<HOST_REGS;hr++)
537 if(hr!=EXCLUDE_REG) {
538 if(regmap[hr]<0) count++;
544 void dirty_reg(struct regstat *cur,signed char reg)
548 for (hr=0;hr<HOST_REGS;hr++) {
549 if((cur->regmap[hr]&63)==reg) {
555 // If we dirty the lower half of a 64 bit register which is now being
556 // sign-extended, we need to dump the upper half.
557 // Note: Do this only after completion of the instruction, because
558 // some instructions may need to read the full 64-bit value even if
559 // overwriting it (eg SLTI, DSRA32).
560 static void flush_dirty_uppers(struct regstat *cur)
563 for (hr=0;hr<HOST_REGS;hr++) {
564 if((cur->dirty>>hr)&1) {
567 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
572 void set_const(struct regstat *cur,signed char reg,uint64_t value)
576 for (hr=0;hr<HOST_REGS;hr++) {
577 if(cur->regmap[hr]==reg) {
579 cur->constmap[hr]=value;
581 else if((cur->regmap[hr]^64)==reg) {
583 cur->constmap[hr]=value>>32;
588 void clear_const(struct regstat *cur,signed char reg)
592 for (hr=0;hr<HOST_REGS;hr++) {
593 if((cur->regmap[hr]&63)==reg) {
594 cur->isconst&=~(1<<hr);
599 int is_const(struct regstat *cur,signed char reg)
604 for (hr=0;hr<HOST_REGS;hr++) {
605 if((cur->regmap[hr]&63)==reg) {
606 return (cur->isconst>>hr)&1;
611 uint64_t get_const(struct regstat *cur,signed char reg)
615 for (hr=0;hr<HOST_REGS;hr++) {
616 if(cur->regmap[hr]==reg) {
617 return cur->constmap[hr];
620 printf("Unknown constant in r%d\n",reg);
624 // Least soon needed registers
625 // Look at the next ten instructions and see which registers
626 // will be used. Try not to reallocate these.
627 void lsn(u_char hsn[], int i, int *preferred_reg)
637 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
639 // Don't go past an unconditonal jump
646 if(rs1[i+j]) hsn[rs1[i+j]]=j;
647 if(rs2[i+j]) hsn[rs2[i+j]]=j;
648 if(rt1[i+j]) hsn[rt1[i+j]]=j;
649 if(rt2[i+j]) hsn[rt2[i+j]]=j;
650 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
651 // Stores can allocate zero
655 // On some architectures stores need invc_ptr
656 #if defined(HOST_IMM8)
657 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
661 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
669 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
671 // Follow first branch
672 int t=(ba[i+b]-start)>>2;
673 j=7-b;if(t+j>=slen) j=slen-t-1;
676 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
677 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
678 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
679 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
682 // TODO: preferred register based on backward branch
684 // Delay slot should preferably not overwrite branch conditions or cycle count
685 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
686 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
687 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
693 // Coprocessor load/store needs FTEMP, even if not declared
694 if(itype[i]==C1LS||itype[i]==C2LS) {
697 // Load L/R also uses FTEMP as a temporary register
698 if(itype[i]==LOADLR) {
701 // Also SWL/SWR/SDL/SDR
702 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
705 // Don't remove the TLB registers either
706 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
709 // Don't remove the miniht registers
710 if(itype[i]==UJUMP||itype[i]==RJUMP)
717 // We only want to allocate registers if we're going to use them again soon
718 int needed_again(int r, int i)
724 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
726 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
727 return 0; // Don't need any registers if exiting the block
735 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
737 // Don't go past an unconditonal jump
741 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
748 if(rs1[i+j]==r) rn=j;
749 if(rs2[i+j]==r) rn=j;
750 if((unneeded_reg[i+j]>>r)&1) rn=10;
751 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
759 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
761 // Follow first branch
763 int t=(ba[i+b]-start)>>2;
764 j=7-b;if(t+j>=slen) j=slen-t-1;
767 if(!((unneeded_reg[t+j]>>r)&1)) {
768 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
769 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
779 // Try to match register allocations at the end of a loop with those
781 int loop_reg(int i, int r, int hr)
790 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
792 // Don't go past an unconditonal jump
799 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
804 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
805 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
806 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
808 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
810 int t=(ba[i+k]-start)>>2;
811 int reg=get_reg(regs[t].regmap_entry,r);
812 if(reg>=0) return reg;
813 //reg=get_reg(regs[t+1].regmap_entry,r);
814 //if(reg>=0) return reg;
822 // Allocate every register, preserving source/target regs
823 void alloc_all(struct regstat *cur,int i)
827 for(hr=0;hr<HOST_REGS;hr++) {
828 if(hr!=EXCLUDE_REG) {
829 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
830 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
833 cur->dirty&=~(1<<hr);
836 if((cur->regmap[hr]&63)==0)
839 cur->dirty&=~(1<<hr);
846 void div64(int64_t dividend,int64_t divisor)
850 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
851 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
853 void divu64(uint64_t dividend,uint64_t divisor)
857 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
858 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
861 void mult64(uint64_t m1,uint64_t m2)
863 unsigned long long int op1, op2, op3, op4;
864 unsigned long long int result1, result2, result3, result4;
865 unsigned long long int temp1, temp2, temp3, temp4;
881 op1 = op2 & 0xFFFFFFFF;
882 op2 = (op2 >> 32) & 0xFFFFFFFF;
883 op3 = op4 & 0xFFFFFFFF;
884 op4 = (op4 >> 32) & 0xFFFFFFFF;
887 temp2 = (temp1 >> 32) + op1 * op4;
889 temp4 = (temp3 >> 32) + op2 * op4;
891 result1 = temp1 & 0xFFFFFFFF;
892 result2 = temp2 + (temp3 & 0xFFFFFFFF);
893 result3 = (result2 >> 32) + temp4;
894 result4 = (result3 >> 32);
896 lo = result1 | (result2 << 32);
897 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
906 void multu64(uint64_t m1,uint64_t m2)
908 unsigned long long int op1, op2, op3, op4;
909 unsigned long long int result1, result2, result3, result4;
910 unsigned long long int temp1, temp2, temp3, temp4;
912 op1 = m1 & 0xFFFFFFFF;
913 op2 = (m1 >> 32) & 0xFFFFFFFF;
914 op3 = m2 & 0xFFFFFFFF;
915 op4 = (m2 >> 32) & 0xFFFFFFFF;
918 temp2 = (temp1 >> 32) + op1 * op4;
920 temp4 = (temp3 >> 32) + op2 * op4;
922 result1 = temp1 & 0xFFFFFFFF;
923 result2 = temp2 + (temp3 & 0xFFFFFFFF);
924 result3 = (result2 >> 32) + temp4;
925 result4 = (result3 >> 32);
927 lo = result1 | (result2 << 32);
928 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
930 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
931 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
934 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
942 else original=loaded;
945 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
948 original>>=64-(bits^56);
949 original<<=64-(bits^56);
953 else original=loaded;
958 #include "assem_x86.c"
961 #include "assem_x64.c"
964 #include "assem_arm.c"
967 // Add virtual address mapping to linked list
968 void ll_add(struct ll_entry **head,int vaddr,void *addr)
970 struct ll_entry *new_entry;
971 new_entry=malloc(sizeof(struct ll_entry));
972 assert(new_entry!=NULL);
973 new_entry->vaddr=vaddr;
975 new_entry->addr=addr;
976 new_entry->next=*head;
980 // Add virtual address mapping for 32-bit compiled block
981 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
983 ll_add(head,vaddr,addr);
985 (*head)->reg32=reg32;
989 // Check if an address is already compiled
990 // but don't return addresses which are about to expire from the cache
991 void *check_addr(u_int vaddr)
993 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
994 if(ht_bin[0]==vaddr) {
995 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
996 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
998 if(ht_bin[2]==vaddr) {
999 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1000 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1002 u_int page=get_page(vaddr);
1003 struct ll_entry *head;
1006 if(head->vaddr==vaddr&&head->reg32==0) {
1007 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1008 // Update existing entry with current address
1009 if(ht_bin[0]==vaddr) {
1010 ht_bin[1]=(int)head->addr;
1013 if(ht_bin[2]==vaddr) {
1014 ht_bin[3]=(int)head->addr;
1017 // Insert into hash table with low priority.
1018 // Don't evict existing entries, as they are probably
1019 // addresses that are being accessed frequently.
1021 ht_bin[1]=(int)head->addr;
1023 }else if(ht_bin[2]==-1) {
1024 ht_bin[3]=(int)head->addr;
1035 void remove_hash(int vaddr)
1037 //printf("remove hash: %x\n",vaddr);
1038 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1039 if(ht_bin[2]==vaddr) {
1040 ht_bin[2]=ht_bin[3]=-1;
1042 if(ht_bin[0]==vaddr) {
1043 ht_bin[0]=ht_bin[2];
1044 ht_bin[1]=ht_bin[3];
1045 ht_bin[2]=ht_bin[3]=-1;
1049 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1051 struct ll_entry *next;
1053 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1054 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1056 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1057 remove_hash((*head)->vaddr);
1064 head=&((*head)->next);
1069 // Remove all entries from linked list
1070 void ll_clear(struct ll_entry **head)
1072 struct ll_entry *cur;
1073 struct ll_entry *next;
1084 // Dereference the pointers and remove if it matches
1085 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1088 int ptr=get_pointer(head->addr);
1089 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1090 if(((ptr>>shift)==(addr>>shift)) ||
1091 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1093 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1094 u_int host_addr=(u_int)kill_pointer(head->addr);
1096 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1103 // This is called when we write to a compiled block (see do_invstub)
1104 void invalidate_page(u_int page)
1106 struct ll_entry *head;
1107 struct ll_entry *next;
1111 inv_debug("INVALIDATE: %x\n",head->vaddr);
1112 remove_hash(head->vaddr);
1117 head=jump_out[page];
1120 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1121 u_int host_addr=(u_int)kill_pointer(head->addr);
1123 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1130 void invalidate_block(u_int block)
1132 u_int page=get_page(block<<12);
1133 u_int vpage=get_vpage(block<<12);
1134 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1135 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1138 struct ll_entry *head;
1139 head=jump_dirty[vpage];
1140 //printf("page=%d vpage=%d\n",page,vpage);
1143 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1144 get_bounds((int)head->addr,&start,&end);
1145 //printf("start: %x end: %x\n",start,end);
1146 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1147 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1148 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1149 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1153 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1154 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1155 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1156 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1163 //printf("first=%d last=%d\n",first,last);
1164 invalidate_page(page);
1165 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1166 assert(last<page+5);
1167 // Invalidate the adjacent pages if a block crosses a 4K boundary
1169 invalidate_page(first);
1172 for(first=page+1;first<last;first++) {
1173 invalidate_page(first);
1179 // Don't trap writes
1180 invalid_code[block]=1;
1182 invalid_code[((u_int)0x80000000>>12)|page]=1;
1185 // If there is a valid TLB entry for this page, remove write protect
1186 if(tlb_LUT_w[block]) {
1187 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1188 // CHECK: Is this right?
1189 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1190 u_int real_block=tlb_LUT_w[block]>>12;
1191 invalid_code[real_block]=1;
1192 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1194 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1198 memset(mini_ht,-1,sizeof(mini_ht));
1201 void invalidate_addr(u_int addr)
1203 invalidate_block(addr>>12);
1205 // This is called when loading a save state.
1206 // Anything could have changed, so invalidate everything.
1207 void invalidate_all_pages()
1210 for(page=0;page<4096;page++)
1211 invalidate_page(page);
1212 for(page=0;page<1048576;page++)
1213 if(!invalid_code[page]) {
1214 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1215 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1218 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1221 memset(mini_ht,-1,sizeof(mini_ht));
1225 for(page=0;page<0x100000;page++) {
1226 if(tlb_LUT_r[page]) {
1227 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1228 if(!tlb_LUT_w[page]||!invalid_code[page])
1229 memory_map[page]|=0x40000000; // Write protect
1231 else memory_map[page]=-1;
1232 if(page==0x80000) page=0xC0000;
1238 // Add an entry to jump_out after making a link
1239 void add_link(u_int vaddr,void *src)
1241 u_int page=get_page(vaddr);
1242 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1243 ll_add(jump_out+page,vaddr,src);
1244 //int ptr=get_pointer(src);
1245 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1248 // If a code block was found to be unmodified (bit was set in
1249 // restore_candidate) and it remains unmodified (bit is clear
1250 // in invalid_code) then move the entries for that 4K page from
1251 // the dirty list to the clean list.
1252 void clean_blocks(u_int page)
1254 struct ll_entry *head;
1255 inv_debug("INV: clean_blocks page=%d\n",page);
1256 head=jump_dirty[page];
1258 if(!invalid_code[head->vaddr>>12]) {
1259 // Don't restore blocks which are about to expire from the cache
1260 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1262 if(verify_dirty((int)head->addr)) {
1263 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1266 get_bounds((int)head->addr,&start,&end);
1267 if(start-(u_int)rdram<RAM_SIZE) {
1268 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1269 inv|=invalid_code[i];
1272 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1273 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1274 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1275 if(addr<start||addr>=end) inv=1;
1277 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1281 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1282 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1285 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1287 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1288 //printf("page=%x, addr=%x\n",page,head->vaddr);
1289 //assert(head->vaddr>>12==(page|0x80000));
1290 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1291 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1293 if(ht_bin[0]==head->vaddr) {
1294 ht_bin[1]=(int)clean_addr; // Replace existing entry
1296 if(ht_bin[2]==head->vaddr) {
1297 ht_bin[3]=(int)clean_addr; // Replace existing entry
1310 void mov_alloc(struct regstat *current,int i)
1312 // Note: Don't need to actually alloc the source registers
1313 if((~current->is32>>rs1[i])&1) {
1314 //alloc_reg64(current,i,rs1[i]);
1315 alloc_reg64(current,i,rt1[i]);
1316 current->is32&=~(1LL<<rt1[i]);
1318 //alloc_reg(current,i,rs1[i]);
1319 alloc_reg(current,i,rt1[i]);
1320 current->is32|=(1LL<<rt1[i]);
1322 clear_const(current,rs1[i]);
1323 clear_const(current,rt1[i]);
1324 dirty_reg(current,rt1[i]);
1327 void shiftimm_alloc(struct regstat *current,int i)
1329 clear_const(current,rs1[i]);
1330 clear_const(current,rt1[i]);
1331 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1334 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1336 alloc_reg(current,i,rt1[i]);
1337 current->is32|=1LL<<rt1[i];
1338 dirty_reg(current,rt1[i]);
1341 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1344 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1345 alloc_reg64(current,i,rt1[i]);
1346 current->is32&=~(1LL<<rt1[i]);
1347 dirty_reg(current,rt1[i]);
1350 if(opcode2[i]==0x3c) // DSLL32
1353 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1354 alloc_reg64(current,i,rt1[i]);
1355 current->is32&=~(1LL<<rt1[i]);
1356 dirty_reg(current,rt1[i]);
1359 if(opcode2[i]==0x3e) // DSRL32
1362 alloc_reg64(current,i,rs1[i]);
1364 alloc_reg64(current,i,rt1[i]);
1365 current->is32&=~(1LL<<rt1[i]);
1367 alloc_reg(current,i,rt1[i]);
1368 current->is32|=1LL<<rt1[i];
1370 dirty_reg(current,rt1[i]);
1373 if(opcode2[i]==0x3f) // DSRA32
1376 alloc_reg64(current,i,rs1[i]);
1377 alloc_reg(current,i,rt1[i]);
1378 current->is32|=1LL<<rt1[i];
1379 dirty_reg(current,rt1[i]);
1384 void shift_alloc(struct regstat *current,int i)
1387 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1389 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1390 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1391 alloc_reg(current,i,rt1[i]);
1392 if(rt1[i]==rs2[i]) {
1393 alloc_reg_temp(current,i,-1);
1394 minimum_free_regs[i]=1;
1396 current->is32|=1LL<<rt1[i];
1397 } else { // DSLLV/DSRLV/DSRAV
1398 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1399 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1400 alloc_reg64(current,i,rt1[i]);
1401 current->is32&=~(1LL<<rt1[i]);
1402 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1404 alloc_reg_temp(current,i,-1);
1405 minimum_free_regs[i]=1;
1408 clear_const(current,rs1[i]);
1409 clear_const(current,rs2[i]);
1410 clear_const(current,rt1[i]);
1411 dirty_reg(current,rt1[i]);
1415 void alu_alloc(struct regstat *current,int i)
1417 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1419 if(rs1[i]&&rs2[i]) {
1420 alloc_reg(current,i,rs1[i]);
1421 alloc_reg(current,i,rs2[i]);
1424 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1425 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1427 alloc_reg(current,i,rt1[i]);
1429 current->is32|=1LL<<rt1[i];
1431 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1433 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1435 alloc_reg64(current,i,rs1[i]);
1436 alloc_reg64(current,i,rs2[i]);
1437 alloc_reg(current,i,rt1[i]);
1439 alloc_reg(current,i,rs1[i]);
1440 alloc_reg(current,i,rs2[i]);
1441 alloc_reg(current,i,rt1[i]);
1444 current->is32|=1LL<<rt1[i];
1446 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1448 if(rs1[i]&&rs2[i]) {
1449 alloc_reg(current,i,rs1[i]);
1450 alloc_reg(current,i,rs2[i]);
1454 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1455 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1457 alloc_reg(current,i,rt1[i]);
1458 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1460 if(!((current->uu>>rt1[i])&1)) {
1461 alloc_reg64(current,i,rt1[i]);
1463 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1464 if(rs1[i]&&rs2[i]) {
1465 alloc_reg64(current,i,rs1[i]);
1466 alloc_reg64(current,i,rs2[i]);
1470 // Is is really worth it to keep 64-bit values in registers?
1472 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1473 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1477 current->is32&=~(1LL<<rt1[i]);
1479 current->is32|=1LL<<rt1[i];
1483 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1485 if(rs1[i]&&rs2[i]) {
1486 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1487 alloc_reg64(current,i,rs1[i]);
1488 alloc_reg64(current,i,rs2[i]);
1489 alloc_reg64(current,i,rt1[i]);
1491 alloc_reg(current,i,rs1[i]);
1492 alloc_reg(current,i,rs2[i]);
1493 alloc_reg(current,i,rt1[i]);
1497 alloc_reg(current,i,rt1[i]);
1498 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1499 // DADD used as move, or zeroing
1500 // If we have a 64-bit source, then make the target 64 bits too
1501 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1502 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1503 alloc_reg64(current,i,rt1[i]);
1504 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1505 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1506 alloc_reg64(current,i,rt1[i]);
1508 if(opcode2[i]>=0x2e&&rs2[i]) {
1509 // DSUB used as negation - 64-bit result
1510 // If we have a 32-bit register, extend it to 64 bits
1511 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1512 alloc_reg64(current,i,rt1[i]);
1516 if(rs1[i]&&rs2[i]) {
1517 current->is32&=~(1LL<<rt1[i]);
1519 current->is32&=~(1LL<<rt1[i]);
1520 if((current->is32>>rs1[i])&1)
1521 current->is32|=1LL<<rt1[i];
1523 current->is32&=~(1LL<<rt1[i]);
1524 if((current->is32>>rs2[i])&1)
1525 current->is32|=1LL<<rt1[i];
1527 current->is32|=1LL<<rt1[i];
1531 clear_const(current,rs1[i]);
1532 clear_const(current,rs2[i]);
1533 clear_const(current,rt1[i]);
1534 dirty_reg(current,rt1[i]);
1537 void imm16_alloc(struct regstat *current,int i)
1539 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1541 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1542 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1543 current->is32&=~(1LL<<rt1[i]);
1544 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1545 // TODO: Could preserve the 32-bit flag if the immediate is zero
1546 alloc_reg64(current,i,rt1[i]);
1547 alloc_reg64(current,i,rs1[i]);
1549 clear_const(current,rs1[i]);
1550 clear_const(current,rt1[i]);
1552 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1553 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1554 current->is32|=1LL<<rt1[i];
1555 clear_const(current,rs1[i]);
1556 clear_const(current,rt1[i]);
1558 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1559 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1560 if(rs1[i]!=rt1[i]) {
1561 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1562 alloc_reg64(current,i,rt1[i]);
1563 current->is32&=~(1LL<<rt1[i]);
1566 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1567 if(is_const(current,rs1[i])) {
1568 int v=get_const(current,rs1[i]);
1569 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1570 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1571 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1573 else clear_const(current,rt1[i]);
1575 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1576 if(is_const(current,rs1[i])) {
1577 int v=get_const(current,rs1[i]);
1578 set_const(current,rt1[i],v+imm[i]);
1580 else clear_const(current,rt1[i]);
1581 current->is32|=1LL<<rt1[i];
1584 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1585 current->is32|=1LL<<rt1[i];
1587 dirty_reg(current,rt1[i]);
1590 void load_alloc(struct regstat *current,int i)
1592 clear_const(current,rt1[i]);
1593 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1594 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1595 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1596 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1597 alloc_reg(current,i,rt1[i]);
1598 assert(get_reg(current->regmap,rt1[i])>=0);
1599 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1601 current->is32&=~(1LL<<rt1[i]);
1602 alloc_reg64(current,i,rt1[i]);
1604 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1606 current->is32&=~(1LL<<rt1[i]);
1607 alloc_reg64(current,i,rt1[i]);
1608 alloc_all(current,i);
1609 alloc_reg64(current,i,FTEMP);
1610 minimum_free_regs[i]=HOST_REGS;
1612 else current->is32|=1LL<<rt1[i];
1613 dirty_reg(current,rt1[i]);
1614 // If using TLB, need a register for pointer to the mapping table
1615 if(using_tlb) alloc_reg(current,i,TLREG);
1616 // LWL/LWR need a temporary register for the old value
1617 if(opcode[i]==0x22||opcode[i]==0x26)
1619 alloc_reg(current,i,FTEMP);
1620 alloc_reg_temp(current,i,-1);
1621 minimum_free_regs[i]=1;
1626 // Load to r0 or unneeded register (dummy load)
1627 // but we still need a register to calculate the address
1628 if(opcode[i]==0x22||opcode[i]==0x26)
1630 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1632 // If using TLB, need a register for pointer to the mapping table
1633 if(using_tlb) alloc_reg(current,i,TLREG);
1634 alloc_reg_temp(current,i,-1);
1635 minimum_free_regs[i]=1;
1636 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1638 alloc_all(current,i);
1639 alloc_reg64(current,i,FTEMP);
1640 minimum_free_regs[i]=HOST_REGS;
1645 void store_alloc(struct regstat *current,int i)
1647 clear_const(current,rs2[i]);
1648 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1649 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1650 alloc_reg(current,i,rs2[i]);
1651 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1652 alloc_reg64(current,i,rs2[i]);
1653 if(rs2[i]) alloc_reg(current,i,FTEMP);
1655 // If using TLB, need a register for pointer to the mapping table
1656 if(using_tlb) alloc_reg(current,i,TLREG);
1657 #if defined(HOST_IMM8)
1658 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1659 else alloc_reg(current,i,INVCP);
1661 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1662 alloc_reg(current,i,FTEMP);
1664 // We need a temporary register for address generation
1665 alloc_reg_temp(current,i,-1);
1666 minimum_free_regs[i]=1;
1669 void c1ls_alloc(struct regstat *current,int i)
1671 //clear_const(current,rs1[i]); // FIXME
1672 clear_const(current,rt1[i]);
1673 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1674 alloc_reg(current,i,CSREG); // Status
1675 alloc_reg(current,i,FTEMP);
1676 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1677 alloc_reg64(current,i,FTEMP);
1679 // If using TLB, need a register for pointer to the mapping table
1680 if(using_tlb) alloc_reg(current,i,TLREG);
1681 #if defined(HOST_IMM8)
1682 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1683 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1684 alloc_reg(current,i,INVCP);
1686 // We need a temporary register for address generation
1687 alloc_reg_temp(current,i,-1);
1690 void c2ls_alloc(struct regstat *current,int i)
1692 clear_const(current,rt1[i]);
1693 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1694 alloc_reg(current,i,FTEMP);
1695 // If using TLB, need a register for pointer to the mapping table
1696 if(using_tlb) alloc_reg(current,i,TLREG);
1697 #if defined(HOST_IMM8)
1698 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1699 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1700 alloc_reg(current,i,INVCP);
1702 // We need a temporary register for address generation
1703 alloc_reg_temp(current,i,-1);
1704 minimum_free_regs[i]=1;
1707 #ifndef multdiv_alloc
1708 void multdiv_alloc(struct regstat *current,int i)
1715 // case 0x1D: DMULTU
1718 clear_const(current,rs1[i]);
1719 clear_const(current,rs2[i]);
1722 if((opcode2[i]&4)==0) // 32-bit
1724 current->u&=~(1LL<<HIREG);
1725 current->u&=~(1LL<<LOREG);
1726 alloc_reg(current,i,HIREG);
1727 alloc_reg(current,i,LOREG);
1728 alloc_reg(current,i,rs1[i]);
1729 alloc_reg(current,i,rs2[i]);
1730 current->is32|=1LL<<HIREG;
1731 current->is32|=1LL<<LOREG;
1732 dirty_reg(current,HIREG);
1733 dirty_reg(current,LOREG);
1737 current->u&=~(1LL<<HIREG);
1738 current->u&=~(1LL<<LOREG);
1739 current->uu&=~(1LL<<HIREG);
1740 current->uu&=~(1LL<<LOREG);
1741 alloc_reg64(current,i,HIREG);
1742 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1743 alloc_reg64(current,i,rs1[i]);
1744 alloc_reg64(current,i,rs2[i]);
1745 alloc_all(current,i);
1746 current->is32&=~(1LL<<HIREG);
1747 current->is32&=~(1LL<<LOREG);
1748 dirty_reg(current,HIREG);
1749 dirty_reg(current,LOREG);
1750 minimum_free_regs[i]=HOST_REGS;
1755 // Multiply by zero is zero.
1756 // MIPS does not have a divide by zero exception.
1757 // The result is undefined, we return zero.
1758 alloc_reg(current,i,HIREG);
1759 alloc_reg(current,i,LOREG);
1760 current->is32|=1LL<<HIREG;
1761 current->is32|=1LL<<LOREG;
1762 dirty_reg(current,HIREG);
1763 dirty_reg(current,LOREG);
1768 void cop0_alloc(struct regstat *current,int i)
1770 if(opcode2[i]==0) // MFC0
1773 clear_const(current,rt1[i]);
1774 alloc_all(current,i);
1775 alloc_reg(current,i,rt1[i]);
1776 current->is32|=1LL<<rt1[i];
1777 dirty_reg(current,rt1[i]);
1780 else if(opcode2[i]==4) // MTC0
1783 clear_const(current,rs1[i]);
1784 alloc_reg(current,i,rs1[i]);
1785 alloc_all(current,i);
1788 alloc_all(current,i); // FIXME: Keep r0
1790 alloc_reg(current,i,0);
1795 // TLBR/TLBWI/TLBWR/TLBP/ERET
1796 assert(opcode2[i]==0x10);
1797 alloc_all(current,i);
1799 minimum_free_regs[i]=HOST_REGS;
1802 void cop1_alloc(struct regstat *current,int i)
1804 alloc_reg(current,i,CSREG); // Load status
1805 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1808 clear_const(current,rt1[i]);
1810 alloc_reg64(current,i,rt1[i]); // DMFC1
1811 current->is32&=~(1LL<<rt1[i]);
1813 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1814 current->is32|=1LL<<rt1[i];
1816 dirty_reg(current,rt1[i]);
1818 alloc_reg_temp(current,i,-1);
1820 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1823 clear_const(current,rs1[i]);
1825 alloc_reg64(current,i,rs1[i]); // DMTC1
1827 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1828 alloc_reg_temp(current,i,-1);
1832 alloc_reg(current,i,0);
1833 alloc_reg_temp(current,i,-1);
1836 minimum_free_regs[i]=1;
1838 void fconv_alloc(struct regstat *current,int i)
1840 alloc_reg(current,i,CSREG); // Load status
1841 alloc_reg_temp(current,i,-1);
1842 minimum_free_regs[i]=1;
1844 void float_alloc(struct regstat *current,int i)
1846 alloc_reg(current,i,CSREG); // Load status
1847 alloc_reg_temp(current,i,-1);
1848 minimum_free_regs[i]=1;
1850 void c2op_alloc(struct regstat *current,int i)
1852 alloc_reg_temp(current,i,-1);
1854 void fcomp_alloc(struct regstat *current,int i)
1856 alloc_reg(current,i,CSREG); // Load status
1857 alloc_reg(current,i,FSREG); // Load flags
1858 dirty_reg(current,FSREG); // Flag will be modified
1859 alloc_reg_temp(current,i,-1);
1860 minimum_free_regs[i]=1;
1863 void syscall_alloc(struct regstat *current,int i)
1865 alloc_cc(current,i);
1866 dirty_reg(current,CCREG);
1867 alloc_all(current,i);
1868 minimum_free_regs[i]=HOST_REGS;
1872 void delayslot_alloc(struct regstat *current,int i)
1883 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1884 printf("Disabled speculative precompilation\n");
1888 imm16_alloc(current,i);
1892 load_alloc(current,i);
1896 store_alloc(current,i);
1899 alu_alloc(current,i);
1902 shift_alloc(current,i);
1905 multdiv_alloc(current,i);
1908 shiftimm_alloc(current,i);
1911 mov_alloc(current,i);
1914 cop0_alloc(current,i);
1918 cop1_alloc(current,i);
1921 c1ls_alloc(current,i);
1924 c2ls_alloc(current,i);
1927 fconv_alloc(current,i);
1930 float_alloc(current,i);
1933 fcomp_alloc(current,i);
1936 c2op_alloc(current,i);
1941 // Special case where a branch and delay slot span two pages in virtual memory
1942 static void pagespan_alloc(struct regstat *current,int i)
1945 current->wasconst=0;
1947 minimum_free_regs[i]=HOST_REGS;
1948 alloc_all(current,i);
1949 alloc_cc(current,i);
1950 dirty_reg(current,CCREG);
1951 if(opcode[i]==3) // JAL
1953 alloc_reg(current,i,31);
1954 dirty_reg(current,31);
1956 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1958 alloc_reg(current,i,rs1[i]);
1960 alloc_reg(current,i,rt1[i]);
1961 dirty_reg(current,rt1[i]);
1964 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1966 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1967 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1968 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1970 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1971 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1975 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1977 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1978 if(!((current->is32>>rs1[i])&1))
1980 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1984 if(opcode[i]==0x11) // BC1
1986 alloc_reg(current,i,FSREG);
1987 alloc_reg(current,i,CSREG);
1992 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1994 stubs[stubcount][0]=type;
1995 stubs[stubcount][1]=addr;
1996 stubs[stubcount][2]=retaddr;
1997 stubs[stubcount][3]=a;
1998 stubs[stubcount][4]=b;
1999 stubs[stubcount][5]=c;
2000 stubs[stubcount][6]=d;
2001 stubs[stubcount][7]=e;
2005 // Write out a single register
2006 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2009 for(hr=0;hr<HOST_REGS;hr++) {
2010 if(hr!=EXCLUDE_REG) {
2011 if((regmap[hr]&63)==r) {
2014 emit_storereg(r,hr);
2016 if((is32>>regmap[hr])&1) {
2017 emit_sarimm(hr,31,hr);
2018 emit_storereg(r|64,hr);
2022 emit_storereg(r|64,hr);
2032 //if(!tracedebug) return 0;
2035 for(i=0;i<2097152;i++) {
2036 unsigned int temp=sum;
2039 sum^=((u_int *)rdram)[i];
2048 sum^=((u_int *)reg)[i];
2056 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2058 #ifndef DISABLE_COP1
2061 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2071 void memdebug(int i)
2073 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2074 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2077 //if(Count>=-2084597794) {
2078 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2080 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2081 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2082 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2085 printf("TRACE: %x\n",(&i)[-1]);
2089 printf("TRACE: %x \n",(&j)[10]);
2090 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2094 //printf("TRACE: %x\n",(&i)[-1]);
2097 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2099 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2102 void alu_assemble(int i,struct regstat *i_regs)
2104 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2106 signed char s1,s2,t;
2107 t=get_reg(i_regs->regmap,rt1[i]);
2109 s1=get_reg(i_regs->regmap,rs1[i]);
2110 s2=get_reg(i_regs->regmap,rs2[i]);
2111 if(rs1[i]&&rs2[i]) {
2114 if(opcode2[i]&2) emit_sub(s1,s2,t);
2115 else emit_add(s1,s2,t);
2118 if(s1>=0) emit_mov(s1,t);
2119 else emit_loadreg(rs1[i],t);
2123 if(opcode2[i]&2) emit_neg(s2,t);
2124 else emit_mov(s2,t);
2127 emit_loadreg(rs2[i],t);
2128 if(opcode2[i]&2) emit_neg(t,t);
2131 else emit_zeroreg(t);
2135 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2137 signed char s1l,s2l,s1h,s2h,tl,th;
2138 tl=get_reg(i_regs->regmap,rt1[i]);
2139 th=get_reg(i_regs->regmap,rt1[i]|64);
2141 s1l=get_reg(i_regs->regmap,rs1[i]);
2142 s2l=get_reg(i_regs->regmap,rs2[i]);
2143 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2144 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2145 if(rs1[i]&&rs2[i]) {
2148 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2149 else emit_adds(s1l,s2l,tl);
2151 #ifdef INVERTED_CARRY
2152 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2154 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2156 else emit_add(s1h,s2h,th);
2160 if(s1l>=0) emit_mov(s1l,tl);
2161 else emit_loadreg(rs1[i],tl);
2163 if(s1h>=0) emit_mov(s1h,th);
2164 else emit_loadreg(rs1[i]|64,th);
2169 if(opcode2[i]&2) emit_negs(s2l,tl);
2170 else emit_mov(s2l,tl);
2173 emit_loadreg(rs2[i],tl);
2174 if(opcode2[i]&2) emit_negs(tl,tl);
2177 #ifdef INVERTED_CARRY
2178 if(s2h>=0) emit_mov(s2h,th);
2179 else emit_loadreg(rs2[i]|64,th);
2181 emit_adcimm(-1,th); // x86 has inverted carry flag
2186 if(s2h>=0) emit_rscimm(s2h,0,th);
2188 emit_loadreg(rs2[i]|64,th);
2189 emit_rscimm(th,0,th);
2192 if(s2h>=0) emit_mov(s2h,th);
2193 else emit_loadreg(rs2[i]|64,th);
2200 if(th>=0) emit_zeroreg(th);
2205 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2207 signed char s1l,s1h,s2l,s2h,t;
2208 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2210 t=get_reg(i_regs->regmap,rt1[i]);
2213 s1l=get_reg(i_regs->regmap,rs1[i]);
2214 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2215 s2l=get_reg(i_regs->regmap,rs2[i]);
2216 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2217 if(rs2[i]==0) // rx<r0
2220 if(opcode2[i]==0x2a) // SLT
2221 emit_shrimm(s1h,31,t);
2222 else // SLTU (unsigned can not be less than zero)
2225 else if(rs1[i]==0) // r0<rx
2228 if(opcode2[i]==0x2a) // SLT
2229 emit_set_gz64_32(s2h,s2l,t);
2230 else // SLTU (set if not zero)
2231 emit_set_nz64_32(s2h,s2l,t);
2234 assert(s1l>=0);assert(s1h>=0);
2235 assert(s2l>=0);assert(s2h>=0);
2236 if(opcode2[i]==0x2a) // SLT
2237 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2239 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2243 t=get_reg(i_regs->regmap,rt1[i]);
2246 s1l=get_reg(i_regs->regmap,rs1[i]);
2247 s2l=get_reg(i_regs->regmap,rs2[i]);
2248 if(rs2[i]==0) // rx<r0
2251 if(opcode2[i]==0x2a) // SLT
2252 emit_shrimm(s1l,31,t);
2253 else // SLTU (unsigned can not be less than zero)
2256 else if(rs1[i]==0) // r0<rx
2259 if(opcode2[i]==0x2a) // SLT
2260 emit_set_gz32(s2l,t);
2261 else // SLTU (set if not zero)
2262 emit_set_nz32(s2l,t);
2265 assert(s1l>=0);assert(s2l>=0);
2266 if(opcode2[i]==0x2a) // SLT
2267 emit_set_if_less32(s1l,s2l,t);
2269 emit_set_if_carry32(s1l,s2l,t);
2275 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2277 signed char s1l,s1h,s2l,s2h,th,tl;
2278 tl=get_reg(i_regs->regmap,rt1[i]);
2279 th=get_reg(i_regs->regmap,rt1[i]|64);
2280 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2284 s1l=get_reg(i_regs->regmap,rs1[i]);
2285 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2286 s2l=get_reg(i_regs->regmap,rs2[i]);
2287 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2288 if(rs1[i]&&rs2[i]) {
2289 assert(s1l>=0);assert(s1h>=0);
2290 assert(s2l>=0);assert(s2h>=0);
2291 if(opcode2[i]==0x24) { // AND
2292 emit_and(s1l,s2l,tl);
2293 emit_and(s1h,s2h,th);
2295 if(opcode2[i]==0x25) { // OR
2296 emit_or(s1l,s2l,tl);
2297 emit_or(s1h,s2h,th);
2299 if(opcode2[i]==0x26) { // XOR
2300 emit_xor(s1l,s2l,tl);
2301 emit_xor(s1h,s2h,th);
2303 if(opcode2[i]==0x27) { // NOR
2304 emit_or(s1l,s2l,tl);
2305 emit_or(s1h,s2h,th);
2312 if(opcode2[i]==0x24) { // AND
2316 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2318 if(s1l>=0) emit_mov(s1l,tl);
2319 else emit_loadreg(rs1[i],tl);
2320 if(s1h>=0) emit_mov(s1h,th);
2321 else emit_loadreg(rs1[i]|64,th);
2325 if(s2l>=0) emit_mov(s2l,tl);
2326 else emit_loadreg(rs2[i],tl);
2327 if(s2h>=0) emit_mov(s2h,th);
2328 else emit_loadreg(rs2[i]|64,th);
2335 if(opcode2[i]==0x27) { // NOR
2337 if(s1l>=0) emit_not(s1l,tl);
2339 emit_loadreg(rs1[i],tl);
2342 if(s1h>=0) emit_not(s1h,th);
2344 emit_loadreg(rs1[i]|64,th);
2350 if(s2l>=0) emit_not(s2l,tl);
2352 emit_loadreg(rs2[i],tl);
2355 if(s2h>=0) emit_not(s2h,th);
2357 emit_loadreg(rs2[i]|64,th);
2373 s1l=get_reg(i_regs->regmap,rs1[i]);
2374 s2l=get_reg(i_regs->regmap,rs2[i]);
2375 if(rs1[i]&&rs2[i]) {
2378 if(opcode2[i]==0x24) { // AND
2379 emit_and(s1l,s2l,tl);
2381 if(opcode2[i]==0x25) { // OR
2382 emit_or(s1l,s2l,tl);
2384 if(opcode2[i]==0x26) { // XOR
2385 emit_xor(s1l,s2l,tl);
2387 if(opcode2[i]==0x27) { // NOR
2388 emit_or(s1l,s2l,tl);
2394 if(opcode2[i]==0x24) { // AND
2397 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2399 if(s1l>=0) emit_mov(s1l,tl);
2400 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2404 if(s2l>=0) emit_mov(s2l,tl);
2405 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2407 else emit_zeroreg(tl);
2409 if(opcode2[i]==0x27) { // NOR
2411 if(s1l>=0) emit_not(s1l,tl);
2413 emit_loadreg(rs1[i],tl);
2419 if(s2l>=0) emit_not(s2l,tl);
2421 emit_loadreg(rs2[i],tl);
2425 else emit_movimm(-1,tl);
2434 void imm16_assemble(int i,struct regstat *i_regs)
2436 if (opcode[i]==0x0f) { // LUI
2439 t=get_reg(i_regs->regmap,rt1[i]);
2442 if(!((i_regs->isconst>>t)&1))
2443 emit_movimm(imm[i]<<16,t);
2447 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2450 t=get_reg(i_regs->regmap,rt1[i]);
2451 s=get_reg(i_regs->regmap,rs1[i]);
2456 if(!((i_regs->isconst>>t)&1)) {
2458 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2459 emit_addimm(t,imm[i],t);
2461 if(!((i_regs->wasconst>>s)&1))
2462 emit_addimm(s,imm[i],t);
2464 emit_movimm(constmap[i][s]+imm[i],t);
2470 if(!((i_regs->isconst>>t)&1))
2471 emit_movimm(imm[i],t);
2476 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2478 signed char sh,sl,th,tl;
2479 th=get_reg(i_regs->regmap,rt1[i]|64);
2480 tl=get_reg(i_regs->regmap,rt1[i]);
2481 sh=get_reg(i_regs->regmap,rs1[i]|64);
2482 sl=get_reg(i_regs->regmap,rs1[i]);
2488 emit_addimm64_32(sh,sl,imm[i],th,tl);
2491 emit_addimm(sl,imm[i],tl);
2494 emit_movimm(imm[i],tl);
2495 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2500 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2502 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2503 signed char sh,sl,t;
2504 t=get_reg(i_regs->regmap,rt1[i]);
2505 sh=get_reg(i_regs->regmap,rs1[i]|64);
2506 sl=get_reg(i_regs->regmap,rs1[i]);
2510 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2511 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2512 if(opcode[i]==0x0a) { // SLTI
2514 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2515 emit_slti32(t,imm[i],t);
2517 emit_slti32(sl,imm[i],t);
2522 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2523 emit_sltiu32(t,imm[i],t);
2525 emit_sltiu32(sl,imm[i],t);
2530 if(opcode[i]==0x0a) // SLTI
2531 emit_slti64_32(sh,sl,imm[i],t);
2533 emit_sltiu64_32(sh,sl,imm[i],t);
2536 // SLTI(U) with r0 is just stupid,
2537 // nonetheless examples can be found
2538 if(opcode[i]==0x0a) // SLTI
2539 if(0<imm[i]) emit_movimm(1,t);
2540 else emit_zeroreg(t);
2543 if(imm[i]) emit_movimm(1,t);
2544 else emit_zeroreg(t);
2550 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2552 signed char sh,sl,th,tl;
2553 th=get_reg(i_regs->regmap,rt1[i]|64);
2554 tl=get_reg(i_regs->regmap,rt1[i]);
2555 sh=get_reg(i_regs->regmap,rs1[i]|64);
2556 sl=get_reg(i_regs->regmap,rs1[i]);
2557 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2558 if(opcode[i]==0x0c) //ANDI
2562 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2563 emit_andimm(tl,imm[i],tl);
2565 if(!((i_regs->wasconst>>sl)&1))
2566 emit_andimm(sl,imm[i],tl);
2568 emit_movimm(constmap[i][sl]&imm[i],tl);
2573 if(th>=0) emit_zeroreg(th);
2579 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2583 emit_loadreg(rs1[i]|64,th);
2588 if(opcode[i]==0x0d) //ORI
2590 emit_orimm(tl,imm[i],tl);
2592 if(!((i_regs->wasconst>>sl)&1))
2593 emit_orimm(sl,imm[i],tl);
2595 emit_movimm(constmap[i][sl]|imm[i],tl);
2597 if(opcode[i]==0x0e) //XORI
2599 emit_xorimm(tl,imm[i],tl);
2601 if(!((i_regs->wasconst>>sl)&1))
2602 emit_xorimm(sl,imm[i],tl);
2604 emit_movimm(constmap[i][sl]^imm[i],tl);
2608 emit_movimm(imm[i],tl);
2609 if(th>=0) emit_zeroreg(th);
2617 void shiftimm_assemble(int i,struct regstat *i_regs)
2619 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2623 t=get_reg(i_regs->regmap,rt1[i]);
2624 s=get_reg(i_regs->regmap,rs1[i]);
2633 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2635 if(opcode2[i]==0) // SLL
2637 emit_shlimm(s<0?t:s,imm[i],t);
2639 if(opcode2[i]==2) // SRL
2641 emit_shrimm(s<0?t:s,imm[i],t);
2643 if(opcode2[i]==3) // SRA
2645 emit_sarimm(s<0?t:s,imm[i],t);
2649 if(s>=0 && s!=t) emit_mov(s,t);
2653 //emit_storereg(rt1[i],t); //DEBUG
2656 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2659 signed char sh,sl,th,tl;
2660 th=get_reg(i_regs->regmap,rt1[i]|64);
2661 tl=get_reg(i_regs->regmap,rt1[i]);
2662 sh=get_reg(i_regs->regmap,rs1[i]|64);
2663 sl=get_reg(i_regs->regmap,rs1[i]);
2668 if(th>=0) emit_zeroreg(th);
2675 if(opcode2[i]==0x38) // DSLL
2677 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2678 emit_shlimm(sl,imm[i],tl);
2680 if(opcode2[i]==0x3a) // DSRL
2682 emit_shrdimm(sl,sh,imm[i],tl);
2683 if(th>=0) emit_shrimm(sh,imm[i],th);
2685 if(opcode2[i]==0x3b) // DSRA
2687 emit_shrdimm(sl,sh,imm[i],tl);
2688 if(th>=0) emit_sarimm(sh,imm[i],th);
2692 if(sl!=tl) emit_mov(sl,tl);
2693 if(th>=0&&sh!=th) emit_mov(sh,th);
2699 if(opcode2[i]==0x3c) // DSLL32
2702 signed char sl,tl,th;
2703 tl=get_reg(i_regs->regmap,rt1[i]);
2704 th=get_reg(i_regs->regmap,rt1[i]|64);
2705 sl=get_reg(i_regs->regmap,rs1[i]);
2714 emit_shlimm(th,imm[i]&31,th);
2719 if(opcode2[i]==0x3e) // DSRL32
2722 signed char sh,tl,th;
2723 tl=get_reg(i_regs->regmap,rt1[i]);
2724 th=get_reg(i_regs->regmap,rt1[i]|64);
2725 sh=get_reg(i_regs->regmap,rs1[i]|64);
2729 if(th>=0) emit_zeroreg(th);
2732 emit_shrimm(tl,imm[i]&31,tl);
2737 if(opcode2[i]==0x3f) // DSRA32
2741 tl=get_reg(i_regs->regmap,rt1[i]);
2742 sh=get_reg(i_regs->regmap,rs1[i]|64);
2748 emit_sarimm(tl,imm[i]&31,tl);
2755 #ifndef shift_assemble
2756 void shift_assemble(int i,struct regstat *i_regs)
2758 printf("Need shift_assemble for this architecture.\n");
2763 void load_assemble(int i,struct regstat *i_regs)
2765 int s,th,tl,addr,map=-1;
2768 int memtarget=0,c=0;
2769 int fastload_reg_override=0;
2771 th=get_reg(i_regs->regmap,rt1[i]|64);
2772 tl=get_reg(i_regs->regmap,rt1[i]);
2773 s=get_reg(i_regs->regmap,rs1[i]);
2775 for(hr=0;hr<HOST_REGS;hr++) {
2776 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2778 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2780 c=(i_regs->wasconst>>s)&1;
2782 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2783 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2786 //printf("load_assemble: c=%d\n",c);
2787 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2788 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2790 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2792 // could be FIFO, must perform the read
2794 assem_debug("(forced read)\n");
2795 tl=get_reg(i_regs->regmap,-1);
2799 if(offset||s<0||c) addr=tl;
2801 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2803 //printf("load_assemble: c=%d\n",c);
2804 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2805 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2807 if(th>=0) reglist&=~(1<<th);
2811 map=get_reg(i_regs->regmap,ROREG);
2812 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2814 //#define R29_HACK 1
2816 // Strmnnrmn's speed hack
2817 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2821 if(sp_in_mirror&&rs1[i]==29) {
2822 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2823 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
2824 fastload_reg_override=HOST_TEMPREG;
2828 emit_cmpimm(addr,RAM_SIZE);
2830 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2831 // Hint to branch predictor that the branch is unlikely to be taken
2833 emit_jno_unlikely(0);
2841 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2842 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2843 map=get_reg(i_regs->regmap,TLREG);
2846 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2847 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2849 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2850 if (opcode[i]==0x20) { // LB
2853 #ifdef HOST_IMM_ADDR32
2855 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2859 //emit_xorimm(addr,3,tl);
2860 //gen_tlb_addr_r(tl,map);
2861 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2863 #ifdef BIG_ENDIAN_MIPS
2864 if(!c) emit_xorimm(addr,3,tl);
2865 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2869 if(fastload_reg_override) a=fastload_reg_override;
2871 emit_movsbl_indexed_tlb(x,a,map,tl);
2875 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2878 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2880 if (opcode[i]==0x21) { // LH
2883 #ifdef HOST_IMM_ADDR32
2885 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2890 #ifdef BIG_ENDIAN_MIPS
2891 if(!c) emit_xorimm(addr,2,tl);
2892 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2896 if(fastload_reg_override) a=fastload_reg_override;
2898 //emit_movswl_indexed_tlb(x,tl,map,tl);
2901 gen_tlb_addr_r(a,map);
2902 emit_movswl_indexed(x,a,tl);
2905 emit_movswl_indexed(x,a,tl);
2907 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2913 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2916 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2918 if (opcode[i]==0x23) { // LW
2922 if(fastload_reg_override) a=fastload_reg_override;
2923 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2924 #ifdef HOST_IMM_ADDR32
2926 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2929 emit_readword_indexed_tlb(0,a,map,tl);
2932 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2935 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2937 if (opcode[i]==0x24) { // LBU
2940 #ifdef HOST_IMM_ADDR32
2942 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2946 //emit_xorimm(addr,3,tl);
2947 //gen_tlb_addr_r(tl,map);
2948 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2950 #ifdef BIG_ENDIAN_MIPS
2951 if(!c) emit_xorimm(addr,3,tl);
2952 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2956 if(fastload_reg_override) a=fastload_reg_override;
2958 emit_movzbl_indexed_tlb(x,a,map,tl);
2962 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2965 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2967 if (opcode[i]==0x25) { // LHU
2970 #ifdef HOST_IMM_ADDR32
2972 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2977 #ifdef BIG_ENDIAN_MIPS
2978 if(!c) emit_xorimm(addr,2,tl);
2979 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2983 if(fastload_reg_override) a=fastload_reg_override;
2985 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2988 gen_tlb_addr_r(a,map);
2989 emit_movzwl_indexed(x,a,tl);
2992 emit_movzwl_indexed(x,a,tl);
2994 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3000 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3003 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3005 if (opcode[i]==0x27) { // LWU
3010 if(fastload_reg_override) a=fastload_reg_override;
3011 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3012 #ifdef HOST_IMM_ADDR32
3014 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3017 emit_readword_indexed_tlb(0,a,map,tl);
3020 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3023 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3027 if (opcode[i]==0x37) { // LD
3031 if(fastload_reg_override) a=fastload_reg_override;
3032 //gen_tlb_addr_r(tl,map);
3033 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3034 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3035 #ifdef HOST_IMM_ADDR32
3037 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3040 emit_readdword_indexed_tlb(0,a,map,th,tl);
3043 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3046 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3049 //emit_storereg(rt1[i],tl); // DEBUG
3050 //if(opcode[i]==0x23)
3051 //if(opcode[i]==0x24)
3052 //if(opcode[i]==0x23||opcode[i]==0x24)
3053 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3057 emit_readword((int)&last_count,ECX);
3059 if(get_reg(i_regs->regmap,CCREG)<0)
3060 emit_loadreg(CCREG,HOST_CCREG);
3061 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3062 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3063 emit_writeword(HOST_CCREG,(int)&Count);
3066 if(get_reg(i_regs->regmap,CCREG)<0)
3067 emit_loadreg(CCREG,0);
3069 emit_mov(HOST_CCREG,0);
3071 emit_addimm(0,2*ccadj[i],0);
3072 emit_writeword(0,(int)&Count);
3074 emit_call((int)memdebug);
3076 restore_regs(0x100f);
3080 #ifndef loadlr_assemble
3081 void loadlr_assemble(int i,struct regstat *i_regs)
3083 printf("Need loadlr_assemble for this architecture.\n");
3088 void store_assemble(int i,struct regstat *i_regs)
3093 int jaddr=0,jaddr2,type;
3094 int memtarget=0,c=0;
3095 int agr=AGEN1+(i&1);
3096 int faststore_reg_override=0;
3098 th=get_reg(i_regs->regmap,rs2[i]|64);
3099 tl=get_reg(i_regs->regmap,rs2[i]);
3100 s=get_reg(i_regs->regmap,rs1[i]);
3101 temp=get_reg(i_regs->regmap,agr);
3102 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3105 c=(i_regs->wasconst>>s)&1;
3107 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3108 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3113 for(hr=0;hr<HOST_REGS;hr++) {
3114 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3116 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3117 if(offset||s<0||c) addr=temp;
3122 if(sp_in_mirror&&rs1[i]==29) {
3123 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3124 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
3125 faststore_reg_override=HOST_TEMPREG;
3130 // Strmnnrmn's speed hack
3131 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3133 emit_cmpimm(addr,RAM_SIZE);
3134 #ifdef DESTRUCTIVE_SHIFT
3135 if(s==addr) emit_mov(s,temp);
3139 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3143 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3144 // Hint to branch predictor that the branch is unlikely to be taken
3146 emit_jno_unlikely(0);
3154 if (opcode[i]==0x28) x=3; // SB
3155 if (opcode[i]==0x29) x=2; // SH
3156 map=get_reg(i_regs->regmap,TLREG);
3159 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3160 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3163 if (opcode[i]==0x28) { // SB
3166 #ifdef BIG_ENDIAN_MIPS
3167 if(!c) emit_xorimm(addr,3,temp);
3168 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3172 if(faststore_reg_override) a=faststore_reg_override;
3173 //gen_tlb_addr_w(temp,map);
3174 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3175 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3179 if (opcode[i]==0x29) { // SH
3182 #ifdef BIG_ENDIAN_MIPS
3183 if(!c) emit_xorimm(addr,2,temp);
3184 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3188 if(faststore_reg_override) a=faststore_reg_override;
3190 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3193 gen_tlb_addr_w(a,map);
3194 emit_writehword_indexed(tl,x,a);
3196 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3200 if (opcode[i]==0x2B) { // SW
3203 if(faststore_reg_override) a=faststore_reg_override;
3204 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3205 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3209 if (opcode[i]==0x3F) { // SD
3212 if(faststore_reg_override) a=faststore_reg_override;
3215 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3216 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3217 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3220 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3221 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3222 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3229 #ifdef DESTRUCTIVE_SHIFT
3230 // The x86 shift operation is 'destructive'; it overwrites the
3231 // source register, so we need to make a copy first and use that.
3234 #if defined(HOST_IMM8)
3235 int ir=get_reg(i_regs->regmap,INVCP);
3237 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3239 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3241 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3242 emit_callne(invalidate_addr_reg[addr]);
3246 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3251 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3252 } else if(c&&!memtarget) {
3253 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3255 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3256 //if(opcode[i]==0x2B || opcode[i]==0x28)
3257 //if(opcode[i]==0x2B || opcode[i]==0x29)
3258 //if(opcode[i]==0x2B)
3259 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3267 emit_readword((int)&last_count,ECX);
3269 if(get_reg(i_regs->regmap,CCREG)<0)
3270 emit_loadreg(CCREG,HOST_CCREG);
3271 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3272 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3273 emit_writeword(HOST_CCREG,(int)&Count);
3276 if(get_reg(i_regs->regmap,CCREG)<0)
3277 emit_loadreg(CCREG,0);
3279 emit_mov(HOST_CCREG,0);
3281 emit_addimm(0,2*ccadj[i],0);
3282 emit_writeword(0,(int)&Count);
3284 emit_call((int)memdebug);
3289 restore_regs(0x100f);
3294 void storelr_assemble(int i,struct regstat *i_regs)
3301 int case1,case2,case3;
3302 int done0,done1,done2;
3303 int memtarget=0,c=0;
3304 int agr=AGEN1+(i&1);
3306 th=get_reg(i_regs->regmap,rs2[i]|64);
3307 tl=get_reg(i_regs->regmap,rs2[i]);
3308 s=get_reg(i_regs->regmap,rs1[i]);
3309 temp=get_reg(i_regs->regmap,agr);
3310 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3313 c=(i_regs->isconst>>s)&1;
3315 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3316 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3320 for(hr=0;hr<HOST_REGS;hr++) {
3321 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3326 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3327 if(!offset&&s!=temp) emit_mov(s,temp);
3333 if(!memtarget||!rs1[i]) {
3339 int map=get_reg(i_regs->regmap,ROREG);
3340 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3341 gen_tlb_addr_w(temp,map);
3343 if((u_int)rdram!=0x80000000)
3344 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3347 int map=get_reg(i_regs->regmap,TLREG);
3350 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3351 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3352 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3353 if(!jaddr&&!memtarget) {
3357 gen_tlb_addr_w(temp,map);
3360 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3361 temp2=get_reg(i_regs->regmap,FTEMP);
3362 if(!rs2[i]) temp2=th=tl;
3365 #ifndef BIG_ENDIAN_MIPS
3366 emit_xorimm(temp,3,temp);
3368 emit_testimm(temp,2);
3371 emit_testimm(temp,1);
3375 if (opcode[i]==0x2A) { // SWL
3376 emit_writeword_indexed(tl,0,temp);
3378 if (opcode[i]==0x2E) { // SWR
3379 emit_writebyte_indexed(tl,3,temp);
3381 if (opcode[i]==0x2C) { // SDL
3382 emit_writeword_indexed(th,0,temp);
3383 if(rs2[i]) emit_mov(tl,temp2);
3385 if (opcode[i]==0x2D) { // SDR
3386 emit_writebyte_indexed(tl,3,temp);
3387 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3392 set_jump_target(case1,(int)out);
3393 if (opcode[i]==0x2A) { // SWL
3394 // Write 3 msb into three least significant bytes
3395 if(rs2[i]) emit_rorimm(tl,8,tl);
3396 emit_writehword_indexed(tl,-1,temp);
3397 if(rs2[i]) emit_rorimm(tl,16,tl);
3398 emit_writebyte_indexed(tl,1,temp);
3399 if(rs2[i]) emit_rorimm(tl,8,tl);
3401 if (opcode[i]==0x2E) { // SWR
3402 // Write two lsb into two most significant bytes
3403 emit_writehword_indexed(tl,1,temp);
3405 if (opcode[i]==0x2C) { // SDL
3406 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3407 // Write 3 msb into three least significant bytes
3408 if(rs2[i]) emit_rorimm(th,8,th);
3409 emit_writehword_indexed(th,-1,temp);
3410 if(rs2[i]) emit_rorimm(th,16,th);
3411 emit_writebyte_indexed(th,1,temp);
3412 if(rs2[i]) emit_rorimm(th,8,th);
3414 if (opcode[i]==0x2D) { // SDR
3415 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3416 // Write two lsb into two most significant bytes
3417 emit_writehword_indexed(tl,1,temp);
3422 set_jump_target(case2,(int)out);
3423 emit_testimm(temp,1);
3426 if (opcode[i]==0x2A) { // SWL
3427 // Write two msb into two least significant bytes
3428 if(rs2[i]) emit_rorimm(tl,16,tl);
3429 emit_writehword_indexed(tl,-2,temp);
3430 if(rs2[i]) emit_rorimm(tl,16,tl);
3432 if (opcode[i]==0x2E) { // SWR
3433 // Write 3 lsb into three most significant bytes
3434 emit_writebyte_indexed(tl,-1,temp);
3435 if(rs2[i]) emit_rorimm(tl,8,tl);
3436 emit_writehword_indexed(tl,0,temp);
3437 if(rs2[i]) emit_rorimm(tl,24,tl);
3439 if (opcode[i]==0x2C) { // SDL
3440 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3441 // Write two msb into two least significant bytes
3442 if(rs2[i]) emit_rorimm(th,16,th);
3443 emit_writehword_indexed(th,-2,temp);
3444 if(rs2[i]) emit_rorimm(th,16,th);
3446 if (opcode[i]==0x2D) { // SDR
3447 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3448 // Write 3 lsb into three most significant bytes
3449 emit_writebyte_indexed(tl,-1,temp);
3450 if(rs2[i]) emit_rorimm(tl,8,tl);
3451 emit_writehword_indexed(tl,0,temp);
3452 if(rs2[i]) emit_rorimm(tl,24,tl);
3457 set_jump_target(case3,(int)out);
3458 if (opcode[i]==0x2A) { // SWL
3459 // Write msb into least significant byte
3460 if(rs2[i]) emit_rorimm(tl,24,tl);
3461 emit_writebyte_indexed(tl,-3,temp);
3462 if(rs2[i]) emit_rorimm(tl,8,tl);
3464 if (opcode[i]==0x2E) { // SWR
3465 // Write entire word
3466 emit_writeword_indexed(tl,-3,temp);
3468 if (opcode[i]==0x2C) { // SDL
3469 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3470 // Write msb into least significant byte
3471 if(rs2[i]) emit_rorimm(th,24,th);
3472 emit_writebyte_indexed(th,-3,temp);
3473 if(rs2[i]) emit_rorimm(th,8,th);
3475 if (opcode[i]==0x2D) { // SDR
3476 if(rs2[i]) emit_mov(th,temp2);
3477 // Write entire word
3478 emit_writeword_indexed(tl,-3,temp);
3480 set_jump_target(done0,(int)out);
3481 set_jump_target(done1,(int)out);
3482 set_jump_target(done2,(int)out);
3483 if (opcode[i]==0x2C) { // SDL
3484 emit_testimm(temp,4);
3487 emit_andimm(temp,~3,temp);
3488 emit_writeword_indexed(temp2,4,temp);
3489 set_jump_target(done0,(int)out);
3491 if (opcode[i]==0x2D) { // SDR
3492 emit_testimm(temp,4);
3495 emit_andimm(temp,~3,temp);
3496 emit_writeword_indexed(temp2,-4,temp);
3497 set_jump_target(done0,(int)out);
3500 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3503 int map=get_reg(i_regs->regmap,ROREG);
3504 if(map<0) map=HOST_TEMPREG;
3505 gen_orig_addr_w(temp,map);
3507 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3509 #if defined(HOST_IMM8)
3510 int ir=get_reg(i_regs->regmap,INVCP);
3512 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3514 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3516 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3517 emit_callne(invalidate_addr_reg[temp]);
3521 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3526 //save_regs(0x100f);
3527 emit_readword((int)&last_count,ECX);
3528 if(get_reg(i_regs->regmap,CCREG)<0)
3529 emit_loadreg(CCREG,HOST_CCREG);
3530 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3531 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3532 emit_writeword(HOST_CCREG,(int)&Count);
3533 emit_call((int)memdebug);
3535 //restore_regs(0x100f);
3539 void c1ls_assemble(int i,struct regstat *i_regs)
3541 #ifndef DISABLE_COP1
3547 int jaddr,jaddr2=0,jaddr3,type;
3548 int agr=AGEN1+(i&1);
3550 th=get_reg(i_regs->regmap,FTEMP|64);
3551 tl=get_reg(i_regs->regmap,FTEMP);
3552 s=get_reg(i_regs->regmap,rs1[i]);
3553 temp=get_reg(i_regs->regmap,agr);
3554 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3559 for(hr=0;hr<HOST_REGS;hr++) {
3560 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3562 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3563 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3565 // Loads use a temporary register which we need to save
3568 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3572 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3573 //else c=(i_regs->wasconst>>s)&1;
3574 if(s>=0) c=(i_regs->wasconst>>s)&1;
3575 // Check cop1 unusable
3577 signed char rs=get_reg(i_regs->regmap,CSREG);
3579 emit_testimm(rs,0x20000000);
3582 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3585 if (opcode[i]==0x39) { // SWC1 (get float address)
3586 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3588 if (opcode[i]==0x3D) { // SDC1 (get double address)
3589 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3591 // Generate address + offset
3594 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3598 map=get_reg(i_regs->regmap,TLREG);
3601 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3602 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3604 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3605 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3608 if (opcode[i]==0x39) { // SWC1 (read float)
3609 emit_readword_indexed(0,tl,tl);
3611 if (opcode[i]==0x3D) { // SDC1 (read double)
3612 emit_readword_indexed(4,tl,th);
3613 emit_readword_indexed(0,tl,tl);
3615 if (opcode[i]==0x31) { // LWC1 (get target address)
3616 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3618 if (opcode[i]==0x35) { // LDC1 (get target address)
3619 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3626 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3628 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3630 #ifdef DESTRUCTIVE_SHIFT
3631 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3632 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3636 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3637 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3639 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3640 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3643 if (opcode[i]==0x31) { // LWC1
3644 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3645 //gen_tlb_addr_r(ar,map);
3646 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3647 #ifdef HOST_IMM_ADDR32
3648 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3651 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3654 if (opcode[i]==0x35) { // LDC1
3656 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3657 //gen_tlb_addr_r(ar,map);
3658 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3659 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3660 #ifdef HOST_IMM_ADDR32
3661 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3664 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3667 if (opcode[i]==0x39) { // SWC1
3668 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3669 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3672 if (opcode[i]==0x3D) { // SDC1
3674 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3675 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3676 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3680 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3681 #ifndef DESTRUCTIVE_SHIFT
3682 temp=offset||c||s<0?ar:s;
3684 #if defined(HOST_IMM8)
3685 int ir=get_reg(i_regs->regmap,INVCP);
3687 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3689 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3691 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3692 emit_callne(invalidate_addr_reg[temp]);
3696 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3700 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3701 if (opcode[i]==0x31) { // LWC1 (write float)
3702 emit_writeword_indexed(tl,0,temp);
3704 if (opcode[i]==0x35) { // LDC1 (write double)
3705 emit_writeword_indexed(th,4,temp);
3706 emit_writeword_indexed(tl,0,temp);
3708 //if(opcode[i]==0x39)
3709 /*if(opcode[i]==0x39||opcode[i]==0x31)
3712 emit_readword((int)&last_count,ECX);
3713 if(get_reg(i_regs->regmap,CCREG)<0)
3714 emit_loadreg(CCREG,HOST_CCREG);
3715 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3716 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3717 emit_writeword(HOST_CCREG,(int)&Count);
3718 emit_call((int)memdebug);
3722 cop1_unusable(i, i_regs);
3726 void c2ls_assemble(int i,struct regstat *i_regs)
3731 int memtarget=0,c=0;
3732 int jaddr2=0,jaddr3,type;
3733 int agr=AGEN1+(i&1);
3735 u_int copr=(source[i]>>16)&0x1f;
3736 s=get_reg(i_regs->regmap,rs1[i]);
3737 tl=get_reg(i_regs->regmap,FTEMP);
3743 for(hr=0;hr<HOST_REGS;hr++) {
3744 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3746 if(i_regs->regmap[HOST_CCREG]==CCREG)
3747 reglist&=~(1<<HOST_CCREG);
3750 if (opcode[i]==0x3a) { // SWC2
3751 ar=get_reg(i_regs->regmap,agr);
3752 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3757 if(s>=0) c=(i_regs->wasconst>>s)&1;
3758 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3759 if (!offset&&!c&&s>=0) ar=s;
3762 if (opcode[i]==0x3a) { // SWC2
3763 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3771 emit_jmp(0); // inline_readstub/inline_writestub?
3775 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3779 if (opcode[i]==0x32) { // LWC2
3780 #ifdef HOST_IMM_ADDR32
3781 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3784 emit_readword_indexed(0,ar,tl);
3786 if (opcode[i]==0x3a) { // SWC2
3787 #ifdef DESTRUCTIVE_SHIFT
3788 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3790 emit_writeword_indexed(tl,0,ar);
3794 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3795 if (opcode[i]==0x3a) { // SWC2
3796 #if defined(HOST_IMM8)
3797 int ir=get_reg(i_regs->regmap,INVCP);
3799 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3801 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3803 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3804 emit_callne(invalidate_addr_reg[ar]);
3808 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3811 if (opcode[i]==0x32) { // LWC2
3812 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3816 #ifndef multdiv_assemble
3817 void multdiv_assemble(int i,struct regstat *i_regs)
3819 printf("Need multdiv_assemble for this architecture.\n");
3824 void mov_assemble(int i,struct regstat *i_regs)
3826 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3827 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3829 signed char sh,sl,th,tl;
3830 th=get_reg(i_regs->regmap,rt1[i]|64);
3831 tl=get_reg(i_regs->regmap,rt1[i]);
3834 sh=get_reg(i_regs->regmap,rs1[i]|64);
3835 sl=get_reg(i_regs->regmap,rs1[i]);
3836 if(sl>=0) emit_mov(sl,tl);
3837 else emit_loadreg(rs1[i],tl);
3839 if(sh>=0) emit_mov(sh,th);
3840 else emit_loadreg(rs1[i]|64,th);
3846 #ifndef fconv_assemble
3847 void fconv_assemble(int i,struct regstat *i_regs)
3849 printf("Need fconv_assemble for this architecture.\n");
3855 void float_assemble(int i,struct regstat *i_regs)
3857 printf("Need float_assemble for this architecture.\n");
3862 void syscall_assemble(int i,struct regstat *i_regs)
3864 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3865 assert(ccreg==HOST_CCREG);
3866 assert(!is_delayslot);
3867 emit_movimm(start+i*4,EAX); // Get PC
3868 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3869 emit_jmp((int)jump_syscall_hle); // XXX
3872 void hlecall_assemble(int i,struct regstat *i_regs)
3874 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3875 assert(ccreg==HOST_CCREG);
3876 assert(!is_delayslot);
3877 emit_movimm(start+i*4+4,0); // Get PC
3878 emit_movimm((int)psxHLEt[source[i]&7],1);
3879 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3880 emit_jmp((int)jump_hlecall);
3883 void intcall_assemble(int i,struct regstat *i_regs)
3885 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3886 assert(ccreg==HOST_CCREG);
3887 assert(!is_delayslot);
3888 emit_movimm(start+i*4,0); // Get PC
3889 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3890 emit_jmp((int)jump_intcall);
3893 void ds_assemble(int i,struct regstat *i_regs)
3898 alu_assemble(i,i_regs);break;
3900 imm16_assemble(i,i_regs);break;
3902 shift_assemble(i,i_regs);break;
3904 shiftimm_assemble(i,i_regs);break;
3906 load_assemble(i,i_regs);break;
3908 loadlr_assemble(i,i_regs);break;
3910 store_assemble(i,i_regs);break;
3912 storelr_assemble(i,i_regs);break;
3914 cop0_assemble(i,i_regs);break;
3916 cop1_assemble(i,i_regs);break;
3918 c1ls_assemble(i,i_regs);break;
3920 cop2_assemble(i,i_regs);break;
3922 c2ls_assemble(i,i_regs);break;
3924 c2op_assemble(i,i_regs);break;
3926 fconv_assemble(i,i_regs);break;
3928 float_assemble(i,i_regs);break;
3930 fcomp_assemble(i,i_regs);break;
3932 multdiv_assemble(i,i_regs);break;
3934 mov_assemble(i,i_regs);break;
3944 printf("Jump in the delay slot. This is probably a bug.\n");
3949 // Is the branch target a valid internal jump?
3950 int internal_branch(uint64_t i_is32,int addr)
3952 if(addr&1) return 0; // Indirect (register) jump
3953 if(addr>=start && addr<start+slen*4-4)
3955 int t=(addr-start)>>2;
3956 // Delay slots are not valid branch targets
3957 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3958 // 64 -> 32 bit transition requires a recompile
3959 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3961 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3962 else printf("optimizable: yes\n");
3964 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3966 if(requires_32bit[t]&~i_is32) return 0;
3974 #ifndef wb_invalidate
3975 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3976 uint64_t u,uint64_t uu)
3979 for(hr=0;hr<HOST_REGS;hr++) {
3980 if(hr!=EXCLUDE_REG) {
3981 if(pre[hr]!=entry[hr]) {
3984 if(get_reg(entry,pre[hr])<0) {
3986 if(!((u>>pre[hr])&1)) {
3987 emit_storereg(pre[hr],hr);
3988 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3989 emit_sarimm(hr,31,hr);
3990 emit_storereg(pre[hr]|64,hr);
3994 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3995 emit_storereg(pre[hr],hr);
4004 // Move from one register to another (no writeback)
4005 for(hr=0;hr<HOST_REGS;hr++) {
4006 if(hr!=EXCLUDE_REG) {
4007 if(pre[hr]!=entry[hr]) {
4008 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4010 if((nr=get_reg(entry,pre[hr]))>=0) {
4020 // Load the specified registers
4021 // This only loads the registers given as arguments because
4022 // we don't want to load things that will be overwritten
4023 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4027 for(hr=0;hr<HOST_REGS;hr++) {
4028 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4029 if(entry[hr]!=regmap[hr]) {
4030 if(regmap[hr]==rs1||regmap[hr]==rs2)
4037 emit_loadreg(regmap[hr],hr);
4044 for(hr=0;hr<HOST_REGS;hr++) {
4045 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4046 if(entry[hr]!=regmap[hr]) {
4047 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4049 assert(regmap[hr]!=64);
4050 if((is32>>(regmap[hr]&63))&1) {
4051 int lr=get_reg(regmap,regmap[hr]-64);
4053 emit_sarimm(lr,31,hr);
4055 emit_loadreg(regmap[hr],hr);
4059 emit_loadreg(regmap[hr],hr);
4067 // Load registers prior to the start of a loop
4068 // so that they are not loaded within the loop
4069 static void loop_preload(signed char pre[],signed char entry[])
4072 for(hr=0;hr<HOST_REGS;hr++) {
4073 if(hr!=EXCLUDE_REG) {
4074 if(pre[hr]!=entry[hr]) {
4076 if(get_reg(pre,entry[hr])<0) {
4077 assem_debug("loop preload:\n");
4078 //printf("loop preload: %d\n",hr);
4082 else if(entry[hr]<TEMPREG)
4084 emit_loadreg(entry[hr],hr);
4086 else if(entry[hr]-64<TEMPREG)
4088 emit_loadreg(entry[hr],hr);
4097 // Generate address for load/store instruction
4098 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4099 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4101 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4103 int agr=AGEN1+(i&1);
4104 int mgr=MGEN1+(i&1);
4105 if(itype[i]==LOAD) {
4106 ra=get_reg(i_regs->regmap,rt1[i]);
4107 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4110 if(itype[i]==LOADLR) {
4111 ra=get_reg(i_regs->regmap,FTEMP);
4113 if(itype[i]==STORE||itype[i]==STORELR) {
4114 ra=get_reg(i_regs->regmap,agr);
4115 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4117 if(itype[i]==C1LS||itype[i]==C2LS) {
4118 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4119 ra=get_reg(i_regs->regmap,FTEMP);
4120 else { // SWC1/SDC1/SWC2/SDC2
4121 ra=get_reg(i_regs->regmap,agr);
4122 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4125 int rs=get_reg(i_regs->regmap,rs1[i]);
4126 int rm=get_reg(i_regs->regmap,TLREG);
4129 int c=(i_regs->wasconst>>rs)&1;
4131 // Using r0 as a base address
4133 if(!entry||entry[rm]!=mgr) {
4134 generate_map_const(offset,rm);
4135 } // else did it in the previous cycle
4137 if(!entry||entry[ra]!=agr) {
4138 if (opcode[i]==0x22||opcode[i]==0x26) {
4139 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4140 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4141 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4143 emit_movimm(offset,ra);
4145 } // else did it in the previous cycle
4148 if(!entry||entry[ra]!=rs1[i])
4149 emit_loadreg(rs1[i],ra);
4150 //if(!entry||entry[ra]!=rs1[i])
4151 // printf("poor load scheduling!\n");
4155 if(!entry||entry[rm]!=mgr) {
4156 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4157 // Stores to memory go thru the mapper to detect self-modifying
4158 // code, loads don't.
4159 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4160 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4161 generate_map_const(constmap[i][rs]+offset,rm);
4163 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4164 generate_map_const(constmap[i][rs]+offset,rm);
4168 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4169 if(!entry||entry[ra]!=agr) {
4170 if (opcode[i]==0x22||opcode[i]==0x26) {
4171 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4172 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4173 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4175 #ifdef HOST_IMM_ADDR32
4176 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4177 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4179 emit_movimm(constmap[i][rs]+offset,ra);
4181 } // else did it in the previous cycle
4182 } // else load_consts already did it
4184 if(offset&&!c&&rs1[i]) {
4186 emit_addimm(rs,offset,ra);
4188 emit_addimm(ra,offset,ra);
4193 // Preload constants for next instruction
4194 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4196 #ifndef HOST_IMM_ADDR32
4198 agr=MGEN1+((i+1)&1);
4199 ra=get_reg(i_regs->regmap,agr);
4201 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4202 int offset=imm[i+1];
4203 int c=(regs[i+1].wasconst>>rs)&1;
4205 if(itype[i+1]==STORE||itype[i+1]==STORELR
4206 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4207 // Stores to memory go thru the mapper to detect self-modifying
4208 // code, loads don't.
4209 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4210 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4211 generate_map_const(constmap[i+1][rs]+offset,ra);
4213 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4214 generate_map_const(constmap[i+1][rs]+offset,ra);
4217 /*else if(rs1[i]==0) {
4218 generate_map_const(offset,ra);
4223 agr=AGEN1+((i+1)&1);
4224 ra=get_reg(i_regs->regmap,agr);
4226 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4227 int offset=imm[i+1];
4228 int c=(regs[i+1].wasconst>>rs)&1;
4229 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4230 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4231 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4232 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4233 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4235 #ifdef HOST_IMM_ADDR32
4236 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4237 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4239 emit_movimm(constmap[i+1][rs]+offset,ra);
4242 else if(rs1[i+1]==0) {
4243 // Using r0 as a base address
4244 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4245 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4246 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4247 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4249 emit_movimm(offset,ra);
4256 int get_final_value(int hr, int i, int *value)
4258 int reg=regs[i].regmap[hr];
4260 if(regs[i+1].regmap[hr]!=reg) break;
4261 if(!((regs[i+1].isconst>>hr)&1)) break;
4266 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4267 *value=constmap[i][hr];
4271 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4272 // Load in delay slot, out-of-order execution
4273 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4275 #ifdef HOST_IMM_ADDR32
4276 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4278 // Precompute load address
4279 *value=constmap[i][hr]+imm[i+2];
4283 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4285 #ifdef HOST_IMM_ADDR32
4286 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4288 // Precompute load address
4289 *value=constmap[i][hr]+imm[i+1];
4290 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4295 *value=constmap[i][hr];
4296 //printf("c=%x\n",(int)constmap[i][hr]);
4297 if(i==slen-1) return 1;
4299 return !((unneeded_reg[i+1]>>reg)&1);
4301 return !((unneeded_reg_upper[i+1]>>reg)&1);
4305 // Load registers with known constants
4306 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4310 for(hr=0;hr<HOST_REGS;hr++) {
4311 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4312 //if(entry[hr]!=regmap[hr]) {
4313 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4314 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4316 if(get_final_value(hr,i,&value)) {
4321 emit_movimm(value,hr);
4329 for(hr=0;hr<HOST_REGS;hr++) {
4330 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4331 //if(entry[hr]!=regmap[hr]) {
4332 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4333 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4334 if((is32>>(regmap[hr]&63))&1) {
4335 int lr=get_reg(regmap,regmap[hr]-64);
4337 emit_sarimm(lr,31,hr);
4342 if(get_final_value(hr,i,&value)) {
4347 emit_movimm(value,hr);
4356 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4360 for(hr=0;hr<HOST_REGS;hr++) {
4361 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4362 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4363 int value=constmap[i][hr];
4368 emit_movimm(value,hr);
4374 for(hr=0;hr<HOST_REGS;hr++) {
4375 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4376 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4377 if((is32>>(regmap[hr]&63))&1) {
4378 int lr=get_reg(regmap,regmap[hr]-64);
4380 emit_sarimm(lr,31,hr);
4384 int value=constmap[i][hr];
4389 emit_movimm(value,hr);
4397 // Write out all dirty registers (except cycle count)
4398 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4401 for(hr=0;hr<HOST_REGS;hr++) {
4402 if(hr!=EXCLUDE_REG) {
4403 if(i_regmap[hr]>0) {
4404 if(i_regmap[hr]!=CCREG) {
4405 if((i_dirty>>hr)&1) {
4406 if(i_regmap[hr]<64) {
4407 emit_storereg(i_regmap[hr],hr);
4409 if( ((i_is32>>i_regmap[hr])&1) ) {
4410 #ifdef DESTRUCTIVE_WRITEBACK
4411 emit_sarimm(hr,31,hr);
4412 emit_storereg(i_regmap[hr]|64,hr);
4414 emit_sarimm(hr,31,HOST_TEMPREG);
4415 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4420 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4421 emit_storereg(i_regmap[hr],hr);
4430 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4431 // This writes the registers not written by store_regs_bt
4432 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4435 int t=(addr-start)>>2;
4436 for(hr=0;hr<HOST_REGS;hr++) {
4437 if(hr!=EXCLUDE_REG) {
4438 if(i_regmap[hr]>0) {
4439 if(i_regmap[hr]!=CCREG) {
4440 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4441 if((i_dirty>>hr)&1) {
4442 if(i_regmap[hr]<64) {
4443 emit_storereg(i_regmap[hr],hr);
4445 if( ((i_is32>>i_regmap[hr])&1) ) {
4446 #ifdef DESTRUCTIVE_WRITEBACK
4447 emit_sarimm(hr,31,hr);
4448 emit_storereg(i_regmap[hr]|64,hr);
4450 emit_sarimm(hr,31,HOST_TEMPREG);
4451 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4456 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4457 emit_storereg(i_regmap[hr],hr);
4468 // Load all registers (except cycle count)
4469 void load_all_regs(signed char i_regmap[])
4472 for(hr=0;hr<HOST_REGS;hr++) {
4473 if(hr!=EXCLUDE_REG) {
4474 if(i_regmap[hr]==0) {
4478 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4480 emit_loadreg(i_regmap[hr],hr);
4486 // Load all current registers also needed by next instruction
4487 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4490 for(hr=0;hr<HOST_REGS;hr++) {
4491 if(hr!=EXCLUDE_REG) {
4492 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4493 if(i_regmap[hr]==0) {
4497 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4499 emit_loadreg(i_regmap[hr],hr);
4506 // Load all regs, storing cycle count if necessary
4507 void load_regs_entry(int t)
4510 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4511 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4512 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4513 emit_storereg(CCREG,HOST_CCREG);
4516 for(hr=0;hr<HOST_REGS;hr++) {
4517 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4518 if(regs[t].regmap_entry[hr]==0) {
4521 else if(regs[t].regmap_entry[hr]!=CCREG)
4523 emit_loadreg(regs[t].regmap_entry[hr],hr);
4528 for(hr=0;hr<HOST_REGS;hr++) {
4529 if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4530 assert(regs[t].regmap_entry[hr]!=64);
4531 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4532 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4534 emit_loadreg(regs[t].regmap_entry[hr],hr);
4538 emit_sarimm(lr,31,hr);
4543 emit_loadreg(regs[t].regmap_entry[hr],hr);
4549 // Store dirty registers prior to branch
4550 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4552 if(internal_branch(i_is32,addr))
4554 int t=(addr-start)>>2;
4556 for(hr=0;hr<HOST_REGS;hr++) {
4557 if(hr!=EXCLUDE_REG) {
4558 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4559 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4560 if((i_dirty>>hr)&1) {
4561 if(i_regmap[hr]<64) {
4562 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4563 emit_storereg(i_regmap[hr],hr);
4564 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4565 #ifdef DESTRUCTIVE_WRITEBACK
4566 emit_sarimm(hr,31,hr);
4567 emit_storereg(i_regmap[hr]|64,hr);
4569 emit_sarimm(hr,31,HOST_TEMPREG);
4570 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4575 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4576 emit_storereg(i_regmap[hr],hr);
4587 // Branch out of this block, write out all dirty regs
4588 wb_dirtys(i_regmap,i_is32,i_dirty);
4592 // Load all needed registers for branch target
4593 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4595 //if(addr>=start && addr<(start+slen*4))
4596 if(internal_branch(i_is32,addr))
4598 int t=(addr-start)>>2;
4600 // Store the cycle count before loading something else
4601 if(i_regmap[HOST_CCREG]!=CCREG) {
4602 assert(i_regmap[HOST_CCREG]==-1);
4604 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4605 emit_storereg(CCREG,HOST_CCREG);
4608 for(hr=0;hr<HOST_REGS;hr++) {
4609 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4610 #ifdef DESTRUCTIVE_WRITEBACK
4611 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4613 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4615 if(regs[t].regmap_entry[hr]==0) {
4618 else if(regs[t].regmap_entry[hr]!=CCREG)
4620 emit_loadreg(regs[t].regmap_entry[hr],hr);
4626 for(hr=0;hr<HOST_REGS;hr++) {
4627 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4628 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4629 assert(regs[t].regmap_entry[hr]!=64);
4630 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4631 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4633 emit_loadreg(regs[t].regmap_entry[hr],hr);
4637 emit_sarimm(lr,31,hr);
4642 emit_loadreg(regs[t].regmap_entry[hr],hr);
4645 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4646 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4648 emit_sarimm(lr,31,hr);
4655 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4657 if(addr>=start && addr<start+slen*4-4)
4659 int t=(addr-start)>>2;
4661 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4662 for(hr=0;hr<HOST_REGS;hr++)
4666 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4668 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4675 if(i_regmap[hr]<TEMPREG)
4677 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4680 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4682 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4687 else // Same register but is it 32-bit or dirty?
4690 if(!((regs[t].dirty>>hr)&1))
4694 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4696 //printf("%x: dirty no match\n",addr);
4701 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4703 //printf("%x: is32 no match\n",addr);
4709 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4711 if(requires_32bit[t]&~i_is32) return 0;
4713 // Delay slots are not valid branch targets
4714 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4715 // Delay slots require additional processing, so do not match
4716 if(is_ds[t]) return 0;
4721 for(hr=0;hr<HOST_REGS;hr++)
4727 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4741 // Used when a branch jumps into the delay slot of another branch
4742 void ds_assemble_entry(int i)
4744 int t=(ba[i]-start)>>2;
4745 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4746 assem_debug("Assemble delay slot at %x\n",ba[i]);
4747 assem_debug("<->\n");
4748 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4749 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4750 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4751 address_generation(t,®s[t],regs[t].regmap_entry);
4752 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4753 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4758 alu_assemble(t,®s[t]);break;
4760 imm16_assemble(t,®s[t]);break;
4762 shift_assemble(t,®s[t]);break;
4764 shiftimm_assemble(t,®s[t]);break;
4766 load_assemble(t,®s[t]);break;
4768 loadlr_assemble(t,®s[t]);break;
4770 store_assemble(t,®s[t]);break;
4772 storelr_assemble(t,®s[t]);break;
4774 cop0_assemble(t,®s[t]);break;
4776 cop1_assemble(t,®s[t]);break;
4778 c1ls_assemble(t,®s[t]);break;
4780 cop2_assemble(t,®s[t]);break;
4782 c2ls_assemble(t,®s[t]);break;
4784 c2op_assemble(t,®s[t]);break;
4786 fconv_assemble(t,®s[t]);break;
4788 float_assemble(t,®s[t]);break;
4790 fcomp_assemble(t,®s[t]);break;
4792 multdiv_assemble(t,®s[t]);break;
4794 mov_assemble(t,®s[t]);break;
4804 printf("Jump in the delay slot. This is probably a bug.\n");
4806 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4807 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4808 if(internal_branch(regs[t].is32,ba[i]+4))
4809 assem_debug("branch: internal\n");
4811 assem_debug("branch: external\n");
4812 assert(internal_branch(regs[t].is32,ba[i]+4));
4813 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4817 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4826 //if(ba[i]>=start && ba[i]<(start+slen*4))
4827 if(internal_branch(branch_regs[i].is32,ba[i]))
4829 int t=(ba[i]-start)>>2;
4830 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4838 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4840 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4842 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4843 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4847 else if(*adj==0||invert) {
4848 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4854 emit_cmpimm(HOST_CCREG,-CLOCK_DIVIDER*(count+2));
4858 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4861 void do_ccstub(int n)
4864 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4865 set_jump_target(stubs[n][1],(int)out);
4867 if(stubs[n][6]==NULLDS) {
4868 // Delay slot instruction is nullified ("likely" branch)
4869 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4871 else if(stubs[n][6]!=TAKEN) {
4872 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4875 if(internal_branch(branch_regs[i].is32,ba[i]))
4876 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4880 // Save PC as return address
4881 emit_movimm(stubs[n][5],EAX);
4882 emit_writeword(EAX,(int)&pcaddr);
4886 // Return address depends on which way the branch goes
4887 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4889 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4890 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4891 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4892 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4902 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4906 #ifdef DESTRUCTIVE_WRITEBACK
4908 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4909 emit_loadreg(rs1[i],s1l);
4912 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4913 emit_loadreg(rs2[i],s1l);
4916 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4917 emit_loadreg(rs2[i],s2l);
4920 int addr=-1,alt=-1,ntaddr=-1;
4923 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4924 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4925 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4933 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4934 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4935 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4941 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4945 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4946 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4947 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4953 assert(hr<HOST_REGS);
4955 if((opcode[i]&0x2f)==4) // BEQ
4957 #ifdef HAVE_CMOV_IMM
4959 if(s2l>=0) emit_cmp(s1l,s2l);
4960 else emit_test(s1l,s1l);
4961 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4966 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4968 if(s2h>=0) emit_cmp(s1h,s2h);
4969 else emit_test(s1h,s1h);
4970 emit_cmovne_reg(alt,addr);
4972 if(s2l>=0) emit_cmp(s1l,s2l);
4973 else emit_test(s1l,s1l);
4974 emit_cmovne_reg(alt,addr);
4977 if((opcode[i]&0x2f)==5) // BNE
4979 #ifdef HAVE_CMOV_IMM
4981 if(s2l>=0) emit_cmp(s1l,s2l);
4982 else emit_test(s1l,s1l);
4983 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4988 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4990 if(s2h>=0) emit_cmp(s1h,s2h);
4991 else emit_test(s1h,s1h);
4992 emit_cmovne_reg(alt,addr);
4994 if(s2l>=0) emit_cmp(s1l,s2l);
4995 else emit_test(s1l,s1l);
4996 emit_cmovne_reg(alt,addr);
4999 if((opcode[i]&0x2f)==6) // BLEZ
5001 //emit_movimm(ba[i],alt);
5002 //emit_movimm(start+i*4+8,addr);
5003 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5005 if(s1h>=0) emit_mov(addr,ntaddr);
5006 emit_cmovl_reg(alt,addr);
5009 emit_cmovne_reg(ntaddr,addr);
5010 emit_cmovs_reg(alt,addr);
5013 if((opcode[i]&0x2f)==7) // BGTZ
5015 //emit_movimm(ba[i],addr);
5016 //emit_movimm(start+i*4+8,ntaddr);
5017 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5019 if(s1h>=0) emit_mov(addr,alt);
5020 emit_cmovl_reg(ntaddr,addr);
5023 emit_cmovne_reg(alt,addr);
5024 emit_cmovs_reg(ntaddr,addr);
5027 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5029 //emit_movimm(ba[i],alt);
5030 //emit_movimm(start+i*4+8,addr);
5031 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5032 if(s1h>=0) emit_test(s1h,s1h);
5033 else emit_test(s1l,s1l);
5034 emit_cmovs_reg(alt,addr);
5036 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5038 //emit_movimm(ba[i],addr);
5039 //emit_movimm(start+i*4+8,alt);
5040 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5041 if(s1h>=0) emit_test(s1h,s1h);
5042 else emit_test(s1l,s1l);
5043 emit_cmovs_reg(alt,addr);
5045 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5046 if(source[i]&0x10000) // BC1T
5048 //emit_movimm(ba[i],alt);
5049 //emit_movimm(start+i*4+8,addr);
5050 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5051 emit_testimm(s1l,0x800000);
5052 emit_cmovne_reg(alt,addr);
5056 //emit_movimm(ba[i],addr);
5057 //emit_movimm(start+i*4+8,alt);
5058 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5059 emit_testimm(s1l,0x800000);
5060 emit_cmovne_reg(alt,addr);
5063 emit_writeword(addr,(int)&pcaddr);
5068 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5069 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5070 r=get_reg(branch_regs[i].regmap,RTEMP);
5072 emit_writeword(r,(int)&pcaddr);
5074 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5076 // Update cycle count
5077 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5078 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5079 emit_call((int)cc_interrupt);
5080 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5081 if(stubs[n][6]==TAKEN) {
5082 if(internal_branch(branch_regs[i].is32,ba[i]))
5083 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5084 else if(itype[i]==RJUMP) {
5085 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5086 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5088 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5090 }else if(stubs[n][6]==NOTTAKEN) {
5091 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5092 else load_all_regs(branch_regs[i].regmap);
5093 }else if(stubs[n][6]==NULLDS) {
5094 // Delay slot instruction is nullified ("likely" branch)
5095 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5096 else load_all_regs(regs[i].regmap);
5098 load_all_regs(branch_regs[i].regmap);
5100 emit_jmp(stubs[n][2]); // return address
5102 /* This works but uses a lot of memory...
5103 emit_readword((int)&last_count,ECX);
5104 emit_add(HOST_CCREG,ECX,EAX);
5105 emit_writeword(EAX,(int)&Count);
5106 emit_call((int)gen_interupt);
5107 emit_readword((int)&Count,HOST_CCREG);
5108 emit_readword((int)&next_interupt,EAX);
5109 emit_readword((int)&pending_exception,EBX);
5110 emit_writeword(EAX,(int)&last_count);
5111 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5113 int jne_instr=(int)out;
5115 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5116 load_all_regs(branch_regs[i].regmap);
5117 emit_jmp(stubs[n][2]); // return address
5118 set_jump_target(jne_instr,(int)out);
5119 emit_readword((int)&pcaddr,EAX);
5120 // Call get_addr_ht instead of doing the hash table here.
5121 // This code is executed infrequently and takes up a lot of space
5122 // so smaller is better.
5123 emit_storereg(CCREG,HOST_CCREG);
5125 emit_call((int)get_addr_ht);
5126 emit_loadreg(CCREG,HOST_CCREG);
5127 emit_addimm(ESP,4,ESP);
5131 add_to_linker(int addr,int target,int ext)
5133 link_addr[linkcount][0]=addr;
5134 link_addr[linkcount][1]=target;
5135 link_addr[linkcount][2]=ext;
5139 void ujump_assemble(int i,struct regstat *i_regs)
5141 signed char *i_regmap=i_regs->regmap;
5142 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5143 address_generation(i+1,i_regs,regs[i].regmap_entry);
5145 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5146 if(rt1[i]==31&&temp>=0)
5148 int return_address=start+i*4+8;
5149 if(get_reg(branch_regs[i].regmap,31)>0)
5150 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5155 unsigned int return_address;
5156 rt=get_reg(branch_regs[i].regmap,31);
5157 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5159 return_address=start+i*4+8;
5162 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5163 int temp=-1; // note: must be ds-safe
5167 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5168 else emit_movimm(return_address,rt);
5176 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5179 emit_movimm(return_address,rt); // PC into link register
5181 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5186 ds_assemble(i+1,i_regs);
5187 uint64_t bc_unneeded=branch_regs[i].u;
5188 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5189 bc_unneeded|=1|(1LL<<rt1[i]);
5190 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5191 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5192 bc_unneeded,bc_unneeded_upper);
5193 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5195 cc=get_reg(branch_regs[i].regmap,CCREG);
5196 assert(cc==HOST_CCREG);
5197 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5199 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5201 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5202 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5203 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5204 if(internal_branch(branch_regs[i].is32,ba[i]))
5205 assem_debug("branch: internal\n");
5207 assem_debug("branch: external\n");
5208 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5209 ds_assemble_entry(i);
5212 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5217 void rjump_assemble(int i,struct regstat *i_regs)
5219 signed char *i_regmap=i_regs->regmap;
5222 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5224 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5225 // Delay slot abuse, make a copy of the branch address register
5226 temp=get_reg(branch_regs[i].regmap,RTEMP);
5228 assert(regs[i].regmap[temp]==RTEMP);
5232 address_generation(i+1,i_regs,regs[i].regmap_entry);
5236 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5237 int return_address=start+i*4+8;
5238 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5244 int rh=get_reg(regs[i].regmap,RHASH);
5245 if(rh>=0) do_preload_rhash(rh);
5248 ds_assemble(i+1,i_regs);
5249 uint64_t bc_unneeded=branch_regs[i].u;
5250 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5251 bc_unneeded|=1|(1LL<<rt1[i]);
5252 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5253 bc_unneeded&=~(1LL<<rs1[i]);
5254 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5255 bc_unneeded,bc_unneeded_upper);
5256 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5258 int rt,return_address;
5259 assert(rt1[i+1]!=rt1[i]);
5260 assert(rt2[i+1]!=rt1[i]);
5261 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5262 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5264 return_address=start+i*4+8;
5268 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5271 emit_movimm(return_address,rt); // PC into link register
5273 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5276 cc=get_reg(branch_regs[i].regmap,CCREG);
5277 assert(cc==HOST_CCREG);
5279 int rh=get_reg(branch_regs[i].regmap,RHASH);
5280 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5282 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5283 do_preload_rhtbl(ht);
5287 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5288 #ifdef DESTRUCTIVE_WRITEBACK
5289 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5290 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5291 emit_loadreg(rs1[i],rs);
5296 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5300 do_miniht_load(ht,rh);
5303 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5304 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5306 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5307 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5309 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5312 do_miniht_jump(rs,rh,ht);
5317 //if(rs!=EAX) emit_mov(rs,EAX);
5318 //emit_jmp((int)jump_vaddr_eax);
5319 emit_jmp(jump_vaddr_reg[rs]);
5324 emit_shrimm(rs,16,rs);
5325 emit_xor(temp,rs,rs);
5326 emit_movzwl_reg(rs,rs);
5327 emit_shlimm(rs,4,rs);
5328 emit_cmpmem_indexed((int)hash_table,rs,temp);
5329 emit_jne((int)out+14);
5330 emit_readword_indexed((int)hash_table+4,rs,rs);
5332 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5333 emit_addimm_no_flags(8,rs);
5334 emit_jeq((int)out-17);
5335 // No hit on hash table, call compiler
5338 #ifdef DEBUG_CYCLE_COUNT
5339 emit_readword((int)&last_count,ECX);
5340 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5341 emit_readword((int)&next_interupt,ECX);
5342 emit_writeword(HOST_CCREG,(int)&Count);
5343 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5344 emit_writeword(ECX,(int)&last_count);
5347 emit_storereg(CCREG,HOST_CCREG);
5348 emit_call((int)get_addr);
5349 emit_loadreg(CCREG,HOST_CCREG);
5350 emit_addimm(ESP,4,ESP);
5352 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5353 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5357 void cjump_assemble(int i,struct regstat *i_regs)
5359 signed char *i_regmap=i_regs->regmap;
5362 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5363 assem_debug("match=%d\n",match);
5364 int s1h,s1l,s2h,s2l;
5365 int prev_cop1_usable=cop1_usable;
5366 int unconditional=0,nop=0;
5369 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5370 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5371 if(!match) invert=1;
5372 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5373 if(i>(ba[i]-start)>>2) invert=1;
5377 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5378 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5379 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5380 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5383 s1l=get_reg(i_regmap,rs1[i]);
5384 s1h=get_reg(i_regmap,rs1[i]|64);
5385 s2l=get_reg(i_regmap,rs2[i]);
5386 s2h=get_reg(i_regmap,rs2[i]|64);
5388 if(rs1[i]==0&&rs2[i]==0)
5390 if(opcode[i]&1) nop=1;
5391 else unconditional=1;
5392 //assert(opcode[i]!=5);
5393 //assert(opcode[i]!=7);
5394 //assert(opcode[i]!=0x15);
5395 //assert(opcode[i]!=0x17);
5401 only32=(regs[i].was32>>rs2[i])&1;
5406 only32=(regs[i].was32>>rs1[i])&1;
5409 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5413 // Out of order execution (delay slot first)
5415 address_generation(i+1,i_regs,regs[i].regmap_entry);
5416 ds_assemble(i+1,i_regs);
5418 uint64_t bc_unneeded=branch_regs[i].u;
5419 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5420 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5421 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5423 bc_unneeded_upper|=1;
5424 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5425 bc_unneeded,bc_unneeded_upper);
5426 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5427 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5428 cc=get_reg(branch_regs[i].regmap,CCREG);
5429 assert(cc==HOST_CCREG);
5431 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5432 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5433 //assem_debug("cycle count (adj)\n");
5435 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5436 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5437 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5438 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5440 assem_debug("branch: internal\n");
5442 assem_debug("branch: external\n");
5443 if(internal&&is_ds[(ba[i]-start)>>2]) {
5444 ds_assemble_entry(i);
5447 add_to_linker((int)out,ba[i],internal);
5450 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5451 if(((u_int)out)&7) emit_addnop(0);
5456 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5459 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5462 int taken=0,nottaken=0,nottaken1=0;
5463 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5464 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5468 if(opcode[i]==4) // BEQ
5470 if(s2h>=0) emit_cmp(s1h,s2h);
5471 else emit_test(s1h,s1h);
5475 if(opcode[i]==5) // BNE
5477 if(s2h>=0) emit_cmp(s1h,s2h);
5478 else emit_test(s1h,s1h);
5479 if(invert) taken=(int)out;
5480 else add_to_linker((int)out,ba[i],internal);
5483 if(opcode[i]==6) // BLEZ
5486 if(invert) taken=(int)out;
5487 else add_to_linker((int)out,ba[i],internal);
5492 if(opcode[i]==7) // BGTZ
5497 if(invert) taken=(int)out;
5498 else add_to_linker((int)out,ba[i],internal);
5503 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5505 if(opcode[i]==4) // BEQ
5507 if(s2l>=0) emit_cmp(s1l,s2l);
5508 else emit_test(s1l,s1l);
5513 add_to_linker((int)out,ba[i],internal);
5517 if(opcode[i]==5) // BNE
5519 if(s2l>=0) emit_cmp(s1l,s2l);
5520 else emit_test(s1l,s1l);
5525 add_to_linker((int)out,ba[i],internal);
5529 if(opcode[i]==6) // BLEZ
5536 add_to_linker((int)out,ba[i],internal);
5540 if(opcode[i]==7) // BGTZ
5547 add_to_linker((int)out,ba[i],internal);
5552 if(taken) set_jump_target(taken,(int)out);
5553 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5554 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5556 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5557 add_to_linker((int)out,ba[i],internal);
5560 add_to_linker((int)out,ba[i],internal*2);
5566 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5567 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5568 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5570 assem_debug("branch: internal\n");
5572 assem_debug("branch: external\n");
5573 if(internal&&is_ds[(ba[i]-start)>>2]) {
5574 ds_assemble_entry(i);
5577 add_to_linker((int)out,ba[i],internal);
5581 set_jump_target(nottaken,(int)out);
5584 if(nottaken1) set_jump_target(nottaken1,(int)out);
5586 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5588 } // (!unconditional)
5592 // In-order execution (branch first)
5593 //if(likely[i]) printf("IOL\n");
5596 int taken=0,nottaken=0,nottaken1=0;
5597 if(!unconditional&&!nop) {
5601 if((opcode[i]&0x2f)==4) // BEQ
5603 if(s2h>=0) emit_cmp(s1h,s2h);
5604 else emit_test(s1h,s1h);
5608 if((opcode[i]&0x2f)==5) // BNE
5610 if(s2h>=0) emit_cmp(s1h,s2h);
5611 else emit_test(s1h,s1h);
5615 if((opcode[i]&0x2f)==6) // BLEZ
5623 if((opcode[i]&0x2f)==7) // BGTZ
5633 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5635 if((opcode[i]&0x2f)==4) // BEQ
5637 if(s2l>=0) emit_cmp(s1l,s2l);
5638 else emit_test(s1l,s1l);
5642 if((opcode[i]&0x2f)==5) // BNE
5644 if(s2l>=0) emit_cmp(s1l,s2l);
5645 else emit_test(s1l,s1l);
5649 if((opcode[i]&0x2f)==6) // BLEZ
5655 if((opcode[i]&0x2f)==7) // BGTZ
5661 } // if(!unconditional)
5663 uint64_t ds_unneeded=branch_regs[i].u;
5664 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5665 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5666 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5667 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5669 ds_unneeded_upper|=1;
5672 if(taken) set_jump_target(taken,(int)out);
5673 assem_debug("1:\n");
5674 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5675 ds_unneeded,ds_unneeded_upper);
5677 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5678 address_generation(i+1,&branch_regs[i],0);
5679 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5680 ds_assemble(i+1,&branch_regs[i]);
5681 cc=get_reg(branch_regs[i].regmap,CCREG);
5683 emit_loadreg(CCREG,cc=HOST_CCREG);
5684 // CHECK: Is the following instruction (fall thru) allocated ok?
5686 assert(cc==HOST_CCREG);
5687 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5688 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5689 assem_debug("cycle count (adj)\n");
5690 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5691 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5693 assem_debug("branch: internal\n");
5695 assem_debug("branch: external\n");
5696 if(internal&&is_ds[(ba[i]-start)>>2]) {
5697 ds_assemble_entry(i);
5700 add_to_linker((int)out,ba[i],internal);
5705 cop1_usable=prev_cop1_usable;
5706 if(!unconditional) {
5707 if(nottaken1) set_jump_target(nottaken1,(int)out);
5708 set_jump_target(nottaken,(int)out);
5709 assem_debug("2:\n");
5711 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5712 ds_unneeded,ds_unneeded_upper);
5713 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5714 address_generation(i+1,&branch_regs[i],0);
5715 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5716 ds_assemble(i+1,&branch_regs[i]);
5718 cc=get_reg(branch_regs[i].regmap,CCREG);
5719 if(cc==-1&&!likely[i]) {
5720 // Cycle count isn't in a register, temporarily load it then write it out
5721 emit_loadreg(CCREG,HOST_CCREG);
5722 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5725 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5726 emit_storereg(CCREG,HOST_CCREG);
5729 cc=get_reg(i_regmap,CCREG);
5730 assert(cc==HOST_CCREG);
5731 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5734 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5740 void sjump_assemble(int i,struct regstat *i_regs)
5742 signed char *i_regmap=i_regs->regmap;
5745 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5746 assem_debug("smatch=%d\n",match);
5748 int prev_cop1_usable=cop1_usable;
5749 int unconditional=0,nevertaken=0;
5752 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5753 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5754 if(!match) invert=1;
5755 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5756 if(i>(ba[i]-start)>>2) invert=1;
5759 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5760 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5763 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5764 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5767 s1l=get_reg(i_regmap,rs1[i]);
5768 s1h=get_reg(i_regmap,rs1[i]|64);
5772 if(opcode2[i]&1) unconditional=1;
5774 // These are never taken (r0 is never less than zero)
5775 //assert(opcode2[i]!=0);
5776 //assert(opcode2[i]!=2);
5777 //assert(opcode2[i]!=0x10);
5778 //assert(opcode2[i]!=0x12);
5781 only32=(regs[i].was32>>rs1[i])&1;
5785 // Out of order execution (delay slot first)
5787 address_generation(i+1,i_regs,regs[i].regmap_entry);
5788 ds_assemble(i+1,i_regs);
5790 uint64_t bc_unneeded=branch_regs[i].u;
5791 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5792 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5793 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5795 bc_unneeded_upper|=1;
5796 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5797 bc_unneeded,bc_unneeded_upper);
5798 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5799 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5801 int rt,return_address;
5802 rt=get_reg(branch_regs[i].regmap,31);
5803 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5805 // Save the PC even if the branch is not taken
5806 return_address=start+i*4+8;
5807 emit_movimm(return_address,rt); // PC into link register
5809 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5813 cc=get_reg(branch_regs[i].regmap,CCREG);
5814 assert(cc==HOST_CCREG);
5816 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5817 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5818 assem_debug("cycle count (adj)\n");
5820 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5821 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5822 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5823 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5825 assem_debug("branch: internal\n");
5827 assem_debug("branch: external\n");
5828 if(internal&&is_ds[(ba[i]-start)>>2]) {
5829 ds_assemble_entry(i);
5832 add_to_linker((int)out,ba[i],internal);
5835 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5836 if(((u_int)out)&7) emit_addnop(0);
5840 else if(nevertaken) {
5841 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5844 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5848 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5849 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5853 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5860 add_to_linker((int)out,ba[i],internal);
5864 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5871 add_to_linker((int)out,ba[i],internal);
5879 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5886 add_to_linker((int)out,ba[i],internal);
5890 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5897 add_to_linker((int)out,ba[i],internal);
5904 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5905 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5907 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5908 add_to_linker((int)out,ba[i],internal);
5911 add_to_linker((int)out,ba[i],internal*2);
5917 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5918 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5919 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5921 assem_debug("branch: internal\n");
5923 assem_debug("branch: external\n");
5924 if(internal&&is_ds[(ba[i]-start)>>2]) {
5925 ds_assemble_entry(i);
5928 add_to_linker((int)out,ba[i],internal);
5932 set_jump_target(nottaken,(int)out);
5936 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5938 } // (!unconditional)
5942 // In-order execution (branch first)
5946 int rt,return_address;
5947 rt=get_reg(branch_regs[i].regmap,31);
5949 // Save the PC even if the branch is not taken
5950 return_address=start+i*4+8;
5951 emit_movimm(return_address,rt); // PC into link register
5953 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5957 if(!unconditional) {
5958 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5962 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5968 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5978 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5984 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5991 } // if(!unconditional)
5993 uint64_t ds_unneeded=branch_regs[i].u;
5994 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5995 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5996 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5997 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5999 ds_unneeded_upper|=1;
6002 //assem_debug("1:\n");
6003 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6004 ds_unneeded,ds_unneeded_upper);
6006 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6007 address_generation(i+1,&branch_regs[i],0);
6008 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6009 ds_assemble(i+1,&branch_regs[i]);
6010 cc=get_reg(branch_regs[i].regmap,CCREG);
6012 emit_loadreg(CCREG,cc=HOST_CCREG);
6013 // CHECK: Is the following instruction (fall thru) allocated ok?
6015 assert(cc==HOST_CCREG);
6016 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6017 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6018 assem_debug("cycle count (adj)\n");
6019 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6020 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6022 assem_debug("branch: internal\n");
6024 assem_debug("branch: external\n");
6025 if(internal&&is_ds[(ba[i]-start)>>2]) {
6026 ds_assemble_entry(i);
6029 add_to_linker((int)out,ba[i],internal);
6034 cop1_usable=prev_cop1_usable;
6035 if(!unconditional) {
6036 set_jump_target(nottaken,(int)out);
6037 assem_debug("1:\n");
6039 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6040 ds_unneeded,ds_unneeded_upper);
6041 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6042 address_generation(i+1,&branch_regs[i],0);
6043 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6044 ds_assemble(i+1,&branch_regs[i]);
6046 cc=get_reg(branch_regs[i].regmap,CCREG);
6047 if(cc==-1&&!likely[i]) {
6048 // Cycle count isn't in a register, temporarily load it then write it out
6049 emit_loadreg(CCREG,HOST_CCREG);
6050 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6053 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6054 emit_storereg(CCREG,HOST_CCREG);
6057 cc=get_reg(i_regmap,CCREG);
6058 assert(cc==HOST_CCREG);
6059 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6062 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6068 void fjump_assemble(int i,struct regstat *i_regs)
6070 signed char *i_regmap=i_regs->regmap;
6073 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6074 assem_debug("fmatch=%d\n",match);
6078 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6079 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6080 if(!match) invert=1;
6081 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6082 if(i>(ba[i]-start)>>2) invert=1;
6086 fs=get_reg(branch_regs[i].regmap,FSREG);
6087 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6090 fs=get_reg(i_regmap,FSREG);
6093 // Check cop1 unusable
6095 cs=get_reg(i_regmap,CSREG);
6097 emit_testimm(cs,0x20000000);
6100 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6105 // Out of order execution (delay slot first)
6107 ds_assemble(i+1,i_regs);
6109 uint64_t bc_unneeded=branch_regs[i].u;
6110 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6111 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6112 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6114 bc_unneeded_upper|=1;
6115 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6116 bc_unneeded,bc_unneeded_upper);
6117 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6118 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6119 cc=get_reg(branch_regs[i].regmap,CCREG);
6120 assert(cc==HOST_CCREG);
6121 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6122 assem_debug("cycle count (adj)\n");
6125 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6128 emit_testimm(fs,0x800000);
6129 if(source[i]&0x10000) // BC1T
6135 add_to_linker((int)out,ba[i],internal);
6144 add_to_linker((int)out,ba[i],internal);
6152 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6153 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6154 else if(match) emit_addnop(13);
6156 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6157 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6159 assem_debug("branch: internal\n");
6161 assem_debug("branch: external\n");
6162 if(internal&&is_ds[(ba[i]-start)>>2]) {
6163 ds_assemble_entry(i);
6166 add_to_linker((int)out,ba[i],internal);
6169 set_jump_target(nottaken,(int)out);
6173 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6175 } // (!unconditional)
6179 // In-order execution (branch first)
6183 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6186 emit_testimm(fs,0x800000);
6187 if(source[i]&0x10000) // BC1T
6198 } // if(!unconditional)
6200 uint64_t ds_unneeded=branch_regs[i].u;
6201 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6202 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6203 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6204 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6206 ds_unneeded_upper|=1;
6208 //assem_debug("1:\n");
6209 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6210 ds_unneeded,ds_unneeded_upper);
6212 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6213 address_generation(i+1,&branch_regs[i],0);
6214 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6215 ds_assemble(i+1,&branch_regs[i]);
6216 cc=get_reg(branch_regs[i].regmap,CCREG);
6218 emit_loadreg(CCREG,cc=HOST_CCREG);
6219 // CHECK: Is the following instruction (fall thru) allocated ok?
6221 assert(cc==HOST_CCREG);
6222 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6223 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6224 assem_debug("cycle count (adj)\n");
6225 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6226 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6228 assem_debug("branch: internal\n");
6230 assem_debug("branch: external\n");
6231 if(internal&&is_ds[(ba[i]-start)>>2]) {
6232 ds_assemble_entry(i);
6235 add_to_linker((int)out,ba[i],internal);
6240 if(1) { // <- FIXME (don't need this)
6241 set_jump_target(nottaken,(int)out);
6242 assem_debug("1:\n");
6244 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6245 ds_unneeded,ds_unneeded_upper);
6246 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6247 address_generation(i+1,&branch_regs[i],0);
6248 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6249 ds_assemble(i+1,&branch_regs[i]);
6251 cc=get_reg(branch_regs[i].regmap,CCREG);
6252 if(cc==-1&&!likely[i]) {
6253 // Cycle count isn't in a register, temporarily load it then write it out
6254 emit_loadreg(CCREG,HOST_CCREG);
6255 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6258 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6259 emit_storereg(CCREG,HOST_CCREG);
6262 cc=get_reg(i_regmap,CCREG);
6263 assert(cc==HOST_CCREG);
6264 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6267 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6273 static void pagespan_assemble(int i,struct regstat *i_regs)
6275 int s1l=get_reg(i_regs->regmap,rs1[i]);
6276 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6277 int s2l=get_reg(i_regs->regmap,rs2[i]);
6278 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6279 void *nt_branch=NULL;
6282 int unconditional=0;
6292 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6296 int addr,alt,ntaddr;
6297 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6301 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6302 (i_regs->regmap[hr]&63)!=rs1[i] &&
6303 (i_regs->regmap[hr]&63)!=rs2[i] )
6312 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6313 (i_regs->regmap[hr]&63)!=rs1[i] &&
6314 (i_regs->regmap[hr]&63)!=rs2[i] )
6320 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6324 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6325 (i_regs->regmap[hr]&63)!=rs1[i] &&
6326 (i_regs->regmap[hr]&63)!=rs2[i] )
6333 assert(hr<HOST_REGS);
6334 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6335 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6337 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6338 if(opcode[i]==2) // J
6342 if(opcode[i]==3) // JAL
6345 int rt=get_reg(i_regs->regmap,31);
6346 emit_movimm(start+i*4+8,rt);
6349 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6352 if(opcode2[i]==9) // JALR
6354 int rt=get_reg(i_regs->regmap,rt1[i]);
6355 emit_movimm(start+i*4+8,rt);
6358 if((opcode[i]&0x3f)==4) // BEQ
6365 #ifdef HAVE_CMOV_IMM
6367 if(s2l>=0) emit_cmp(s1l,s2l);
6368 else emit_test(s1l,s1l);
6369 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6375 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6377 if(s2h>=0) emit_cmp(s1h,s2h);
6378 else emit_test(s1h,s1h);
6379 emit_cmovne_reg(alt,addr);
6381 if(s2l>=0) emit_cmp(s1l,s2l);
6382 else emit_test(s1l,s1l);
6383 emit_cmovne_reg(alt,addr);
6386 if((opcode[i]&0x3f)==5) // BNE
6388 #ifdef HAVE_CMOV_IMM
6390 if(s2l>=0) emit_cmp(s1l,s2l);
6391 else emit_test(s1l,s1l);
6392 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6398 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6400 if(s2h>=0) emit_cmp(s1h,s2h);
6401 else emit_test(s1h,s1h);
6402 emit_cmovne_reg(alt,addr);
6404 if(s2l>=0) emit_cmp(s1l,s2l);
6405 else emit_test(s1l,s1l);
6406 emit_cmovne_reg(alt,addr);
6409 if((opcode[i]&0x3f)==0x14) // BEQL
6412 if(s2h>=0) emit_cmp(s1h,s2h);
6413 else emit_test(s1h,s1h);
6417 if(s2l>=0) emit_cmp(s1l,s2l);
6418 else emit_test(s1l,s1l);
6419 if(nottaken) set_jump_target(nottaken,(int)out);
6423 if((opcode[i]&0x3f)==0x15) // BNEL
6426 if(s2h>=0) emit_cmp(s1h,s2h);
6427 else emit_test(s1h,s1h);
6431 if(s2l>=0) emit_cmp(s1l,s2l);
6432 else emit_test(s1l,s1l);
6435 if(taken) set_jump_target(taken,(int)out);
6437 if((opcode[i]&0x3f)==6) // BLEZ
6439 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6441 if(s1h>=0) emit_mov(addr,ntaddr);
6442 emit_cmovl_reg(alt,addr);
6445 emit_cmovne_reg(ntaddr,addr);
6446 emit_cmovs_reg(alt,addr);
6449 if((opcode[i]&0x3f)==7) // BGTZ
6451 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6453 if(s1h>=0) emit_mov(addr,alt);
6454 emit_cmovl_reg(ntaddr,addr);
6457 emit_cmovne_reg(alt,addr);
6458 emit_cmovs_reg(ntaddr,addr);
6461 if((opcode[i]&0x3f)==0x16) // BLEZL
6463 assert((opcode[i]&0x3f)!=0x16);
6465 if((opcode[i]&0x3f)==0x17) // BGTZL
6467 assert((opcode[i]&0x3f)!=0x17);
6469 assert(opcode[i]!=1); // BLTZ/BGEZ
6471 //FIXME: Check CSREG
6472 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6473 if((source[i]&0x30000)==0) // BC1F
6475 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6476 emit_testimm(s1l,0x800000);
6477 emit_cmovne_reg(alt,addr);
6479 if((source[i]&0x30000)==0x10000) // BC1T
6481 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6482 emit_testimm(s1l,0x800000);
6483 emit_cmovne_reg(alt,addr);
6485 if((source[i]&0x30000)==0x20000) // BC1FL
6487 emit_testimm(s1l,0x800000);
6491 if((source[i]&0x30000)==0x30000) // BC1TL
6493 emit_testimm(s1l,0x800000);
6499 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6500 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6501 if(likely[i]||unconditional)
6503 emit_movimm(ba[i],HOST_BTREG);
6505 else if(addr!=HOST_BTREG)
6507 emit_mov(addr,HOST_BTREG);
6509 void *branch_addr=out;
6511 int target_addr=start+i*4+5;
6513 void *compiled_target_addr=check_addr(target_addr);
6514 emit_extjump_ds((int)branch_addr,target_addr);
6515 if(compiled_target_addr) {
6516 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6517 add_link(target_addr,stub);
6519 else set_jump_target((int)branch_addr,(int)stub);
6522 set_jump_target((int)nottaken,(int)out);
6523 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6524 void *branch_addr=out;
6526 int target_addr=start+i*4+8;
6528 void *compiled_target_addr=check_addr(target_addr);
6529 emit_extjump_ds((int)branch_addr,target_addr);
6530 if(compiled_target_addr) {
6531 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6532 add_link(target_addr,stub);
6534 else set_jump_target((int)branch_addr,(int)stub);
6538 // Assemble the delay slot for the above
6539 static void pagespan_ds()
6541 assem_debug("initial delay slot:\n");
6542 u_int vaddr=start+1;
6543 u_int page=get_page(vaddr);
6544 u_int vpage=get_vpage(vaddr);
6545 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6547 ll_add(jump_in+page,vaddr,(void *)out);
6548 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6549 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6550 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6551 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6552 emit_writeword(HOST_BTREG,(int)&branch_target);
6553 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6554 address_generation(0,®s[0],regs[0].regmap_entry);
6555 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6556 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6561 alu_assemble(0,®s[0]);break;
6563 imm16_assemble(0,®s[0]);break;
6565 shift_assemble(0,®s[0]);break;
6567 shiftimm_assemble(0,®s[0]);break;
6569 load_assemble(0,®s[0]);break;
6571 loadlr_assemble(0,®s[0]);break;
6573 store_assemble(0,®s[0]);break;
6575 storelr_assemble(0,®s[0]);break;
6577 cop0_assemble(0,®s[0]);break;
6579 cop1_assemble(0,®s[0]);break;
6581 c1ls_assemble(0,®s[0]);break;
6583 cop2_assemble(0,®s[0]);break;
6585 c2ls_assemble(0,®s[0]);break;
6587 c2op_assemble(0,®s[0]);break;
6589 fconv_assemble(0,®s[0]);break;
6591 float_assemble(0,®s[0]);break;
6593 fcomp_assemble(0,®s[0]);break;
6595 multdiv_assemble(0,®s[0]);break;
6597 mov_assemble(0,®s[0]);break;
6607 printf("Jump in the delay slot. This is probably a bug.\n");
6609 int btaddr=get_reg(regs[0].regmap,BTREG);
6611 btaddr=get_reg(regs[0].regmap,-1);
6612 emit_readword((int)&branch_target,btaddr);
6614 assert(btaddr!=HOST_CCREG);
6615 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6617 emit_movimm(start+4,HOST_TEMPREG);
6618 emit_cmp(btaddr,HOST_TEMPREG);
6620 emit_cmpimm(btaddr,start+4);
6622 int branch=(int)out;
6624 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6625 emit_jmp(jump_vaddr_reg[btaddr]);
6626 set_jump_target(branch,(int)out);
6627 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6628 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6631 // Basic liveness analysis for MIPS registers
6632 void unneeded_registers(int istart,int iend,int r)
6636 uint64_t temp_u,temp_uu;
6641 u=unneeded_reg[iend+1];
6642 uu=unneeded_reg_upper[iend+1];
6645 for (i=iend;i>=istart;i--)
6647 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6648 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6650 // If subroutine call, flag return address as a possible branch target
6651 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6653 if(ba[i]<start || ba[i]>=(start+slen*4))
6655 // Branch out of this block, flush all regs
6659 if(itype[i]==UJUMP&&rt1[i]==31)
6661 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6663 if(itype[i]==RJUMP&&rs1[i]==31)
6665 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6667 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6668 if(itype[i]==UJUMP&&rt1[i]==31)
6670 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6671 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6673 if(itype[i]==RJUMP&&rs1[i]==31)
6675 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6676 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6679 branch_unneeded_reg[i]=u;
6680 branch_unneeded_reg_upper[i]=uu;
6681 // Merge in delay slot
6682 tdep=(~uu>>rt1[i+1])&1;
6683 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6684 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6685 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6686 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6687 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6689 // If branch is "likely" (and conditional)
6690 // then we skip the delay slot on the fall-thru path
6693 u&=unneeded_reg[i+2];
6694 uu&=unneeded_reg_upper[i+2];
6705 // Internal branch, flag target
6706 bt[(ba[i]-start)>>2]=1;
6707 if(ba[i]<=start+i*4) {
6709 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6711 // Unconditional branch
6714 // Conditional branch (not taken case)
6715 temp_u=unneeded_reg[i+2];
6716 temp_uu=unneeded_reg_upper[i+2];
6718 // Merge in delay slot
6719 tdep=(~temp_uu>>rt1[i+1])&1;
6720 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6721 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6722 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6723 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6724 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6725 temp_u|=1;temp_uu|=1;
6726 // If branch is "likely" (and conditional)
6727 // then we skip the delay slot on the fall-thru path
6730 temp_u&=unneeded_reg[i+2];
6731 temp_uu&=unneeded_reg_upper[i+2];
6739 tdep=(~temp_uu>>rt1[i])&1;
6740 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6741 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6742 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6743 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6744 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6745 temp_u|=1;temp_uu|=1;
6746 unneeded_reg[i]=temp_u;
6747 unneeded_reg_upper[i]=temp_uu;
6748 // Only go three levels deep. This recursion can take an
6749 // excessive amount of time if there are a lot of nested loops.
6751 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6753 unneeded_reg[(ba[i]-start)>>2]=1;
6754 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6757 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6759 // Unconditional branch
6760 u=unneeded_reg[(ba[i]-start)>>2];
6761 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6762 branch_unneeded_reg[i]=u;
6763 branch_unneeded_reg_upper[i]=uu;
6766 //branch_unneeded_reg[i]=u;
6767 //branch_unneeded_reg_upper[i]=uu;
6768 // Merge in delay slot
6769 tdep=(~uu>>rt1[i+1])&1;
6770 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6771 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6772 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6773 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6774 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6777 // Conditional branch
6778 b=unneeded_reg[(ba[i]-start)>>2];
6779 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6780 branch_unneeded_reg[i]=b;
6781 branch_unneeded_reg_upper[i]=bu;
6784 //branch_unneeded_reg[i]=b;
6785 //branch_unneeded_reg_upper[i]=bu;
6786 // Branch delay slot
6787 tdep=(~uu>>rt1[i+1])&1;
6788 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6789 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6790 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6791 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6792 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6794 // If branch is "likely" then we skip the
6795 // delay slot on the fall-thru path
6800 u&=unneeded_reg[i+2];
6801 uu&=unneeded_reg_upper[i+2];
6812 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6813 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6814 //branch_unneeded_reg[i]=1;
6815 //branch_unneeded_reg_upper[i]=1;
6817 branch_unneeded_reg[i]=1;
6818 branch_unneeded_reg_upper[i]=1;
6824 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6826 // SYSCALL instruction (software interrupt)
6830 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6832 // ERET instruction (return from interrupt)
6837 tdep=(~uu>>rt1[i])&1;
6838 // Written registers are unneeded
6843 // Accessed registers are needed
6848 // Source-target dependencies
6849 uu&=~(tdep<<dep1[i]);
6850 uu&=~(tdep<<dep2[i]);
6851 // R0 is always unneeded
6855 unneeded_reg_upper[i]=uu;
6857 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6860 for(r=1;r<=CCREG;r++) {
6861 if((unneeded_reg[i]>>r)&1) {
6862 if(r==HIREG) printf(" HI");
6863 else if(r==LOREG) printf(" LO");
6864 else printf(" r%d",r);
6868 for(r=1;r<=CCREG;r++) {
6869 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6870 if(r==HIREG) printf(" HI");
6871 else if(r==LOREG) printf(" LO");
6872 else printf(" r%d",r);
6878 for (i=iend;i>=istart;i--)
6880 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6885 // Identify registers which are likely to contain 32-bit values
6886 // This is used to predict whether any branches will jump to a
6887 // location with 64-bit values in registers.
6888 static void provisional_32bit()
6892 uint64_t lastbranch=1;
6897 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6898 if(i>1) is32=lastbranch;
6904 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6906 if(i>2) is32=lastbranch;
6910 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6912 if(rs1[i-2]==0||rs2[i-2]==0)
6915 is32|=1LL<<rs1[i-2];
6918 is32|=1LL<<rs2[i-2];
6923 // If something jumps here with 64-bit values
6924 // then promote those registers to 64 bits
6927 uint64_t temp_is32=is32;
6930 if(ba[j]==start+i*4)
6931 //temp_is32&=branch_regs[j].is32;
6936 if(ba[j]==start+i*4)
6947 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6948 // Branches don't write registers, consider the delay slot instead.
6959 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6960 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6969 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6970 if(op==0x22) is32|=1LL<<rt; // LWL
6973 if (op==0x08||op==0x09|| // ADDI/ADDIU
6974 op==0x0a||op==0x0b|| // SLTI/SLTIU
6980 if(op==0x18||op==0x19) { // DADDI/DADDIU
6983 // is32|=((is32>>s1)&1LL)<<rt;
6985 if(op==0x0d||op==0x0e) { // ORI/XORI
6986 uint64_t sr=((is32>>s1)&1LL);
7002 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7005 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7008 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7009 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7013 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7018 uint64_t sr=((is32>>s1)&1LL);
7023 uint64_t sr=((is32>>s2)&1LL);
7031 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7036 uint64_t sr=((is32>>s1)&1LL);
7046 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7047 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7050 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7055 uint64_t sr=((is32>>s1)&1LL);
7061 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7062 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7066 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7067 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7070 if(op2==0) is32|=1LL<<rt; // MFC0
7074 if(op2==0) is32|=1LL<<rt; // MFC1
7075 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7076 if(op2==2) is32|=1LL<<rt; // CFC1
7098 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7100 if(rt1[i-1]==31) // JAL/JALR
7102 // Subroutine call will return here, don't alloc any registers
7107 // Internal branch will jump here, match registers to caller
7115 // Identify registers which may be assumed to contain 32-bit values
7116 // and where optimizations will rely on this.
7117 // This is used to determine whether backward branches can safely
7118 // jump to a location with 64-bit values in registers.
7119 static void provisional_r32()
7124 for (i=slen-1;i>=0;i--)
7127 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7129 if(ba[i]<start || ba[i]>=(start+slen*4))
7131 // Branch out of this block, don't need anything
7137 // Need whatever matches the target
7138 // (and doesn't get overwritten by the delay slot instruction)
7140 int t=(ba[i]-start)>>2;
7141 if(ba[i]>start+i*4) {
7143 //if(!(requires_32bit[t]&~regs[i].was32))
7144 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7145 if(!(pr32[t]&~regs[i].was32))
7146 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7149 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7150 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7153 // Conditional branch may need registers for following instructions
7154 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7157 //r32|=requires_32bit[i+2];
7160 // Mark this address as a branch target since it may be called
7161 // upon return from interrupt
7165 // Merge in delay slot
7167 // These are overwritten unless the branch is "likely"
7168 // and the delay slot is nullified if not taken
7169 r32&=~(1LL<<rt1[i+1]);
7170 r32&=~(1LL<<rt2[i+1]);
7172 // Assume these are needed (delay slot)
7175 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7179 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7181 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7183 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7185 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7187 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7190 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7192 // SYSCALL instruction (software interrupt)
7195 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7197 // ERET instruction (return from interrupt)
7201 r32&=~(1LL<<rt1[i]);
7202 r32&=~(1LL<<rt2[i]);
7205 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7209 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7211 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7213 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7215 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7217 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7219 //requires_32bit[i]=r32;
7222 // Dirty registers which are 32-bit, require 32-bit input
7223 // as they will be written as 32-bit values
7224 for(hr=0;hr<HOST_REGS;hr++)
7226 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7227 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7228 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7229 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7230 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7237 // Write back dirty registers as soon as we will no longer modify them,
7238 // so that we don't end up with lots of writes at the branches.
7239 void clean_registers(int istart,int iend,int wr)
7243 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7244 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7246 will_dirty_i=will_dirty_next=0;
7247 wont_dirty_i=wont_dirty_next=0;
7249 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7250 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7252 for (i=iend;i>=istart;i--)
7254 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7256 if(ba[i]<start || ba[i]>=(start+slen*4))
7258 // Branch out of this block, flush all regs
7259 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7261 // Unconditional branch
7264 // Merge in delay slot (will dirty)
7265 for(r=0;r<HOST_REGS;r++) {
7266 if(r!=EXCLUDE_REG) {
7267 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7268 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7269 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7270 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7271 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7272 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7273 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7274 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7275 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7276 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7277 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7278 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7279 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7280 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7286 // Conditional branch
7288 wont_dirty_i=wont_dirty_next;
7289 // Merge in delay slot (will dirty)
7290 for(r=0;r<HOST_REGS;r++) {
7291 if(r!=EXCLUDE_REG) {
7293 // Might not dirty if likely branch is not taken
7294 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7295 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7296 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7297 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7298 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7299 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7300 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7301 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7302 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7303 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7304 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7305 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7306 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7307 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7312 // Merge in delay slot (wont dirty)
7313 for(r=0;r<HOST_REGS;r++) {
7314 if(r!=EXCLUDE_REG) {
7315 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7316 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7317 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7318 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7319 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7320 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7321 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7322 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7323 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7324 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7328 #ifndef DESTRUCTIVE_WRITEBACK
7329 branch_regs[i].dirty&=wont_dirty_i;
7331 branch_regs[i].dirty|=will_dirty_i;
7337 if(ba[i]<=start+i*4) {
7339 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7341 // Unconditional branch
7344 // Merge in delay slot (will dirty)
7345 for(r=0;r<HOST_REGS;r++) {
7346 if(r!=EXCLUDE_REG) {
7347 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7348 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7349 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7350 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7351 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7352 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7353 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7354 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7355 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7356 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7357 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7358 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7359 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7360 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7364 // Conditional branch (not taken case)
7365 temp_will_dirty=will_dirty_next;
7366 temp_wont_dirty=wont_dirty_next;
7367 // Merge in delay slot (will dirty)
7368 for(r=0;r<HOST_REGS;r++) {
7369 if(r!=EXCLUDE_REG) {
7371 // Will not dirty if likely branch is not taken
7372 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7373 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7374 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7375 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7376 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7377 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7378 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7379 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7380 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7381 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7382 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7383 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7384 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7385 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7390 // Merge in delay slot (wont dirty)
7391 for(r=0;r<HOST_REGS;r++) {
7392 if(r!=EXCLUDE_REG) {
7393 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7394 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7395 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7396 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7397 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7398 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7399 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7400 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7401 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7402 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7405 // Deal with changed mappings
7407 for(r=0;r<HOST_REGS;r++) {
7408 if(r!=EXCLUDE_REG) {
7409 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7410 temp_will_dirty&=~(1<<r);
7411 temp_wont_dirty&=~(1<<r);
7412 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7413 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7414 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7416 temp_will_dirty|=1<<r;
7417 temp_wont_dirty|=1<<r;
7424 will_dirty[i]=temp_will_dirty;
7425 wont_dirty[i]=temp_wont_dirty;
7426 clean_registers((ba[i]-start)>>2,i-1,0);
7428 // Limit recursion. It can take an excessive amount
7429 // of time if there are a lot of nested loops.
7430 will_dirty[(ba[i]-start)>>2]=0;
7431 wont_dirty[(ba[i]-start)>>2]=-1;
7436 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7438 // Unconditional branch
7441 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7442 for(r=0;r<HOST_REGS;r++) {
7443 if(r!=EXCLUDE_REG) {
7444 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7445 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7446 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7448 if(branch_regs[i].regmap[r]>=0) {
7449 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7450 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7455 // Merge in delay slot
7456 for(r=0;r<HOST_REGS;r++) {
7457 if(r!=EXCLUDE_REG) {
7458 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7459 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7460 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7461 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7462 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7463 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7464 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7465 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7466 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7467 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7468 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7469 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7470 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7471 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7475 // Conditional branch
7476 will_dirty_i=will_dirty_next;
7477 wont_dirty_i=wont_dirty_next;
7478 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7479 for(r=0;r<HOST_REGS;r++) {
7480 if(r!=EXCLUDE_REG) {
7481 signed char target_reg=branch_regs[i].regmap[r];
7482 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7483 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7484 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7486 else if(target_reg>=0) {
7487 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7488 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7490 // Treat delay slot as part of branch too
7491 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7492 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7493 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7497 will_dirty[i+1]&=~(1<<r);
7502 // Merge in delay slot
7503 for(r=0;r<HOST_REGS;r++) {
7504 if(r!=EXCLUDE_REG) {
7506 // Might not dirty if likely branch is not taken
7507 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7508 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7509 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7510 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7511 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7512 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7513 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7514 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7515 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7516 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7517 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7518 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7519 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7520 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7525 // Merge in delay slot (won't dirty)
7526 for(r=0;r<HOST_REGS;r++) {
7527 if(r!=EXCLUDE_REG) {
7528 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7529 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7530 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7531 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7532 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7533 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7534 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7535 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7536 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7537 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7541 #ifndef DESTRUCTIVE_WRITEBACK
7542 branch_regs[i].dirty&=wont_dirty_i;
7544 branch_regs[i].dirty|=will_dirty_i;
7549 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7551 // SYSCALL instruction (software interrupt)
7555 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7557 // ERET instruction (return from interrupt)
7561 will_dirty_next=will_dirty_i;
7562 wont_dirty_next=wont_dirty_i;
7563 for(r=0;r<HOST_REGS;r++) {
7564 if(r!=EXCLUDE_REG) {
7565 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7566 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7567 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7568 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7569 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7570 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7571 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7572 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7574 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7576 // Don't store a register immediately after writing it,
7577 // may prevent dual-issue.
7578 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7579 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7585 will_dirty[i]=will_dirty_i;
7586 wont_dirty[i]=wont_dirty_i;
7587 // Mark registers that won't be dirtied as not dirty
7589 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7590 for(r=0;r<HOST_REGS;r++) {
7591 if((will_dirty_i>>r)&1) {
7597 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7598 regs[i].dirty|=will_dirty_i;
7599 #ifndef DESTRUCTIVE_WRITEBACK
7600 regs[i].dirty&=wont_dirty_i;
7601 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7603 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7604 for(r=0;r<HOST_REGS;r++) {
7605 if(r!=EXCLUDE_REG) {
7606 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7607 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7608 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7616 for(r=0;r<HOST_REGS;r++) {
7617 if(r!=EXCLUDE_REG) {
7618 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7619 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7620 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7628 // Deal with changed mappings
7629 temp_will_dirty=will_dirty_i;
7630 temp_wont_dirty=wont_dirty_i;
7631 for(r=0;r<HOST_REGS;r++) {
7632 if(r!=EXCLUDE_REG) {
7634 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7636 #ifndef DESTRUCTIVE_WRITEBACK
7637 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7639 regs[i].wasdirty|=will_dirty_i&(1<<r);
7642 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7643 // Register moved to a different register
7644 will_dirty_i&=~(1<<r);
7645 wont_dirty_i&=~(1<<r);
7646 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7647 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7649 #ifndef DESTRUCTIVE_WRITEBACK
7650 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7652 regs[i].wasdirty|=will_dirty_i&(1<<r);
7656 will_dirty_i&=~(1<<r);
7657 wont_dirty_i&=~(1<<r);
7658 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7659 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7660 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7663 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7672 void disassemble_inst(int i)
7674 if (bt[i]) printf("*"); else printf(" ");
7677 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7679 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7681 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7683 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7685 if (opcode[i]==0x9&&rt1[i]!=31)
7686 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7688 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7691 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7693 if(opcode[i]==0xf) //LUI
7694 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7696 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7700 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7704 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7708 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7711 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7714 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7717 if((opcode2[i]&0x1d)==0x10)
7718 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7719 else if((opcode2[i]&0x1d)==0x11)
7720 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7722 printf (" %x: %s\n",start+i*4,insn[i]);
7726 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7727 else if(opcode2[i]==4)
7728 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7729 else printf (" %x: %s\n",start+i*4,insn[i]);
7733 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7734 else if(opcode2[i]>3)
7735 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7736 else printf (" %x: %s\n",start+i*4,insn[i]);
7740 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7741 else if(opcode2[i]>3)
7742 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7743 else printf (" %x: %s\n",start+i*4,insn[i]);
7746 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7749 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7752 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7755 //printf (" %s %8x\n",insn[i],source[i]);
7756 printf (" %x: %s\n",start+i*4,insn[i]);
7760 // clear the state completely, instead of just marking
7761 // things invalid like invalidate_all_pages() does
7762 void new_dynarec_clear_full()
7765 out=(u_char *)BASE_ADDR;
7766 memset(invalid_code,1,sizeof(invalid_code));
7767 memset(hash_table,0xff,sizeof(hash_table));
7768 memset(mini_ht,-1,sizeof(mini_ht));
7769 memset(restore_candidate,0,sizeof(restore_candidate));
7770 memset(shadow,0,sizeof(shadow));
7772 expirep=16384; // Expiry pointer, +2 blocks
7773 pending_exception=0;
7781 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7783 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7784 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7785 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7787 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7788 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7789 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7792 void new_dynarec_init()
7794 printf("Init new dynarec\n");
7795 out=(u_char *)BASE_ADDR;
7796 if (mmap (out, 1<<TARGET_SIZE_2,
7797 PROT_READ | PROT_WRITE | PROT_EXEC,
7798 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7799 -1, 0) <= 0) {printf("mmap() failed\n");}
7801 rdword=&readmem_dword;
7802 fake_pc.f.r.rs=&readmem_dword;
7803 fake_pc.f.r.rt=&readmem_dword;
7804 fake_pc.f.r.rd=&readmem_dword;
7807 new_dynarec_clear_full();
7809 // Copy this into local area so we don't have to put it in every literal pool
7810 invc_ptr=invalid_code;
7813 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7814 writemem[n] = write_nomem_new;
7815 writememb[n] = write_nomemb_new;
7816 writememh[n] = write_nomemh_new;
7818 writememd[n] = write_nomemd_new;
7820 readmem[n] = read_nomem_new;
7821 readmemb[n] = read_nomemb_new;
7822 readmemh[n] = read_nomemh_new;
7824 readmemd[n] = read_nomemd_new;
7827 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7828 writemem[n] = write_rdram_new;
7829 writememb[n] = write_rdramb_new;
7830 writememh[n] = write_rdramh_new;
7832 writememd[n] = write_rdramd_new;
7835 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7836 writemem[n] = write_nomem_new;
7837 writememb[n] = write_nomemb_new;
7838 writememh[n] = write_nomemh_new;
7840 writememd[n] = write_nomemd_new;
7842 readmem[n] = read_nomem_new;
7843 readmemb[n] = read_nomemb_new;
7844 readmemh[n] = read_nomemh_new;
7846 readmemd[n] = read_nomemd_new;
7854 void new_dynarec_cleanup()
7857 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7858 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7859 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7860 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7862 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7866 int new_recompile_block(int addr)
7869 if(addr==0x800cd050) {
7871 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7873 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7876 //if(Count==365117028) tracedebug=1;
7877 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7878 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7879 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7881 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7882 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7883 /*if(Count>=312978186) {
7887 start = (u_int)addr&~3;
7888 //assert(((u_int)addr&1)==0);
7890 if(!sp_in_mirror&&(signed int)(psxRegs.GPR.n.sp&0xffe00000)>0x80200000&&
7891 0x10000<=psxRegs.GPR.n.sp&&(psxRegs.GPR.n.sp&~0xe0e00000)<RAM_SIZE) {
7892 printf("SP hack enabled (%08x), @%08x\n", psxRegs.GPR.n.sp, psxRegs.pc);
7895 if (Config.HLE && start == 0x80001000) // hlecall
7897 // XXX: is this enough? Maybe check hleSoftCall?
7898 u_int beginning=(u_int)out;
7899 u_int page=get_page(start);
7900 invalid_code[start>>12]=0;
7901 emit_movimm(start,0);
7902 emit_writeword(0,(int)&pcaddr);
7903 emit_jmp((int)new_dyna_leave);
7905 __clear_cache((void *)beginning,out);
7907 ll_add(jump_in+page,start,(void *)beginning);
7910 else if ((u_int)addr < 0x00200000 ||
7911 (0xa0000000 <= addr && addr < 0xa0200000)) {
7912 // used for BIOS calls mostly?
7913 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7914 pagelimit = (addr&0xa0000000)|0x00200000;
7916 else if (!Config.HLE && (
7917 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7918 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7920 source = (u_int *)((u_int)psxR+(start&0x7ffff));
7921 pagelimit = (addr&0xfff00000)|0x80000;
7926 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7927 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7928 pagelimit = 0xa4001000;
7932 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
7933 source = (u_int *)((u_int)rdram+start-0x80000000);
7934 pagelimit = 0x80000000+RAM_SIZE;
7937 else if ((signed int)addr >= (signed int)0xC0000000) {
7938 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7939 //if(tlb_LUT_r[start>>12])
7940 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7941 if((signed int)memory_map[start>>12]>=0) {
7942 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7943 pagelimit=(start+4096)&0xFFFFF000;
7944 int map=memory_map[start>>12];
7947 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7948 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7950 assem_debug("pagelimit=%x\n",pagelimit);
7951 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7954 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7955 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7956 return -1; // Caller will invoke exception handler
7958 //printf("source= %x\n",(int)source);
7962 printf("Compile at bogus memory address: %x \n", (int)addr);
7966 /* Pass 1: disassemble */
7967 /* Pass 2: register dependencies, branch targets */
7968 /* Pass 3: register allocation */
7969 /* Pass 4: branch dependencies */
7970 /* Pass 5: pre-alloc */
7971 /* Pass 6: optimize clean/dirty state */
7972 /* Pass 7: flag 32-bit registers */
7973 /* Pass 8: assembly */
7974 /* Pass 9: linker */
7975 /* Pass 10: garbage collection / free memory */
7979 unsigned int type,op,op2;
7981 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7983 /* Pass 1 disassembly */
7985 for(i=0;!done;i++) {
7986 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7987 minimum_free_regs[i]=0;
7988 opcode[i]=op=source[i]>>26;
7991 case 0x00: strcpy(insn[i],"special"); type=NI;
7995 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7996 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7997 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7998 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7999 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8000 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8001 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8002 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8003 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8004 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8005 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8006 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8007 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8008 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8009 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8010 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8011 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8012 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8013 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8014 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8015 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8016 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8017 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8018 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8019 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8020 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8021 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8022 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8023 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8024 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8025 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8026 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8027 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8028 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8029 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8031 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8032 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8033 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8034 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8035 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8036 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8037 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8038 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8039 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8040 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8041 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8042 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8043 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8044 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8045 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8046 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8047 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8051 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8052 op2=(source[i]>>16)&0x1f;
8055 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8056 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8057 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8058 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8059 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8060 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8061 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8062 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8063 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8064 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8065 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8066 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8067 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8068 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8071 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8072 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8073 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8074 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8075 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8076 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8077 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8078 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8079 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8080 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8081 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8082 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8083 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8084 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8085 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8086 op2=(source[i]>>21)&0x1f;
8089 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8090 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8091 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8092 switch(source[i]&0x3f)
8094 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8095 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8096 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8097 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8099 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8101 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8106 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8107 op2=(source[i]>>21)&0x1f;
8110 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8111 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8112 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8113 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8114 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8115 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8116 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8117 switch((source[i]>>16)&0x3)
8119 case 0x00: strcpy(insn[i],"BC1F"); break;
8120 case 0x01: strcpy(insn[i],"BC1T"); break;
8121 case 0x02: strcpy(insn[i],"BC1FL"); break;
8122 case 0x03: strcpy(insn[i],"BC1TL"); break;
8125 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8126 switch(source[i]&0x3f)
8128 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8129 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8130 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8131 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8132 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8133 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8134 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8135 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8136 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8137 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8138 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8139 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8140 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8141 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8142 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8143 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8144 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8145 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8146 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8147 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8148 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8149 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8150 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8151 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8152 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8153 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8154 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8155 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8156 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8157 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8158 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8159 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8160 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8161 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8162 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8165 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8166 switch(source[i]&0x3f)
8168 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8169 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8170 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8171 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8172 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8173 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8174 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8175 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8176 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8177 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8178 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8179 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8180 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8181 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8182 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8183 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8184 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8185 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8186 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8187 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8188 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8189 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8190 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8191 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8192 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8193 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8194 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8195 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8196 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8197 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8198 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8199 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8200 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8201 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8202 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8205 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8206 switch(source[i]&0x3f)
8208 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8209 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8212 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8213 switch(source[i]&0x3f)
8215 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8216 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8222 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8223 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8224 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8225 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8226 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8227 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8228 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8229 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8231 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8232 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8233 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8234 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8235 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8236 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8237 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8239 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8241 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8242 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8243 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8244 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8246 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8247 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8249 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8250 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8251 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8252 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8254 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8255 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8256 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8258 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8259 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8261 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8262 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8263 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8266 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8267 // note: COP MIPS-1 encoding differs from MIPS32
8268 op2=(source[i]>>21)&0x1f;
8269 if (source[i]&0x3f) {
8270 if (gte_handlers[source[i]&0x3f]!=NULL) {
8271 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8277 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8278 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8279 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8280 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8283 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8284 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8285 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8287 default: strcpy(insn[i],"???"); type=NI;
8288 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8293 /* Get registers/immediates */
8301 rs1[i]=(source[i]>>21)&0x1f;
8303 rt1[i]=(source[i]>>16)&0x1f;
8305 imm[i]=(short)source[i];
8309 rs1[i]=(source[i]>>21)&0x1f;
8310 rs2[i]=(source[i]>>16)&0x1f;
8313 imm[i]=(short)source[i];
8314 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8317 // LWL/LWR only load part of the register,
8318 // therefore the target register must be treated as a source too
8319 rs1[i]=(source[i]>>21)&0x1f;
8320 rs2[i]=(source[i]>>16)&0x1f;
8321 rt1[i]=(source[i]>>16)&0x1f;
8323 imm[i]=(short)source[i];
8324 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8325 if(op==0x26) dep1[i]=rt1[i]; // LWR
8328 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8329 else rs1[i]=(source[i]>>21)&0x1f;
8331 rt1[i]=(source[i]>>16)&0x1f;
8333 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8334 imm[i]=(unsigned short)source[i];
8336 imm[i]=(short)source[i];
8338 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8339 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8340 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8347 // The JAL instruction writes to r31.
8354 rs1[i]=(source[i]>>21)&0x1f;
8358 // The JALR instruction writes to rd.
8360 rt1[i]=(source[i]>>11)&0x1f;
8365 rs1[i]=(source[i]>>21)&0x1f;
8366 rs2[i]=(source[i]>>16)&0x1f;
8369 if(op&2) { // BGTZ/BLEZ
8377 rs1[i]=(source[i]>>21)&0x1f;
8382 if(op2&0x10) { // BxxAL
8384 // NOTE: If the branch is not taken, r31 is still overwritten
8386 likely[i]=(op2&2)>>1;
8393 likely[i]=((source[i])>>17)&1;
8396 rs1[i]=(source[i]>>21)&0x1f; // source
8397 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8398 rt1[i]=(source[i]>>11)&0x1f; // destination
8400 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8401 us1[i]=rs1[i];us2[i]=rs2[i];
8403 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8404 dep1[i]=rs1[i];dep2[i]=rs2[i];
8406 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8407 dep1[i]=rs1[i];dep2[i]=rs2[i];
8411 rs1[i]=(source[i]>>21)&0x1f; // source
8412 rs2[i]=(source[i]>>16)&0x1f; // divisor
8415 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8416 us1[i]=rs1[i];us2[i]=rs2[i];
8424 if(op2==0x10) rs1[i]=HIREG; // MFHI
8425 if(op2==0x11) rt1[i]=HIREG; // MTHI
8426 if(op2==0x12) rs1[i]=LOREG; // MFLO
8427 if(op2==0x13) rt1[i]=LOREG; // MTLO
8428 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8429 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8433 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8434 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8435 rt1[i]=(source[i]>>11)&0x1f; // destination
8437 // DSLLV/DSRLV/DSRAV are 64-bit
8438 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8441 rs1[i]=(source[i]>>16)&0x1f;
8443 rt1[i]=(source[i]>>11)&0x1f;
8445 imm[i]=(source[i]>>6)&0x1f;
8446 // DSxx32 instructions
8447 if(op2>=0x3c) imm[i]|=0x20;
8448 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8449 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8456 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8457 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8458 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8459 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8467 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8468 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8469 if(op2==5) us1[i]=rs1[i]; // DMTC1
8473 rs1[i]=(source[i]>>21)&0x1F;
8477 imm[i]=(short)source[i];
8480 rs1[i]=(source[i]>>21)&0x1F;
8484 imm[i]=(short)source[i];
8513 /* Calculate branch target addresses */
8515 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8516 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8517 ba[i]=start+i*4+8; // Ignore never taken branch
8518 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8519 ba[i]=start+i*4+8; // Ignore never taken branch
8520 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8521 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8524 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8526 // branch in delay slot?
8527 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8528 // don't handle first branch and call interpreter if it's hit
8529 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8532 // basic load delay detection
8533 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8534 int t=(ba[i-1]-start)/4;
8535 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8536 // jump target wants DS result - potential load delay effect
8537 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8539 bt[t+1]=1; // expected return from interpreter
8541 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8542 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8543 // v0 overwrite like this is a sign of trouble, bail out
8544 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8550 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8554 i--; // don't compile the DS
8558 /* Is this the end of the block? */
8559 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8560 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8564 if(stop_after_jal) done=1;
8566 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8568 // Don't recompile stuff that's already compiled
8569 if(check_addr(start+i*4+4)) done=1;
8570 // Don't get too close to the limit
8571 if(i>MAXBLOCK/2) done=1;
8573 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8574 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8576 // Does the block continue due to a branch?
8579 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8580 if(ba[j]==start+i*4+4) done=j=0;
8581 if(ba[j]==start+i*4+8) done=j=0;
8584 //assert(i<MAXBLOCK-1);
8585 if(start+i*4==pagelimit-4) done=1;
8586 assert(start+i*4<pagelimit);
8587 if (i==MAXBLOCK-1) done=1;
8588 // Stop if we're compiling junk
8589 if(itype[i]==NI&&opcode[i]==0x11) {
8590 done=stop_after_jal=1;
8591 printf("Disabled speculative precompilation\n");
8595 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8596 if(start+i*4==pagelimit) {
8602 /* Pass 2 - Register dependencies and branch targets */
8604 unneeded_registers(0,slen-1,0);
8606 /* Pass 3 - Register allocation */
8608 struct regstat current; // Current register allocations/status
8611 current.u=unneeded_reg[0];
8612 current.uu=unneeded_reg_upper[0];
8613 clear_all_regs(current.regmap);
8614 alloc_reg(¤t,0,CCREG);
8615 dirty_reg(¤t,CCREG);
8623 provisional_32bit();
8626 // First instruction is delay slot
8631 unneeded_reg_upper[0]=1;
8632 current.regmap[HOST_BTREG]=BTREG;
8640 for(hr=0;hr<HOST_REGS;hr++)
8642 // Is this really necessary?
8643 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8649 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8651 if(rs1[i-2]==0||rs2[i-2]==0)
8654 current.is32|=1LL<<rs1[i-2];
8655 int hr=get_reg(current.regmap,rs1[i-2]|64);
8656 if(hr>=0) current.regmap[hr]=-1;
8659 current.is32|=1LL<<rs2[i-2];
8660 int hr=get_reg(current.regmap,rs2[i-2]|64);
8661 if(hr>=0) current.regmap[hr]=-1;
8667 // If something jumps here with 64-bit values
8668 // then promote those registers to 64 bits
8671 uint64_t temp_is32=current.is32;
8674 if(ba[j]==start+i*4)
8675 temp_is32&=branch_regs[j].is32;
8679 if(ba[j]==start+i*4)
8683 if(temp_is32!=current.is32) {
8684 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8685 #ifndef DESTRUCTIVE_WRITEBACK
8688 for(hr=0;hr<HOST_REGS;hr++)
8690 int r=current.regmap[hr];
8693 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8695 //printf("restore %d\n",r);
8699 current.is32=temp_is32;
8706 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8707 regs[i].wasconst=current.isconst;
8708 regs[i].was32=current.is32;
8709 regs[i].wasdirty=current.dirty;
8710 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8711 // To change a dirty register from 32 to 64 bits, we must write
8712 // it out during the previous cycle (for branches, 2 cycles)
8713 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8715 uint64_t temp_is32=current.is32;
8718 if(ba[j]==start+i*4+4)
8719 temp_is32&=branch_regs[j].is32;
8723 if(ba[j]==start+i*4+4)
8727 if(temp_is32!=current.is32) {
8728 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8729 for(hr=0;hr<HOST_REGS;hr++)
8731 int r=current.regmap[hr];
8734 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8735 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8737 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8739 //printf("dump %d/r%d\n",hr,r);
8740 current.regmap[hr]=-1;
8741 if(get_reg(current.regmap,r|64)>=0)
8742 current.regmap[get_reg(current.regmap,r|64)]=-1;
8750 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8752 uint64_t temp_is32=current.is32;
8755 if(ba[j]==start+i*4+8)
8756 temp_is32&=branch_regs[j].is32;
8760 if(ba[j]==start+i*4+8)
8764 if(temp_is32!=current.is32) {
8765 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8766 for(hr=0;hr<HOST_REGS;hr++)
8768 int r=current.regmap[hr];
8771 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8772 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8774 //printf("dump %d/r%d\n",hr,r);
8775 current.regmap[hr]=-1;
8776 if(get_reg(current.regmap,r|64)>=0)
8777 current.regmap[get_reg(current.regmap,r|64)]=-1;
8785 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8787 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8788 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8789 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8798 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8799 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8800 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8801 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8802 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8805 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8809 ds=0; // Skip delay slot, already allocated as part of branch
8810 // ...but we need to alloc it in case something jumps here
8812 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8813 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8815 current.u=branch_unneeded_reg[i-1];
8816 current.uu=branch_unneeded_reg_upper[i-1];
8818 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8819 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8820 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8823 struct regstat temp;
8824 memcpy(&temp,¤t,sizeof(current));
8825 temp.wasdirty=temp.dirty;
8826 temp.was32=temp.is32;
8827 // TODO: Take into account unconditional branches, as below
8828 delayslot_alloc(&temp,i);
8829 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8830 regs[i].wasdirty=temp.wasdirty;
8831 regs[i].was32=temp.was32;
8832 regs[i].dirty=temp.dirty;
8833 regs[i].is32=temp.is32;
8837 // Create entry (branch target) regmap
8838 for(hr=0;hr<HOST_REGS;hr++)
8840 int r=temp.regmap[hr];
8842 if(r!=regmap_pre[i][hr]) {
8843 regs[i].regmap_entry[hr]=-1;
8848 if((current.u>>r)&1) {
8849 regs[i].regmap_entry[hr]=-1;
8850 regs[i].regmap[hr]=-1;
8851 //Don't clear regs in the delay slot as the branch might need them
8852 //current.regmap[hr]=-1;
8854 regs[i].regmap_entry[hr]=r;
8857 if((current.uu>>(r&63))&1) {
8858 regs[i].regmap_entry[hr]=-1;
8859 regs[i].regmap[hr]=-1;
8860 //Don't clear regs in the delay slot as the branch might need them
8861 //current.regmap[hr]=-1;
8863 regs[i].regmap_entry[hr]=r;
8867 // First instruction expects CCREG to be allocated
8868 if(i==0&&hr==HOST_CCREG)
8869 regs[i].regmap_entry[hr]=CCREG;
8871 regs[i].regmap_entry[hr]=-1;
8875 else { // Not delay slot
8878 //current.isconst=0; // DEBUG
8879 //current.wasconst=0; // DEBUG
8880 //regs[i].wasconst=0; // DEBUG
8881 clear_const(¤t,rt1[i]);
8882 alloc_cc(¤t,i);
8883 dirty_reg(¤t,CCREG);
8885 delayslot_alloc(¤t,i+1);
8887 alloc_reg(¤t,i,31);
8888 dirty_reg(¤t,31);
8889 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8890 //assert(rt1[i+1]!=rt1[i]);
8892 alloc_reg(¤t,i,PTEMP);
8894 //current.is32|=1LL<<rt1[i];
8896 //current.isconst=0; // DEBUG
8898 //printf("i=%d, isconst=%x\n",i,current.isconst);
8901 //current.isconst=0;
8902 //current.wasconst=0;
8903 //regs[i].wasconst=0;
8904 clear_const(¤t,rs1[i]);
8905 clear_const(¤t,rt1[i]);
8906 alloc_cc(¤t,i);
8907 dirty_reg(¤t,CCREG);
8908 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8909 alloc_reg(¤t,i,rs1[i]);
8911 alloc_reg(¤t,i,rt1[i]);
8912 dirty_reg(¤t,rt1[i]);
8913 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
8914 assert(rt1[i+1]!=rt1[i]);
8916 alloc_reg(¤t,i,PTEMP);
8920 if(rs1[i]==31) { // JALR
8921 alloc_reg(¤t,i,RHASH);
8922 #ifndef HOST_IMM_ADDR32
8923 alloc_reg(¤t,i,RHTBL);
8927 delayslot_alloc(¤t,i+1);
8929 // The delay slot overwrites our source register,
8930 // allocate a temporary register to hold the old value.
8934 delayslot_alloc(¤t,i+1);
8936 alloc_reg(¤t,i,RTEMP);
8938 //current.isconst=0; // DEBUG
8943 //current.isconst=0;
8944 //current.wasconst=0;
8945 //regs[i].wasconst=0;
8946 clear_const(¤t,rs1[i]);
8947 clear_const(¤t,rs2[i]);
8948 if((opcode[i]&0x3E)==4) // BEQ/BNE
8950 alloc_cc(¤t,i);
8951 dirty_reg(¤t,CCREG);
8952 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8953 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8954 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8956 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8957 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8959 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8960 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8961 // The delay slot overwrites one of our conditions.
8962 // Allocate the branch condition registers instead.
8966 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8967 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8968 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8970 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8971 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8977 delayslot_alloc(¤t,i+1);
8981 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8983 alloc_cc(¤t,i);
8984 dirty_reg(¤t,CCREG);
8985 alloc_reg(¤t,i,rs1[i]);
8986 if(!(current.is32>>rs1[i]&1))
8988 alloc_reg64(¤t,i,rs1[i]);
8990 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8991 // The delay slot overwrites one of our conditions.
8992 // Allocate the branch condition registers instead.
8996 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8997 if(!((current.is32>>rs1[i])&1))
8999 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9005 delayslot_alloc(¤t,i+1);
9009 // Don't alloc the delay slot yet because we might not execute it
9010 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9015 alloc_cc(¤t,i);
9016 dirty_reg(¤t,CCREG);
9017 alloc_reg(¤t,i,rs1[i]);
9018 alloc_reg(¤t,i,rs2[i]);
9019 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9021 alloc_reg64(¤t,i,rs1[i]);
9022 alloc_reg64(¤t,i,rs2[i]);
9026 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9031 alloc_cc(¤t,i);
9032 dirty_reg(¤t,CCREG);
9033 alloc_reg(¤t,i,rs1[i]);
9034 if(!(current.is32>>rs1[i]&1))
9036 alloc_reg64(¤t,i,rs1[i]);
9040 //current.isconst=0;
9043 //current.isconst=0;
9044 //current.wasconst=0;
9045 //regs[i].wasconst=0;
9046 clear_const(¤t,rs1[i]);
9047 clear_const(¤t,rt1[i]);
9048 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9049 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9051 alloc_cc(¤t,i);
9052 dirty_reg(¤t,CCREG);
9053 alloc_reg(¤t,i,rs1[i]);
9054 if(!(current.is32>>rs1[i]&1))
9056 alloc_reg64(¤t,i,rs1[i]);
9058 if (rt1[i]==31) { // BLTZAL/BGEZAL
9059 alloc_reg(¤t,i,31);
9060 dirty_reg(¤t,31);
9061 //#ifdef REG_PREFETCH
9062 //alloc_reg(¤t,i,PTEMP);
9064 //current.is32|=1LL<<rt1[i];
9066 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9067 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9068 // Allocate the branch condition registers instead.
9072 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9073 if(!((current.is32>>rs1[i])&1))
9075 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9081 delayslot_alloc(¤t,i+1);
9085 // Don't alloc the delay slot yet because we might not execute it
9086 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9091 alloc_cc(¤t,i);
9092 dirty_reg(¤t,CCREG);
9093 alloc_reg(¤t,i,rs1[i]);
9094 if(!(current.is32>>rs1[i]&1))
9096 alloc_reg64(¤t,i,rs1[i]);
9100 //current.isconst=0;
9106 if(likely[i]==0) // BC1F/BC1T
9108 // TODO: Theoretically we can run out of registers here on x86.
9109 // The delay slot can allocate up to six, and we need to check
9110 // CSREG before executing the delay slot. Possibly we can drop
9111 // the cycle count and then reload it after checking that the
9112 // FPU is in a usable state, or don't do out-of-order execution.
9113 alloc_cc(¤t,i);
9114 dirty_reg(¤t,CCREG);
9115 alloc_reg(¤t,i,FSREG);
9116 alloc_reg(¤t,i,CSREG);
9117 if(itype[i+1]==FCOMP) {
9118 // The delay slot overwrites the branch condition.
9119 // Allocate the branch condition registers instead.
9120 alloc_cc(¤t,i);
9121 dirty_reg(¤t,CCREG);
9122 alloc_reg(¤t,i,CSREG);
9123 alloc_reg(¤t,i,FSREG);
9127 delayslot_alloc(¤t,i+1);
9128 alloc_reg(¤t,i+1,CSREG);
9132 // Don't alloc the delay slot yet because we might not execute it
9133 if(likely[i]) // BC1FL/BC1TL
9135 alloc_cc(¤t,i);
9136 dirty_reg(¤t,CCREG);
9137 alloc_reg(¤t,i,CSREG);
9138 alloc_reg(¤t,i,FSREG);
9144 imm16_alloc(¤t,i);
9148 load_alloc(¤t,i);
9152 store_alloc(¤t,i);
9155 alu_alloc(¤t,i);
9158 shift_alloc(¤t,i);
9161 multdiv_alloc(¤t,i);
9164 shiftimm_alloc(¤t,i);
9167 mov_alloc(¤t,i);
9170 cop0_alloc(¤t,i);
9174 cop1_alloc(¤t,i);
9177 c1ls_alloc(¤t,i);
9180 c2ls_alloc(¤t,i);
9183 c2op_alloc(¤t,i);
9186 fconv_alloc(¤t,i);
9189 float_alloc(¤t,i);
9192 fcomp_alloc(¤t,i);
9197 syscall_alloc(¤t,i);
9200 pagespan_alloc(¤t,i);
9204 // Drop the upper half of registers that have become 32-bit
9205 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9206 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9207 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9208 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9211 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9212 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9213 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9214 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9218 // Create entry (branch target) regmap
9219 for(hr=0;hr<HOST_REGS;hr++)
9222 r=current.regmap[hr];
9224 if(r!=regmap_pre[i][hr]) {
9225 // TODO: delay slot (?)
9226 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9227 if(or<0||(r&63)>=TEMPREG){
9228 regs[i].regmap_entry[hr]=-1;
9232 // Just move it to a different register
9233 regs[i].regmap_entry[hr]=r;
9234 // If it was dirty before, it's still dirty
9235 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9242 regs[i].regmap_entry[hr]=0;
9246 if((current.u>>r)&1) {
9247 regs[i].regmap_entry[hr]=-1;
9248 //regs[i].regmap[hr]=-1;
9249 current.regmap[hr]=-1;
9251 regs[i].regmap_entry[hr]=r;
9254 if((current.uu>>(r&63))&1) {
9255 regs[i].regmap_entry[hr]=-1;
9256 //regs[i].regmap[hr]=-1;
9257 current.regmap[hr]=-1;
9259 regs[i].regmap_entry[hr]=r;
9263 // Branches expect CCREG to be allocated at the target
9264 if(regmap_pre[i][hr]==CCREG)
9265 regs[i].regmap_entry[hr]=CCREG;
9267 regs[i].regmap_entry[hr]=-1;
9270 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9272 /* Branch post-alloc */
9275 current.was32=current.is32;
9276 current.wasdirty=current.dirty;
9277 switch(itype[i-1]) {
9279 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9280 branch_regs[i-1].isconst=0;
9281 branch_regs[i-1].wasconst=0;
9282 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9283 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9284 alloc_cc(&branch_regs[i-1],i-1);
9285 dirty_reg(&branch_regs[i-1],CCREG);
9286 if(rt1[i-1]==31) { // JAL
9287 alloc_reg(&branch_regs[i-1],i-1,31);
9288 dirty_reg(&branch_regs[i-1],31);
9289 branch_regs[i-1].is32|=1LL<<31;
9291 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9292 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9295 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9296 branch_regs[i-1].isconst=0;
9297 branch_regs[i-1].wasconst=0;
9298 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9299 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9300 alloc_cc(&branch_regs[i-1],i-1);
9301 dirty_reg(&branch_regs[i-1],CCREG);
9302 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9303 if(rt1[i-1]!=0) { // JALR
9304 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9305 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9306 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9309 if(rs1[i-1]==31) { // JALR
9310 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9311 #ifndef HOST_IMM_ADDR32
9312 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9316 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9317 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9320 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9322 alloc_cc(¤t,i-1);
9323 dirty_reg(¤t,CCREG);
9324 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9325 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9326 // The delay slot overwrote one of our conditions
9327 // Delay slot goes after the test (in order)
9328 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9329 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9330 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9333 delayslot_alloc(¤t,i);
9338 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9339 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9340 // Alloc the branch condition registers
9341 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9342 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9343 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9345 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9346 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9349 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9350 branch_regs[i-1].isconst=0;
9351 branch_regs[i-1].wasconst=0;
9352 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9353 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9356 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9358 alloc_cc(¤t,i-1);
9359 dirty_reg(¤t,CCREG);
9360 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9361 // The delay slot overwrote the branch condition
9362 // Delay slot goes after the test (in order)
9363 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9364 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9365 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9368 delayslot_alloc(¤t,i);
9373 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9374 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9375 // Alloc the branch condition register
9376 alloc_reg(¤t,i-1,rs1[i-1]);
9377 if(!(current.is32>>rs1[i-1]&1))
9379 alloc_reg64(¤t,i-1,rs1[i-1]);
9382 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9383 branch_regs[i-1].isconst=0;
9384 branch_regs[i-1].wasconst=0;
9385 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9386 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9389 // Alloc the delay slot in case the branch is taken
9390 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9392 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9393 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9394 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9395 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9396 alloc_cc(&branch_regs[i-1],i);
9397 dirty_reg(&branch_regs[i-1],CCREG);
9398 delayslot_alloc(&branch_regs[i-1],i);
9399 branch_regs[i-1].isconst=0;
9400 alloc_reg(¤t,i,CCREG); // Not taken path
9401 dirty_reg(¤t,CCREG);
9402 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9405 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9407 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9408 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9409 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9410 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9411 alloc_cc(&branch_regs[i-1],i);
9412 dirty_reg(&branch_regs[i-1],CCREG);
9413 delayslot_alloc(&branch_regs[i-1],i);
9414 branch_regs[i-1].isconst=0;
9415 alloc_reg(¤t,i,CCREG); // Not taken path
9416 dirty_reg(¤t,CCREG);
9417 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9421 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9422 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9424 alloc_cc(¤t,i-1);
9425 dirty_reg(¤t,CCREG);
9426 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9427 // The delay slot overwrote the branch condition
9428 // Delay slot goes after the test (in order)
9429 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9430 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9431 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9434 delayslot_alloc(¤t,i);
9439 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9440 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9441 // Alloc the branch condition register
9442 alloc_reg(¤t,i-1,rs1[i-1]);
9443 if(!(current.is32>>rs1[i-1]&1))
9445 alloc_reg64(¤t,i-1,rs1[i-1]);
9448 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9449 branch_regs[i-1].isconst=0;
9450 branch_regs[i-1].wasconst=0;
9451 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9452 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9455 // Alloc the delay slot in case the branch is taken
9456 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9458 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9459 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9460 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9461 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9462 alloc_cc(&branch_regs[i-1],i);
9463 dirty_reg(&branch_regs[i-1],CCREG);
9464 delayslot_alloc(&branch_regs[i-1],i);
9465 branch_regs[i-1].isconst=0;
9466 alloc_reg(¤t,i,CCREG); // Not taken path
9467 dirty_reg(¤t,CCREG);
9468 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9470 // FIXME: BLTZAL/BGEZAL
9471 if(opcode2[i-1]&0x10) { // BxxZAL
9472 alloc_reg(&branch_regs[i-1],i-1,31);
9473 dirty_reg(&branch_regs[i-1],31);
9474 branch_regs[i-1].is32|=1LL<<31;
9478 if(likely[i-1]==0) // BC1F/BC1T
9480 alloc_cc(¤t,i-1);
9481 dirty_reg(¤t,CCREG);
9482 if(itype[i]==FCOMP) {
9483 // The delay slot overwrote the branch condition
9484 // Delay slot goes after the test (in order)
9485 delayslot_alloc(¤t,i);
9490 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9491 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9492 // Alloc the branch condition register
9493 alloc_reg(¤t,i-1,FSREG);
9495 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9496 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9500 // Alloc the delay slot in case the branch is taken
9501 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9502 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9503 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9504 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9505 alloc_cc(&branch_regs[i-1],i);
9506 dirty_reg(&branch_regs[i-1],CCREG);
9507 delayslot_alloc(&branch_regs[i-1],i);
9508 branch_regs[i-1].isconst=0;
9509 alloc_reg(¤t,i,CCREG); // Not taken path
9510 dirty_reg(¤t,CCREG);
9511 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9516 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9518 if(rt1[i-1]==31) // JAL/JALR
9520 // Subroutine call will return here, don't alloc any registers
9523 clear_all_regs(current.regmap);
9524 alloc_reg(¤t,i,CCREG);
9525 dirty_reg(¤t,CCREG);
9529 // Internal branch will jump here, match registers to caller
9530 current.is32=0x3FFFFFFFFLL;
9532 clear_all_regs(current.regmap);
9533 alloc_reg(¤t,i,CCREG);
9534 dirty_reg(¤t,CCREG);
9537 if(ba[j]==start+i*4+4) {
9538 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9539 current.is32=branch_regs[j].is32;
9540 current.dirty=branch_regs[j].dirty;
9545 if(ba[j]==start+i*4+4) {
9546 for(hr=0;hr<HOST_REGS;hr++) {
9547 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9548 current.regmap[hr]=-1;
9550 current.is32&=branch_regs[j].is32;
9551 current.dirty&=branch_regs[j].dirty;
9560 // Count cycles in between branches
9562 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9567 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9569 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9571 else if(itype[i]==C2LS)
9581 flush_dirty_uppers(¤t);
9583 regs[i].is32=current.is32;
9584 regs[i].dirty=current.dirty;
9585 regs[i].isconst=current.isconst;
9586 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9588 for(hr=0;hr<HOST_REGS;hr++) {
9589 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9590 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9591 regs[i].wasconst&=~(1<<hr);
9595 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9598 /* Pass 4 - Cull unused host registers */
9602 for (i=slen-1;i>=0;i--)
9605 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9607 if(ba[i]<start || ba[i]>=(start+slen*4))
9609 // Branch out of this block, don't need anything
9615 // Need whatever matches the target
9617 int t=(ba[i]-start)>>2;
9618 for(hr=0;hr<HOST_REGS;hr++)
9620 if(regs[i].regmap_entry[hr]>=0) {
9621 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9625 // Conditional branch may need registers for following instructions
9626 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9629 nr|=needed_reg[i+2];
9630 for(hr=0;hr<HOST_REGS;hr++)
9632 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9633 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9637 // Don't need stuff which is overwritten
9638 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9639 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9640 // Merge in delay slot
9641 for(hr=0;hr<HOST_REGS;hr++)
9644 // These are overwritten unless the branch is "likely"
9645 // and the delay slot is nullified if not taken
9646 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9647 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9649 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9650 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9651 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9652 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9653 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9654 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9655 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9656 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9657 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9658 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9659 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9661 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9662 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9663 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9665 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9666 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9667 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9671 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9673 // SYSCALL instruction (software interrupt)
9676 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9678 // ERET instruction (return from interrupt)
9684 for(hr=0;hr<HOST_REGS;hr++) {
9685 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9686 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9687 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9688 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9692 for(hr=0;hr<HOST_REGS;hr++)
9694 // Overwritten registers are not needed
9695 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9696 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9697 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9698 // Source registers are needed
9699 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9700 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9701 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9702 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9703 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9704 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9705 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9706 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9707 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9708 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9709 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9711 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9712 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9713 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9715 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9716 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9717 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9719 // Don't store a register immediately after writing it,
9720 // may prevent dual-issue.
9721 // But do so if this is a branch target, otherwise we
9722 // might have to load the register before the branch.
9723 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9724 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9725 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9726 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9727 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9729 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9730 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9731 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9732 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9736 // Cycle count is needed at branches. Assume it is needed at the target too.
9737 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9738 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9739 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9744 // Deallocate unneeded registers
9745 for(hr=0;hr<HOST_REGS;hr++)
9748 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9749 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9750 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9751 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9753 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9756 regs[i].regmap[hr]=-1;
9757 regs[i].isconst&=~(1<<hr);
9759 regmap_pre[i+2][hr]=-1;
9760 regs[i+2].wasconst&=~(1<<hr);
9765 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9767 int d1=0,d2=0,map=0,temp=0;
9768 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9774 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9775 itype[i+1]==STORE || itype[i+1]==STORELR ||
9776 itype[i+1]==C1LS || itype[i+1]==C2LS)
9779 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9780 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9783 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9784 itype[i+1]==C1LS || itype[i+1]==C2LS)
9786 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9787 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9788 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9789 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9790 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9791 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9792 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9793 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9794 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9795 regs[i].regmap[hr]!=map )
9797 regs[i].regmap[hr]=-1;
9798 regs[i].isconst&=~(1<<hr);
9799 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9800 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9801 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9802 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9803 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9804 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9805 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9806 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9807 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9808 branch_regs[i].regmap[hr]!=map)
9810 branch_regs[i].regmap[hr]=-1;
9811 branch_regs[i].regmap_entry[hr]=-1;
9812 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9814 if(!likely[i]&&i<slen-2) {
9815 regmap_pre[i+2][hr]=-1;
9816 regs[i+2].wasconst&=~(1<<hr);
9827 int d1=0,d2=0,map=-1,temp=-1;
9828 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9834 if(itype[i]==LOAD || itype[i]==LOADLR ||
9835 itype[i]==STORE || itype[i]==STORELR ||
9836 itype[i]==C1LS || itype[i]==C2LS)
9838 } else if(itype[i]==STORE || itype[i]==STORELR ||
9839 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9842 if(itype[i]==LOADLR || itype[i]==STORELR ||
9843 itype[i]==C1LS || itype[i]==C2LS)
9845 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9846 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9847 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9848 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9849 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9850 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9852 if(i<slen-1&&!is_ds[i]) {
9853 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9854 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9855 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9857 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9858 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9860 regmap_pre[i+1][hr]=-1;
9861 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9862 regs[i+1].wasconst&=~(1<<hr);
9864 regs[i].regmap[hr]=-1;
9865 regs[i].isconst&=~(1<<hr);
9873 /* Pass 5 - Pre-allocate registers */
9875 // If a register is allocated during a loop, try to allocate it for the
9876 // entire loop, if possible. This avoids loading/storing registers
9877 // inside of the loop.
9879 signed char f_regmap[HOST_REGS];
9880 clear_all_regs(f_regmap);
9881 for(i=0;i<slen-1;i++)
9883 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9885 if(ba[i]>=start && ba[i]<(start+i*4))
9886 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9887 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9888 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9889 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9890 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9891 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9893 int t=(ba[i]-start)>>2;
9894 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9895 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
9896 for(hr=0;hr<HOST_REGS;hr++)
9898 if(regs[i].regmap[hr]>64) {
9899 if(!((regs[i].dirty>>hr)&1))
9900 f_regmap[hr]=regs[i].regmap[hr];
9901 else f_regmap[hr]=-1;
9903 else if(regs[i].regmap[hr]>=0) {
9904 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9905 // dealloc old register
9907 for(n=0;n<HOST_REGS;n++)
9909 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9911 // and alloc new one
9912 f_regmap[hr]=regs[i].regmap[hr];
9915 if(branch_regs[i].regmap[hr]>64) {
9916 if(!((branch_regs[i].dirty>>hr)&1))
9917 f_regmap[hr]=branch_regs[i].regmap[hr];
9918 else f_regmap[hr]=-1;
9920 else if(branch_regs[i].regmap[hr]>=0) {
9921 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9922 // dealloc old register
9924 for(n=0;n<HOST_REGS;n++)
9926 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9928 // and alloc new one
9929 f_regmap[hr]=branch_regs[i].regmap[hr];
9933 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9934 f_regmap[hr]=branch_regs[i].regmap[hr];
9936 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
9937 f_regmap[hr]=branch_regs[i].regmap[hr];
9939 // Avoid dirty->clean transition
9940 #ifdef DESTRUCTIVE_WRITEBACK
9941 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9943 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9944 // case above, however it's always a good idea. We can't hoist the
9945 // load if the register was already allocated, so there's no point
9946 // wasting time analyzing most of these cases. It only "succeeds"
9947 // when the mapping was different and the load can be replaced with
9948 // a mov, which is of negligible benefit. So such cases are
9950 if(f_regmap[hr]>0) {
9951 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
9955 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9956 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9957 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9959 // NB This can exclude the case where the upper-half
9960 // register is lower numbered than the lower-half
9961 // register. Not sure if it's worth fixing...
9962 if(get_reg(regs[j].regmap,r&63)<0) break;
9963 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
9964 if(regs[j].is32&(1LL<<(r&63))) break;
9966 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9967 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9969 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9970 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9972 if(get_reg(regs[i].regmap,r&63)<0) break;
9973 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9976 while(k>1&®s[k-1].regmap[hr]==-1) {
9977 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9978 //printf("no free regs for store %x\n",start+(k-1)*4);
9981 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9982 //printf("no-match due to different register\n");
9985 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9986 //printf("no-match due to branch\n");
9989 // call/ret fast path assumes no registers allocated
9990 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
9994 // NB This can exclude the case where the upper-half
9995 // register is lower numbered than the lower-half
9996 // register. Not sure if it's worth fixing...
9997 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9998 if(regs[k-1].is32&(1LL<<(r&63))) break;
10003 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10004 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10005 //printf("bad match after branch\n");
10009 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
10010 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10012 regs[k].regmap_entry[hr]=f_regmap[hr];
10013 regs[k].regmap[hr]=f_regmap[hr];
10014 regmap_pre[k+1][hr]=f_regmap[hr];
10015 regs[k].wasdirty&=~(1<<hr);
10016 regs[k].dirty&=~(1<<hr);
10017 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
10018 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
10019 regs[k].wasconst&=~(1<<hr);
10020 regs[k].isconst&=~(1<<hr);
10025 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10028 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10029 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
10030 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10031 regs[i].regmap_entry[hr]=f_regmap[hr];
10032 regs[i].regmap[hr]=f_regmap[hr];
10033 regs[i].wasdirty&=~(1<<hr);
10034 regs[i].dirty&=~(1<<hr);
10035 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
10036 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
10037 regs[i].wasconst&=~(1<<hr);
10038 regs[i].isconst&=~(1<<hr);
10039 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10040 branch_regs[i].wasdirty&=~(1<<hr);
10041 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
10042 branch_regs[i].regmap[hr]=f_regmap[hr];
10043 branch_regs[i].dirty&=~(1<<hr);
10044 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
10045 branch_regs[i].wasconst&=~(1<<hr);
10046 branch_regs[i].isconst&=~(1<<hr);
10047 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10048 regmap_pre[i+2][hr]=f_regmap[hr];
10049 regs[i+2].wasdirty&=~(1<<hr);
10050 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
10051 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10052 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10057 // Alloc register clean at beginning of loop,
10058 // but may dirty it in pass 6
10059 regs[k].regmap_entry[hr]=f_regmap[hr];
10060 regs[k].regmap[hr]=f_regmap[hr];
10061 regs[k].dirty&=~(1<<hr);
10062 regs[k].wasconst&=~(1<<hr);
10063 regs[k].isconst&=~(1<<hr);
10064 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10065 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10066 branch_regs[k].regmap[hr]=f_regmap[hr];
10067 branch_regs[k].dirty&=~(1<<hr);
10068 branch_regs[k].wasconst&=~(1<<hr);
10069 branch_regs[k].isconst&=~(1<<hr);
10070 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10071 regmap_pre[k+2][hr]=f_regmap[hr];
10072 regs[k+2].wasdirty&=~(1<<hr);
10073 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10074 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10079 regmap_pre[k+1][hr]=f_regmap[hr];
10080 regs[k+1].wasdirty&=~(1<<hr);
10083 if(regs[j].regmap[hr]==f_regmap[hr])
10084 regs[j].regmap_entry[hr]=f_regmap[hr];
10088 if(regs[j].regmap[hr]>=0)
10090 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10091 //printf("no-match due to different register\n");
10094 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10095 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10098 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10100 // Stop on unconditional branch
10103 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10106 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10109 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10112 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10113 //printf("no-match due to different register (branch)\n");
10117 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10118 //printf("No free regs for store %x\n",start+j*4);
10121 if(f_regmap[hr]>=64) {
10122 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10127 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10138 // Non branch or undetermined branch target
10139 for(hr=0;hr<HOST_REGS;hr++)
10141 if(hr!=EXCLUDE_REG) {
10142 if(regs[i].regmap[hr]>64) {
10143 if(!((regs[i].dirty>>hr)&1))
10144 f_regmap[hr]=regs[i].regmap[hr];
10146 else if(regs[i].regmap[hr]>=0) {
10147 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10148 // dealloc old register
10150 for(n=0;n<HOST_REGS;n++)
10152 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10154 // and alloc new one
10155 f_regmap[hr]=regs[i].regmap[hr];
10160 // Try to restore cycle count at branch targets
10162 for(j=i;j<slen-1;j++) {
10163 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10164 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10165 //printf("no free regs for store %x\n",start+j*4);
10169 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10171 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10173 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10174 regs[k].regmap[HOST_CCREG]=CCREG;
10175 regmap_pre[k+1][HOST_CCREG]=CCREG;
10176 regs[k+1].wasdirty|=1<<HOST_CCREG;
10177 regs[k].dirty|=1<<HOST_CCREG;
10178 regs[k].wasconst&=~(1<<HOST_CCREG);
10179 regs[k].isconst&=~(1<<HOST_CCREG);
10182 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10184 // Work backwards from the branch target
10185 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10187 //printf("Extend backwards\n");
10190 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10191 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10192 //printf("no free regs for store %x\n",start+(k-1)*4);
10197 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10198 //printf("Extend CC, %x ->\n",start+k*4);
10200 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10201 regs[k].regmap[HOST_CCREG]=CCREG;
10202 regmap_pre[k+1][HOST_CCREG]=CCREG;
10203 regs[k+1].wasdirty|=1<<HOST_CCREG;
10204 regs[k].dirty|=1<<HOST_CCREG;
10205 regs[k].wasconst&=~(1<<HOST_CCREG);
10206 regs[k].isconst&=~(1<<HOST_CCREG);
10211 //printf("Fail Extend CC, %x ->\n",start+k*4);
10215 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10216 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10217 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10218 itype[i]!=FCONV&&itype[i]!=FCOMP)
10220 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10225 // Cache memory offset or tlb map pointer if a register is available
10226 #ifndef HOST_IMM_ADDR32
10231 int earliest_available[HOST_REGS];
10232 int loop_start[HOST_REGS];
10233 int score[HOST_REGS];
10234 int end[HOST_REGS];
10235 int reg=using_tlb?MMREG:ROREG;
10238 for(hr=0;hr<HOST_REGS;hr++) {
10239 score[hr]=0;earliest_available[hr]=0;
10240 loop_start[hr]=MAXBLOCK;
10242 for(i=0;i<slen-1;i++)
10244 // Can't do anything if no registers are available
10245 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10246 for(hr=0;hr<HOST_REGS;hr++) {
10247 score[hr]=0;earliest_available[hr]=i+1;
10248 loop_start[hr]=MAXBLOCK;
10251 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10253 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10254 for(hr=0;hr<HOST_REGS;hr++) {
10255 score[hr]=0;earliest_available[hr]=i+1;
10256 loop_start[hr]=MAXBLOCK;
10260 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10261 for(hr=0;hr<HOST_REGS;hr++) {
10262 score[hr]=0;earliest_available[hr]=i+1;
10263 loop_start[hr]=MAXBLOCK;
10268 // Mark unavailable registers
10269 for(hr=0;hr<HOST_REGS;hr++) {
10270 if(regs[i].regmap[hr]>=0) {
10271 score[hr]=0;earliest_available[hr]=i+1;
10272 loop_start[hr]=MAXBLOCK;
10274 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10275 if(branch_regs[i].regmap[hr]>=0) {
10276 score[hr]=0;earliest_available[hr]=i+2;
10277 loop_start[hr]=MAXBLOCK;
10281 // No register allocations after unconditional jumps
10282 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10284 for(hr=0;hr<HOST_REGS;hr++) {
10285 score[hr]=0;earliest_available[hr]=i+2;
10286 loop_start[hr]=MAXBLOCK;
10288 i++; // Skip delay slot too
10289 //printf("skip delay slot: %x\n",start+i*4);
10293 if(itype[i]==LOAD||itype[i]==LOADLR||
10294 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10295 for(hr=0;hr<HOST_REGS;hr++) {
10296 if(hr!=EXCLUDE_REG) {
10298 for(j=i;j<slen-1;j++) {
10299 if(regs[j].regmap[hr]>=0) break;
10300 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10301 if(branch_regs[j].regmap[hr]>=0) break;
10303 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10305 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10308 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10309 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10310 int t=(ba[j]-start)>>2;
10311 if(t<j&&t>=earliest_available[hr]) {
10312 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10313 // Score a point for hoisting loop invariant
10314 if(t<loop_start[hr]) loop_start[hr]=t;
10315 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10321 if(regs[t].regmap[hr]==reg) {
10322 // Score a point if the branch target matches this register
10327 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10328 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10333 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10335 // Stop on unconditional branch
10339 if(itype[j]==LOAD||itype[j]==LOADLR||
10340 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10347 // Find highest score and allocate that register
10349 for(hr=0;hr<HOST_REGS;hr++) {
10350 if(hr!=EXCLUDE_REG) {
10351 if(score[hr]>score[maxscore]) {
10353 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10357 if(score[maxscore]>1)
10359 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10360 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10361 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10362 assert(regs[j].regmap[maxscore]<0);
10363 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10364 regs[j].regmap[maxscore]=reg;
10365 regs[j].dirty&=~(1<<maxscore);
10366 regs[j].wasconst&=~(1<<maxscore);
10367 regs[j].isconst&=~(1<<maxscore);
10368 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10369 branch_regs[j].regmap[maxscore]=reg;
10370 branch_regs[j].wasdirty&=~(1<<maxscore);
10371 branch_regs[j].dirty&=~(1<<maxscore);
10372 branch_regs[j].wasconst&=~(1<<maxscore);
10373 branch_regs[j].isconst&=~(1<<maxscore);
10374 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10375 regmap_pre[j+2][maxscore]=reg;
10376 regs[j+2].wasdirty&=~(1<<maxscore);
10378 // loop optimization (loop_preload)
10379 int t=(ba[j]-start)>>2;
10380 if(t==loop_start[maxscore]) {
10381 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10382 regs[t].regmap_entry[maxscore]=reg;
10387 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10388 regmap_pre[j+1][maxscore]=reg;
10389 regs[j+1].wasdirty&=~(1<<maxscore);
10394 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10395 for(hr=0;hr<HOST_REGS;hr++) {
10396 score[hr]=0;earliest_available[hr]=i+i;
10397 loop_start[hr]=MAXBLOCK;
10405 // This allocates registers (if possible) one instruction prior
10406 // to use, which can avoid a load-use penalty on certain CPUs.
10407 for(i=0;i<slen-1;i++)
10409 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10413 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10414 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10417 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10419 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10421 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10422 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10423 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10424 regs[i].isconst&=~(1<<hr);
10425 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10426 constmap[i][hr]=constmap[i+1][hr];
10427 regs[i+1].wasdirty&=~(1<<hr);
10428 regs[i].dirty&=~(1<<hr);
10433 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10435 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10437 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10438 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10439 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10440 regs[i].isconst&=~(1<<hr);
10441 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10442 constmap[i][hr]=constmap[i+1][hr];
10443 regs[i+1].wasdirty&=~(1<<hr);
10444 regs[i].dirty&=~(1<<hr);
10448 // Preload target address for load instruction (non-constant)
10449 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10450 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10452 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10454 regs[i].regmap[hr]=rs1[i+1];
10455 regmap_pre[i+1][hr]=rs1[i+1];
10456 regs[i+1].regmap_entry[hr]=rs1[i+1];
10457 regs[i].isconst&=~(1<<hr);
10458 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10459 constmap[i][hr]=constmap[i+1][hr];
10460 regs[i+1].wasdirty&=~(1<<hr);
10461 regs[i].dirty&=~(1<<hr);
10465 // Load source into target register
10466 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10467 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10469 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10471 regs[i].regmap[hr]=rs1[i+1];
10472 regmap_pre[i+1][hr]=rs1[i+1];
10473 regs[i+1].regmap_entry[hr]=rs1[i+1];
10474 regs[i].isconst&=~(1<<hr);
10475 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10476 constmap[i][hr]=constmap[i+1][hr];
10477 regs[i+1].wasdirty&=~(1<<hr);
10478 regs[i].dirty&=~(1<<hr);
10482 // Preload map address
10483 #ifndef HOST_IMM_ADDR32
10484 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10485 hr=get_reg(regs[i+1].regmap,TLREG);
10487 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10488 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10490 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10492 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10493 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10494 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10495 regs[i].isconst&=~(1<<hr);
10496 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10497 constmap[i][hr]=constmap[i+1][hr];
10498 regs[i+1].wasdirty&=~(1<<hr);
10499 regs[i].dirty&=~(1<<hr);
10501 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10503 // move it to another register
10504 regs[i+1].regmap[hr]=-1;
10505 regmap_pre[i+2][hr]=-1;
10506 regs[i+1].regmap[nr]=TLREG;
10507 regmap_pre[i+2][nr]=TLREG;
10508 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10509 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10510 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10511 regs[i].isconst&=~(1<<nr);
10512 regs[i+1].isconst&=~(1<<nr);
10513 regs[i].dirty&=~(1<<nr);
10514 regs[i+1].wasdirty&=~(1<<nr);
10515 regs[i+1].dirty&=~(1<<nr);
10516 regs[i+2].wasdirty&=~(1<<nr);
10522 // Address for store instruction (non-constant)
10523 if(itype[i+1]==STORE||itype[i+1]==STORELR
10524 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10525 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10526 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10527 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10528 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10530 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10532 regs[i].regmap[hr]=rs1[i+1];
10533 regmap_pre[i+1][hr]=rs1[i+1];
10534 regs[i+1].regmap_entry[hr]=rs1[i+1];
10535 regs[i].isconst&=~(1<<hr);
10536 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10537 constmap[i][hr]=constmap[i+1][hr];
10538 regs[i+1].wasdirty&=~(1<<hr);
10539 regs[i].dirty&=~(1<<hr);
10543 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10544 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10546 hr=get_reg(regs[i+1].regmap,FTEMP);
10548 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10550 regs[i].regmap[hr]=rs1[i+1];
10551 regmap_pre[i+1][hr]=rs1[i+1];
10552 regs[i+1].regmap_entry[hr]=rs1[i+1];
10553 regs[i].isconst&=~(1<<hr);
10554 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10555 constmap[i][hr]=constmap[i+1][hr];
10556 regs[i+1].wasdirty&=~(1<<hr);
10557 regs[i].dirty&=~(1<<hr);
10559 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10561 // move it to another register
10562 regs[i+1].regmap[hr]=-1;
10563 regmap_pre[i+2][hr]=-1;
10564 regs[i+1].regmap[nr]=FTEMP;
10565 regmap_pre[i+2][nr]=FTEMP;
10566 regs[i].regmap[nr]=rs1[i+1];
10567 regmap_pre[i+1][nr]=rs1[i+1];
10568 regs[i+1].regmap_entry[nr]=rs1[i+1];
10569 regs[i].isconst&=~(1<<nr);
10570 regs[i+1].isconst&=~(1<<nr);
10571 regs[i].dirty&=~(1<<nr);
10572 regs[i+1].wasdirty&=~(1<<nr);
10573 regs[i+1].dirty&=~(1<<nr);
10574 regs[i+2].wasdirty&=~(1<<nr);
10578 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10579 if(itype[i+1]==LOAD)
10580 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10581 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10582 hr=get_reg(regs[i+1].regmap,FTEMP);
10583 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10584 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10585 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10587 if(hr>=0&®s[i].regmap[hr]<0) {
10588 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10589 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10590 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10591 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10592 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10593 regs[i].isconst&=~(1<<hr);
10594 regs[i+1].wasdirty&=~(1<<hr);
10595 regs[i].dirty&=~(1<<hr);
10604 /* Pass 6 - Optimize clean/dirty state */
10605 clean_registers(0,slen-1,1);
10607 /* Pass 7 - Identify 32-bit registers */
10613 for (i=slen-1;i>=0;i--)
10616 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10618 if(ba[i]<start || ba[i]>=(start+slen*4))
10620 // Branch out of this block, don't need anything
10626 // Need whatever matches the target
10627 // (and doesn't get overwritten by the delay slot instruction)
10629 int t=(ba[i]-start)>>2;
10630 if(ba[i]>start+i*4) {
10632 if(!(requires_32bit[t]&~regs[i].was32))
10633 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10636 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10637 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10638 if(!(pr32[t]&~regs[i].was32))
10639 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10642 // Conditional branch may need registers for following instructions
10643 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10646 r32|=requires_32bit[i+2];
10647 r32&=regs[i].was32;
10648 // Mark this address as a branch target since it may be called
10649 // upon return from interrupt
10653 // Merge in delay slot
10655 // These are overwritten unless the branch is "likely"
10656 // and the delay slot is nullified if not taken
10657 r32&=~(1LL<<rt1[i+1]);
10658 r32&=~(1LL<<rt2[i+1]);
10660 // Assume these are needed (delay slot)
10663 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10667 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10669 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10671 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10673 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10675 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10678 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10680 // SYSCALL instruction (software interrupt)
10683 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10685 // ERET instruction (return from interrupt)
10689 r32&=~(1LL<<rt1[i]);
10690 r32&=~(1LL<<rt2[i]);
10693 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10697 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10699 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10701 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10703 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10705 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10707 requires_32bit[i]=r32;
10709 // Dirty registers which are 32-bit, require 32-bit input
10710 // as they will be written as 32-bit values
10711 for(hr=0;hr<HOST_REGS;hr++)
10713 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10714 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10715 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10716 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10720 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10723 for (i=slen-1;i>=0;i--)
10725 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10727 // Conditional branch
10728 if((source[i]>>16)!=0x1000&&i<slen-2) {
10729 // Mark this address as a branch target since it may be called
10730 // upon return from interrupt
10737 if(itype[slen-1]==SPAN) {
10738 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10741 /* Debug/disassembly */
10742 if((void*)assem_debug==(void*)printf)
10743 for(i=0;i<slen;i++)
10747 for(r=1;r<=CCREG;r++) {
10748 if((unneeded_reg[i]>>r)&1) {
10749 if(r==HIREG) printf(" HI");
10750 else if(r==LOREG) printf(" LO");
10751 else printf(" r%d",r);
10756 for(r=1;r<=CCREG;r++) {
10757 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10758 if(r==HIREG) printf(" HI");
10759 else if(r==LOREG) printf(" LO");
10760 else printf(" r%d",r);
10764 for(r=0;r<=CCREG;r++) {
10765 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10766 if((regs[i].was32>>r)&1) {
10767 if(r==CCREG) printf(" CC");
10768 else if(r==HIREG) printf(" HI");
10769 else if(r==LOREG) printf(" LO");
10770 else printf(" r%d",r);
10775 #if defined(__i386__) || defined(__x86_64__)
10776 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10779 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10782 if(needed_reg[i]&1) printf("eax ");
10783 if((needed_reg[i]>>1)&1) printf("ecx ");
10784 if((needed_reg[i]>>2)&1) printf("edx ");
10785 if((needed_reg[i]>>3)&1) printf("ebx ");
10786 if((needed_reg[i]>>5)&1) printf("ebp ");
10787 if((needed_reg[i]>>6)&1) printf("esi ");
10788 if((needed_reg[i]>>7)&1) printf("edi ");
10790 for(r=0;r<=CCREG;r++) {
10791 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10792 if((requires_32bit[i]>>r)&1) {
10793 if(r==CCREG) printf(" CC");
10794 else if(r==HIREG) printf(" HI");
10795 else if(r==LOREG) printf(" LO");
10796 else printf(" r%d",r);
10801 for(r=0;r<=CCREG;r++) {
10802 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10803 if((pr32[i]>>r)&1) {
10804 if(r==CCREG) printf(" CC");
10805 else if(r==HIREG) printf(" HI");
10806 else if(r==LOREG) printf(" LO");
10807 else printf(" r%d",r);
10810 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10812 #if defined(__i386__) || defined(__x86_64__)
10813 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10815 if(regs[i].wasdirty&1) printf("eax ");
10816 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10817 if((regs[i].wasdirty>>2)&1) printf("edx ");
10818 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10819 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10820 if((regs[i].wasdirty>>6)&1) printf("esi ");
10821 if((regs[i].wasdirty>>7)&1) printf("edi ");
10824 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10826 if(regs[i].wasdirty&1) printf("r0 ");
10827 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10828 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10829 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10830 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10831 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10832 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10833 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10834 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10835 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10836 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10837 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10840 disassemble_inst(i);
10841 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10842 #if defined(__i386__) || defined(__x86_64__)
10843 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10844 if(regs[i].dirty&1) printf("eax ");
10845 if((regs[i].dirty>>1)&1) printf("ecx ");
10846 if((regs[i].dirty>>2)&1) printf("edx ");
10847 if((regs[i].dirty>>3)&1) printf("ebx ");
10848 if((regs[i].dirty>>5)&1) printf("ebp ");
10849 if((regs[i].dirty>>6)&1) printf("esi ");
10850 if((regs[i].dirty>>7)&1) printf("edi ");
10853 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10854 if(regs[i].dirty&1) printf("r0 ");
10855 if((regs[i].dirty>>1)&1) printf("r1 ");
10856 if((regs[i].dirty>>2)&1) printf("r2 ");
10857 if((regs[i].dirty>>3)&1) printf("r3 ");
10858 if((regs[i].dirty>>4)&1) printf("r4 ");
10859 if((regs[i].dirty>>5)&1) printf("r5 ");
10860 if((regs[i].dirty>>6)&1) printf("r6 ");
10861 if((regs[i].dirty>>7)&1) printf("r7 ");
10862 if((regs[i].dirty>>8)&1) printf("r8 ");
10863 if((regs[i].dirty>>9)&1) printf("r9 ");
10864 if((regs[i].dirty>>10)&1) printf("r10 ");
10865 if((regs[i].dirty>>12)&1) printf("r12 ");
10868 if(regs[i].isconst) {
10869 printf("constants: ");
10870 #if defined(__i386__) || defined(__x86_64__)
10871 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10872 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10873 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10874 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10875 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10876 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10877 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10880 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10881 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10882 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10883 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10884 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10885 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10886 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10887 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10888 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10889 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10890 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10891 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10897 for(r=0;r<=CCREG;r++) {
10898 if((regs[i].is32>>r)&1) {
10899 if(r==CCREG) printf(" CC");
10900 else if(r==HIREG) printf(" HI");
10901 else if(r==LOREG) printf(" LO");
10902 else printf(" r%d",r);
10908 for(r=0;r<=CCREG;r++) {
10909 if((p32[i]>>r)&1) {
10910 if(r==CCREG) printf(" CC");
10911 else if(r==HIREG) printf(" HI");
10912 else if(r==LOREG) printf(" LO");
10913 else printf(" r%d",r);
10916 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10917 else printf("\n");*/
10918 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10919 #if defined(__i386__) || defined(__x86_64__)
10920 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10921 if(branch_regs[i].dirty&1) printf("eax ");
10922 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10923 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10924 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10925 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10926 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10927 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10930 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10931 if(branch_regs[i].dirty&1) printf("r0 ");
10932 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10933 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10934 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10935 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10936 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10937 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10938 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10939 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10940 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10941 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10942 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10946 for(r=0;r<=CCREG;r++) {
10947 if((branch_regs[i].is32>>r)&1) {
10948 if(r==CCREG) printf(" CC");
10949 else if(r==HIREG) printf(" HI");
10950 else if(r==LOREG) printf(" LO");
10951 else printf(" r%d",r);
10959 /* Pass 8 - Assembly */
10960 linkcount=0;stubcount=0;
10961 ds=0;is_delayslot=0;
10963 uint64_t is32_pre=0;
10965 u_int beginning=(u_int)out;
10966 if((u_int)addr&1) {
10970 u_int instr_addr0_override=0;
10973 if (start == 0x80030000) {
10974 // nasty hack for fastbios thing
10975 // override block entry to this code
10976 instr_addr0_override=(u_int)out;
10977 emit_movimm(start,0);
10978 // abuse io address var as a flag that we
10979 // have already returned here once
10980 emit_readword((int)&address,1);
10981 emit_writeword(0,(int)&pcaddr);
10982 emit_writeword(0,(int)&address);
10984 emit_jne((int)new_dyna_leave);
10987 for(i=0;i<slen;i++)
10989 //if(ds) printf("ds: ");
10990 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10992 ds=0; // Skip delay slot
10993 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10996 #ifndef DESTRUCTIVE_WRITEBACK
10997 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10999 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11000 unneeded_reg[i],unneeded_reg_upper[i]);
11001 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11002 unneeded_reg[i],unneeded_reg_upper[i]);
11004 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11005 is32_pre=branch_regs[i].is32;
11006 dirty_pre=branch_regs[i].dirty;
11008 is32_pre=regs[i].is32;
11009 dirty_pre=regs[i].dirty;
11013 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11015 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11016 unneeded_reg[i],unneeded_reg_upper[i]);
11017 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11019 // branch target entry point
11020 instr_addr[i]=(u_int)out;
11021 assem_debug("<->\n");
11023 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
11024 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11025 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11026 address_generation(i,®s[i],regs[i].regmap_entry);
11027 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11028 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11030 // Load the delay slot registers if necessary
11031 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11032 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11033 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11034 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11035 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11036 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11040 // Preload registers for following instruction
11041 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11042 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11043 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11044 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11045 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11046 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11048 // TODO: if(is_ooo(i)) address_generation(i+1);
11049 if(itype[i]==CJUMP||itype[i]==FJUMP)
11050 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11051 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11052 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11053 if(bt[i]) cop1_usable=0;
11057 alu_assemble(i,®s[i]);break;
11059 imm16_assemble(i,®s[i]);break;
11061 shift_assemble(i,®s[i]);break;
11063 shiftimm_assemble(i,®s[i]);break;
11065 load_assemble(i,®s[i]);break;
11067 loadlr_assemble(i,®s[i]);break;
11069 store_assemble(i,®s[i]);break;
11071 storelr_assemble(i,®s[i]);break;
11073 cop0_assemble(i,®s[i]);break;
11075 cop1_assemble(i,®s[i]);break;
11077 c1ls_assemble(i,®s[i]);break;
11079 cop2_assemble(i,®s[i]);break;
11081 c2ls_assemble(i,®s[i]);break;
11083 c2op_assemble(i,®s[i]);break;
11085 fconv_assemble(i,®s[i]);break;
11087 float_assemble(i,®s[i]);break;
11089 fcomp_assemble(i,®s[i]);break;
11091 multdiv_assemble(i,®s[i]);break;
11093 mov_assemble(i,®s[i]);break;
11095 syscall_assemble(i,®s[i]);break;
11097 hlecall_assemble(i,®s[i]);break;
11099 intcall_assemble(i,®s[i]);break;
11101 ujump_assemble(i,®s[i]);ds=1;break;
11103 rjump_assemble(i,®s[i]);ds=1;break;
11105 cjump_assemble(i,®s[i]);ds=1;break;
11107 sjump_assemble(i,®s[i]);ds=1;break;
11109 fjump_assemble(i,®s[i]);ds=1;break;
11111 pagespan_assemble(i,®s[i]);break;
11113 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11114 literal_pool(1024);
11116 literal_pool_jumpover(256);
11119 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11120 // If the block did not end with an unconditional branch,
11121 // add a jump to the next instruction.
11123 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11124 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11126 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11127 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11128 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11129 emit_loadreg(CCREG,HOST_CCREG);
11130 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11132 else if(!likely[i-2])
11134 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11135 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11139 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11140 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11142 add_to_linker((int)out,start+i*4,0);
11149 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11150 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11151 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11152 emit_loadreg(CCREG,HOST_CCREG);
11153 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11154 add_to_linker((int)out,start+i*4,0);
11158 // TODO: delay slot stubs?
11160 for(i=0;i<stubcount;i++)
11162 switch(stubs[i][0])
11170 do_readstub(i);break;
11175 do_writestub(i);break;
11177 do_ccstub(i);break;
11179 do_invstub(i);break;
11181 do_cop1stub(i);break;
11183 do_unalignedwritestub(i);break;
11187 if (instr_addr0_override)
11188 instr_addr[0] = instr_addr0_override;
11190 /* Pass 9 - Linker */
11191 for(i=0;i<linkcount;i++)
11193 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11195 if(!link_addr[i][2])
11198 void *addr=check_addr(link_addr[i][1]);
11199 emit_extjump(link_addr[i][0],link_addr[i][1]);
11201 set_jump_target(link_addr[i][0],(int)addr);
11202 add_link(link_addr[i][1],stub);
11204 else set_jump_target(link_addr[i][0],(int)stub);
11209 int target=(link_addr[i][1]-start)>>2;
11210 assert(target>=0&&target<slen);
11211 assert(instr_addr[target]);
11212 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11213 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11215 set_jump_target(link_addr[i][0],instr_addr[target]);
11219 // External Branch Targets (jump_in)
11220 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11221 for(i=0;i<slen;i++)
11225 if(instr_addr[i]) // TODO - delay slots (=null)
11227 u_int vaddr=start+i*4;
11228 u_int page=get_page(vaddr);
11229 u_int vpage=get_vpage(vaddr);
11231 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11233 if(!requires_32bit[i])
11238 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11239 assem_debug("jump_in: %x\n",start+i*4);
11240 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11241 int entry_point=do_dirty_stub(i);
11242 ll_add(jump_in+page,vaddr,(void *)entry_point);
11243 // If there was an existing entry in the hash table,
11244 // replace it with the new address.
11245 // Don't add new entries. We'll insert the
11246 // ones that actually get used in check_addr().
11247 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11248 if(ht_bin[0]==vaddr) {
11249 ht_bin[1]=entry_point;
11251 if(ht_bin[2]==vaddr) {
11252 ht_bin[3]=entry_point;
11257 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11258 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11259 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11260 //int entry_point=(int)out;
11261 ////assem_debug("entry_point: %x\n",entry_point);
11262 //load_regs_entry(i);
11263 //if(entry_point==(int)out)
11264 // entry_point=instr_addr[i];
11266 // emit_jmp(instr_addr[i]);
11267 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11268 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11269 int entry_point=do_dirty_stub(i);
11270 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11275 // Write out the literal pool if necessary
11277 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11279 if(((u_int)out)&7) emit_addnop(13);
11281 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11282 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11283 memcpy(copy,source,slen*4);
11287 __clear_cache((void *)beginning,out);
11290 // If we're within 256K of the end of the buffer,
11291 // start over from the beginning. (Is 256K enough?)
11292 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11294 // Trap writes to any of the pages we compiled
11295 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11297 #ifndef DISABLE_TLB
11298 memory_map[i]|=0x40000000;
11299 if((signed int)start>=(signed int)0xC0000000) {
11301 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11303 memory_map[j]|=0x40000000;
11304 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11309 // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
11310 if(get_page(start)<(RAM_SIZE>>12))
11311 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11312 invalid_code[((u_int)0x80000000>>12)|i]=0;
11315 /* Pass 10 - Free memory by expiring oldest blocks */
11317 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11318 while(expirep!=end)
11320 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11321 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11322 inv_debug("EXP: Phase %d\n",expirep);
11323 switch((expirep>>11)&3)
11326 // Clear jump_in and jump_dirty
11327 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11328 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11329 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11330 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11334 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11335 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11338 // Clear hash table
11339 for(i=0;i<32;i++) {
11340 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11341 if((ht_bin[3]>>shift)==(base>>shift) ||
11342 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11343 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11344 ht_bin[2]=ht_bin[3]=-1;
11346 if((ht_bin[1]>>shift)==(base>>shift) ||
11347 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11348 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11349 ht_bin[0]=ht_bin[2];
11350 ht_bin[1]=ht_bin[3];
11351 ht_bin[2]=ht_bin[3]=-1;
11358 if((expirep&2047)==0)
11361 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11362 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11365 expirep=(expirep+1)&65535;
11370 // vim:shiftwidth=2:expandtab